APPLICATION NOTE

POWER LINE MODEM APPLICATION

REMOTE CONTROL USING ST7537 AND ST6
By Joël HULOUX, Patrice MOREL

SUMMARY Page
I INTERFACE BETWEEN ST7537 AND ST626X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.I INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.2 PINS DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.2.1 RSTO and NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.2.2 Carrier Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.2.3 Rx/Tx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.2.4 Rxd and Txd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.2.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.2.6 Oscin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.2.7 Other ST6265 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.2.7.1 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.2.7.2 PA4..pA7 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I.3 SOFTWARE INITIALISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I.4 TIMER 1 FOR 1200BPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I.5 INTERRUPT ROUTINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I.5.1 NMI interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I.5.2 Receive Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I.5.3 Timer 1 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
II TRANSMISSION METHOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
II.1 MAIN ASPECT OF COMMUNICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
II.1.1 Asynchronous 1200bps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
II.1.2 Carrier Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
II.1.3 Programs Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
II 2 PACKED MESSAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
II.3 C.S.M.A. PROTOCOL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
II.4 REAL TIME AND COMMUNICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
II.5 FRAME DEFINITION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
II.5.1 Standard Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
II.5.2 Acknowledge Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
II.6 COMMUNICATION REGISTERS DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
II.6.1 Communication Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
II.6.2 Network/Application Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
II.6.3 Parity Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
II.7 MAINS FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
II.7.1 Main Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
II.7.2 Reception Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
II.7.3 Acknowledge Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

AN535/1094 1/20
REMOTE CONTROL USING ST7537 AND ST6

III APPLICATION : DIMMER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

III.1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
III.2 SCHEMATICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
III.3 PINS DESCRIPTION & SOFTWARE INITIALISATION . . . . . . . . . . . . . . . . . . . . . . . . . 13
III.3.1 Slave Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
III.3.2 Master Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
III.4 DIMMER CONTROL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
III.4.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
III.4.2 Triac Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
III.4.3 Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
III.5 APPLICATION SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
III.5.1 Display Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
III.5.2 Slave System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
III.5.2.1 AR Timer Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
III.5.2.2 Registers for Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
III.5.2.3 Dimmer Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
III.5.2.4 Push-button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
III.5.2.5 Potentiometers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IV NETWORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IV.1 NETWORK SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IV.1.1 Communication between 2 Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IV.1.2 Communication with Several Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IV.1.3 Timinig Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IV.2 EXAMPLE OF IMPLEMENTATION OF SOFT CARRIER DETECTOR . . . . . . . . . . . . . 17
IV.3 IMPLEMENTATION OF C.S.M.A. ON ST6265 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
V CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VI ANNEXE A : ST6x PROGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VII ANNEXE B : SCHEMATICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PRELIMINARY
All benefits and features of the ST7537CFN have been detailed in Application Note AN655.
I suggest the reader to read this one before starting with this new application.

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 REMOTE CONTROL USING ST7537 AND ST6

I- INTERFACE BETWEEN ST7537 AND ST626x the receive program, even if the ST6 is doing
SGS-THOMSON is now introducing with this inter- something else. So the pin pA0 has to be pro-
face between the power line modem ST7537 and grammed as an interrupt (with pull-up) to allow
the low cost family ST6MCU a wide range of appli- receiving.
cations for home automation. This module allows I.2.3 - Rx/Tx
communication between distant equipment by the The Rx/Tx pin is used to switch between receive
mains and then remote control can be done in an and transmit mode. It has to be connected to an
easy way. This include applications like lighting output port of the ST6, to allow the ST6 to switch
dimmer, heater control, or phone remote system. between Rx and Tx. pC4 has to be programmed as
output port.
Figure 1 : Hardware Connection Between
ST7537 and ST6265 I.2.4 - Rxd and Txd
ST7537 ST6265 Digital datas are going over these pins. They have
C WD pA1 to be connected to pC2 and pC3 for the data
o Rx/Tx PC4 transfer. Then, the programmer can use the PSI
m
m CD pA0 (Programmable Serial Interface) or work on the
Mu
a n Txd pC3 data values by programming pC3 as output and
i i
n c
Rxd pC2 Reset
+
pC2 as input (without interrupt and with pull-up).
s a RSTO NMI
t I.2.5 - Watchdog
i MCLK %2 Oscin
o pA7...pA4
This pin is connected to pA1, which must have a
n falling edge at least every 1.5s (MAX value). This
feature has been included in ST7537 for security
F = 11.0592MHz reason. So pA1 has to be set and reset at least
every 1.5s (see RSTO pin description).
Address
AN535-01.AI

Switches I.2.6 - Oscin

The maximum operating frequency of ST6265 mi-
crocontroller is 8MHz with a 5V DC supply (and
I.1 - Interface 8.5MHz with 6V). In order to use the 11.0592MHz
The choice of these ST6 pins is not the only one, provided by the P.L.M., we must decrease this
but the software suggested is written for this inter- frequency. An easy way is to divide by 2 the master
face. clock :
I.2 - Pins Descriptions Figure 3 : The Flip-flop D-type Divide the Clock
I.2.1 - RSTO and NMI MCLK OSCIN
The RSTO is the reset output of the ST7537. It set CLK Q
to high when the supply voltage is lower than a limit

AN535-03.AI
D Q
(typically 7.6V) or when no negative transition oc-
curs on the watchdog input for more than 1.5s.
Then, the RSTO is going back to low level. This
falling edge is used to make an NMI on the ST6 A flip-flop D-type is used to divide MCLK by 2. So,
chip. The NMI vector (number 0) must be the same the microcontroller has an input frequency of
as the reset vector in order to comply with Home 5.5296MHz (quartz frequency divided by 2).
System specifications. I.2.7 - Other ST6265 Pins
I.2.7.1 - RESET Pin
Figure 2 : RSTO Generate a NMI
To provide a good initialisation, a 2.2µF capacitor
H is connected to the ST6265 reset pin. An internal
RSTO pin
300kΩ is loading the capacitor during the power on.
L
AN535-02.AI

This provides a delay that allows power supply

Non Masquable Interrupt stabilisation. The high value of the resistor requires
(Falling Edge)
a tantalum capacitor type.
I.2.2 - Carrier Detect I.2.7.2 - pA4..pA7 Pins
The Carrier detect is driven low when the signal These pins are used to enter an objet address
amplitude on the receive analog input is greater (network conf iguration). pA4..pA7 are pro-
than a carrier detection level (typically 5mV). It has grammed in input with pull-up.Address number can
to be connected to an interrupt pin in order to start be modified if necessary.
3/20
REMOTE CONTROL USING ST7537 AND ST6

I.3 - Software Initialization

At reset state, all the ports are in input with pull-up, and interrupt register (IOR) is cleared, so the reset
routine must configure the ports to comply with hardware connections.
Table 1 : Port Configuration
Register Bits Values Byte Value (e.g.) Description
IOR GEN (D4) set 50 h Enable all interrupts
LES (D6) set Level sensitive mode on interrupt #1 (port A)
DDRA D0 res 02 h A0 in input
D1 set A1 in output
D4..D7 res A4..A7 in input
ORA DO set 03 h A0 interrupt with pull-up
D1 set A1 in output push-pull set to 1
D4..D7 res A4..A7 in input with pull-up
DRA D0 res 02h
D1 set
D4..D7 res
DDRB D0..D7 set FF h B0..B7 in output
ORB D0..D7 set FF h B0..B7 in push-pull output
DRB D0..D7 set FF h set to 1
DDRC D2 res 0C h C2 in input
D3 set C3 in output
C4 set C4 in output
ORC D2 res 0C h C2 interrupt with pull-up
D3 set C3 in output push-pull set to 1
D4 set C4 in output push-pull set to 1
DRC D2 res 0C h
D3 set
D4 set

The hexadecimal values are given only for exam- one is used for C.S.M.A. management (see II.3).
ple, these values will change due to the others pins Table 2 : Baudrate Variation
programming (application software). In the pro-
gram, every write to port A and port C must be done Min. Nom. Max. Unit
by writing a copy register, because these ports are Rate 1,199.96 1,200.08 1,200.2 Bps
in input and output, and this includes single bit
operation (see ST6265 datasheet for further de- That means the following registers values :
tails).
Table 3 : Timer 1 and Oscillator Configuration
I.4 - Timer 1 for 1200Bps
Register Bit Value
The MCU frequency is 5.5296MHz. With an inter-
nal clock divider set to 1, a prescaler set to 4 and Oscillator control register RS0 0
OSCR RS1 0
a counter set to 96, the transmit and receive rate is
1200.08Bps (Figure 4). Timer status control register PS0 0
TSCR1 PS1 1
The quartz is a 11.0592MHz with a accuracy of PS2 0
100ppm. That means a final variation of 0.12Bps Timer counter register D0 - D7 96
around 1200.08Bps. TCR1 (decimal
When the timer 1 is not used for the baudrate this value)

Figure 4 : Dividing MCU Clock to Obtain 1200Bps

ST6265

TIMER/
FLIP-FLOP OSCILLATOR PRESCALER COUNTER
WATCHDOG
D TYPE DIVIDER
DIVIDER
AN535-04.EPS

MC LK OSCIN Fint Ftimer

%2 %1 %12 %4 Count 96

4/20
 REMOTE CONTROL USING ST7537 AND ST6

I.5 - Interrupt Routines II - TRANSMISSION METHOD

Interrupt vectors are mostly defined by the trans-
mission program. NMI (vector #0) and the port A II.1 - Main Aspect of Communication
interrupt (vector #1) are used by the communica- - Asynchronous 1200Bps,
tion program. The port C (vector #2) does not need - Transmit mode must be set for less than 1s
interrupt. The Timer 1 and ADC interrupt is used for (Cenelec specifications),
communication timing (see CSMA recommenda- - Carrier detect is set between 4 and 6ms after the
tion). beginning of the Reception (the first 3 or 4 bits
AutoReload timer interrupt is also available. are lost) and is reseted in the same delay (an
interference byte is received at the end of the
Table 4 : Interrupt Programming frame). This delay corresponds to the demodula-
Vector #0 NMI JP RESET tor trainning.
Vector #1 Port A and B JP RECEIVE
(or cascaded interrupt) II.1.1 - Asynchronous 1200Bps
Vector #2 Port C and SPI NOP and RETI In order to transmit at 1200Bps, the transmit pro-
Vector #3 AR Timer Available interrupt gram needs a timer (TIMER 1) to send a bit every
for application 1/1200s. In the receiving routine, the program is
Vector #4 ADC and Timer 1 Communication timing synchronised on every startbit, and use a timer
(Timer 1) to read a bit every 1/1200s. This allows
I.5.1 - NMI Interrupt synchronisation on each byte, and the reception is
aborted if carrier disappears between byte recep-
The RSTO pin of the ST7537 is connected to the
NMI pin of the ST6265 pin. The NMI interrupt tion. During byte reception Txd is set to ”0” in order
to be independent of CD level (noise independant).
provides the reset of the system.

I.5.2 - Receive Interrupt II.1.2 - Carrier Detect

This interrupt manages frame reception, that The Figure 5 shows the timing diagram of a com-
means : munication.
- Power line modem pins control, In order to allow a good transmission, the frame
- Bit reception (synchronisation), must contain a header that is more than 3 bits long
- Byte control, and that contains no 0 (start bit) : FF h for example.
- Frame control. An easy way to avoid the last bad bit is to know the
The interrupt program set bits in network/applica- frame length (fixed length for instance).
tion register (NA-CTRL) then the main program is
able to know the communication status by reading II.1.3 - Programs Specifications
this register. In transmit mode, the Rx/Tx pin must be low, and
set to high after the transmission of the frame.
I.5.3 - Timer 1 Interrupt Transmission time must be shorter than 1s : that
This interrupt is enabled at the end of a frame allows a maximum frame length of :
reception or transmission to allow a delay between 1200
= 109 bytes (1 byte = 1 start bit + 8 data bits
communication events (see C.S.M.A. specifica- 11
tions). It also leave time for application program. + 1 parity bit + 1 stopbit = 11 bits).
Figure 5 : Flow Diagram of Digital Datas
Bits lost

TRANSMITTED DATAS TXD-REMOTE

CD

RECEIVED DATAS RXD

AN535-05.AI

Wrong bits

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REMOTE CONTROL USING ST7537 AND ST6

Figure 6 : Byte Format

H
ST DATAS P SP
L
ST : Start Bit (low)

AN535-06.AI
P : Parity Bit
SP : Stop Bit (high)

Figure 7 : Frames Format

Standard Frame

PARITY
PREAMBLE HEADER DATAS CHECK

FFh 9Bh 58h 7 bytes 1 byte

Acknowledge Frame
PARITY

AN535-07.AI
FFh E9h 58h CHECK
1 byte

II.2 - Packed message II.3 - C.S.M.A. Protocol Specifications

The power line medium and the modulation em- The protocol used is Carrier Sense Multiple Access
ployed require a special two level encapsulation Protocol. The telegram acknowledge is used to
mechanism : detect non-delivery. Before transmitting, the device
must verify that there is no carrier on the network
- The byte level,
thanks to /CD, then send its message (standard
- The packet level. frame) and wait for an acknowledge of the remote
The byte level control is a low level control, it only device (acknowledge frame). The device is able to
checks the start bit, the stop bit and the parity bit. check the transmission integrity by comparing the
The parity control can be done with byte shift and transmitted and the received parity check byte. The
bit test (sla, jrr, jrs, ...) (Figure 6). remote device is sending an acknowledge only if
the packet is good (byte and packet control).
The packet level control is checking the received The C.S.M.A. protocol definition includes a timing
values. Preamble is used to synchronise and avoid for each stage of the communication. These values
loose of meaning datas. Header works out the are given in the Table 5.
frame type (Figure 7). For instance :
This is the theoretical definition of CSMA specifica-
- 9B58h : Standard frame tions. The programs proposed are using a register
- E958h : Acknowledge frame that is decreased in the main loop, providing a
The parity check byte is composed by all the parity pseudo-random value (1 to 5). For the timing, the
bits of the data block of the frame (see parity timer 1 counts for a delay (depending on the ran-
register). dom register).
Table 5 : C.S.M.A. Specifications
Stage Min. Time Max. Time Number of Values
Total duration of transmission 2s
Duration of transmission after starting 1s
Length to wait from the end of a remote transmission 85ms 115ms 7
to initiate a transmission
Acknowledge sent after 0ms 30ms Defined by software
Retry transmitting (after ack. time) 0ms 42ms Uniformly distributed
Duration between two transmissions of the same device 125ms

6/20
 REMOTE CONTROL USING ST7537 AND ST6

II.4 - Real Time and Communication - Preamble : FFh

Time is one of the most important factor in this - Header : 9B58h
communication application : - Datas : Explained below
- Mains is acting as a network (see C.S.M.A. speci- - Parity check : Parity bits of the data block
fication),
- Home automation system requires a time delay Figure 9 : Data Block Format
below 0.5s. H.A. C.B. S.A. D.A. ORDER DATA
So, communication time as to be taken into ac- 2 bytes 1 byte 1 byte 1 byte 1 byte 1 byte
count. The table below gives values for message
The Datas block is the real message. It contains
delivery (message + acknowledge) with the follow-
the house address, to prevent from sending order
ing values :
to other houses objects. The source and destina-
- Standard frame time : 100ms, tion addresses are used to define who’s talking to
- Acknowledge frame time : 40ms,
who. The Control byte contains network facilities
- C.S.M.A. specifications. as priority, frame counter, ...
In order to approximate to the reality, we have - H.A : (Home address) address of the house
considered 1 error communication and/or a time - C.B : (Control byte) contain frame counter,
waited to dispose of communication channel. priority, group command bit
In Table 6, Tother is the time from the moment the - S.A. : (Source Address) address from the
object wants to transmit (but somebody is already transmitter
transmitting) to the moment the communication - D.A. : (Destination Address) address of the
channel is free. receiver
A message needs about 155ms to be transmitted - Order : Object of the message
with acknowledge. In the worth case, even if 7 - Data : Data byte eventually
objects want to transmit in the same delay, all the
messages will be delivered in less than 2s. II.5.2 - Acknowledge Frame
Figure 10 : Acknowledge Frame Format
II.5 - Frame Definition
RECEIVED
Here is the definition of frames implemented in PREAMBLE HEADER
PARITY
ST6265 microcontroller.
- Header : E958h
II.5.1 - Standard Frame
The standard frame is 11 bytes long, that means
Figure 8 : Standard Frame Format 100ms at 1200Bps (with 11 bits by byte).
PARITY The acknowledge frame is 4 bytes long, that means
PREAMBLE HEADER DATAS
CHECK 40ms at 1200Bps (with 11 bits by byte).

Table 6 : Message Delivery Time

No Communication Errors One Communication Error
Communication Time (ms)
Min. Mean Max. Min. Mean Max.
Don’t wait before transmit 140 155 170 310 326 342
Wait before transmit 220 252 285 390 423.5 457
+ Tother + Tother + Tother + Tother + Tother + Tother

7/20
REMOTE CONTROL USING ST7537 AND ST6

II.6 - Communication Registers Definition

II.6.1 - Communication Registers

Several registers are used by communication programs. they are listed below :
Table 7 : Communication Register Definition
Register Name Register Description
outstart Output buffer start address
in_start Input buffer start address
out_par Parity byte to be send
rand_r Random register
b_count Byte counter
reg_delay Delay before allowing carrier detect
portacopy Port A data copy
portccopy Port C data copy
start_sav Begining of interrupt stack (down stack)
na_ctrl communication control register (see below)
r_pa_reg Register for received parity calculation
t_pa_reg Register for transmit parity calculation
retry Register for transmission retry(before aborting)
r_mess_r Received message register
t_mess_r Transmit message register
reg_trans buffer for a single value
r_ad_r Instantaneous address (read on switch)
t_dat_r Transmitted data register
r_dat_r Received data register
t_r_adr Transmitted remote address
t_adr Transmitted address

These 21 registers have a name, but more than 17 munication status by looking at the Network/Appli-
bytes are needed for communication. In fact, com- cation register.
munication program needs 43 registers (that in- The network/application register is used in two
c lu d e so f t wa re s t a c k a nd bu ff e r f o r ways :
communication). - Tointerface the application program with the com-
munication program. The application program is
II.6.2 - Network /Application Register able to know if order has been received or if an
Application program is not sequential because of acknowledge has been received,
the use of several interrupts. These interrupts are - To enable protocol control inside network pro-
used for reception and communication timing. The gram. That means byte error, unexpected frame,
main program is able to know what are the com- time-out, bad frame parity, transmit-enable.
Table 8 : NA_CTRL Definition
D0 D1 D2 D3 D4 D5 D6 D7
Byte error Unexpected Bad frame Time-out Transmit Too many frame order
frame parity enable errors acknowledge received

8/20
 REMOTE CONTROL USING ST7537 AND ST6

II.6.3 - Parity Register II.7 - Mains Flow

The ST6 must be able to receive a frame whenever
Parity registers are used to compare received and it comes, but it is really important to leave CPU time
transmitted parity frame value (last byte of frame). for Application program. That’s why the main is a
The parity registers have the same look, that is loop, where the application program is running.
given below : When a frame arrives, an IT occurs, the MCU
Table 9 : Parity Registers Definition receives the frame, modifies the communication
status in Na_ctrl register and then go back to the
D0 D1 D2 D3 D4 D5 D6 D7 main loop. If it is an order, the MCU send an
0 Pdata Porder Pda Psa Pctrl Pha2 Pha1 acknowledge and does the order.

- Pdatas : Parity of data byte II.7.1 - Main Flow (see Figure 11)
- Porder : Parity of order byte When the board send a frame, it is waiting for an
- Pda : Parity of destination address byte acknowledge, and tries 3 times if nothing is coming
- Psa : Parity of Source address byte for a delay. If an acknowledge arrives, it is checked
(parity check) and if a problem occurs, the MCU
- Pctrl : Parity of control byte
tries again (3 times maximum).The slave system
- Pha1 : Parity of first home address byte main flow is the same as the master system, but of
- Pha2 : Parity of second home address byte course, the application program changes.
Figure 11 : Main Program Organisation

11
1 Carrier
MAIN Detect
10
NMI

2 12
Init Receive

17
Application
Recovering

4 9
Yes 13
Order Send Ack
Received? Do Order Timer 1
IT

5 7 16
Waiting Yes Transmit/
Ack
Ack? Control Receive
Enable

8
AN535-08.AI

Application

9/20
REMOTE CONTROL USING ST7537 AND ST6

Figure 12 : Receive Routine

1
Receive it

2
Receive
Init

Next Char.

3
No Carrier Wait
Time Out Char.
Startbit

4 Good Char. 5
Receive Frame
Char. Built
Bad Char. All car.
Received
Unespected Good Frame
7 Frame
RETI 6
Modify

AN535-09.AI
Status
Order Done

II.7.2 - Reception Flow and a timer control. The parity byte is calculated as
The synchronisation is done on each startbit : it’s a the frame is sent, and it is sent after.
byte synchronisation. In order to leave MCU time for application, receive
IT is disabled after each frame reception and for a
II.7.3 - Acknowledge Control Flow delay of 30ms. This time is controlled by the Timer
The transmit part will not be detailed, it is just a pins 1 and the reg_delay register.
Figure 13 : Ack Control Routine

1
Ack
Control

2
Yes Acknowledge No
Received?

3
Compare No 4
Parity Check Time
Out

Yes

7
Retry
Send
AN535-10.EPS

Frame
5
Ret

10/20
 REMOTE CONTROL USING ST7537 AND ST6

III - APPLICATION : DIMMER CONTROL you change the number on the display. This feature
has been added to prove that the ST6265 is able
III.1 - General Description (see Figure 14) to receive and send order while it is dimming.
This section gives an example of an application that If you plug the master system in first, it will try to
allows the dimming control of a remote light (or connect with the slave system three times, then it
something else) by using the transmission with will light the error led (digital point of the 7 segments
P.L.M. This application needs two boards : display). So you will have to plug the slave system
- A master system, with a push-button (Dim- and send an order (push the button and turn the
ming/off), 2 potentiometers and a 7 segments display potentiometer) in order to return in normal
display, mode.
- A slave system, with a 7 segments display and a The dimming control is done by the use of a triac
plug for dimming control. (BTA08-600TW) so the load connected to the plug
When the user presses the key (command), or must not exceed 1000W.
turns a potentiometer, the master system sends a
message, lights the decimal point on and waits an III.2 - Schematics (see Figures 15 and 16)
acknowledge. The remote board receives the mes-
sage, sends an acknowledge and does the order. This section gives the schematics of the two
boards. pB7, pC0 and pA2 have different meaning
If no problem occurs, the master system receives
the good acknowledge and switches the decimal on the master and on the slave board, that ’s why
we give two schematics. But it is possible to make
point off. Otherwise, after trying sending the mes-
a single board with dual implantation.
sage 3 times, the decimal point remains lighting : a
communication error occurs. Warning : on this board the VDD is connected (via
With the push-button, you can turn the light off or 0Ω resistor) to the neutral mains.
on. With the dimmer potentiometer, you can control That means all the board is on the Mains supply
the light intensity. With the display potentiometer, voltage!
Figure 14 : Dimmer Control Application Description

Mains

Power Line Modem Power Line Modem

ST7537 ST7537

Mains plug

Dimming/off

Dimmer Display
AN535-11.AI

Master System Slave System

11/20
REMOTE CONTROL USING ST7537 AND ST6

Figure 15 : Slave Board Schematic

ST6265
J1 : jumper for 50/60Hz selection

B0 B1 B2 B3 B4 B5 B6 C0 A2 B7

2.2kΩ
220Ω

220Ω

220Ω

220Ω
220Ω

220Ω
220Ω

1kΩ
J1 VDD 0Ω Neutral

4.7kΩ
G A B C D E F

A 2N2907 33Ω
G A1

820Ω
F B BTA08-600TW
A2
G
LOAD

E C 1MΩ
Phase
6.8nF
DP
D

AN535-12.EPS
VDD

Figure 16 : Master Board Schematic

ST6265

B0 B1 B2 B3 B4 B5 B6 B7 A2 A3 C0
220Ω

220Ω

220Ω

220Ω

220Ω

220Ω

220Ω

220Ω

Push
VDD Button

G A B C D E F
A 470Ω
P1 P2

F B

G
P1, P2 : 100kΩ linears
E C
DP
DP
D
AN535-13.AI

VDD

12/20
 REMOTE CONTROL USING ST7537 AND ST6

III.3 - Pins Description & Software Initialisation - C0 is connected to a push-button, and has to be
programmed in input with pull-up,
III.3.1 - Slave Board - A2 and A3 are input for analogic values coming
On this board, there is a 7 segments display appli- from the potentiometers, so they have to be pro-
cation and a dimmer application. grammed in input, and reading an analogic value
The display application is very simple. The pins B0 is done by programming one of these two pins in
to B6 have to be programmed in output with pull-up analog input, but not both in the same time.
(push-pull). They are connected to the display by Table 11 : Master System Pins Configuration
220Ω resistors to limit the LED current. The display Byte
is a common anode so the pins have to be reseted Bits
Register Value Description
Values
to make the display lighting. (e.g.)
The dimmer application is most sophisticated, be- DDRA D2 res 00 h A2 in input
D3 res A3 in input
cause it requires a zero crossing detection, and the
possibility to wait a delay before firing the triac. See ORA D2 res/set 04 h (A2 in input analog
D3 set/res /08 h A3 in input) / (A3 in
dimmer control part for more information. input analog A2 in
DRA D2 set 0C h
The pin A2 is connected to the phase (via 1MΩ), in D3 set input)
order to provide the zero crossing. This needs DDRB D0..D7 set FF h B0..B7 in output
Neutral connected to VDD to have a reference level. ORB D0..D7 set FF h B0..B7 in push-pull
A2 has to be programmed in input. output set to 1
The pin B7 has to be programmed in push-pull DRB D0..D7 set FF h
output to provide the pulse. B7 is the only pin that DDRC D0 res 00 h C0 in input
is connectedto Auto Reload timer, so the fire signal ORC D0 res 00 h
needs to be amplified before driving the triac (the C0 with pull-up
DRC D0 res 00 h
amplification stage is realised with a PNP transis-
tor). At reset state B7 is configured in input with III.4 - Dimmer Control
pull-up, so B7 is held at VSS by a 2.2kΩ resistor.
This application is working with both 50Hz and III.4.1 - General Description
60Hz mains. The jumper connected to C0 is used This section describes the main aspect of the
to select between the two type of mains. Co has to power control system used on the slave system.
be programmed in input with pull-up. For further details, refers to power control applica-
The pin configuration is the following : tions notes.
Table 10 : Slave System Pins Configuration The output power is controlled by the phase delay
of the triac drive. This delay is referred to the zero
Byte
Register
Bits
Value Description crossing of the line voltage. That needs an addi-
Values tional connection to main voltage, but in a remote
(e.g.)
DDRA D2 res 00 h A2 in input application, this is not a problem.
ORA D2 res 00 h
A2 in input Figure 17 : Power Control Based on the
DRA D2 set 04h Monitoring of the Zero Crossing of
DDRB D0..D7 set FF h B0..B7 in output the Voltage
ORB D0..D7 set FF h B0..B7 in push-pull R L
DRB D0..D7 set FF h output set to 1
DDRC D0 res 00 h C0 in input VLOAD
ORC D0 res 00 h V LINE
C0 with pull-up
DRC D0 res 00 h Vg

III.3.2 - Master Board

On the master system, there are a display applica-
tion and a control application :
- The display application the same as in slave
system, but here, the decimal point is connected Vg
to B7. This decimal point is used as a warning
AN535-14.AI

light for communication acknowledgement. B0 to td 10ms (50Hz) VLINE

B7 have to be programmed in output push-pull, VLOAD

13/20
REMOTE CONTROL USING ST7537 AND ST6

III.4.2 - Triac Specification III.5.2 - Slave System

The triac used is a BTA08-600TW(SGS-Thomson)
Logic Level triac. It has a maximum specified gate III.5.2.1 - AR Timer Configuration
triggering current of 10mA (at 25°C). The current is The dimmer application is using the Auto Reload
provided by the amplifier stage (transistor), and the timer to provide the time delay (Td). When a zero
pulse width is programmed by software. crossing voltage is detected on the mains voltage,
the AR timer is launched with a delay (correspond-
III.4.3 - Timing Specification ing to Td), And immediately after, the reload value
Td determines the power used by the load. Be- is changed to a value corresponding to 10ms delay
tween two pulses, there is a delay of 10ms, except (50Hz). So, when an interrupt occurs (Receive
during Td variation. mode for instance) the MCU is running in IT mode
while the AR timer is providing the power control.
Figure 18 : Load Power Consumption versus The dimming intensity is controlled by the time
Time Delay delay, which has to be between Arr_min, and
Arr_max.
Power The 10ms (or 8ms for 60Hz) delay is provided with
the Arr_sd value. The Arcp value isloaded with Arrc
+ puls_siz ; this register defines the pulse width. All
theses values are depending on the AR timer con-
R figuration :
- AR timer in autorelad mode with
R, L IT disabled : Armc = 20h
- AR prescaler set to 128 and
clock division set to 3 : Arsc1 = 0E1h
AN535-15.AI

Table 12 : AR Timer Configuration

10ms Td
Register 50Hz Values 60Hz Values
As shown in Figure 18, a small delay variation can Armc 20h
affect the load power (that means light intensity in Arsc1 0E1h
dimmer control), so this application is very sensitive Arrc during MCU control Arr_min < Arrc < Arr_max
to delay variations, and the timer has to be tuned Arrc during AR timer Arr_sd_10 Arr_sd_8
very precisely. The timer is loaded with values control
stored in a table in ROM (one table for 50Hz, one Arcp Arrc + pulse_siz
for 60Hz).
The values of Arr_min, Arr_max, Arr_sd are de-
III.5 - Application Software pending on the frequency of the MCU (Fint) and of
the mains (50Hz or 60Hz). The delay waited be-
III.5.1 - Display Application tween the zero crossing detection and the triac
pulse is given by :
The display routine is only checking the range of
the transmitted data and setting the corresponding Td = Tar ⋅ (FFh − Arrc).
port B pins in order to display a digit. The display Where Tar is the time for 1 count : Tar = 6.98E-5s
data is stored in the led_status register. (at 5.5MHz).
Figure 19 : Timing Chart of Zero Cross Level Signal (pA2) and Triac Trigger Signal (pB7)

pA2
pB7

Td Td Td 10ms 10ms 10ms 10ms Td Td

AN535-16.AI

APPLI. MODE IT MODE APPLI. MODE

MCU control AR Timer Control MCU control

14/20
 REMOTE CONTROL USING ST7537 AND ST6

III.5.2.2 - Registers for Power Control Figure 20 : Application Recover and Dimmer
The application register is used to store the dim- Procedure Flows
ming status (on/off) and the zero crossing voltage.
Table 13 : Application Register Definition a) 1 b) 1
Application Dimmer
Recover Application
D0 D1 D2 D3 D4 D5 D6 D7
lght_on zero_dt 0 0 0 0 0 0

- lght_on : Set when dimming 2

- zero_dt : Set when pA0 is 0 Call
dim ctrl
Other bits are unused. 2 No
Cross
Zero?
III.5.2.3 - Dimmer Flow
3
The dimmer procedure has to be launched very Call Yes
often because it provides dimmer synchronisation. aff value
If this procedure is not launched for more than
0.2ms, a test has to be performed in order to see if
a zero crossing has appened during this delay. In 4 3
AR Timer
this case, it is to late to synchronise on this zero get level
Control
crossing so the zero_dt bit of appli_reg has to be
modified and the software will synchronise on the
following zero crossing (Figure 20).
In the left flow : see Figure 20a 5 4

AN535-17.EPS
- Dimm_ctrl check if a new value has arrived for End Ret
dimmer, calculate the new delay and eventually
switch off or on the dimmer control,
- Aff_value checks if a new value has arrived for Figure 21 : Application Recover and Button and
display, calculate the new digit and display it, Potentiometer Control Procedure
- get_level is a macro that get the level of the main Flows
voltage (1 for positive voltage and 0 for negative)
and that modify the zero_dt bit of application 1 1
register. This macro avoids delayed zero crossing Button and Application
Potentiometers Recover
detection.
In the right flow : see Figure 20b
- Zero crossing detectionis done by comparing the 3
2 6
instantaneous level (on pA2 pin) with the bit Button Yes Send Order : Call
Switch aff_value
zero_dt in application register, Pressed?
Dimmer
- AR timer control loads the arrc value correspond- No
ing to time delay, launch the timer, reload arrc
value for a 10ms delay and arcp for the pulse 5
3 6 End
width. Display Yes Send Order :
Potentiometer New Value
Turned? for Display
III.5.2.4 - Push-button
No
The detection of an action on the button is made
simply by reading the value on pin C0. If somebody 4
push on it the MCU sends a frame and waits for an Dimmer No
Application
acknowledge. This action needs more than 130ms On?
so it makes a kind of debounce. Yes

III.5.2.5 - Potentiometers 5 6
Dimmer
The main program reads the converted value on Potentiometer
Yes Send Order :
New Delay
potentiometers,and compares it to the stored value Turned? for Dimmer
AN535-18.AI

(in dimm_val and in aff_val). If the difference be- No

tween the read and stored value is higher than 8,
the MCU send an order to remote system.
15/20
REMOTE CONTROL USING ST7537 AND ST6

IV - NETWORK If it is not the case, or if T has not received the

IV.1 NETWORK SPECIFICATION acknowledge, T tries again to send the order. Of
Power Line communication uses mains distribution course the frame format must allows error detec-
cables that constitute a network adapted to the tion by the receiver (order checksum) an by the
control of devices already connected on it. The transmitter (checksum in ack. frame). In most of
ST7537CFN power line modem complies with the the case, communication occurs without error, and
regulation described in the CENELEC EN50.065-1 the both units must keep silent for a delay Tsilent
document, (so frequency, bit coding and other use- in order to leave time for application control. To
ful featuresare included in the chip). Nevertheless, allow the two units to transmit, the unit T has to wait
the designer of an application has to take in ac- more than R2, so R will be the first to take the
count the power line communication specification channel if it needs to transmit.
when writing his protocol. For instance, access If the two units send a frame exactly at the same
protocols are required for coexistence on the me- time, they will not receive ack. frame, so they will
dium. The following paragraphs give a concrete retry after a delay (Twack). Arandom value is added
case of communication on power line network. In to make one of the two unit faster than the other
first, only 2 devices are connected to the network. one. The total delay is Tretrans.
Then, others devices are connected, and we will be
confronted to a real network specification. IV.1.2 - Communication with Several Units
Figure 23
IV.1.1 - Communication between 2 Units
This is the simplest case of communication. Only Mains 50/60Hz

two devices are able to send and receive packet on

the network. One unit sends an order, the other one Order Frame
ST7537 ST7537 ST7537 ST7537
is replying with an acknowledge.

AN535-21.EPS
Ack. Fram e
PLM PLM PLM PLM
COM. COM. COM. COM.
Figure 22 Unit 4 Unit 3 Unit 2 Unit 1

Mains
With several units, the timing is the same, but even
if a unit is not concerned with a communication, it
Order Frame has to get the frames in account for timing control.
ST7537 ST7537
Ack. Frame For instance, it has to reload its time to keep silent.
AN535-20.EPS

PLM PLM
COM. COM. And if several units have reload there time to keep
Unit T Unit R silent at the end of a communication, the values
reloaded must be different to avoid conflicts on the
The unit T checks that the network is free for access next communication. Again, a random value is
thanks to the Carrier Detector, then it sends its added to make timing different.
frame and waits an acknowledge during a delay Here is a data timing chart of the transmitted signal
Twack. The unit R receive a frame and sends an of the different units (see Figure 24).
acknowledge if R is the destination of the frame. R Anyway, all units must send there message in less
must send the ack. frame before the end of Twack. than two seconds.

16/20
 REMOTE CONTROL USING ST7537 AND ST6

Figure 24

Message Message to U2 U1
Tretans Twack

Ack. U2

U3 wants Tsilent (Priority)

to transmit
Message to U5 U3

U4 wants Tsilent (Priority)

to transmit Tsilent (Priority)
Message U4

AN535-22.EPS
Ack. U5

IV.1.3 - Timing Control

All these timing are resumes in the following table.
Symbol Description Time Comment
Tmax Total duration of transmission 2s
Maximum duration of transmission after starting 1s Feature included in ST7537CFN
TsilentR Lenght to wait from the end of a remote transmission to 85 .. 125ms At least 7 values
initiate a transmission
Twack Acknowledge sent after 0 .. 30ms
Tretransmit Retry transmitting 30 .. 72ms
TsilentT Duration between two transmissions of the same device 125ms

In order to implement these timing, an easy way is You will be able to have good communication with
to use a single timer and several registers corre- a receive signal of around 50dBµV which means a
sponding to the different delays you want to count. dynamic of around 70dB.
The timer will decrease the registers at each over- Because we want to get the benefit of the very good
flow, and the counters are ”launched” by loading a sensitivity of the ST7537, we will program Txd to
value in the corresponding register. An example of ”0” in receive mode and create by soft a frame
implementation on ST6265 is given in part III. detector . We will use the CD signal as mentioned
This access protocol allows an additional network by CENELEC only when we want to transmit a
priority: if you allow unit 1 (U1) to transmit before frame . Different software frame detector can be
unit 2 (U2), then U1 will always sends its messages implemented depending of the resources of your
before U2, and will have a highest network priority. microcontroller. You can program your microcon-
By choosing the range of TsilentR of a unit, you will troller to go in receive frame when it received the
then choose its priority. expected byte.
Values for TsilentR.
Figure 25
Range Priority
85..94ms Highest priority
AN535-23.EPS

RxD PREAMBLE EXPECTED BYTE

95..104ms Standard priority
105..115ms Lowest priority RANDOM DATAS FRAME

IV.2 - Example of Implementation of Soft Car- So the preamble is for demodulator training (when
rier Detector you start a communication the 3 first bits are lost
We have seen that by programming the TxD to ”0” by the receiver) and when you will match with
in receive mode we increase the sensitivity of the expected byte the microcontroller will go in receive
ST7537 because there is no more clamping by CD. frame routine.

17/20
REMOTE CONTROL USING ST7537 AND ST6

On the ST6 microcontroller we have implemented With this way of programming , the places where
the following frame detector. counters are loaded are very significant :
- Xmit_count is loaded at the end of the message
Figure 26 sending procedure in order to wait an acknow-
ledge (30ms) and at the end of the reception of a
RxD good acknowledge (time between two transmis-

AN535-24.EPS
RANDOM DATAS ”1” FFh DATA sions of the same device : 125ms).
FRAME - Rmit_count is loaded at the end of a reception
with a random value (time between two transmis-
We put Txd =” 1” on the transmitter for around 4ms sion of different devices : 85 to 115ms).
(for demodulator training) and The timer will allow the sending of a frame after
after we send in asynchronous mode FFh following C.S.M.A. delays.
by the complete frame. On the receiver , we check Figure 27 : Sending a frame after C.S.M.A
that we have RxD equal to ”1” for at least 7ms (we Delays
are looking for FFh) , then we go in receive and we
will have frame synchronisation on the first start bit
of the data. SEND_FRAM
We did a trial in our lab with this system during
2 hours without having the ST6 going in frame
receive routine on bad datas dued to noise signal.

IV.3 - Implementation of C.S.M.A on ST6265

RECEIPT_FLAG
The C.S.M.A. (Carrier Sense Multiple Access) SET ?
needs a Timer for its implementation. But the
No
ST6265 timer 1 is already used for bit time and No
software carrier detect. Furthermore, sometimes
the timer has several functions at the same time,
so the timer programming becomes very compli- XMIT_FLAG
cated. SET ?
In order to simplify this programming, we have
implemented a single time delay corresponding to Yes
Yes No
bit time (f = 1200Hz ). So for each mode there is a
counter corresponding to a delay. The counters are
incremented (or decremented) in the timer interrupt RMIT_FLAG
routine while they are cleared (or affected with SET ?

values) in main program.

For C.S.MA. specifications, we use two counters :
- Xmit_count
This is the delay before retransmitting SEND_TRAM
- Rmit_count
This is the delay before transmitting after a recep-
tion
These counters are decremented in Timer 1 inter-
rupt routine and flags are set when they become
AN535-25.EPS

null. These flags are allowing the sending of a

RET
frame. Acknowledge frames are not concerned
with these timing.

18/20
 REMOTE CONTROL USING ST7537 AND ST6

V - CONCLUSION
The ST7537 master and slave systems are demon- - Frame transmission : the transmission is asyn-
strative applications with low cost components. chronous with odd parity and there is a frame
These boards are realised with discrete compo- parity byte at the end of the frame, but if errors
nents but the size of these applications can be are detected, they are not corrected. A correcting
reduced by using a switching power supply and code should be implemented in less than
SMD (the ST7537 and the ST6265 are both avail- 200 bytes on ST6x,
able in small outline plastic). Severalimprovements - Power control : the 50Hz/60Hz detection should
should be done in order to make a more flexible be done automatically instead of using a jumper.
product : And the number of stages in dimming mode
- Network management : All the addresses are should be increased to obtain a pseudo-continu-
fixed except the slave system address (switches). ous variation.
The software should be able to change the Home
address, and objects addresses. This job needs All these modifications are realisable, because the
management frame reception, emission and con- program is less than 800 bytes long and the MCU
trol, is working at 5.5MHz, so there is place and CPU
- Byte transmission improvement : the software is time left. The software is divided in module, so parts
reading the value on Rxd pin only one time (at the can be removed, and mains programs source
half of the bit), it would be better to do it several (master.asm and slave.Asm) are less than
time to avoid spike perturbations, 300 lines long.

VI - ANNEXE A : ST6x PROGRAMS

The program is divided in several modules, so it is easy to take parts of it and it is more readable. The
master system and the slave system have common parts, but the mains programs are not the same.
Table 14 : Modules Used in Master and Slave Boards
Name Function System
6215_reg.asm Common 62xx core registers Master/Slave
ST6_7537.asm Byte communication with ST7537 Master/Slave
Def_fram.asm Frame control Master/Slave
Address.asm Address switches management Master/Slave
Display.asm 7 segment display management Master/Slave
Pot_et_b.asm Potentiometers and push-button management Master
Powerctl.asm Power control Slave
Master.asm Main master program Master
Dimmer.asm Main slave program Slave

The master and slave programs are compiled without linker, but when using the powerctl.asm module the
option :
block 64% S64
is included in order to provide a good window banking for the tables in rom (AR values for dimmer
application). That makes the object code bigger than it is but it is the price to pay.

19/20
20/20
+5V MASTER
DP
1 1
1
RV1 2 RV2 2
R25 R24 BP1
100kΩ 100kΩ 220Ω 470Ω BP
3 3 2

+10V

1
1 2 2 Q8
10 pA0 OAOAO 22 C8 2 1 2N2907
C11
C15 100nF 2.2µF 3
4321 13 pA1 1 2
2.2µF
SW1 14 pA2 NMI 23 R11
VII - ANNEXE B : SCHEMATICS

180Ω 3
SW DIP4 1 1 2
15 pA3 C7 C10 2 Q4
5678 R13 4.7kΩ 100nF 2.2µF C9 2N2222
16 pA4 pC0 28 2 1 100nF
R9 R12
R14 4.7kΩ 1 2 47kΩ 2.2Ω 1
17 pA5
R15 4.7kΩ R10
18 pA6 pC1 27 2 14 27 26 5 2.2Ω
R16 4.7kΩ R2 1kΩ
AF1 19 pA7 A D D I T RAI 3
5082-7850 V V E F X
pC2 26 D D M O F 2
R17 220Ω IC2 PAFB 6 R4 C6
+5V 11 G 1 pB0 D D I I R8 1kΩ 2.2Ω 1µF
ST62E65 ATO 7 1
A R18 220Ω
3 1 A 2 pB1 pC3 25
1 VCM PABC/ 8 1
12 F B R19 220Ω
13 B 4 pB2 18 MCLK PABC 9 2 Q5
pC4 24 2N2907
R20 220Ω R3
G 10 C 5 pB3 +5V 19 WD/ IC1 TEST1 10 3 2.2Ω
REMOTE CONTROL USING ST7537 AND ST6

R21 220Ω 20 RX/TX/

ST7537 TEST2 11
8 D 6 pB4 4
E C OSCOUT 21 3
R22 220Ω P 21 CD/ TEST3 12
DP 5 Q R D 2 2 Q1
7 E 7 pB5 2N2222
D X X 22 TXD TEST4 13
R23 220Ω T T OSCIN 20
2 F 8 pB6 IC4 1
A A 23 RXD
6 L L 74HC74 X X TRE C1
T T R5
9 pB7 1 2 24 RSTO A D 2.2Ω 1 C4 1 3 1µF MKT
DP 11 12 6 N C CLK 3 V V A A 4
L S L L 2 Q3 6.8nF
25 DVCC S NPO 2 2 1 2
1 S S 1 2 2N2907
1 2 R6 R7 5 R1
28 15 16 17 3 1 1MΩ
+5V 47kΩ 180Ω 2 1 2
C17 +5V XT1
D1
100nF +5V 3 TRANSIL C19
+5V 2 IC4 1 2 2 2 Q2 P6KE6V8CP 1µF MKT
C18 C20 C6 C2 2 C3 2N2222 1
10µF 100nF 22pF 22pF
1 100nF 15V 2 1 1 1 1
R28 0Ω +5V
p2A 1
Phase 1
R29 1kΩ 1 W2
Q7 2
2N2907 STR3PTS IC3 IC5
L 2 1 p1A
O R26 33Ω 3 L78L05 L78S10 TRE
+5V +10V
A D2 A1 2 1 D3 10 1 1
D BTA08- G 3 3 1 3 11
600TW R27 R30 R31 1 1 2 1 1 2 1 1 D4 12 3 110V
A2 3 C15 C13 C23
820Ω 2.2kΩ 4.7kΩ C14 10µF C12 10µF C22 1000µF 14 5 2 SW2
p2B 2 100nF 100nF 100nF D5
2 2 15V 2 2 15V 2 2 25V 220V Commut
R32 1MΩ 16 7 3 Mains 3 p1C
D6
p2C 3 UI 30 x 10.6 110V
Neutral 4
C24 4 x 1N4004
6.8nF
SLAVE 2 p1B

AN535-19.AI
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