y

t rin g
i
a e
M ne r
i s g i u
Electronic
onic
s h Instruments
Instru
n p
ments
g
A E ity a
r
Dr.
. Electrica
a l
r. Ashis
Ashis
Electrical
Maity
a r
Engineering
Engineerin
D ricIIIITT Kharagpur
K
Kharagph
c t I T
le I
E
 Few important information
y
t rin g
i
‰References:
Press India a e
¾Electronic Instrumentation and Measurements, ts, David A. Be
Bell, 3rdd Editio
Edition, Oxford University

M ne r
¾Electrical Measurements & Instrumentation, n, U.A. Bakshi,
hi, A. V. B
Bakshi,, TTechnical
Publications
i s gi u
p
¾Electronic Instrumentation, H. S.. Kalsi, 3rd Edition,n, McGraw
McGra Hillll Education
Educat

s h n
¾Linear Integrated Circuits by D. Roy Ch
g
Choudhury
dhury and S Shail B. Jain, New
N Age International

E a
Publisher

. A l
¾Digital Design -With an Introduction
roduc
r
to tthee Veri

a
Verilog HDLDL by M.Mo
M.Morris Mano and M. D. Ciletti,

r a
Pearson.
‰Course page:
D ric Kh
http://www.facweb.iitkgp.ac.in/~ashismaity/Electronic_measurement_Spring_2025.
b.iitk .ac.in/~as ismaity/Ele
html
c t I T
‰Surprise Class Test.
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 2
Lecture-wise plan (post mid-term session)
y
t rin g
i
‰Module-1: Analog Electronic Basics
characteristics [4]
a e
¾Class-1: Introduction to electronic Instrumentation,
tation, compara
comparator and its st
static and dynamic

M ne r
¾Class-2: Operational amplifier: Differential gain ve
versus common
ommon mo mode gain,
ain Non-idealities:

s gi
input bias current and input offset current,
current and input
i ut offset voltage.
volt [4]
4]

h i
¾Class-3: Offset Cancellation in op-amp,
¾Class-4: Development of Instrumentation
p u
amp, Difference
Dif
mentatio Amplifier
e amplifier [4]
lifier [4]
‰Module-2: Analog Instruments
uments
s E n a g
. A
¾Class-5: Analog DC Voltmeters,
l a r
meters Emitter
tte Followe
Follower, FET Input Voltmeter,
Voltm Difference Amplifier

r a
Voltmeter [1]

D ric Kh
¾Class-6: Op-Amp
Amp Amplifier
Amplif Voltmeter, Vo Voltage-to-Current
ge-to-Current based Voltmeter, Series Ohmmeter,
Shunt Ohmmeter,
meter, Linear
Lin Ohmmeter
hmmeter [1[1]

t
¾Class-7: Analogg AC
A Voltmeters,
tmeters, Op-amp
mp Halfwave Precision Rectifier Voltmeter , AC Voltage-

c T
to-Current Based Voltmeter
tmeter (Full-Wave)
(F Wave) [1]

e
¾Class-8: Electronic
I I
ronic Multimeter

l
Multim and Differe
Different Probes, Tutorial [1]

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 3
Lecture-wise plan (post mid-term session)
y
t rin g
i
‰Module-3: Digital Electronic Basics

a e
¾Class-9: Flip-Flops, Design of Ripple Counterss and BCD Counters
Cou s [5]
¾Class-10: Scale-of-1000 Counter, Scale of-2000
2000 Counter,
Counter BCD-to-Seven
o-Seven Segment Decoder,

M ne r
LED Displays: 3.3 digits and 4.5 digits [1]
¾Class-11: Analog-to-Digital Conversion,, Static
tic Characteristic, Sample and Hold, Linear-Ramp
Ch acteristic, Sa
ADC [1]
i s gi u
p
¾Class-12: Digital-Ramp ADC, Digital-to-analog
igital to ana converter
nverter [1]
[1
¾Class-13: Tutorial

s h n g
E a
‰Module-4: Digital Instruments
ments

.
Digital Voltmeter [1]]A
¾Class-14: Single-slope ramp
l a r
amp generator
ge tor type
ype digital
dig voltmeter,
tmeter, Dual Slope Integrator Based
¾Class-15: Digital
Meter [1]
¾Class-16: Accuracy
r
D ric Kh
gital Ohmme
a
Ohmmeter, Digital
gital AC Voltmeter
curacy Measurements,
Vo meter and Dig
asurements, Reciprocal
Digital Multimeter, Digital Frequency
Counting Based Frequency Meter [1]
procal Co

c t
¾Class-17: Pulse-Width measurement,
and Digital Instruments
measurem nt, W

I
nts [1]
T
Waveshaping
esha Circuit, Comparison between Analog
¾Class-18: Tutorial
e
orial
l I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 4
Lecture-wise plan (post mid-term session)
y
t rin g
i
‰Module-5: Signal and Function Generators
a e
¾Class-19: Basic theory for oscillation, Low
w frequen
frequency signal
nal gene
generator, Wein Bridge
Oscillators
M ne r
s gi
¾Class-20: Bistable operation, Astablele multivibrator
ultiv ator

h i
¾Class-21: Function Generators:
ors: Triangular
Generator, Sine wave generator
rator
p u
Triangu wave ave generators,
gener , Square Wave
W

¾Class-21: Tutorial
s E n a g
‰Module-6: Oscilloscope
pe
. A l a r
¾Class-22: Analog
Electrostatic r
D ric Kh
nalog Osc
a
Oscilloscope:
ope: Basic Construction,
onstruction Electrostatic Focusing,
deflection, Deflection Amplifier
ic deflect mplifier [1]
¾Class-23: Horizontal
izo
Conclusion [1,3]
c t Sweep G

I T
Generator, Displaying waveform, Lissajous figures,
erat , Displ

l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 5
Introduction to electronic instruments
y
t rin g
‰Why electronic instrument is required?
¾Detection of low-level signal i
a e
¾High input impedance
M ne r
i s gi u
‰Variants:

s h
¾Analog instruments: measurement
n
asurement done
g p
d e by a moving coil on a calibrated
ca scale

. A
¾Digital instruments: measured
E r
asured qquantity
l a
nt y is direc
directly displayed
isplayed in numerical value

r a a
D ric Kh
c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 6
 y
t rin g
i
a e
M ne r
i s g i u
Analogg Instrument
Instr
s h rumen
n t p
basic
basics
g
A E ity a
r
Dr.
. Electrica
a l
r. Ashis
Ashis
Electrical
Maity
a r
Engineering
Engineerin
D ricIIIITT Kharagpur
K
Kharagph
c t I T
le I
E
Comparator versus Op-amp
y
t rin g
VP
+
‰Properties:
i
a e
¾Infinite DC-gain, Ad(0)=∞

M ne r
VO ¾Infinite loop bandwidth,
ndwidth, fBBW=∞
¾Infinite input impedance,
im edanc Ri=∞ ∞
VN
-
i s gi
¾Zero output
u
impedance, Ro=0
put impe

s h
‰Ideal op
n
op-amp
amp does
p
d es not exist!
g
exist Then,
en, what is the significance?

. A
deal com
‰Ideal

l E
comparator
a
tor does not exist! Then, what is the significance?
r
r
‰The symbols of a comparator
compara and
a
nd an op-amp
a
amp are the
th same.

D ric Kh
‰Is there any fundamental
ndamen difference in
n operation?
operation
¾Op-amp operatess in

c t
i closed
sed loop whereas
configuration. Exception:
I
ion: Sch
T
Schmitt
ere the comparator
tt trigger
trigge
co operates in open-loop

le I
¾Their region of operations are different.
fferent. Op-amp operates in small signal domain

E
whereas thee comparat
comparator in large signal.
ig
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 8
Comparator
y
t rin g VO

i
VOOH ܸைு െ ܸ୓௅
VP
+ ‫ܣ‬௩ ‫ ݏ‬ൌ Ž‹

a e
VO
୼௏ುಿ ՜଴ ȟܸ௉ே

M ne r (VP-VN)
‫ܣ‬௩ ‫ ݏ‬ൌ∞ (ideal case)
VN

s gi
-

i u
VOL

‰Resolution: the minimum m

s h n g p
input difference the
. A l E ra VO
VOH

comparator can sense.

r a a
D ric Kh
‫ܣ‬௩ ‫ ݏ‬ൌ finite DC-gain
‰The finite DC-gain
gain of the
t (VP-VN)

t
∆V
∆VPN
comparator fixes the
th
c T
VOL
resolution (ΔVPN)of the
comparator
l e I I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 9
Operational amplifier (op-amp)
y
t rin g
i
VO
VP
+ VOH
VO
a e
M ne r
Linear region
Open-loop response
VN (VP-VN)

s gi
- ∆VPN

h i p u VOL

s
‰Amplifier operates in the linear
inear

E n a g
A
region.

l r
VOOH
‰Feedback enhances the
r .
h linear
ne
a a Linear region

D ric Kh
region Closed-loop response
(VP-VN)
‰Slope defines the DC-gain
he DC n of ∆VPN

t
R2
the amplifier
T
VOL

‰Concept of small-signal
c
gnal vers
e I
versus
I
R1
-

28-02-2025
E l
large-signal response
sponse
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur
vd
+
10
vo
 Operational amplifier: Differential gain versus common mod
mode gain
y
t rin g
i
ȟܸ
ܸை
‫ܣ‬ௗ Ͳ ൌ ൌ ݃௠భǡమ ‫ݎ‬୭ଶ ‫ݎ צ‬୭ସ

a e
Ad(s) M3 M4 ȟܸௗ
+ VG VO
VO

M ne r
vd V1 V2 ȟܸை ͳ ݃௠భమ
M1 M2 ‫ܣ‬஼ெ Ͳ ൌ ൌെ ൈ
ȟܸ஼ெ ͳ ൅ ʹ݃௠భǡమ ‫ݎ‬௢଺ ݃௠యǡర

s gi
vd

i u
-

p
IF

h
ACM(s)
VCM ߥ଴ ൌ ‫ܣ‬ௗ ‫ݒ‬ௗ ൅ ‫ܣ‬஼ெ ‫ݒ‬஼ெ

n
M6

A s
VCM

E a g
.
‰Two types of operation:: differential
l r
diff ntial and common-mode
r a
mmon m
a
D ric Kh
gh differential
‰Usually, a high differen al gain and low
w common
commo mode gain is desirable
‰Common modee rejection

c t
re ion ratio CMRRMRR

I T
e I
‫ܣ‬ௗ ‫ܣ‬ௗ

l
‫ ܴܴܯܥ‬ൌ ‫ܴ ܴܯܥ‬ቚ ൌ ʹͲ Ž‘‰
‫ܯܥܣ‬ ୢ஻ ‫ܣ‬஼ெ

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 11
Various non-idealities
y
t rin g
Different non-idealities in op-amp:
‰AC performance: i
a e
¾Finite loop gain
M ne r
¾Finite loop bandwidth
i s gi u
¾High input impedance
¾Low output impedance
s h n g p
¾Limited slew rate

. A l E r a
‰DC performance:
r a a
D ric Kh
¾Input bias current
rrent

t
¾Input offset current
rent
¾Input offset voltage

e c I I T
28-02-2025
E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 12
Non-idealities: Input bias current R2

y
t rin
• Assumption: Bias currents are equal, i.e., IB(+)=IB(-) g R1

• How much output offset is getting created?

ated? i
a e vd
-
vo

¾If vd=0, vo=+IB(-)R2

M ne r +

i s gi
¾Example: R2=1 MΩ, IB(-)= 500 nA,, vo= 50
500 mV
m
u
• How to compensate the output

s h
put offset duee to input
n
inpu bias
p
as current?

g
curren
R2

. A l E r a R2 I2

R1

r a a I1 R1

D ric Kh
vo vo
IB(-)
T yo
Try yourself!
urself!
vC
c t I T
RC=R1||R2
IB(+ )
RC vC

l e I Hint: R1 will carry current

Hint

E
Conceptual
al developmen
development
Practical implementation
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 13
Non-idealities: Input offset current
y
t rin g
• Assumption: Bias currents are NOT equal, i.e., IB(+)≠IB(-) and |IIOS|=IB((-))−IB(+(+)
i
a e
• How much output offset is getting created?
d?
¾vC=−IB(+)RC,
M ne r
s gi
¾I1=−vC/R1=IB(+)RC/R1

u
R2

i
I2
¾I1+I2=IB(-)
¾Try yourself!

s h n g p I1 R1
vo

a
vO=R2IOS
E
IB(-)
(-

. A l a r IB(++ )

r
D ric Kh a RC vC

c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 14
Non-idealities: Input offset voltage
y
t rin
• Input offset voltage can arise for different reasons:
asons: g
9Input pair mismatch i
a e
M ne r
9Output transistors mismatch
Op-amp
Op amp with
w input offset
offs voltage with any polarity
• How to quantify?
i s gi u
p
9Differential input voltage between
ween inverting
invert and
d non-in
non-inverting
ng terminal.
termin
9Voltage to be applied to make
s h
ke outpu
n
output zero.
ero.
g
A
• What is its implication at the ooutput?
.
pu ?
l E r a
a
R2

r a
R2

D ric Kh
R1 R1 Try yourself!

t
vo
VOS
vo Calculate the output voltage

e c I I T ܴଶ due to input offset of

l
vd ܸ୓ ൌ ͳ ൅ ܸ
ܴଵ ୓ୗ an inverting amplifier

28-02-2025
E
Non-inverting amplifierr and calc
calculation of output voltage due to input offset
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 15
Calculation of total output offset voltage
y
t rin
• Total offset voltage due to input bias current, g
t, input ooffsett current and
an input
offset voltage i
a e
M ne r
¾If compensating resistance RC is NOT used:
sed:

i s gi u
ோమ
ܸ୓୘ ൌ ͳ ൅ ܸ୓ୗ ൅ ܴଶ ‫ܫ‬஻

p
ோభ

s
9 Assumption: input offseth n g
et current IOS < input
put bias current IB

. A
9 Depending on the polarity

l E r a
ity of VOS, the associated
sociated te
term could
uld be positive
positiv or negative
¾If compensating resistance
es nc is used:
r
ed:
a a
ܸ୓୘ ൌ ͳ ൅
D ric Kh
ோమ
ܸ୓ୗୗ ൅ ܴଶ ‫ܫ‬ைௌ

t
ோభ

e c I I T
l
9 As IOS < IB, the
he use of RC reducess the offse
offset voltage.

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 16
Offset Voltage Compensation
• When offset compensation y
t rin g
i
• When no offset null
nu pinss are availab
available:
pin is available:
a e
M ne
gp
A
. a ra
a
External offset compensation network

r
D ric Kh
xternal offset compensation
External
in
n an inverting
inver
pensation network
amplifier
mplifier
net
in a non-inverting amplifier

t
Offset compensation

c I T
network in 741 op-amp

le I
9 R4<<R
R3

E
9 Example:
e: R4=100 Ω, R3=100 kΩ, V=15 V, then -15 mV ≤VOS ≤ +15 mV
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 17
Development of difference amplifier
y
t rin g
i
R2 tes the d
‰Evaluates difference
ence of the two signals
R1
a e ansistor
‰Transistor-level equival
equivalent: differential
M ne r
-
vd vo amplifier
+ ܴଶ

i s gi u
p
‫ܣ‬ௗ ൌ െ

h
ܴͳ
Inverting amplifier

s E n a g R2

A
R2

R1
R2

r . a l a r R1
R1
-

D ric Kh
- - vd vo
vo vo R1
R1 +

t
ܴଶ
‫ܣ‬ௗ ൌ ͳ ൅ + ܴଶ VCM

T
+

c
ܴଵ ‫ܣ‬ௗ ൌ

I
ܴଵ R2 ܴଶ

I
vd

e
R2 ‫ܣ‬ௗ ൌ

l
ܴଵ

E
Non-inverting
ing amplifier
amplifie Modified non-inverting amplifier Difference amplifier
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 18
Difference amplifier
R2
y
t rin g
R1
- ‰Criteria: i
‰Identify the feedback

a e
ack configuration
conf ation

vd
R1
vo
M ne ral mode:
¾Differential mode Inverting
rting and non-inverting
inv gains
+
i s gi
should
ould be same.
am
u
p
VCM

h
R2
m
¾Common mode: uld be zero.
CM-gain should ze

s‰Analysi
E n a g
‰Analysis in differentia
differential-mode
mode op
operation

. A l a r
r a
ோమ ோమ ோమ
‫ݒ‬௢ ൌ ‫ݒ‬௢ଵ ൅ ‫ݒ‬௢ଶ =െ ‫ݒ‬ ൅ ‫ݒ‬ ൌ ‫ݒ‬ௗଶ െ ‫ݒ‬ௗଵ

D ric Kh
ோభ ௗଵ ோభ ௗଶ ோభ

‫ݒ‬௢ ܴଶ

c t ‫ܣ‬ௗ ൌ

IT
‫ݒ‬ௗଶ െ ‫ݒ‬ௗௗଵଵ
ൌ
ܴଵ

le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 19
 Difference amplifier
y
t rin g
i
I1 I2 R2 ‰Analysis in common-mode
on-mod operation
eration
R1
a e
M ne r
- ͳ ܸ஼ெ ܴʹ
vo ‫ܫ‬ଵ ൌ
ܴଵ
ܸ஼ெ
ெെ
ܴଵ ൅ ܴଶ

s gi
R1
VCM
+

h i ͳ

p uܸ஼ெ ܴʹ

n
R2 ‫ܫ‬ଶ ൌ െ ܸ‫݋‬

s g
ܴଶ ܴଵ ൅ ܴଶ

. A l E r a
As ‫ܫ‬ଵ ൌ ‫ܫ‬ଶ ǡ ܸ‫ ݋‬ൌ Ͳ

‰Advantage: CM-gain=0,
gain=0 CMRR=∞R=∞
r a a
‰Input Impedance
ance Rin=2R1
D ric Kh
‰Limitations: Tradeoff
ff between
t
betwee Ad aand Rin.
c I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 20
Development of instrumentation amplifier
y
t r in g
‰Objective:
¾To increase input impedance i
a e
v2 +
¾To increase differential gain
M ne r - R2
‰Modification-1:
i s gi u R1

inverting terminals.
s h
¾Identify the inverting and non-

n g p R1
-
vo

A
¾First objective is satisfied.

.
ed.

l E ra +

a
¾Two buffer op-ampss dod notot provide
de
r a
R2

D ric Kh
any DC-gain -

t
v1 +

e c I I T
28-02-2025
E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 21
Development of instrumentation amplifier
y
t r in g
‰Objective:
¾To increase input impedance i
a e
v2 +

¾To increase differential gain

M ne r - R4 R2
‰Modification-2:
i s gi u R3
R1

p
-

h
¾The DC-gain is improved. vo

s
¾First stage amplifies the CM.

E n a g R1
+

A
R3

r
• High output CM

r . a l
atu
a
• Else, first/second stage saturates.
- R4
R2

D ric Kh v1 +

c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 22
Instrumentation amplifier
y
t rin g v2 +

i
‰Objective:

a e
- R4 R2
¾To increase input impedance

M ne r
¾To increase differential gain vo2 R1
-
‰Final modification:
s gi
vo

u
(v1-v2)/2R3 2R3
¾DC-Gain calculation:
௩ ି௩
h i p vo1
R1
+

n
‫ݒ‬଴ଵ ൌ భ మ ൈ ʹܴସ ൅ ‫ݒ‬ଵ െ ‫ݒ‬ଶ ൅ ‫ݒ‬௢ଶ
௩బభ ି௩೚మ
ଶோయ
ோ
ͳ൅ ర
A s E a g - R4
R2

r
ൌ

. l
௩భ ି௩మ ோయ

r a a
௩೚ ோర ோమ
ൌ ͳ൅ v1 +

D ric Kh
௩భ ି௩మ ோయ ோభ

t
• The DC-gain iss improved.
imp d.

c T
• Gain of first stage cann be adjusted
adjus by
changing R3 only.
¾CM-gain is zero.
ero.
l e I I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 23
Try Yourself: Tutorial Problems
y
t rin
‰For the non-inverting amplifier as shown in the g
he figure,
figure ܴଵ = 1 KΩ,
ܴ௙ = 10 KΩ. i
a e
M ne r
¾Calculate the maximum output offset voltage
age due to ܸ௜௢௦ and ‫ܫ‬஻ . Assume
A the
op-amp has ܸ௜௢௦ = 10 mV, ‫ܫ‬஻ = 300 nA and ‫ܫ‬௢௦ = 50 nA.

i s gi
¾Calculate the value of ܴ௖௢௠௣ neededed to re
u
reduce thee effect oof ‫ܫ‬஻ .

connected in the circuit.

s h n
¾Calculate the maximum outputt offset vo
voltage
p
ge if ܴ௖௢௠௣ as calculated
g
alculated in (b) is

. A
‰In an inverting amplifier ܴଵ = 100
l
1 KΩ, E r a
KΩ ܴ௙ = 10 MΩ and ܸ௜௢௦ = 6 mV
and ‫ܫ‬஻ = 500 nA.
r a a
¾Calculate maximum
D ric Kh
mum ou
output offset voltage
vo e caused by b input offset voltage Rf
ܸ௜௢௦ Ǥ

c t I
¾Calculate maximum output ooffset
T
et voltage caused by input bias current ‫ܫ‬஻ . v
R1

e I
i
vo

28-02-2025
E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 24
 y
t rin g
i
a e
Analog E Mctronic
og Electronic
Elec n e r
i s g i u
Instruments
nstru
s h uments
n g p
A E ity a
r
Dr.
. Electrica
a l
r. Ashis
Ashis
Electrical
Maity
a r
Engineering
Engineerin
D ricIIIITT Kharagpur
K
Kharagph
c t I T
le I
E
Basic DC voltmeter

ti y
‰Deflection of PMMC is proportional to the current
urrent
flowing through the moving coil.
a e
M ne
‰Coil/meter resistance (Rm) is quite small.
all.

the range of the voltmeter.

i s gi
‰Additional series/multiplier resistance
stance (R
Rs) increases
creases
u
s h
‰Effect of swamping resistance:
nce:
n g p
. A
¾The coil resistance varies
E a
es with temperature

l
te p ature
r
a
¾Error in low voltage measurement
sur where
whe Rs is comparable
omparable
with Rm.
¾The temperature r
D ric Kh
ure varia
copper wire coil.
il.
a
variation of Rs is much
mu lesser than the

c t
¾Rs is realized by manganin
T
ganin or constantan
I
nstan
‰Be careful about
e
ut the loading
l I
load effect

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 26
Multirange basic DC voltmeter
y
t rin g
i
a e
ns:
‰Limitations:
ot suitable for low-voltage
¾Not w-voltag measurements.

M ne r ¾Not suita
suitable forr voltage
impedance
voltag measurements in high-
mped nce circuitry.
circuitry

i s gi u
h
s En ag p
ternative ssolution:
‰Alternative
‰ ion: Electronic
Ele
¾Ampl thee low-voltage
¾Amplify
voltmeter
low-voltag signal

a l a r Of
¾Offers a high input
inp impedance

i c K h
t r
c I I T
28-02-2025
Ele Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 27
Emitter-follower voltmeter
y
t rin g
i
‫ܫ‬஼
ߚൌ ‫ܫ‬஼ ൎ ‫ܫ‬ா ൌ ߚ‫ܫ‬஻
‫ܫ‬஻
a e
ܴ௜௡ ൌ
ா
ൌ
ఉൈா ఉൈா
ൌ
M ne
s gi
ூಳ ூಶ ூ೘

‰Advantages:
h i
s
¾Input impedance has been increased
n
ncreased byy a

E
A
factor of β.

r .
¾Voltmeter loading is greatly
l
atly reduced.
a
ced.
a
D ric Kh
‰Limitations:
¾Always has VBEE dro
drop, NOT suitable
suitab for low
voltage measurement. nt.
c t I T
e
¾Voltage gain iss limited.

l I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 28
Improved Emitter-follower Voltmeter
‰How to eliminate VBE drop? y ing
‰When E=0, the base of Q2 is
e r
adjusted to make the voltage
n e
across the meter zero.
i g i
across the meter=E-VBE1-(0-V
ge
‰When E is applied, the voltage
sh
(0 VBE2)).
n g
‰No VBE drop across the meteA
meter.
. l E ra
r a a
D ric Kh
‰Limitations:
¾Input voltage iss referenced
refe ced to grou ground,
and may not be suitable
applications.
c tle for all

I T
¾Input impedance
l e
ance is finite.
finite
I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 29
FET-Input Voltmeter
‰Use of JFET to increase
the impedance.
‰Operation of JFET
‰When EG=0, VS=+Ve, R5
needs to be adjusted to
a +Ve voltage to keep
V=0.
. A
r
‰When EG=1 V, VS is also

D ric
increased by 1 V and
appears across the
meter.
he

c t
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 30
Difference Amplifier Voltmeter
y
t rin g
‰Input voltage must be amplified. i
‰Suitable for measuring low-input signals.

a e
M ne
‰When a positive voltage E is applied,, the
he

i
output differential voltage appears
s gi
rs across
acro
the meter.
s h n
E
‰The meter voltage V is directly
A
proportional to input voltage
.
tage E.
l
‰Zero adjustments
r
D ric Kh
ents required.
requi
¾Previous basee cont
a
control circuit
cuit at Q2 can be
used.

c t I T
I
¾Alternate method as given in
i Figure
igure (b)

l e
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 31
Op-amp Amplifier Voltmeter
‰No VBE drop like emitter follower.
‰Input Impedance of the op-amp is
high.
‰Low output impedance where the
meter is connected.
‰The DC-gain is improved.
¾ ࡭ࢂ ૙ ൌ ૚ ൅
ࡾ૛

sh
ൌ ૚૙૚

A
ࡾ૚

. a
‰0.1 μF capacitor across R2 improves
mprov

r
stability under strayy pick
pick-ups.

D ric
up
‰Terminals 1 & 5 and 10 kΩ pot are
used for offset cancellation.
cella .

ct
‰Two Schottky diodes used ed for
I
le I
protection for meterr and IC.
‰Rs is adjusted to get full scale
s
deflection.
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 32
Voltage-to-Current based Voltmeter
‰Meter current=V3/R1. g
‰As V3 is a function of the input
voltage to be measured, the
current through the PMMC
meter can be calibrated on a i s
voltage scale
s h
. A l
r
D ric a
c t I T
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 33
Series Ohmmeter

n g
i
‰Electronic voltmeter (Rin=∞) can be
also used as an ohmmeter.
‰Unknown resistor Rx is in series with
e r
range switch.

n e
s
‰If Rx=0, E=0, If Rx=∞, E=EB.
‰Requires two adjustments before
i g i
use.
ࡱ
s h n
E
‰ࡱ ൌ ࡮ ൈ ࡾࢄ (NOT linear) ar)

A
ࡾ૚ ାࡾࢄ

‰ࡾࢄ ൌ ૚
ࡾ ࡱ
ࡱ࡮ ିࡱ
r . a l
g
D ric K
‰Scale becomes progressive
progressively
cramped at both extremes.
xtrem

c t
‰Accuracy is more at 0.5FSD.
SD.

I T
e I
‰Need a regulated supply
upply to get EB.
‰EB=Range of the
28-02-2025
E l
he voltmete
voltmeter.
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 34
Shunt Ohmmeter
y
t rin
‰EB can be greater than the voltmeter range. g
‰When RX=∞, ࡱ ൌ ࡲࡿࡰ ൌ
ࡱ࡮ ࡾ૛
ࡾ૚ ାࡾ૛
i
a e ൌ ૚Ǥ ૞ ࢂ

M ne
‰If EB is a regulated voltage and R1 and R2
calibration at FSD.
i s gi
are precession resistors, no need of

‰When RX=0, E=0.

s h n
‰In between, ࡱ ൌ
. A
ࡱ࡮ ࡾ૛ ȁȁࡾࡾࢄ
ࡾ૚ ା ࡾ૛ ȁȁࡾࢄ
l E
r
D ric Kh
‰The existing design
sign wo a
‰Meter reading at 0.5FSD, RX=(R1||R2)=1 kkΩ
works well for 1 kΩ
range.

c t I T
‰To set 10 k Ω range,, R1 and R2 need to b
be
10X.
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 35
Linear Ohmmeter
‰Here, the scale is linear.
ࡾ૛ ࡾ૚
‰ࡱ૚ ൌ ࡱ࡮ െ ࡱ࡮ ൌ ࡱ࡮
ࡾ૚ ାࡾ૛ ࡾ૚ ାࡾ૛
M
s
ࡾ૚
‰ࡱࡱ ൌ
i
ࡱ࡮ െ ࢂ࡮ࡱ૚
ࡾ૚ ାࡾ૛

‰ࡱ࢞ ൌ
ࡱࡱ
ࡾ
ࡾࡱ ࢞
s h
A l E
‰Once EE/RE is fixed, thenn the Rx can be
.
measured in linear
r
ear scale.
scale

D ric K
‰For multirangee operation,
a
opera on, switching
switch
arrangement can be
b placed
t
laced at RE.
c I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 36
 Op-amp Halfwave Rectifier Voltmeter

ti y n g
‰PMMC meter action on AC
voltage: deflects both sides of zero
if f < 0.1 Hz. For f > 0.1 Hz, it shows
i
the average value.
‰C1 blocks the DC.
‰Limitation:
h i
¾Error due to diode drop.
A s
¾Silicon diode drop varies with
temperature.
r. a l
D ric K
¾Difficult to put a correction factor.
actor.
‰For half-wave sinusoidal
uso output:

c t
¾Average=0.5 X 0.637 X Peak
I T
amplitude
¾RMS=0.5 X Peak
le
eak amplitude
amplitu I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 37
Op-amp Halfwave Precession Rectifier Voltmeter

ti y n g
‰The diode is placed inside the
loop. No diode drop at the
output.
i
‰The resistances and input
capacitance create a delay.
‰To compensate this C2-C
sh
C3-C
C4
are added.
. A
‰Draw VX.
r
D ric
c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 38
Op-amp Halfwave Precession Rectifier Voltmeter with Amplification
mpli
y n g
i

D ric Kh
c t T
‰Signal amplification done by R2 and R3.
I
‰Av=(1+R2/R3)
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 39
AC Voltage-to-Current Based Voltmeter (Half-Wave)

ty n g
r i
u r
p

ct I T
le I
‰Average meter current ۷ ൌ
ࡱࡼ
ൈ
૙Ǥ૟૜ૠ
૟૜ૠ

E
ࡾ૜ ૛

28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 40

AC Voltage-to-Current Based Voltmeter (Full-Wave)
y g
ࡱࡼ
‰ࡵሺࢇ࢜ࢋ࢘ࢇࢍࢋሻ ൌ ૙Ǥ ૟૜ૠ
ࡾ૜
ࡱࡼ
‰ࡵሺࡾࡹࡿሻ ൌ ૙Ǥ ૠ૙ૠ
ࡾ૜

. A
D rr
c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 41
Laboratory type Electronic Multimeter
y g
it rin

r i c K
c t I T
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 42
Multimeter Probe: High-Voltage Probe
y
t rin g
ai

tr K
Typical
l e c
ical dividing factor is 1/1000
00 II T
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 43
Multimeter Probe: High-Current Probe (AC)
y g

. A
r
D ri K
c t I
‰AC current transformer can measure
T
easure A
AC current
urrent only
only.

le I
ens, a current
‰Transformer core opens, current-carrying condu
conductor is then placed inside and then core gets closed.

E
‰Conductor acts as a single turn primary.
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 44
Multimeter Probe: Hall-effect Probe
‰Similar appearance as a y g
transformer-type current probe.
‰Both DC and AC currents can be
measured.

h
‰When a flat current-carrying

As
conductor is exposed to a
perpendicular magnetic field,
eld, a

r. a
voltage is produced acrosss the
conductor which is perpendicular
perpend

D ric
both to the current
ent direc
direction and

t
magnetic field.

e c
‰V=KH∙I∙B where B=Flux
I T
ux densi
density,
I
28-02-2025
El
KH=Hall coefficient.
ent.

Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 45

Multimeter Probe: Radio-frequency Probes
‰RF voltage can not be measured directly y g
by the multimeter probe.

M
‰RF waveform is clamped and converted ed

Detector Probe. i s
into DC voltage equal to peak value:
lue: Peak
Peak

s h
‰At positive peak, C1 charged
n
arged to (VP− VF)
A
with the polarity shown.
. l E
‰At negative peak
VF) = − 2VP+VF. r
D ric Kh a
ak e=−VP −V
VC1= −V
VP − ((VP−

c t I T
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 46
Tutorial Problems
y
t rin g
i
‰Consider the difference amplifier circuit with
h R1= R3 = 2 kΩ
Ω and R2= R4 =200 kΩ.

a e
¾Find the value of the differential gain (Ad).

M ne r
¾Find the value of the differential input resistance
sistance (Rid).
¾If R3 has ±1% tolerance, and R1, R2, R4 haveve 0% tolerance,
ance, find
fin the wor
worst case common-

i s gi
mode gain (Acm) and hence the corresponding
rrespon
u value
lue of CM
CMRR. [Ans: 1100 V/V, 4 kΩ, -80

p
dB]

s h n g R2

. A l E r a
R1

r a a -

D ric Kh vd vo
R3

c t VCM
IT
+

le I R4

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 47
Tutorial Problems
y
t rin g
i
‰An emitter-follower voltmeter circuit as in figure

a e
R1= 12kΩ, R2 = R3= 2.7kΩ, R4 = R6 = 3.3 kΩ, R5= 500Ω
gure has the following components:
c
500Ω, and RS +Rm =10 kΩ. A
100 μA meter is used, the supply voltage
Determine IB1, IB2, I2, I3, and I4 when M ne r
age is ± 9V,
en E=0.
E=0 Also,
9 andnd the transistors
tr
Als calculate the range
have β=75.
rang of adjustment
for VB2. [Ans: I2, I3=3.07
i s gi u
3.07 mA, IB1, IB22=40.9 μA
μA, I4=2.53 mA
mA, VB2=±632 mV]
h n p
D r
e c
28-02-2025
El Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 48
Tutorial Problems
y
t rin g
i
‰The FET input voltmeter circuit in figure has the follo

a e
following
kΩ, R2 = R3 = 4.7 kΩ, R4 = 1.5 kΩ, R5= 5000 Ω, R6=3.3 kΩ,
g compone
components: R1= 6.8
Ω, RS+Rm = 20 kΩ. The

80, and the FET gate –source voltage M ne r

meter full–scale current is 50 μA, the supply vo
tage is
voltagee is ±10 V, the BJTs have β=
i VGGS =-3V.
3V. Determine
Deter IS, I2, I3, and I4 when
i s gi
E=0. Also, calculate the rangee of adjustment
adjust
u
t for VB2.

s h p
. A
D r
c t
le
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 49
Tutorial Problems
y
t rin g
‰The voltage-to-current converter based DC voltmeter
(FSD) deflection meter with meter coil resistance i
voltmete circuit

a e
cuit uses a 37.5 μA
sistance (Rm) of 900 ΩΩ. If R3 = 80 kΩ,

M ne r
determine the input voltage levels to give FSD and 0.5 FSD. [Ans: 1.5 V]

s gi u
g p
r ra
D
e c
28-02-2025
El Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 50
Tutorial Problems
y
t rin g
‰The precision half-wave rectifier AC electronic
deflection meter with a 460 Ω coil resistance.
ic voltmeter
voltm
ance. If Rs = 450 iuses a 500 μA

a e
450 Ω, calc
calculate the rms
voltage of the input sinusoidal requiredd to give FSD.
M ne r
D. [An[Ans: 1.01 V]

p u

D
28-02-2025
E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 51
Tutorial Problems
y
t rin g
500 Ω coil resistance. Determine a suitable i
‰The precision full-wave rectifier AC voltmeterr circuit usess a 100 μA meter with

a e
resistance for R3 to give FSD on the
ble resistanc
meter for a 500 mV (rms) input. [Ans:
Ans: 4.5 kΩ]
M ne r
i s
s h
. A
r
D ri
c t
le
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 52
 y
t rin g
i
a e
M ne r
i s g i u
Digital
al Electronic
Elect
s h ctronic
n p
Basic
Basics
g
A E ity a
r
Dr.
. Electrica
a l
r. Ashis
Ashis
Electrical
Maity
a r
Engineering
Engineerin
D ricIIIITT Kharagpur
K
Kharagph
c t I T
le I
E
Basic building blocks of digital instruments
y
t rin g
‰Combinational logic gates
‰Latches and flip-flops i
a e
‰BCD/Decade Counters M ne r
‰Registers
i s gi u
s h n
‰Analog-to-Digital converter (A/D or ADC)
g p
A
‰Digital-to-Analog converter
.
rter (D/
E r
(D/A or DAC)
l a
‰Digital displays
r a a
D ric Kh
c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 54
Storage elements: SR Latch
‰SR Latch with NOR gates
ti y rin
a e
M e

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 55
Storage elements: SR Latch
‰SR Latch with NAND gates
ti y rin
a e
M ne
s

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 56
Storage elements: SR Latch
y
t rin g
‰SR Latch with enable signal (En)
i
a e
M

tr K
‰How to eliminate
l e c
ate indeterminate
indeter te state?
state II T
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 57
 Storage elements: D Latch
‰D Latch (Transparent Latch)
ti y r
a e
M ne

ct
le I
‰En control as level-triggered
evel-trigge
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 58
Edge-triggered D flip-flop
y g
‰Master-slave D-FF
it rin

tri K
ec I I T
28-02-2025
El Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 59
Positive and negative edge-triggered D flip-flop
y
t rin g
i
a e
M ne
g i p u
E n a g
. A l a r
r
D ric Kh a
c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 60
Toggle or T flip flop
y n g
i

r. a a
D c h
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 61
Q4 Q3 Q2 Q1 Binary ripple counter: An example of module-16
du counter
0 0 0 0

y
t rin g
i
0 0 0 1 T Q T Q T Q T Q

a e
0 0 1 0

M ne r
0 0 1 1 Clock Qb Qb Qb Qb
0 1 0 0

s gi u
Q4

i
Q1 Q2 Q3
0 1 0 1
Clock
h
0 1 1 0
0
1
1
0
1
0
1
0

A
Q1 s
1
1
0
0
0
1
1
0
r. Q2
1 0 1 1
D Q3
1 1 0 0

c t I T
I
1 1 0 1

e
Q4
1
1
1
1
28-02-2025
1
1
0

E
1l ‰This also
so acts
a as a frequency divider
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 62
BCD/Decade counter: An example of module-10 counter
Previous State
y
t rin g
Next State O
Outp T-FF Inputs

Q4(t) Q3(t) Q2(t) Q1(t) Q4(t+1) i

a e
Q3(t+1) Q2(t+1) Q1(t+1)
uts
u
Y T4 T3 T2 T1

Æ
M ne r Æ Æ

s gi
0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 1 Æ
Æ
h i
0 0

pu 1 0 Æ
Æ
0 Æ
Æ
0 0 1 1

n
0 0 1 0 0 0 1 1 0 0 0 0 1
0 0 1 1

A
Æ
s 0

E a g
1 0 0 Æ 0 Æ 0 1 1 1
0
0
1
1
0
0
0
1

r.
Æ
Æ

a
0
0
l a r 1
1
0
1
1
0
Æ
Æ
0
0
Æ
Æ
0
0
0
0
0
1
1
1

D ric Kh
0 1 1 0 Æ 0 1 1 1 Æ 0 Æ 0 0 0 1

t
0 1 1 1 Æ 1 0 0 0 Æ 0 Æ 1 1 1 1

c T
1 0 0 0 Æ 1 0 0 1 Æ 0 Æ 0 0 0 1
1 0 0 1

le
Æ
I I0 0 0 0 Æ 1 Æ 1 0 0 1

E
‰ࢀ૚ ൌ ૚, ࢀ૛ ൌ ࡽ૝ ࡽ૚ , ࢀ૜ ൌ ࡽ૛ ࡽ૚ , ࢀ૝ ൌ ࡽ૝ ࡽ૚ ൅ ࡽ૜ ࡽ૛ ࡽ૚ , ࢅ ൌ ࡽ૝ ࡽ૚
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 63
BCD/Decade counter: An example of module-10 counter
y
t rin g
i
Q1 Q4 Q3

a e
Q1 Q4
M ne r Q1 Q2

s gi
Y

h i pu
s E n a g
A
T Q T Q T Q T Q

r . a l a r
Clock
D ric Kh
Qb Qb Qb Qb

c t IT Q4

I
Q3

e
Q1 Q2 Q4

28-02-2025
E l
‰ࢀ૚ ൌ ૚, ࢀ૛ ൌ ࡽ૝ ࡽ૚ , ࢀ૜ ൌ ࡽ૛ ࡽ૚ , ࢀ૝ ൌ ࡽ૝ ࡽ૚ ൅ ࡽ૜ ࡽ૛ ࡽ૚ , ࢅ ൌ ࡽ૝ ࡽ૚
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 64
Scale-of-1000 counter LSB

y
t rin g
i
‰Resolution of digital meter BCD/ BCD/
D/ BCD/ CLK

a e
depends on the number of Decade
ade Decade
ade Decade
Counter Counter Counter
digits used in display.
M ne r
‰Counts 0-999.
is gi u
d12 d9 d8 d5 d4 d1
‰If 0-999 counts represent 1
V full-scale, then each
s h n gp BCD-to- BCD-to- BCD-to-

count represents 1 mV.

. A l E ra 7Segment
7Segmen
decoder
deco
7Segment
7Segme
decoder
dec
7Segment
decoder

r a a
D ric Kh
g3 a3 g2 a2 g1 a1

c t IT
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 65
 ૚
Scale-of-2000 counter:૜ Digit Display
૛

y
t rin g
i
‰Resolution of digital meter MSB LSB
depends on the number of
a e BCD/ BCD
BCD/ BCD/ CLK
digits used in display.
M ne r
Flip-Flop Decade
De Decade
D Decade

s gi
‰3-digit display 0-1 V with Counter
unter Counter
nter Counter
smallest increment of 1
h i pu
d13 d12 d9 d8 d5 d4 d1
mV.
s E n a g
A
BCD-to- BC
BCD-to- BCD-to-
‰Additional one extra digit

r .
(0 or 1) can give a range
it
ange upp
a l a r gmen
7Segment
decoder
7Segment
decoder
7Segment
decoder

D ric Kh
to 1999. This process
rocess is
called “over-ranging”.
ging g3 a3 g2 a2 g1 a1

c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 66
 Scale-of-2000 counter
y
t rin g
i
d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 Input
Inpu

a e
pulses

0 0 0 0 0 0 0 0 0 0 0 0 0 0

M ne r
s gi
0 0 0 0 0 0 0 0 0 1 0 0 1 9

i u
MSB LSB

BCD/ BCD/ BCD/

h p
Flip-Flop Decade Decade Decade
Counter Counter Counter
0 0 0 0 0 0 0 0 1 0 0 0 0 10

s n g
d13 d12 d 9 d8 d5 d4 d1

BCD-to- BCD-to- BCD-to-

E a
7Segment 7Segment 7Segment

A
decoder decoder decoder
0 0 0 0 0 1 0 0 1 1 0 0 1 99

l r
g3 a3 g2 a2 g1 a1

0 0 0 0 1

r .
0 0

a a 0 0 0 0 0 0 100

0 1 0 0
D ric Kh
1 1 0 0 1 1 0 0 1 999

1 0 0 0 0

c
0
t 0

I T 0 0 0 0 0 0 1000

1 1 0 0 1
l e 1 0
I 0 1 1 0 0 1 1999

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 67
LED Display
y ing
e r
n e
i s gi
s h n
A lE
c a
tri
ec I
28-02-2025
El Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 68
LED display
‰Passing current through
appropriate segments
ty n g
displays 0-9.
‰Typical voltage drop
across LEDs ~0.8 to 1.2 V.
‰Current controls
brightness of the LEDs.
‰Typical current ~10 mA to
20 mA.
A s
‰Series resistors are
r.
usually put to fix the
he

D ri
current.
‰Advantages: Longg life,
life
operation.
c t
ruggedness, low-voltagee

I T
‰Disadvantage: High
le
g I
power consumption
28-02-2025
E
mption
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 69
Basic concept of converting analog signal to digital signal
al
y
t r in g
Analog i
a e
C
Continuous
in time and

M ne r
signal
amplitude

i s gi u
s h n g p
. A l E ra t
Discrete
r a a
signal
D ric Kh Discrete in

c t I T
time and
continuous

l e I amplitude
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur t 70
Basic concept of converting analog signal to digital signal
al
y
t r in g
Digital
signal i
a e
Four
ur quantization
quantiz levels

M ne r 11

i s gi u 10

s h n g p 01

. A l E ra t 00

a
Sixteen quantization levels
Six
Digital
signal r
D ric Kh a 1111

c t I T
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur
t 0000 71
 Generalized block diagram of an analog-to-digital converter
ter
y
t rin g
Auto-ranging
i
a e An
Analog-to-
(Amplifier or
M ne r
Sample
le and
Digital
git
attenuator)
i s gi Hold
Ho d
u Converter
onver

Analog
sh
Analog
nalog
n gp Di ete
Discrete Digital
Signal
. A gnal
Signal
l E ra Signal Signal

r a a
‰Auto-ranging brings D ric Kh
gs th
the input
nput analo
analog si
signal
nal in th
the dynamic range of the converter.
‰Sample and Hold maintains
c t I T
ntains the input
nput ana
analog signal constant during conversion.
‰Analog-to-digital
l e
al converter I
convert finds the subrange that corresponds to the discrete signal.
he su
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 72
 Sample and Hold (S/H) circuit
y
t rin g
i
S1 S1 S1
V o
a e Vo Vo
Vi C
M ne r
Vi C Vi C

i s gi u
Ideal S/H
s h Switch

n g p
witch implementation:
imp entation
Option-1
ption-1
Switch implementation:
Swi
Option-2
S1
. A l E ra S1

a
Buffer

r a
S1

D ric Kh
Vsampled
Vo Vo Vi

t
C
Vi Vi

c T
C C
S1

l e I I
E
Practical switch
itch implementation
implem Practical implementation of the sample-and-hold
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 73
 Digital Representation of Analog Quantity
‰Least Significant Bit LSB= 1mV
ti y
‰Examples:
a e
¾94.1 mV ≈ 94 mV
M ne
¾94.9 mV ≈ 94 mV
i s gi
h
¾95.1 mV ≈ 95 mV

s
‰Max. quantization error/noise=LSB
noise=LSB
E n a g
. A l
‰Increasing more number of discrete
r
dis te levels
l vels
a
error. r
D ric Kh a
reduces the valuee of LSB and hence qu
quantization
ntization

c t
‰Resolution: Smallest analog ch
change
I T
nge that
at is
i

I
detected by the ADC.
DC.
le
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 74
 Static characteristic of 3-bit ADC

M
i s
h
l E
c a
t r i K
c I I T
‰ࡸࡿ࡮ ൌ
ࡲ࢛࢒࢒ ࡿࢉࢇ࢒ࢋ ࡾࢇ࢔ࢍࢋ

28-02-2025
૛ࡺ
࢔ࢍࢋ

E le
ൌ
ࢂࡾࡱࡲ
૛ࡺ
, Where N=no.
no of bits
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 75
Linear ramp ADC
VS
y
t r in g
Analog
input VIN Vin* i
a e
M ne r
S/H +
V1 Clk Clock
ck
Saw-tooth
i s gi u Generator
enerator
Ramp
Generator
VR

s h n
-

g p
. A l E ra
r a a Clk_E
k_E
Counter

D ric Kh
VS Clr

c t I T
l e I d4 d3 d2 d1
Digital codes equivalent to analog

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur
input
76
Linear ramp ADC VS

y g
Analog

t rin
input VIN Vin*

i
S/H +
V1 Clk Clock

a e Saw-too
Saw-tooth Generator
VR -
Ramp
Ram

M ne r
Generator
Ge

i u
Clk_E
Counter

g
VS Clr

n g p
E ra
d4 d3 d2 d1
Digital codes equivalent to analog

‰ ck period=
‰Clock period=T input

h a
‰Ramp rate=∆V
r R/∆t

K ‰Counter reading= n (equ. to d4d3d2d1)

‰Co
‰Input voltage Vin*=
∆VR
ൈ࢔ൈࢀ
∆t

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 77
Digital ramp ADC
y
t rin g
i
VS

a e
Analog
input VIN
M ne r
Vin*
S/H +

i s gi u
V1 Clk Clock
ock

p
Generator
Generato
VR

sh n
-
g
. A l E ra
r a a
D ric Kh
Clk_E
Counter
VS Clr

c t I T
d4 d3 d2 d1

l e I Digital-to-Analog converter
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 78
 Digital ramp ADC
VS
Analog
input VIN Vin*
S/H +
V1 Clk Clock

s
Generator

i
VR -

s
Clk_E
h Counter
Coun
u

E
VS

A
Clrr

. l
d4 d3 d2 d1

r
D ric aDigital-to-Analog
alog conve
converter

c t I T
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 79
Digital-to-analog converter

ty n g

l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 80
Digital-to-analog converter

‫ܫ‬ൌ
ܸ௥௘௙ I I/2 I/4
tyI/8
n g
ܴ
a
I/2 I/4 M
II/8
/8

g
D ric
ܸ௥௘௙ ܴி ݀ଷ ݀ଶ ݀ଵ

t
ܸை ൌ െ ൅ ൅
ܴ ʹ Ͷ ͺ

l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 81
Digital-to-analog converter

ai

28-02-2025
E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 82
Tutorial Problems
y
t rin g
i
‰A 100 mV level is to be converted into an 8-bit
a e
resolution of the conversion, and analog
bit digital
digita code.
ode. Calculate
og levels represented
r
Calcula the
sented bby the MSB and

M ne r
LSB, and determine the analog level represen
represented byy 11111
11111110.. [Ans:
[ 50 mV,
390.625 μV, 99.218 mV]
i s gi u
h n
ent LED display
‰A 4.5-digit seven-segment
s g p
d play draws a maximum supply current of
A
450 mA. Calculate the current
. l E
urren taken
r a
each segment.
ken by ea [Ans: 15 mA]

r a a
D ric Kh
‰A frequency-divider
ivide circuit
rcuit consists
cons of a 2 MHz
M oscillator, a divide-by-16
counter. Determine the
t T
he time pperiod
c I
riod oof the output from the final stage of the
counter.
l e I [Ans: 8 μs]

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 83
Tutorial Problems
y
‰A ramp-type ADC, as in the figure shown in left, has a 1.5
t rin g
1. MHz clock frequ
frequency and
of clock pulses counted into the register when i
a ramp voltage which rises linearly from 0 to 2 V in 1.333 ms. Determine tthe number

a e
hen the input vvoltage
oltage is 1.2
1 V. [Ans: 1199]
‰A ramp ADC with a 2 MHz clock generator
representing a 1 V input. Calculate the max.M ne r
or is to have
m x. peak
ha 100000 clock pulses
pe of the ramp
ram voltage
tage if t2 = 10% of
t1.
i s gi u [Ans: 1.1 V]
Analog
VS

s h n g p
A E a
input VIN Vin*

r
S/H +

. l
V1 Clk
C Clock
Cloc

r a a
Saw-tooth Generato
Generator

D ric Kh
VR -
Ramp
Generator

t
Clk_E
lk_E
Counter
Cou

c T
VS Clr

le I I d4 d3 d2 d1

E
Digital codess equivalent
e to analog
input
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 84
Tutorial Problems
y
t rin g
‰A 5-bit DAC is shown in the figure. If Vref=10 V, R=5 kkΩ, calculate
alculate the
th analog
output voltage when the input is (a) 00001,
mV, -5 V, -9.6875 V]
01, (b) 10000 i
a e
10000, and
nd (c) 11111
1 [Ans:-312.5

M e

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 85
 y
t rin g
i
a e
M ne r
i s i
onicngInstruments u
Digital Electronic
Electro
s h Insstrume
g p
A E ity a
r
Dr.
. Electrica
a l
r. Ashis
Ashis
Electrical
Maity
a r
Engineering
Engineerin
D ricIIIITT Kharagpur
K
Kharagph
c t I T
le I
E
Topics to be covered
y
t rin g
‰Digital Voltmeter
i
a e
¾Single-slope ramp generator type digital voltmeter
ltmeter

M ne r
¾Dual-slope integrator type digital voltmeter
ter
‰Digital Ohmmeter
i s gi u
‰Digital AC Voltmeter
s h n g p
‰Digital Multimeter

. A l E r a
a
Me
‰Digital Frequency Meter
r
D ric Kh a
c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 87
Single-slope ramp generator type digital voltmeter
y
t rin g
VS
i
a e
Analog-to-Digital
og-to-Digit Converter
nverter

M ne r
Analog Vin*
S/H +
input VIN

i s gi u
V1 Clk Clockk

p
enerator
Generator

h
Saw-tooth
VR

n g
-

s
Ramp

E a
Generator

. A l a r
r a
Clk_E
_E

D ric Kh
Decade Counter
VS Clr

t
d13-d1

c T
B to-7
BCD-to-7 EN V1

le I I gment
Segment
oder
Decoder
Latch

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 88
Single-slope ramp generator type digital voltmeter
y
t rin g VS Analog-to-Digital Converter
Analog-to

i
a e
Analog
input VIN
S/H
Vin*
+
V1 Clk Clock

*
M ne r
Saw-tooth Generator
VR -
Ramp

s gi
Generator
nerator

p u Clk_E
Decade Counter

n
VS

g
Clr

E a
d13-d1
BCD-t 7
BCD-to-7 EN V1

l r
Segm
Segment Latch

a
Decoder

c a h
t r i K
‰Clock period=T
‰Ramp rate=∆VR/∆t

e c T ‰Meter reading=n

28-02-2025
E l ‰Input voltage=
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur
∆VR
∆t
ൈ࢔ൈࢀ
89
 Issues of single-slope ramp generator type digital voltmeter
ter
∆VR y
t rin g
‰Input voltage=
∆t
‰Sources of errors:
ൈ࢔ൈࢀ
i
a e
M ne r
¾Difficult to maintain a precise ramp-rate
ate (∆V
∆VR/∆
/∆t)
¾Clock period (T) can drifts.
i s gi u
‰This type of digital voltmeters
s h n g p
ers are nnott very accurate.
accu

. A l E ra Vreff

a
1:1
VR r
D ric Kh a VO Po ve
Positive
0
VR

• Slope=Ib/C

t
Ib C Edg
Edge • Ib can vary ~10%-20%
VO

c T
• C can vary ~10%-20%

I
Detector
Detect

I
Vref

l e VG VG
28-02-2025
E
A saw-tooth
aw-tooth ramp
ra generator circuit
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 90
Dual-slope integrator type digital voltmeter

ti y ri ܶ௥௘௙ ൌ ܰ௥௘௙ ൈ ܶ n g ݂஼௟௞ ൌ

ͳ

a e
ܶ

M ne r
C VC Fre
Frequencycy Clock
der
divider generator
s gi
Vin
u
VC
R

h i
+VCC

p Clk

n
VO
− Vref
A s E ag VZCD VC

r. a l
- CC
-V
a r
D ric Kh
Integratorr
Integra Zero
ero Cross
Detector (Z
(ZCD)

c t I T
BCD 7
BCD-to-7 EN

le I
SSegmentt Latch
Decade
Counter
28-02-2025
E Decoder
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 91
Function of the integrator
C
y
t r in g
i
20log|VO/V
Vin |

a e
+VCC (dB) -20 dB/decade
ecade
R

M ne r VO

Vin
i s gi u
ω

h p
-VCCC 1/RC
/RC

‰Frequency domain response:

nse:
s E n a g
ࢂࡻ
ൌെ
૚

ࢂ࢏࢔
. A l ࢊࢂࡻ

a r
ࢂ࢏࢏࢔ ࢙ࡾ࡯
૚ ࢚

r a
‰Time response: ൌ െ࡯ ֜ ࢂࡻ ࢚ ൌ െ ‫׬‬૙ ࢂ࢏࢔ ࢚ ࢊ࢚ ൅ ࢂࡻ ሺ૙ሻ

D ric Kh
ࡾ ࢊ࢚ ࡾ࡯
Vin 0 t

0
c t I T t
Vin

e I
t

l
0 VO
Vin /RC

E
VO
-Vin /RC 0 t
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 92
 Dual-slope integrator type digital voltmeter
y ing
ͳ
ܶ௥௘௙ ൌ ܰ௥௘௙ ൈ ܶ ݂஼௟௞ ൌ
ܶ
Clk
r
C VC Frequency Clock
divider generator

e
Vin VC
R +VCC
Clk

e
VO
− Vref VZCD VC
=Nref.T

s gi n
-VCC

i
Integrator Zero Cross
Detector (ZCD)
VC
h
BCD-to-7 EN

n
Decade

s
Segment Latch
Counter
Decoder
=N.T

Vl E
ࢂ ࢚ ࢂ࢘ࢋࢌ ࢚૛

A
‰ࢂࡻ ൌ ࢏࢔ ૚ ൌ

. a
ࡾȉ࡯ ࡾȉ࡯

r
ࢂ ࢂ
‰࢚૛ ൌ ࢚૚ ࢏࢔ ; ࡺ ൌ ࡺ࢘ࢋࢌ ࢏࢔ O

D ricV
ࢂ࢘ࢋࢌ ࢂ࢘ࢋࢌ
‰Results won’t bee erron
erroneous /RC Vref/RC
due to variation of ramp
ra rate.
ct I T ZCD

I
‰Results still may be affected by
clock drifting.
le
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 93
Range Changing
y
t rin
‰For the range selection manually, when inputtg
i
a e
voltage is out of range, DVM display is usually
flash ON and OFF continuously.
sually

M ne
ranging circuits.
i s gi
‰Now-a-days, many DVMs have automatic
automa ic

‰Accuracy specifications:
s h n
A E
¾Example: ±(0.5% of the reading + 1d

. a l r
1d)

r
¾To read 1.8 V, Error=
r= ±(0.5%
a
5% of 1.88 + 1 m
mV)=±0.01
) 1V

D ric Kh
¾% Error= ±0.56%
56% of the reading
ding

ct I T
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 94
Digital Ohmmeter and Digital AC Voltmeter
y
t rin g
i
a e
A

M ne r
Analog Ohmmeter Dig
Digital

i s gi
(Series/Shunt/Linear et
u
Ohmmeter)
ar Ohmm Voltmeter
V eter

sh n gp B

. A l E r a A

r a a
D ric Kh
Analog
A g AC Voltm
Voltmeter
te Digital

t
(Precession
rece Half-wave/Full-wave
Half-
f wave/F wa e Rectifier
Rectifie ) Voltmeter

e c I I T B

28-02-2025
El Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 95
Basic Hand-held Digital Multimeter

ty n g

28-02-2025
E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 96
 Frequency Meter System
y
t rin g
i
a e
VINXX

M ne
s gi
VSQR

i
QR

h
Wave VINX VIN
VQ VSQR Ampli
Amplifier/
VBAS

n
T Q Shaping

s
Attenuator
At BASE
Time-base T-FF Circuit
uit Sine
VBASE

E a
Q Triangula
Triangular

A
VQ

r
Saw-tooth
Saw-

l
Square
S

. a
Rectangular
VQ

r a
Clk_E
Decade Counter
Dec
De ter
e

BCD-to-7
D ric Kh VQ
dn-d
d1
VQ

t
EN
Segment Latch
h

c I T
Decoder

l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 97
Range changing

ty n g
1999 counts in 1 s => 1999 Hz =1.999 kHz

1999 counts in 100 ms => 19990 Hz =19.99

99 kHz

28-02-2025
E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 98
 Accuracy considerations in Frequency Meters t1
‰When time base range is fixed and input
y
t r in g Time base
as

i
signal
frequency is varying.
¾Case 1:
a e Frequency to

M ne r
be mea
measured
• ࢚૚ ൌ ࢔૚ ࢀ૚ , where n1 is an integer.
• Error is zero T1 C
Case 1

i s gi
¾Case 2: Last clock edge just falls into the time
u
t1

h p
base. Time ba
base

s n
• ࢚૚ ് ࢔૛ ࢀ૛ , where n2 is an integer.
er.

g
sign
signal

E a
• Max. error=+ 1 count or LSDD

. A l a r
¾Case 3: First clock edge justt missed thee time
ti e
Frequencyy to
be measured
easure

a
base.
• ࢚૚ ് ࢔૜ ࢀ૜ , where
r
D ric Kh
here n3 is an integer.
• Max. error= −11 count or LSD
T2 Case 2
t1

t
േ૚
‰Ψࡱ࢘࢘࢕࢘ ൌ ൈ ૚૙૙
T
Time base

c I
signal
࢔
‰For lower frequency,
ncy, %erro
e
%error is more.
l
ore.
I Frequency to

E
be measured

28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur T3 Case 3 99

 Accuracy considerations in Frequency Meters
‰When time base error is present
y
t rin g Time base

i
error

a e
and input frequency is fixed. Time base
signal
¾Case 1: When measuring a low
frequency
M ne r Low frequency Counts error

is gi u
to be measured
easu ±1
• Max. error= ± 1 count or LSD

h p Case
se 1
േ૚
• ࡹࢇ࢞Ǥ Ψࡱ࢘࢘࢕࢘ ൌ ൈ ૚૙૙ T1

s n g
࢔૚ Time base
¾Case 2: When measuring a high
E a
error

frequency
A l r
Time base
ase

.
sig
signal

r a
• Max. error= ± x count oor LSD
D
a
D ric Kh
േ࢞
• ࡹࢇ࢞ Ψࡱ࢘࢘࢕࢘
࢘ൌ ൈ ૚૙૙
૚૙ High freq
frequency Counts error
࢔૛ to
o be measured
m ±x
c
• Although max. error countss is more,

high also.
c t
% error may not be that high
gh as n2 is

I T
T2 Case 2

l e I
Total Error= േ(1 LSD++ Time base error)

E
Example: േ(1 LSD++ 1X10-6) meaning
m 1 count
n + 1 count error in 106 counts.
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 100
Numerical example
y
t rin g
1X10-5) is employed to measure frequencies i
‰A digital frequency meter with 8½-digit display

a e
ay and aan accuracy
cies of 100 H
curacy of ±(1
± LSD+
Hz,, 100 kHz and 100 MHz.
Calculate the % error in each case.
M ne r
s gi
¾At f=100 Hz, Count=100,

h i
• Error= ±(1 count + 100 X 1 X 10-5 count)≈±1
u
ount)≈±1 ccount,

p
n
• % Error= ± 1%
¾At f=100 kHz, Count=1000 k,

A s E a g
r .
• % Error= ± 2 X 10-3 %
a l
• Error= ±(1 count + 100 k X 1 X 10

a r
1 -5 count)=±2
unt ±2 cou
count,

D ric Kh
¾At f=100 MHz,, Count=100
Count=10 M,
• Error= ±(1 count
unt + 100 M X 1 X 10-5 ccount)≈±1001
≈±1001 cou
count,

c t
• % Error= ± 1 X 10-3 %

I T
e
‰Conclusion: At low-frequency
I
low-frequ y measurement,
l
measu the % error is more.

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 101
 Reciprocal Counting: Frequency Measurement
y
t rin g VQ VSQR Wave VINX Amplifier/
VIN

i
QR
T Q Shaping
Time-base T-FF Attenuator
Circuit
C

a e
VBASE Sine
Q Triangular
VQ Saw-tooth

M ne r
Square
Rectangular
Clk_E
Decade
De Counter

i s gi u
h p
dn-d1
BCD-to-7 EN VQ

s n g
Segment Latch

E a
Decoder
Decode

. A l a r VQ VBASE

r a
T Q Time-base
ase
T-FF

D ric Kh
VIN VINX Wave VSSQR
Amplifier/ Q
aping
Shaping VQ
Attenuator
Sine Circuit
cuit

t
Triangular
Saw-tooth Clk_E
Clk_

c T
Square Decade Counter

I
Rectangular

l e I BCD-to-7 EN VQ
dn-d1

E
Segment Latch
La
Decoder
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 102
Reciprocal Counting: Frequency Measurement

ti y
VINX

a e
VQ VBASE
T Q Time-basee
Wave T-FF
VIN Amplifier/ VINX VSQR Q

M ne
Shaping VQ
Attenuator
Sine Circuit
Triangular
VSQ

s gi
Saw-tooth Clk_E SQR

i
Square D
Decade unter
e
Counter
Rectangular

s h n
BCD-to-7
Segment

gp Latch
Latc
EN VQ
dn-d1

VQ

A E a
coder
Decoder

‰ࢀ ൌ ࢔ࢀ࡮࡭ࡿࡱ
r . a l a r VQ

D ric Kh
ࢌ࡮࡭ࡿࡱ
‰ࢌ ൌ VBASE

t
࢔

e c I I T
28-02-2025
E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 103
 Reciprocal Counting: Pulse-Width Measurement
y
t rin g
i
VQ VBASE
Time-base
T
VIN Amplifier/ VINX Wave
a eVSQR
Attenuator
Shaping
Circuit M ne r
s gi u
Sine
Triangular
Saw-tooth

h i p
Clk_E
_E

n
Decade Counter

s g
Square
Rectangular

. A l E ra dn-d1

r a a B
BCD-to-7 EN VSQR

D ric Kh
Segment
gment Latch
Decoder

c t IT
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 104
Uses of reciprocal digital frequency meter

ty n g
r i
r

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 105
Waveform shaping in the Frequency Meter
y
t rin g
Sine
i
a e Wave

M ne r
Input Shapin
Shaping Outp
Output

s gi
C ui
Circuit
u
Rec
Rectangular/
Sawtooth

h i p
Square
Triangular
s E n a g
. A l a r
r
D ric Kh a
c t IT
Vin
vo

l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 106
Waveform shaping in the Frequency Meter

ti y n g
i

l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 107
Analog versus Digital Instruments
Analog Instruments
y
t rin g Digital Instruments
ments
Reading the results i
a e
Using deflecting pointer on a calibrated
alibrated Resul
Results are directly displayed, no human

M ne r
scale, human error involved.
d. approximation
oximation is involved.

s gi
Accuracy ±0.1% accuracy (typical),
pical), less
les ac
accuratee ±0.001% accuracy
cy (typ
(typical), more accurate

h i p u
Resolution
s E n
One part in several

a g
everal hundred,
hun d, low O part
One art in several
seve thousands, high

A
resolution
on resolution
solution

Power consumption
r.Always
a l
lwa static
a
tat power r
er consumption
consu Ver
Very low power consumption due to

D ric Kh
dynamic/switching loss.
d

t
Measuring negative value P
Pointerr deflects to the left
le Directly gives the negative value
Overloading

e cMay
IT
ay damage thee instrumen

I
instruments Automatic range selection
Ruggedness

28-02-2025
El Poor Good

Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 110

Tutorial Problem
y
t rin g
i
‰Determine a suitable ramp generator frequencyency for th
the DVM
VM in figure
figur to get a
period=0.25 of the counting period. a e
uency is 1 MH
count of 1999 if the clock generator frequency MHz. Assum
Assume no-counting
[Ans: 400 Hz]
‰Recalculate the highest measured vo M ne r
voltage
age (in a voltage range
ge oof 2 V) for the
i s gi
DVM if the clock frequency driftss by −5%.
−5
u [A
[Ans: 1.900 V]
VS

sh n g p
Analog-to-Digital
Analog to- Converter
onverter

Analog

. A
Vin*

l E r a
a
S/H +

a
input VIN

r
V1 Clk Clock

D ric Kh
Saw-tooth G r
Generator
VR -
Ramp
Generator

c t I T
Clk_E
l
Decadee Counter
C

I
VS Clr

le BCD-to
BCD-to-7 EN V1
d13-d1

E
Se
Segment Latch
Decoder
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 111
 Tutorial Problem
y
t rin g
‰A ramp-generator-type DVM has a 200 kHz clock
i
lock and a 3-digit

a e
digit display.
Determine suitable time durations for t1 and t2 when thee maximum
displa
maxim input is 1 V.
Assume t2=0.25 t1.
M ne r
[Ans:
Ans: 4.99
4.995 ms, 1.25 ms]
‰The DVM in the figure has a rampp generator
i s gi
gene at with a 3 V peak ak value
valu and a 333 Hz
u
frequency. Calculate the clockk generator
when Vin =2.5 V.
generato frequency

s h n g p
quency for the meter
mete to indicate 2.50
[Ans: 100 kHz]

. A l E r a
a
VS Analog-to-Digital
gital Conv
Converter

Analog
input VIN
S/H

Saw-tooth
Vin*
+
r
D ric Kh
V1 a Clk Clock
Generator

t
VR -
Ramp

T
Generator

e c
Clk_E
_E

I I
l
Decade Counter
e
VS Clr

E
d13-d
d1
BCD-to-7
D-to-7 EN V1
ent
Segment Latch
28-02-2025 Decoder Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 112
 Tutorial Problem
y
t rin g
i
‰The dual-slope-integrator DVM in the figure has a 20020 kHzz clock frequency

a e
a 45 Hz integrator control waveform (VC).. Calculate the
freq and
the number of clock pulses

[Ans:
ns: 2222,
2222, 5 ms]
ms M ne r
that occur during t1, and determine a suitable ttime duration for t2 for a 1 V
analog input.
i s gi u Clk

Vin VC
C VC

sh n
Frequency
divider

g p Clock
generator
erator =Nref.TT

E a
+VCC

A
R

r
Clk

l
VO VC

. a
− Vref VZCD VC

r a
=N.T

D ric Kh
-VCC
Integrator Zero Cross
Detector (ZCD)
De D) VO
BCD-to-7
Segment

c t IT
Latch
EN
Decade
ade /RC Vref/RC

e I
Counter
Counte
VZCD

l
Decoder

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 113
Tutorial Problem
y
t rin g
i
‰Calculate the maximum measurement error for a dig

a e
accuracy of ±(0.1% of reading +1 d), when
digital voltmeter w
en indicating 1.490V.
.490V. [A
with an
[Ans: ±2.49 mV,
±0.17%]
M ne r
‰Determine the possible maximum
i s gi
m and minimum
min um indicated
u
indica voltag
voltages for the
instrument in the above problem
V, 1.253 V]
s h n g p
em when the applied voltageage is 1.255V.
1. [Ans: 1.257

. A l E
‰An analog instrument with ±1% accuracy
r a
accuracy and
a a digital meter
m with ± (0.8% of

r
reading +1 d) accuracy
a
racy aare
a
re both used to measure a 56 V quantity. If the analog

D ric Kh
instrument is set to 100V range
ange and digital
ital meter has a 3-1/2 -digit display.
Calculate the measurement
easu ment accuaccuracy
acy in each case. [Ans: ±1.8%, ±0.1%]

c t I T
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 114
Tutorial Problem
y
t rin g
i
‰A digital frequency meter displays a count off 366. The

a e
Th time
clock generator frequency-divided by fivee decade counters
me base hasha a 2 MHz
co nters and 1 flip flop.

would be displayed if the flip-flopM ne r

Calculate the gate time and the measured red frequency.
frequ y. Determine
p is removed
Determ the count that
remove from the time
t base.
base [Ans: 3.66 kHz,
183]
i s gi u
s h
‰ A frequency meter with an accuracy
n g p
accura of േ1 LSDേ (1ൈ10 ൈ10-5) is used to measure

. A
frequencies of 30 Hz, 30 MHz and
l E r a
an 3000 MHz. Calculate
ulate the percentage
p error for

a
each measurement. [A [Ans:: േ3.3%,
േ %, േ0 001 േ0.001%
േ0.001%, േ0.001%] V

r a
INX

D ric Kh
VSQR

t
VBASE

e c I I T VQ

28-02-2025
E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur
VQ

115
 y
t rin g
i
a e
M ne r
i s g i u
Signal
gnalhGenerators
s
G
Generan tors
g p
A E ity a
r
Dr.
. Electrica
a l
r. Ashis
Ashis
Electrical
Maity
a r
Engineering
Engineerin
D ricIIIITT Kharagpur
K
Kharagph
c t I T
le I
E
Type of signal generators
y
t rin g
i
‰Low frequency (LF) sine-wave generators (<20

a e
20 kHz)
d Triangula
‰Function generators: Sine, Square and Triangular
M ne r
‰Radio-frequency (RF) sine-wave generators
rators (>30
>30 kHz to 3 GHz)
Hz)

i s gi u
s h n g p
. A l E r a
r a a
D ric Kh
c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 117
Feedback system
y
t r in g arkhaus Criteria:
i
+ ‰Barkhausen’s

a e
x(s) H(s) y(s)
-
M ne r
‫݆߱ ܪ‬
߱଴ ߚ ݆݆߱
߱଴ ൌͳ

s gi
β(s)

h i p u ‫݆߱ ߚס‬଴ ‫݆߱ ܪ‬଴ ൌ െͳͺͲ଴

‰These conditions
ditions are
a necessary
s E n a g for ge
getting
ng oscilla
oscillation, but NOT

A r
ssufficient
ient
‫ ݏ ݔ‬െ ‫ܪ ݏ ߚ ݏ ݕ‬ሺ‫ݏ‬ሻ ൌ ‫ݏ ݕ‬

r . a l a Under this
‰Under t condition, the system

D ric Kh
‫ݏ ݕ‬ ‫ݏ ܪ‬
ൌ amplifies its own noise at ω0
amplif
‫ݏ ݔ‬ ͳ൅ߚ ‫ݏ ܪ ݏ‬
‰To mitigate the variation, loop

c t I T ௬ ௦ gain is usually fixed twice or

I
If Loop Gain ߚ ‫ ݏ ܪ ݏ‬ൌ െͳǡ
െͳ –Š‡
‡ ൌ∞

l e thrice.
௫ ௦

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 118
 Review of Asymptotic Bode Plot
y
t rin
20log|H(s)β(s)| g ω1

i
a e

Gain (dB)
M ne r ω2

s gi
+
u
ω

i
x(s) H(s) y(s)

h p
Unity gain line
Un
-
β(s)
s E n a g 0.1ω1 10ω1 0.1ω2 10ω2

. A l a r 0º ω

r
D ric Kh a -45º
Phase
hase
-90ºº

t
-135º
135º
‰Concept of phasese m
margin
gin

c T
-180º
0º
‰Does it oscillate?
l e I I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 119
Generation of oscillation +

g
H(s)

20log|H(s)β(s)|
ω1

i y Noise
t rin
ωo -

a e β(s)

M ne r
Gain (dB)

+
s gi
ω2

u
H(s)

h i ωo

p
ω -
Unity gain line

s E n a g β(s)
0.1ω1

. A
10ω1

l
0.1ω
1ω2

a r 10ω2
1
0º
-45º r
D ric Kh a ω
Phase

+
t
-90º
H(s)

c T
-135º

I
-

e I
-180º

Remark:
28-02-2025
Two-pole
E
pole ssystem may l not give a sustained oscillation.
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur
β(s)
120
Generation of oscillation +

g
x(s) H(s) y(s)

i y
t rin
-

a e
β(s)
‰Combinations possible:
M ne r
¾Forward path is independent of ω, whereas
reas the feedback
back path is dependent
pe of ω.

i s gi
¾Forward path is dependent of ω, wherea
whereas th
u
the feedback
edback pat
path is indepe
independent of ω.

‰Various views of oscillatory

s h
¾Both forward and feedback paths
aths are dependent
atory systems:
systems:
de

n g p
ent on ω

. A l E r a
+
r a a +

D ric Kh
x(s) H(s) y(s)
y( x(s) H(s) y(s)
- 180
180º + 360º

c t β(s)

I T
β(s)

le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 121
 Low-Frequency Signal Generators: Wein bridge oscillator
y
t rin g ܴଶ

i
ܴଷ ͳ ൅ ‫ܴݏ‬ଶ ‫ܥ‬ଶ
C1 ‫ ܩܮ‬ൌ ͳ ൅
a e
ͳ ൅ ‫ܴݏ‬ଵ ‫ܥ‬ଵ ܴସ ͳ ൅ ‫ܴݏ‬
ܴଵ ‫ܥ‬ଵ ܴଶ
R1 +VCC ൅
M ne r
‫ܥݏ‬ଵ ‫ܥݏ‬ଵ ͳ ൅ ‫ܴݏ‬ଶ ‫ܥ‬ଶ

s gi
+ Assuming
A ming R=R1=R2 and C=C1=C2

h i p u ܴଷ ͳ
ܴଶ -
s E n a g ‫ ܩܮ‬ൌ ͳ ൅
ܴସ ͵ ൅ ‫ ܥܴݏ‬൅ ͳ
ͳ ൅ ‫ܴݏ‬ଶ ‫ܥ‬ଶ -V
A
VCC
. l a r
R3
‫ܥܴݏ‬
C2 R2
r
D ric Kh a R4
To get sus
sustained oscillation at
ͳ ͳ
Feedback
c t IT
Non nverting
Non-inverting
߱଴ ൌ
ܴ‫ܥ‬
‫݂ ݎ݋‬଴ ൌ
ʹߨܴ‫ܥ‬
network
ork
l e I
amplifier
lifier Loop gain at ω0 or f0 should be “1”

28-02-2025
E ܴଷ ൌ ʹܴସ
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 122
 Low-Frequency Signal Generators: Wein bridge oscillator
y
t rin g
‰To get an oscillation:
oscil n: Av,amp=3
C1
+VCC
i
a e ‰To get a sustain
sustainedd oscillation:
oscilla Av,amp>3
R1
M ne r Excess ggain leads
‰Excess eads to distortion
+
i s gi ‰Modi ation required
‰Modification
u
requ

p
en the ou
¾When output amplitude is small:
-
s h
R5
n g • ‫ܣ‬௩ǡ ௔௠
௔௠௣ ൌ ͳ ൅
ோఱ ାோల

E a
ோర

-VCC
. A R6
l a r
ோ ାோ
• ͳ ൅ ఱ ల ൐ ͵, so that small oscillations

r a
ோర
continues
ontinu
C2 R2
D ric Kh R4
¾When the output amplitude is large:

t
ோఱ
• ‫ܣ‬௩ǡ ௔௠௣ ൌ ͳ ൅

c T
ோర

I
ோ

e I
R3=R5+R6 • ͳ ൅ ఱ ൏ ͵ , so that large oscillations

l
ோర
diminish
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 123
Low-Frequency Signal Generators: Wein bridge oscillator
y
t rin g ‰Frequency range
‰Freque ange chan
changing:
C1
i
a e
¾C1 an
and C2 adjuste
for “range”
adjusted simultaneously
range” selection,
s discrete
R1 +VCC
M ne r djustmen of frequency.
adjustment req

i s gi u ¾R1 and R2 adjusted

djusted for continuous
+
h p
tuning of frequency
tun frequen

s E n a g
. A-
l a r ݂ ൌ
ͳ R5

r a
଴
- CC
-V ʹߨܴ‫ܥ‬R6
C2 D ric Kh
R2
c t I T
R4

le I
R3=R5+R6
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 124
Low-Frequency Signal Generators: Wein bridge oscillator: Controlling the
output amplitude
y
t rin g
i
‰Voltage follower/buffer offers a low output impedance.
mpedanc
a e
‰R9 gives fine tuning of the amplitude and S1 use
used for
or range selection.
s
M ne r
C1
is gi u
R1
s h
+VCC
n g p
. A +
l E ra S1

r a a +VCC

D ric Kh - R5 R7 R8
R9
t -V
VCC VO
R6
C2
ec I I T
28-02-2025
E l R2 R4

Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur

-VCC

125
Development of Function Generator
y
t rin g
generate a square wave. i
‰Nonlinear oscillators or function generators to

a e
‰Three types of multi-vibrators:
M ne
s gi
¾Bistable
¾Astable

h i
n
¾Monostable
‰Bistable circuit:
A s E
¾Two stable states.

r.
¾Required appropriate
a l
triggers to
opriate tri
a
o move ffromm one

D ric Kh
stable state too another stable
¾Using a positivee feedback
ble state.
fee ack loop for creating
re ting a
bistable operation
c t I T
e I
Trig r circuit or
¾Also, known as Schmitt Trigger o hysteretic
comparator

28-02-2025
El Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 126
 Transfer characteristics of Schmitt Trigger
y
t rin g
i
R2 ‰Let’s assume:
me: Vo=-VCC

a e
‰When Vin starts fro
from negative,
negative Vx<0 and Vo=−VCC

R1 +VCC M ne r
en Vin=0, Vx <0 as Vo==−VCC
‰When

+
i s gi
‰When Vin goes
‰Whe
Vx=0
=0,
u
oes positiv
positive and
nd reac
reached VTH, then
Vin Vx
s h Vo
n g p ்ܸு ܴଶ ܸେେେ ܴଵ

E a
െ ൌͲ
-

. A l a r
ܴଵ ൅ ܴଶ ܴଵ ൅ ܴଶ
Vo

r
-VCCC

D ric Kh a ்ܸு ൌ൅
ܸେେ ܴଵ
ܴଶ
+VCC

ܸ௫ ൌ
ܸ௜௡ ܴଶ
൅
ܸ୭ ܴଵ

c t I T VTH
Vin

I
ܴଵ ൅ ܴଶ ܴଵ ൅ ܴଶ

l e
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur
-VCC
127
Transfer characteristics of Schmitt Trigger
y
t rin g
i
R2 ‰Let’s assume:
me: Vo=+=+VCC

a e
‰When Vin starts fro
from positive, Vx>0 and Vo=+VCC

R1 +VCC M ne r
en Vin=0, Vx >0 as Vo==+VCC
‰When

+
i s gi
‰When Vin goes
‰Whe
Vx=0
=0,
u
oes negati
negative and
nd rea
reached VTL, then
Vin Vx
sh Vo
n gp ்ܸ௅ ܴଶ
൅
ܸେେେ ܴଵ
ൌͲ
-

. A l E ra ܴଵ ൅ ܴଶ ܴଵ ൅ ܴଶ Vo

r
-VCCC
a a ܸେେ ܴଵ +VCC

D ric Kh
்ܸ௅ ൌെ
ܴଶ

ܸ௫ ൌ
ܸ௜௡ ܴଶ
൅
ܸ୭ ܴଵ

c t I T
VTL
Vin

I
ܴଵ ൅ ܴଶ ܴଵ ൅ ܴଶ

l e -VCC
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 128
Transfer characteristics of Schmitt Trigger
R2

ti y ri
்ܸு ൌ ൅
ܸେେ ܴଵ
n g Vo

a e
ܴଶ +VCC
R1 +VCC
ܸେେେ ܴଵ
Vin Vx
+
M ne r
்ܸ௅ ൌ െ
ܴଶ VTH
Vin

s gi
Vo VTL
-

h i pu -VCCC

n
Non-inverting
n-invert configuration
onfigurat
s g
-VCC

R2

. A l E r a Vo

r a a
Inverting
ing co
configuration
nfig ion
+VCC

D ric Kh
R1 +V
VCC VTHH=? and VTL=?
+

t
Vx ܸେେେ ܴଵ Vin
Vo VTL VTH

T
்்ܸு ൌ ൅
-

e c I I
ܴଵ ൅ ܴଶ

l
ܸେେ ܴଵ -VCC
Vin -VCCC ்ܸ௅ ൌെ
28-02-2025
E ܴଵ ൅ ܴଶ
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 129
Generating triangular-wave and square wave
y
t rin g
i
C3

a e
R2

M ne
R3 +VCC
- +VCC
s gi
R1

i
I3 V1
+
+

s h -
n
V2

E
-VCC

. A l a
-VCCC
‰ࢀ૚ ൌ
࡯૜ ࢂࢀࡴ ିࢂࢀࡸ
ࡵ૜
ൌെ
r
D ric Kh a
࡯૜ ࡾ૜ ࢂࢀࡴ ିࢂࢀࡸ
ࢂ࡯࡯

t
࡯૜ ࢂࢀࡴ ିࢂࢀࡸ ࡯૜ ࡾ૜ ࢂࢀࡴ ିࢂࢀࡸ
‰ࢀ૛ ൌ ൌ

c T
ࡵ૜ ࢂ࡯࡯
‰ࢀ ൌ ࢀ૚ ൅ ࢀ૛
l e I I
E
૚
‰ࢌ ൌ
ࢀ
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 131
Waveform Shaping Method: Sine Wave Conversion
y n g
Assuming iideal
eal diod
diodee
r i
ܴହ e
ܱ ൌ ܸଵ ൅ ܸ௜௡ െ ܸଵ
ܱ‫ݐݑ‬
ܴସ ൅ ܴହ
u r
p

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E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 132
Function Generator
y
t rin g
i
a e
n e r
i
g gp u
r . A ra
D ric
c t
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 133
Tutorial Problems
‰A Wein bridge oscillator circuit as in the figure
y
t rin g
re has VCC = ±10 V, C1 = C2 = 0.01 μF,
and R1 = R2 = 15 kΩ. Calculate the frequency.
required to give fmax = 800 Hz.
i
a e
ncy. Determ
Determine the new
ne capacitor values
(Ans. 1.06 kHz)
M ne r
is i pu
g

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E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 134
Tutorial Problems
y
t rin g
‰The Wein bridge circuit shown in the figure has R4 = 390
3900 Ω, R5 = 7600 ΩΩ, and R6 = 800

maximum amplitude of the output voltage. i

Ω. Find out the closed loop gains of the amplifier
a e
lifier under two
t modes. Calculate
e. Assume tthe forward
ward diode
di
C the
drop=0.7 V and the
supply voltage is ±12 V
M ne r (Ans. 3.15 V/V,
V, 2.95
2 V/V, ±10.76 V)

i s gi u
p
C1
R1 +VCC
sh n g
+
. A l E r a
r a a
D ric Kh
- R5
-V
VCC

c t I T
R6
C2 R2
l e I R4

28-02-2025
E
R3=R5+R6 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 135
Tutorial Problems
y
t rin g
‰The integrator in the figure has R1 =500 Ω, R2 = 4.7 kkΩ, and
nd C1 = 0.3 μF. If the
Schmitt circuit has ± 1V trigger points, and i
a e
nd the supply
suppl voltage
determine the output frequency when R1 is at its center
oltage is ±12 V,
nter poin
point. Assume the high
M ne r
and low levels of the Schmitt trigger outputs
utputs are ±12 V. (Ans. 1.066 kHz)

i s gi u
h g p

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E l Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 136
 y
t rin g
i
a e
M ne r
i s g i u
Oscilloscopes
Oscillo
s h oscope
n es
g p
A E ity a
r
Dr.
. Electrica
a l
r. Ashis
Ashis
Electrical
Maity
a r
Engineering
Engineerin
D ricIIIITT Kharagpur
K
Kharagph
c t I T
le I
E
Oscilloscopes
y
t rin g
i
‰Useful instrument to view the signal/waveforms
veforms
a e
‰Detailed investigation of signal is possible.
M ne r
¾Peak voltage, frequency, phase difference,
rence, pulse
p width, de
delay time,
me rise time, fall
time etc.
i s gi u
‰Types
s h
¾Analog Oscilloscope/Cathode
n g p
e/Cathode Rayy Oscilloscope (CRO)
CRO)
¾Digital Oscilloscope:
A l E
e: Uses an ADC
. r
AD to con
a
convert the
he analog ssignal to digital

r a
• Acquire the waveform
a
wavef m as a series
ries of sample
s and store it.
it

D ric Kh
mulate enoug
• Accumulate amples to describe
enough samples des e a waveform.
waveform
• Major Classif
Classifications:

c t
ƒ Digitall storage oscilloscope
ƒ Mixed-signal

I T
oscillosco (DSO)
al oscillos
DSO)
oscilloscopee (MSO)

le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 138
Cathode-Ray Oscilloscope
y n g
‰ Filament
Fila heats nickel cathode

i
whic emits electrons.
which
C
‰ Cathode is typically held at -2
kV.
‰ Grid is also made of nickel
controls the flow of electron.

r
Its voltage is adjustable from -
2 kV to -2.05 kV for brightness
control
‰ A1 provides accelerating fields,
limits initial cross section of e-
beams
‰ A2 acts as focus ring.
‰ e-beam can be deflected by
vertical and horizontal
deflection plates.
‰ The signal to be investigated is
applied in the vertical plate.
‰ Time-base circuit generates a
saw-tooth ramp voltage
applied to the horizontal plate
for time domain analysis.
‰ Post deflection acceleration
unit again provides
accelerating fields.
‰ The fluorescent screen glows

E
where e-beam strikes.

28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 139

 Electrostatic Focusing
‰Focusing of e-beam
ti y n g
¾Electrostatic focusing in CRO
¾Electromagnetic focusing in TV a
M
‰At the edge of the plates the field lines
ines
are getting curved due to lateral
i s
repulsion.
s h
‰Equipotential lines are perpendicular
erpendicu to n
field lines.
A
. a l E r
‰Force ࡲ ൌ െࢋ ൈ ࢿ Newton
r
Newto
a
D ric Kh
EElectric field lines of two parallel plates
¾Where e=chargee of electrons=1.602X10
elec =1.602X10-19 C
nten

c t
¾ε= Electric field intensity V/m

I T
¾Negative sign indicatess that the force
orce

l e I
required to movee e from the negative
to the positivee plate in opposite
o
ative plate
to electric
elec
field. Attractive
28-02-2025
E
ve force.
force
Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 140
Electrostatic Focusing
y
t rin g
i
a e
n e
g i
E n
A
. a l a r
r
D ric Kh
Electric ffield lines of two cylindrical plates

c t I T
l e I
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E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 141
Electrostatic Focusing

ty n g
i

l e
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E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 142
Deflection Section
g

r. a
‰When vertical and horizontal l ar
ontal plates
p te are grounded
grounde or left open, e-beam
e hits the center of the screen.

D ric Kh
‰A differential voltage
ge is applie
applied to the deflecting
deflecti plates.
lates.
‰The strike position of e-b
e-beam on the scree
screen depends
pends on tthe deflecting voltage.

ct
‰Deflection factor: V/cm, voltage

I T
required
tage requ d to produce
pro ce one division (1 cm) of deflection
‰Deflection sensitivity:

le I
y: cm/V, the deflection
‰What happens if an AC voltage
produced by 1 V.
tion prod
volta is appliedd in the
t deflecting plates?
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 143
Deflection Amplifier
y g

ct I T
‰Deflection plates
le I
es need ++E/2 and
input with differential
nd –E/2
fferential outputs.
o
–E/2. Required an amplifier with DC or AC

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 144
Waveform Display

ty n g
‰A sine wave is applied on
the vertical deflecting plate. i
‰A sawtooth wave is applied
on the horizontal deflecting
plate.

A s
‰Deflecting sensitivity 2 cm/V
m/V

r.
D ri
c t I T
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 145
Horizontal Sweep Generator
‰Consists of ramp generator
and Schmitt trigger.
‰Sweep time control changes
the time base.
i s
h
ࢂ ࡾ
‰ࢁࢀࡼ ൌ ࡯࡯ ૟
ࡾ૞
ࢂ ࡾ
A s
‰ࡸࢀࡼ ൌ െ ࡱࡱ ૟
ࡾ૞

r. a l
D ric
c t I T
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 146
Peak-to-Peak Voltage and Frequency Measurements
y g
‰Peak-to-peak voltage:
¾VA=4.6 div X 100 mV/div=460 mV. it rin
¾VB=2 div X 100 mV/div=200 mV.
‰Frequency:

h i
¾TA=4.4 div X 0.5 ms/div =2.2 mss
¾fA=1/2.2m=455 Hz

As
¾Similarly calculate fB.

r. a
D ric
ct I T
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 147
Phase and Pulse Measurements
y
t rin g
i
a e
M ne
i s gi
h n
l E
c a h
t r i K
‰Phase:
c I I T ‰Pulse amplitude (PA), pulse width

le
¾1 div=360°/8=45°.
5 (PW) can be measured if we know

E
¾Phase diff=45°X1.4=63°.
=45°X1.4=6 V/div and Time/div.
28-02-2025 Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 148
 Lissajous figures or Lissajous patterns
‰Time base is y g
disconnected and sine
waves are applied to
both horizontal and
vertical inputs.
‰Known as Lissajous
figure.
‰The phase difference
produces various
patterns which vary
D
ary r
from straight diagonal
na
lines to the ellipse of
e c
28-02-2025
El
different eccentricities.
cities.

Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 149

 Measurement of phase difference from Lissajous figures or Lissajous
saj patterns

ti y n g
‰For Figure (a):
¾࣐ ൌ •‹ି૚
ࢅ૚
ࢅ૛
ൌ •‹ି૚
ࢄ૚
ࢄ૛
i

‰For Figure (b):

. A
¾࣐ ൌ ͳͺͲι െ •‹

D
ࢅ
r
ି૚૚ ૚
ࢅ૛

c t I
le I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 150
 Measurement of frequency from Lissajous figures or Lissajous
sajo patterns
y
t rin g
i
‰Signal with unknown frequency (fV) is
applied to vertical plate.
a e
‰A known frequency (fH) is applied in
M ne
horizontal plate.
i s gi
h
ࢌࢂ ࡺ࢛࢓࢈ࢋ࢘ ࢕ࢌ ࢎ࢕࢘࢏ࢠ࢕࢔࢚ࢇ࢒ ࢚ࢇ࢔ࢍࢋ࢔࢏ࢉ࢏ࢋ࢙
ࢍࢋ࢔࢏ࢉ࢏ࢋ࢙
‰ ൌ
ࢌࡴ
s n
ࡺ࢛࢓࢈ࢋ࢘ ࢕ࢌ ࢜ࢋ࢚࢘࢏ࢉࢇ࢒ ࢚ࢇ࢔ࢍࢋ࢔࢏ࢉ࢏ࢋ࢙
ࢍࢋ࢔࢏ࢉ࢏ࢋ࢙

E
. A l
r
D ric K a
c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 151
Measurement of frequency from Lissajous figures or Lissajous
sajo patterns
y ing
e r
e
n ur
g p
a
D r
l e
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 152
Conclusion for the Post Mid-term Session
y
t rin g
i
‰Module-1: Analog Electronic Basics
characteristics [4]
a e
¾Class-1: Introduction to electronic Instrumentation,
tation, compara
comparator and its st
static and dynamic

M ne r
¾Class-2: Operational amplifier: Differential gain ve
versus common
ommon mo mode gain,
ain Non-idealities:

s gi
input bias current and input offset current,
current and input
i ut offset voltage.
volt [4]
4]

h i
¾Class-3: Offset Cancellation in op-amp,
¾Class-4: Development of Instrumentation
p u
amp, Difference
Dif
mentatio Amplifier
e amplifier [4]
lifier [4]
‰Module-2: Analog Instruments
uments
s E n a g
. A
¾Class-5: Analog DC Voltmeters,
l a r
meters Emitter
tte Followe
Follower, FET Input Voltmeter,
Voltm Difference Amplifier

r a
Voltmeter [1]

D ric Kh
¾Class-6: Op-Amp
Amp Amplifier
Amplif Voltmeter, Vo Voltage-to-Current
ge-to-Current based Voltmeter, Series Ohmmeter,
Shunt Ohmmeter,
meter, Linear
Lin Ohmmeter
hmmeter [1[1]

t
¾Class-7: Analogg AC
A Voltmeters,
tmeters, Op-amp
mp Halfwave Precision Rectifier Voltmeter , AC Voltage-

c T
to-Current Based Voltmeter
tmeter (Full-Wave)
(F Wave) [1]

e
¾Class-8: Electronic
I I
ronic Multimeter

l
Multim and Differe
Different Probes, Tutorial [1]

28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 153
Conclusion for the Post Mid-term Session
y
t rin g
i
‰Module-3: Digital Electronic Basics

a e
¾Class-9: Flip-Flops, Design of Ripple Counterss and BCD Counters
Cou s [5]
¾Class-10: Scale-of-1000 Counter, Scale of-2000
2000 Counter,
Counter BCD-to-Seven
o-Seven Segment Decoder,

M ne r
LED Displays: 3.3 digits and 4.5 digits [1]
¾Class-11: Analog-to-Digital Conversion,, Static
tic Characteristic, Sample and Hold, Linear-Ramp
Ch acteristic, Sa
ADC [1]
i s gi u
p
¾Class-12: Digital-Ramp ADC, Digital-to-analog
igital to ana converter
nverter [1]
[1
¾Class-13: Tutorial

s h n g
E a
‰Module-4: Digital Instruments
ments

.
Digital Voltmeter [1]]A
¾Class-14: Single-slope ramp
l a r
amp generator
ge tor type
ype digital
dig voltmeter,
tmeter, Dual Slope Integrator Based
¾Class-15: Digital
Meter [1]
¾Class-16: Accuracy
r
D ric Kh
gital Ohmme
a
Ohmmeter, Digital
gital AC Voltmeter
curacy Measurements,
Vo meter and Dig
asurements, Reciprocal
Digital Multimeter, Digital Frequency
Counting Based Frequency Meter [1]
procal Co

c t
¾Class-17: Pulse-Width measurement,
and Digital Instruments
measurem nt, W

I
nts [1]
T
Waveshaping
esha Circuit, Comparison between Analog
¾Class-18: Tutorial
e
orial
l I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 154
Conclusion for the Post Mid-term Session
y
t rin g
i
‰Module-5: Signal and Function Generators
a e
¾Class-19: Basic theory for oscillation, Low
w frequen
frequency signal
nal gene
generator, Wein Bridge
Oscillators
M ne r
s gi
¾Class-20: Bistable operation, Astablele multivibrator
ultiv ator

h i
¾Class-21: Function Generators:
ors: Triangular
Generator, Sine wave generator
rator
p u
Triangu wave ave generators,
gener , Square Wave
W

¾Class-21: Tutorial
s E n a g
‰Module-6: Oscilloscope
pe
. A l a r
¾Class-22: Analog
Electrostatic r
D ric Kh
nalog Osc
a
Oscilloscope:
ope: Basic Construction,
onstruction Electrostatic Focusing,
deflection, Deflection Amplifier
ic deflect mplifier [1]
¾Class-23: Horizontal
izo
Conclusion [1,3]
c t Sweep G

I T
Generator, Displaying waveform, Lissajous figures,
erat , Displ

l
¾Class-24: Class
e
lass Test
I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 155
 y
t rin g
i
a e
nk yousfor
M n e r
Thank
Allithe best!g
i pu
f attending!
attending

s h n g
. A l E r a
r a a
D ric Kh
c t I T
l e I
28-02-2025
E Dr. Ashis Maity, Electrical Engineering, IIT Kharagpur 156