HYB39S256400/800/160DT(L)/DC(L)

256MBit Synchronous DRAM

256 MBit Synchronous DRAM

• High Performance: • Data Mask for Read / Write control (x4, x8)
• Data Mask for byte control (x16)
-6 -7 -7.5 -8 Units
• Auto Refresh (CBR) and Self Refresh
fCK 166 143 133 125 MHz • Power Down and Clock Suspend Mode
tCK3 6 7 7.5 8 ns • 8192 refresh cycles / 64 ms (7,8 µs)
tAC3 5 5.4 5.4 6 ns • Random Column Address every CLK
( 1-N Rule)
tCK2 7.5 7.5 10 10 ns
• Single 3.3V +/- 0.3V Power Supply
tAC2 5.4 5.4 6 6 ns
• LVTTL Interface versions
• Fully Synchronous to Positive Clock Edge • Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
• 0 to 70 °C operating temperature
• Chipsize Packages:
• Four Banks controlled by BA0 & BA1
54 ball TFBGA (12 mm x 8 mm)
• Programmable CAS Latency: 2 & 3
• -6 parts for PC166 3-3-3 operation
• Programmable Wrap Sequence: Sequential -7 parts for PC133 2-2-2 operation
or Interleave -7.5 parts for PC133 3-3-3 operation
• Programmable Burst Length: -8 parts for PC100 2-2-2 operation
1, 2, 4, 8 and full page
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command

The HYB39S256400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4 banks x

16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.14 µm 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply. All 256Mbit components are available in TSOPII-54 and TFBGA-54
packages.

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Ordering Information
Type Speed Grade Package Description

HYB 39S256400DT-6 PC166-333-520 P-TSOP-54-2 (400mil) 166MHz 4B x 16M x 4 SDRAM

HYB 39S256400DT-7 PC133-222-520 P-TSOP-54-2 (400mil) 143MHz 4B x 16M x 4 SDRAM
HYB 39S256400DT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 16M x 4 SDRAM
HYB 39S256400DT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 16M x 4 SDRAM
HYB 39S256800DT-6 PC166-333-520 P-TSOP-54-2 (400mil) 166MHz 4B x 8M x 8 SDRAM
HYB 39S256800DT-7 PC133-222-520 P-TSOP-54-2 (400mil) 143MHz 4B x 8M x 8 SDRAM
HYB 39S256800DT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 8M x 8 SDRAM
HYB 39S256800DT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 8M x 8 SDRAM
HYB 39S256160DT-6 PC166-333-520 P-TSOP-54-2 (400mil) 166MHz 4B x 4M x 16 SDRAM
HYB 39S256160DT-7 PC133-222-520 P-TSOP-54-2 (400mil) 143MHz 4B x 4M x 16 SDRAM
HYB 39S256160DT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 4M x 16 SDRAM
HYB 39S256160DT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 4M x 16 SDRAM
HYB39S256800DTL-x P-TSOP-54-2 (400mil) 4B x 8M x 8 SDRAM Low Power
Versions (on request)
HYB39S256160DTL-x P-TSOP-54-2 (400mil) 4B x 4M x 16 SDRAM Low Power
Versions (on request)
HYB39S256xx0DC(L)-x P-TFBGA-54 (on request)

Pin Description:

CLK Clock Input DQx Data Input /Output

CKE Clock Enable DQM, LDQM, UDQM Data Mask

CS Chip Select VDD Power (+3.3V)

RAS Row Address Strobe VSS Ground
CAS Column Address Strobe VDDQ Power for DQ’s (+ 3.3V)
WE Write Enable VSSQ Ground for DQ’s
A0-A12 Address Inputs NC not connected
BA0, BA1 Bank Select

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Pinouts (TSOP-54)

16 M x 16
32 M x 8
64 M x 4

VDD VDD VDD 1 54 VSS VSS VSS

DQ0 DQ0 N.C. 2 53 N.C. DQ7 DQ15
VDDQ VDDQ VDDQ 3 52 VSSQ VSSQ VSSQ
DQ1 N.C. N.C. 4 51 N.C. N.C. DQ14
DQ2 DQ1 DQ0 5 50 DQ3 DQ6 DQ13
VSSQ VSSQ VSSQ 6 49 VDDQ VDDQ VDDQ
DQ3 N.C. N.C. 7 48 N.C. N.C. DQ12
DQ4 DQ2 N.C. 8 47 N.C. DQ5 DQ11
VDDQ VDDQ VDDQ 9 46 VSSQ VSSQ VSSQ
DQ5 N.C. N.C. 10 45 N.C. N.C. DQ10
DQ6 DQ3 DQ1 11 44 DQ2 DQ4 DQ9
VSSQ VSSQ VSSQ 12 43 VDDQ VDDQ VDDQ
DQ7 N.C. N.C. 13 42 N.C. N.C. DQ8
VDD VDD VDD 14 41 VSS VSS VSS
LDQM N.C. N.C. 15 40 N.C. N.C. N.C.
WE WE WE 16 39 DQM DQM UDQM
CAS CAS CAS 17 38 CLK CLK CLK
RAS RAS RAS 18 37 CKE CKE CKE
CS CS CS 19 36 A12 A12 A12
BA0 BA0 BA0 20 35 A11 A11 A11
BA1 BA1 BA1 21 34 A9 A9 A9
A10/AP A10/AP A10/AP 22 33 A8 A8 A8
A0 A0 A0 23 32 A7 A7 A7
A1 A1 A1 24 31 A6 A6 A6
A2 A2 A2 25 30 A5 A5 A5
A3 A3 A3 26 29 A4 A4 A4
VDD VDD VDD 27 28 VSS VSS VSS

TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch)

SPP04126

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Pinouts (TFBGA-54)

Pin Configuration for x16 devices:

1 2 3 7 8 9

VSS DQ15 VSSQ A VDDQ DQ0 VDD

DQ14 DQ13 VDDQ B VSSQ DQ2 DQ1

DQ12 DQ11 VSSQ C VDDQ DQ4 DQ3

DQ10 DQ9 VDDQ D VSSQ DQ6 DQ5

DQ8 NC VSS E VDD LDQM DQ7

UDQM CLK CKE F CAS RAS WE

A12 A11 A9 G BA0 BA1 CS

A8 A7 A6 H A0 A1 A10

VSS A5 A4 J A3 A2 VDD

Pin Configuration for x8 devices:

1 2 3 7 8 9

VSS DQ7 VSSQ A VDDQ DQ0 VDD

NC DQ6 VDDQ B VSSQ DQ1 NC

NC DQ5 VSSQ C VDDQ DQ2 NC

NC DQ4 VDDQ D VSSQ DQ3 NC

NC NC VSS E VDD NC NC

DQM CLK CKE F CAS RAS WE

A12 A11 A9 G BA0 BA1 CS

A8 A7 A6 H A0 A1 A10
VSS A5 A4 J A3 A2 VDD

Pin Configuration for x4 devices:

1 2 3 7 8 9

VSS NC VSSQ A VDDQ NC VDD

NC DQ3 VDDQ B VSSQ DQ0 NC

NC NC VSSQ C VDDQ NC NC

NC DQ2 VDDQ D VSSQ DQ1 NC

NC NC VSS E VDD NC NC

DQM CLK CKE F CAS RAS WE

A12 A11 A9 G BA0 BA1 CS

A8 A7 A6 H A0 A1 A10

VSS A5 A4 J A3 A2 VDD

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256MBit Synchronous DRAM

Pinout for x4, x8 & x16 organised 256M-DRAMs

C o lu m n A d d re s s e s R o w A d d re s s e s
A 0 - A 9 , A 1 1 , A P, A0 - A12,
B A0, BA 1 BA0, B A1

C o lu m n A d d re s s C o lu m n A d d re s s R o w A d d re s s
R e fre s h C o u n te r
C o u n te r B u ffe r B u ffe r

Row R ow Row R ow
D e co de r Decoder D e co de r D eco d e r

M em ory M em ory M em ory M em ory

Sense amplifier & I(O) Bus

Sense amplifier & I(O) Bus

Sense amplifier & I(O) Bus

Sense amplifier & I(O) Bus

A rray A rra y A rra y A rra y
Column Decoder

Column Decoder

Column Decoder

Column Decoder

Bank 0 B a nk 1 Bank 2 B a nk 3

8 1 96 81 9 2 8192 8 19 2
x 20 4 8 x 2 0 48 x 20 4 8 x 2048
x 4 B it x 4 B it x 4 B it x 4 B it

In p u t B u ffe r O u tp u t B u ffe r C o n tro l L o g ic &

T im in g G e n e ra to r

DQ0 - DQ3
CLK

CS

WE
DQM
CKE

RAS
CAS

S P B 0 4 1 2 7 _2

Block Diagram for 64M x 4 SDRAM ( 13 / 11 / 2 addressing)

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Column Addresses Row Addresses

A0 - A9, AP, A0 - A12,
BA0, BA1 BA0, BA1

Column Address Column Address Row Address

Refresh Counter
Counter Buffer Buffer

Row Row Row Row

Decoder Decoder Decoder Decoder

Memory Memory Memory Memory

Sense amplifier & I(O) Bus

Sense amplifier & I(O) Bus

Sense amplifier & I(O) Bus

Sense amplifier & I(O) Bus

Array Array Array Array
Column Decoder

Column Decoder

Column Decoder

Bank 0 Bank 1 Bank 2 Column Decoder Bank 3

8192 8192 8192 8192

x 1024 x 1024 x 1024 x 1024
x 8 Bit x 8 Bit x 8 Bit x 8 Bit

Input Buffer Output Buffer Control Logic &

Timing Generator

DQ0 - DQ7
CS

DQM
CLK

WE
CKE

RAS
CAS

SPB04128

Block Diagram for 32M x 8 SDRAM ( 13 / 10 / 2 addressing)

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Column Addresses Row Addresses

A0 - A8, AP, A0 - A12,
BA0, BA1 BA0, BA1

Column Address Column Address Row Address

Refresh Counter
Counter Buffer Buffer

Row Row Row Row

Decoder Decoder Decoder Decoder
Sense amplifier & I(O) Bus

Sense amplifier & I(O) Bus

Sense amplifier & I(O) Bus

Sense amplifier & I(O) Bus

Memory Memory Memory Memory
Array Array Array Array
Column Decoder

Column Decoder

Column Decoder

Bank 0 Bank 1 Bank 2 Column Decoder Bank 3

8192 x 512 8192 x 512 8192 x 512 8192 x 512

x 16 Bit x 16 Bit x 16 Bit x 16 Bit

Input Buffer Output Buffer Control Logic &

Timing Generator

DQ0 - DQ15
DQMU
DQML
CS
CLK

WE
CKE

RAS
CAS

SPB04129

Block Diagram for 16M x16 SDRAM ( 13 / 9 / 2 addressing)

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Signal Pin Description

Pin Type Signal Polarity Function

CLK Input Pulse Positive The system clock input. All of the SDRAM inputs are
Edge sampled on the rising edge of the clock.

CKE Input Level Active Activates the CLK signal when high and deactivates the
High CLK signal when low, thereby initiating either the Power
Down mode, Suspend mode, or the Self Refresh mode.

CS Input Pulse Active CS enables the command decoder when low and disables
Low the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.

RAS Input Pulse Active When sampled at the positive rising edge of the clock,
CAS Low CAS, RAS, and WE define the command to be executed by
WE the SDRAM.

A0 - A12 Input Level – During a Bank Activate command cycle, A0-A12 define the
row address (RA0-RA12) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0-An define the
column address (CA0-CAn) when sampled at the rising
clock edge.CAn depends upon the SDRAM organization:

64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)

32M x8 SDRAM CAn = CA9 (Page Length = 1024 bits)
16M x16 SDRAM CAn = CA8 (Page Length = 512 bits)

In addition to the column address, A10(= AP) is used to

invoke the autoprecharge operation at the end of the burst
read or write cycle. If A10 is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged.
If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.

BA0, BA1 Input Level – Bank Select Inputs. Bank address inputs selects which of
the four banks a command applies to.

DQx Input Level – Data Input/Output pins operate in the same manner as on
Output conventional DRAMs.

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Pin Type Signal Polarity Function

DQM Input Pulse Active The Data Input/Output mask places the DQ buffers in a
LDQM High high impedance state when sampled high. In Read mode,
UDQM DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
One DQM input is present in x4 and x8 SDRAMs, LDQM
and UDQM controls the lower and upper bytes in x16
SDRAMs.

VDD Supply – – Power and ground for the input buffers and the core logic.
VSS
VDDQ Supply – – Isolated power supply and ground for the output buffers to
VSSQ provide improved noise immunity.

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Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.

Operation Device CKE CKE DQM BA0 AP= Addr CS RAS CAS WE
State n-1 n BA1 A10 .
Bank Active Idle3 H X X V V V L L H H
Bank Precharge Any H X X V L X L L H L
Precharge All Any H X X X H X L L H L
Write Active3 H X X V L V L H L L
Write with Autoprecharge Active3 H X X V H V L H L L
Read Active3 H X X V L V L H L H
Read with Autoprecharge Active3 H X X V H V L H L H
Mode Register Set Idle H X X V V V L L L L
No Operation Any H X X X X X L H H H
Burst Stop Active H X X X X X L H H L
Device Deselect Any H X X X X X H X X X
Auto Refresh Idle H H X X X X L L L H
Self Refresh Entry Idle H L X X X X L L L H
Self Refresh Exit Idle H X X X
(Self L H X X X X
L H H X
Refr.)
Clock Suspend Entry Active H L X X X X X X X X
Power Down Entry Idle H X X X
(Precharge or active H L X X X X
standby)
Active4 L H H H
Clock Suspend Exit Active L H X X X X X X X X
Power Down Exit Any H X X X
(Power L H X X X X
Down) L H H L

Data Write/Output Enable Active H X L X X X X X X X

Data Write/Output Disable Active H X H X X X X X X X
Notes
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the
commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle
device is in clock suspend mode.

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256MBit Synchronous DRAM

Mode Register Set Table

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address Bus (Ax)

Operation Mode CAS Latency BT Burst Length

Mode Register (Mx)

Operation Mode Burst Type

M9 Mode M3 Type
0 burst read / burst write 0 Sequential
1 burst read / single write 1 Interleave

Burst Length
CAS Latency
Length
M6 M5 M4 Latency M2 M1 M0
Sequential Interleave
0 0 0 Reserved
0 0 0 1 1
0 0 1 Reserved
0 0 1 2 2
0 1 0 2
0 1 0 4 4
0 1 1 3
0 1 1 8 8
1 0 0
1 0 0
1 0 1
Reserved 1 0 1 Reserved
1 1 0 Reserved
1 1 0
1 1 1
1 1 1 Full Page

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Power On and Initialization

The default power on state of the mode register is supplier specific and may be undefined.
The following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The
power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK
signal must be started at the same time. After power on, an initial pause of 200 µs is required
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow these
steps may lead to unpredictable start-up modes.

Programming the Mode Register

The Mode register designates the operation mode at the read or write cycle. This register is
divided into four fields. First, a Burst Length Field which sets the length of the burst, Second, an
Addressing Selection bit which programs the column access sequence in a burst cycle (interleaved
or sequential). Third, a CAS Latency Field to set the access time at clock cycle. Fourth, an
Operation mode field to differentiate between normal operation (Burst read and burst Write) and a
special Burst Read and Single Write mode. After the initial power up, the mode set operation must
be done before any activate command. Any content of the mode register can be altered by re-
executing the mode set command. All banks must be in precharged state and CKE must be high at
least one clock before the mode set operation. After the mode register is set, a Standby or NOP
command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate
the mode set operation. Address input data at this timing defines parameters to be set as shown in
the previous table.

Read and Write Operation

When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read
or write operations are allowed at up to a 166 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is
a function of the I/O organization and column addressing. Full page burst operation does not self

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256MBit Synchronous DRAM

terminate once the burst length has been reached. In other words, unlike burst lengths of 2, 4 and
8, full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAMs, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations
are possible. With the programmed burst length, alternate access and precharge operations on two
or more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages.

Burst Length and Sequence:

Burst Starting Address Sequential Burst Addressing Interleave Burst Addressing

Length (A2 A1 A0) (decimal) (decimal)
2 xx0 0, 1 0, 1
xx1 1, 0 1, 0
4 x00 0, 1, 2, 3 0, 1, 2, 3
x01 1, 2, 3, 0 1, 0, 3, 2
x10 2, 3, 0, 1 2, 3, 0, 1
x11 3, 0, 1, 2 3, 2, 1, 0
8 000 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
001 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
010 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
011 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
100 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
101 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
110 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
111 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
Full nnn Cn, Cn+1, Cn+2 .... not supported
Page

Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the
CAS -before-RAS refresh of conventional DRAMs. All banks must be precharged before applying
any refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE
are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum tRC time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.

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The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the
word lines after RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control
signals including the clock are disabled. Returning CKE to high enables the clock and initiates the
refresh exit operation. After the exit command, at least one tRC delay is required prior to any access
command.

DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to
“high“ at a clock timing, data outputs are disabled and become high impedance after two clock delay
(DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is
activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero
clocks).

Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency tCSL).

Power Down
In order to reduce standby power consumption, a power down mode is available. All banks
must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can
enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the
receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any
refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh
period (tref) of the device. Exit from this mode is performed by taking CKE “high“. One clock delay
is required for Power Down mode entry and exit.

Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge
function is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-
Precharge function is initiated. The SDRAM automatically enters the precharge operation a time
delay equal to tWR (“write recovery time”) after the last data in.
A burst operation with Auto-Precharge may only be interrupted by a burst start to another bank. It
must not be interrupted by a precharge or a burst stop command.

Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS
latency = 3. Writes require a time delay twr (“write recovery time”) of 2 clocks minimum from the last
data out to apply the precharge command.

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Bank Selection by Address Bits

A10 BA0 BA1
0 0 0 Bank 0
0 0 1 Bank 1
0 1 0 Bank 2
0 1 1 Bank 3
1 x x all Banks

Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.

Capacitance
TA = 0 to 70 °C; VDD,VDDQ = 3.3 V ± 0.3 V, f = 1 MHz

Parameter Symbol Values Unit

min. max.
Input capacitance (CLK) CI1 2.5 3.5 pF
Input capacitance CI2 2.5 3.8 pF
(A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM)
Input / Output capacitance (DQ) CIO 4.0 6.0 pF
Note: Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages
are lower by 0.5 pF.

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Absolute Maximum Ratings

Parameter Symbol Limit Values Unit

min. max.
Input / Output voltage relative to VSS VIN, VOUT – 1.0 4.6 V
Power supply voltage VDD,VDDQ – 1.0 4.6 V
oC
Operating Temperature TA 0 +70
oC
Storage temperature range TSTG -55 +150
Power dissipation per SDRAM component PD – 1 W
Data out current (short circuit) IOS – 50 mA
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability

Recommended Operation Conditions and DC Eletrical Characteristics

TA = 0 to 70 oC;

Parameter Symbol Limit Values Unit Notes

min. typ. max.
Supply Voltage VDD,VDDQ 3.0 3.3 3.6 V 1
Input high voltage VIH 2.0 3.0 V DDQ+0.3 V 1, 2
Input low voltage VIL – 0.3 0 0.8 V 1, 2
Output high voltage (IOUT = – 4.0 mA) VOH 2.4 – – V 1
Output low voltage (IOUT = 4.0 mA) VOL – – 0.4 V 1
Input leakage current, any input IIL –5 – 5 mA
(0 V < VIN < VDD, all other inputs = 0 V)
Output leakage current IOL –5 – 5 mA
(DQs are disabled, 0 V < VOUT < VDDQ)
Notes:
1. All voltages are referenced to VSS.
2. Vih may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to -2.0 V for pulse
width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC
reference.

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Operating Currents
TA = 0 to 70 oC; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V

Parameter & Test Condition Symb. -6 -7 -7.5 -8 Note

max.
Operating Current tRC = t RC(min), IDD1 100 80 80 80 mA 3, 4
One bank active, Burst length = 1 Io = 0 mA
Precharge Standby Current CS =VIH (min.), IDD2P 2 2 2 2 mA 3
in Power Down Mode CKE<=Vil(max)
Precharge Standby Current CS = VIH (min.), IDD2N 35 30 30 25 mA 3
in Non-Power Down Mode CKE>=Vih(min)
No Operating Current CS = VIH(min), IDD3N 40 35 35 30 mA 3
CKE>=VIH(min.)

active state ( max. 4 banks) CS = VIH(min), IDD3P 5 5 5 5 mA 3

CKE<=VIL(max.)
Burst Operating Current IDD4 110 90 90 70 mA 3, 4
Read command cycling
Auto Refresh Current tRFC= tRFC(min) 220 190 190 160 mA
IDD5 5
Auto Refresh command cycling t RFC= 7.8 µs 3 3 3 3 mA

Self Refresh Current

(standard components) x4, x8 IDD6 3 3 3 3 mA
Self Refresh Mode, CKE=0.2V, x16 1.5 1.5 1.5 1.5 mA
tck=infinity
Self Refresh Current
(low power components) x8, x16 IDD6 0.85 0.85 0.85 0.85 mA
Self Refresh Mode, CKE=0.2V,
tck=infinity
Notes:
3. These parameters depend on the cycle rate. All values are measured at 166 MHz for “-6”, at 133 MHz for
“-7” and “-7.5” and at 100 MHz for “-8” components with the outputs open. Input signals are changed once
during tck.
4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3
and BL=4 is assumed and the VDDQ current is excluded.
5. tRFC= tRFC(min) “burst refresh”, tRFC= 7.8 µs “distributed refresh”.

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AC Characteristics 1)2)
TA = 0 to 70 oC; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns

Parameter Symbol Limit Values Unit

-6 -7 -7.5 -8
PC166- PC133- PC133- PC100-
333 222 333 222
min. max. min. max. min. max. min. max.

Clock and Clock Enable

Clock Cycle Time
CAS Latency = 3 tCK 6 – 7 – 7.5 – 8 – ns
CAS Latency = 2 7.5 – 7.5 – 10 – 10 – ns
Clock Frequency
CAS Latency = 3 tCK – 166 – 143 – 133 – 125 MHz
CAS Latency = 2 – 133 – 133 – 100 – 100 MHz
Access Time from Clock
CAS Latency = 3 tAC – 5 – 5.4 – 5.4 – 6 ns 2,
CAS Latency = 2 – 5.4 – 5.4 – 6 – 6 ns 3,
6
Clock High Pulse Width tCH 2 – 2.5 – 2.5 – 3 – ns
Clock Low Pulse Width tCL 2 – 2.5 – 2.5 – 3 – ns
Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 ns

Setup and Hold Times

Input Setup Time tIS 1.5 – 1.5 – 1.5 – 2 – ns 4

Input Hold Time tIH 0.8 – 0.8 – 0.8 – 1 – ns 4

CKE Setup Time tCKS 1.5 – 1.5 – 1.5 – 2 – ns 4

CKE Hold Time tCKH 0.8 – 0.8 – 0.8 – 1 – ns 4

Mode Register Set-up to Active tRSC 2 – 2 – 2 – 2 – CLK

delay
Power Down Mode Entry Time tSB 0 6 0 7 0 7.5 0 8 ns

Common Parameters
Row to Column Delay Time tRCD 15 – 15 – 20 – 20 – ns 5

Row Precharge Time tRP 15 – 15 – 20 – 20 – ns 5

Row Active Time tRAS 36 100k 37 100k 45 100k 48 100k ns 5

Row Cycle Time tRC 60 – 60 – 67 – 70 – ns 5

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Parameter Symbol Limit Values Unit

-6 -7 -7.5 -8
PC166- PC133- PC133- PC100-
333 222 333 222
min. max. min. max. min. max. min. max.

Row Cycle Time during Auto tRFC 60 63 67 70 ns

Refresh
Activate(a) to Activate(b) tRRD 12 – 14 – 15 – 16 – ns 5
Command period
CAS(a) to CAS(b) Command tCCD 1 – 1 – 1 – 1 – CLK
period

Refresh Cycle
Refresh Period (8192 cycles) tREF – 64 – 64 – 64 – 64 ms
Self Refresh Exit Time tSREX 1 – 1 – 1 – 1 CLK

Read Cycle
Data Out Hold Time tOH 2.5 – 3 – 3 – 3 – ns 2,
6
Data Out to Low Impedance Time tLZ 0 – 0 – 0 – 0 – ns
Data Out to High Impedance Time tHZ 3 6 3 7 3 7 3 8 ns
DQM Data Out Disable Latency tDQZ – 2 – 2 – 2 – 2 CLK

Write Cycle
Last Data Input to Precharge tWR 12 – 14 – 15 – 15 – ns 7
(Write without AutoPrecharge)

Last Data Input to Activate tDAL,min (twr/tck) + (trp/tck) CLK 8

(Write with AutoPrecharge)
DQM Write Mask Latency tDQW 0 – 0 – 0 – 0 – CLK

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Notes
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have V IL = 0.4 V and VIH = 2.4 V with the timing referenced to
the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC
measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified
tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and
with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.

t CH

2.4 V
CLOCK 1 .4 V
0.4 V
tT
tCL

t IH
t IS

IN P U T 1 .4 V

t AC tA C
tLZ t OH

O UTPUT 1.4 V
I/O
tHZ 50 pF

Measurement conditions for

IO.vsd
tAC and tOH

3. If clock rising time is longer than 1 ns, a time ( tT /2 − 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (tT − 1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycles and depend on the operating frequency
of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole
number)
6. Access time from clock tAC is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time tOH is 1.8 ns for PC133 components with no termination and 0 pF load.
7. It is recommended to use two clock cycles between the last data-in and the precharge command
in case of a write command without Auto-Precharge. One clock cycle between the last data-in
and the precharge command is also supported, but restricted to cycle times tck greater or equal
the specified twr value, where tck is equal to the actual system clock time
8. When a Write command with AutoPrecharge has been issued, a time of tdal(min) has be fullfilled
before the next Activate Command can be applied. For each of the terms, if not already an
integer, round up to the next highest integer. tck is equal to the actual system clock time.

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Package Outlines - TSOP

Plastic Package P-TSOPII-54

(400 mil, 0.8 mm lead pitch)
Thin Small Outline Package, SMD

15˚±5˚ 10.16 ±0.13 2)

0.1±0.05
1±0.05

0.15 +0.06
-0.03
0.8 0.5 ±0.1
15˚±5˚ 11.76 ±0.2
0.1 54x
3)
26x 0.8 = 20.8
0.35 +0.1 0.2 M 54x
-0.05

54 28
6 max

1 2.5 max 27
1)
22.22 ±0.13 GPX09039

Index Marking

1)
Does not include plastic or metal protrusion of 0.15 max per side
2)
Does not include plastic protrusion of 0.25 max per side
3)
Does not include dambar protrusion of 0.13 max per side

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Package Outlines- TFBGA

TFBGA-54 package
(12 mm x 8 mm, 54 balls)

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