Life

Presentation Outline

01 Recap

02 Microprocessor

03 Bus Structure

04 Pin diagram

05 What next?
 Syllabus Orientation

01 Intel Microprocessor 8085

02 Intel Microcontroller 8051

03 Interfacing 8051 Microcontroller

04 Embedded System Architecture and Design

05 Embedded Hardware Platforms

01 Intel Microprocessor 8085

Introduction to Microprocessor and Buses: 8085

Hardware Architecture, 8085 Pin out, register
organization, instruction format, addressing
modes, instruction set, programming 8085.
 Course Outcomes
Write assembly programs using the 8085-instruction set utilizing the
concepts of its architecture, addressing modes and instruction set

Utilizing the concepts of the architecture, addressing modes, write

assembly programs using the 8051 instruction set

Outline the internal blocks of 8051 and interfacing of peripheral ICs

with the microcontroller

Summarize the concepts of embedded system architecture and design

process

Explain the embedded system design using embedded hardware

platforms
Intel Microprocessor 8085
 Microprocessor

A programmable device that takes in numbers,

performs on them arithmetic or logical operations
according to the program stored in memory and then
produces other numbers as a result
 Microprocessor Vs Human Brain

Microprocessor (CPU) Human Brain Function

Performs arithmetic and logical
ALU (Arithmetic Logic Unit) Cerebrum (Logical Thinking, Calculations)
operations.

Prefrontal Cortex (Decision Making, Directs operations and fetches, decodes,

Control Unit (CU)
Coordination) and executes instructions.

Stores immediate data for quick

Registers & Cache Short-Term Memory (Working Memory)
processing.
Hippocampus (Long-Term & Working
Main Memory (RAM) Temporarily holds data for active tasks.
Memory)
Stores data and instructions for long-term
Storage (HDD/SSD) Memory Storage (LTM in Brain)
retrieval.
Biological Clock (Circadian Rhythm,
Clock (System Clock) Regulates speed and timing of processes.
Neurons Firing Rate)
I/O Devices (Keyboard, Mouse, Monitor, Sensory Organs (Eyes, Ears, Hands, Skin,
Receives input and provides output.
Sensors) Tongue, Nose)
Bus System (Data, Address, Control Nervous System (Neurons, Axons, Transfers data and signals between
Buses) Synapses) components.
 Microprocessor and Buses

Address Bus
From real
world
Input
Memory To real world
Output
8085
MPU

Data Bus

Control Bus
 µp initiated operations

Input Microprocessor Output

• Memory Read
Memory

• Memory Write

• I/O Read

• I/O Write
 Peripheral Communication

• Identify the peripheral / memory location (Address)

• Transfer binary information (Data)

• Provide timing or synchronization signals

 Address Bus
000E
• Group of 16 lines – arbitrary for a µp 000D
000C

• Unidirectional 000B
000A
• µp to peripheral devices / memory 0009
0008
0007
• Identify the peripheral / memory location 0006
0005
0004
• 216 memory
locations (1K = 1024 bits) 0003

64K memory 0002

0001 05
0000 06

Address
 Data Bus

• Group of 8 lines

• Bidirectional

• Transfer binary information (Data)

• Determines what type of µp

• 8085 – 8 bit processor
• 8086 – 16 bit processor
 Control Bus

• Many individual lines

• Provide timing or synchronization signals

• Provide a pulse to indicate a µp operation

• Memory read pulse – activates the memory chip
Break time
Pin out diagram of 8085
 Features of 8085

• 8 – bit general purpose µp

• Can address 64 K memory

• 40 pins

• +5V power supply

• 3 MHz clock frequency

 Signals of 8085 µp

8085

Power supply & Externally

Address Bus Data bus Control & Status Serial I/O
frequency initiated
Pin diagram of 8085
Address Bus

• 16 – address lines

• Split into two segments

A15 – A8 ; A7-A0

• A15 – A8
• Unidirectional – Higher order address

• A7-A0 – Dual purpose

• Lower Address Bus
• Data Bus
Control and Status

• Control : 𝑹𝑫 and 𝑾𝑹

• Status : 𝑰𝑶/ 𝑴, 𝑺𝟏 𝒂𝒏𝒅 𝑺𝟎

Nature of operation

Special signal : ALE

 ALE

• Positive going pulse

• Triggered every time the µp begins an

operation

• Indicates AD7-AD0 as address bits

• Used to Latch the low order address

( From Multiplexed Bus )
• Generates a set of 8 address lines
• A7-A0
 𝑹𝑫 and 𝑾𝑹

• RD
• Selected IO or Memory device has to be read

• Data available on the bus

• WR
• Data available on the bus - written in the
se𝐥𝐞𝐜𝐭𝐞𝐝 𝐈/𝐎 𝐨𝐫 𝐌𝐞𝐦𝐨𝐫𝐲 𝐥𝐨𝐜𝐚𝐭𝐢𝐨𝐧
 ഥ
𝐈𝐎/ 𝐌

• S𝒕𝒂𝒕𝒖𝒔 signal used to differentiate between

I/O and memory operations

• Low – Memory operations

• High – I/O operations

• Combined with 𝑹𝑫 and 𝑾𝑹

 𝐒𝟏 𝐚𝐧𝐝 𝐒𝟎

• Status signals

• Distinguish the various types of operations

• halt, reading, instruction fetching or writing.
 Please download and install the Slido
app on all computers you use

In 8085, the ALE (Address Latch

Enable) signal is used for

ⓘ Start presenting to display the poll results on this slide.

 Please download and install the Slido
app on all computers you use

Which bus determines the

memory capacity of a
microprocessor?

ⓘ Start presenting to display the poll results on this slide.

 Please download and install the Slido
app on all computers you use

The address bus in a

microprocessor is used for

ⓘ Start presenting to display the poll results on this slide.

 Please download and install the Slido
app on all computers you use

8086 is called a 16 bit

microprocessor because it has

ⓘ Start presenting to display the poll results on this slide.

 Please download and install the Slido
app on all computers you use

A microprocessor with a 16-bit

address bus can address up to

ⓘ Start presenting to display the poll results on this slide.

 Power Supply and Clock Frequency

Vcc
+5v power supply
Vss
Ground Reference
XI, X2
A crystal is connected at these two pins.

CLK (OUT)

Used as the system clock for other devices

Externally initiated signals

• INTR / INTA

• RST 7.5 Maskable Interrupts (RST 7.5, RST 6.5,

RST 5.5, INTR) → Can be disabled, used
• RST 6.5 for normal operations.

• RST 5.5 Non-Maskable Interrupt (TRAP) →

Cannot be disabled, used for critical
• TRAP situations.
 Reset Signals

RESET IN’ –
Pin is low(0)
PC is set to zero
Microprocessor unit is reset.

RESET OUT
Indicates that the MPU is being reset.
Can be used to reset other devices.
 DMA Signals
HOLD
• indicates that another device is requesting the use of
the address and data bus
• Relinquishes the use of the buses as soon as the
current machine cycle is completed.
• Removal of the HOLD signal the processor regains the
bus.
HLDA
• Indicates that the hold request has been received
• Removal of a HOLD request, the HLDA goes low.
What Next?
 Architecture

Internal structure and organization

defining how its various components interact to process

instructions
 RST RST RST
INTR 𝑰𝑵𝑻𝑨 5.5 7.5 TRAP SID SOD
6.5

Serial I/O
Interrupt Control Control

8 – bit Internal Data Bus

Instruction W Z
Accumulator Temp. reg. Flags

Register Select
Register B C
D E
Instruction H L
Decoder SP (16)
ALU PC (16)
INC / DEC
(16)

X1

Timing and Control Circuit Address

Data and
Address
X2 Buffer Buffer

ഥ
𝑰𝑶/ 𝑴 𝑹𝑫 𝑾𝑹 ALE S1 S0 HOLD CLK OUT 𝑹𝑬𝑺𝑬𝑻 𝑰𝑵 Ready Address Bus Data Address Bus
HLDA RESET OUT A8 – A15 AD0 – AD7
 Instruction
Accumulator Temp. reg. Flags
Register

Instruction
Decoder
ALU

X1

Timing and Control Circuit

X2

ഥ
𝑰𝑶/ 𝑴 𝑹𝑫 𝑾𝑹 ALE S1 HOLD CLK OUT Reset S0 Ready
 RST RST RST
INTR 𝑰𝑵𝑻𝑨 5.5 7.5 TRAP SID SOD
6.5

Serial I/O
Interrupt Control Control

8 – bit Internal Data Bus

Instruction W Z
Accumulator Temp. reg. Flags

Register Select
Register B C
D E
Instruction H L
Decoder SP (16)
ALU PC (16)
INC / DEC
(16)

X1

Timing and Control Circuit Address

Data and
Address
X2 Buffer Buffer

ഥ
𝑰𝑶/ 𝑴 𝑹𝑫 𝑾𝑹 ALE S1 S0 HOLD CLK OUT 𝑹𝑬𝑺𝑬𝑻 𝑰𝑵 Ready Address Bus Data Address Bus
HLDA RESET OUT A8 – A15 AD0 – AD7
 Timing and Control Unit

• Synchronizes all microprocessor operations with the clock

• Generates the control signals necessary for communication

• Between and µp and peripherals

• 𝑹𝑫 and 𝑾𝑹
• Indicate the availability of data on the data bus
 Registers

• Accumulator
• Register Array
• General Purpose Registers
• Special Registers
• Program Counter
• Stack Pointer
• Flag Register
• Instruction Register
• Temporary Register
 Registers

• Register Array
• GPRs
• B,C,D,E,H,L
• 8 Bit Operations
• HL, BC, DE
• Instruction Register • Register Pair
• Instruction fetched from • 16 bit operations
memory is loaded here • HL – can be used as memory
• Instruction is decoded by the location
instruction decoder • BC, DE – store data
• Not programmable • W, Z
• Temporary registers
• Can’t be accessed by User
• Hold 8 bit data for some
through any instruction instructions
• Unavailable to the
programmer / user
 Instruction Decoding and Execution

• A = 82H

MOV C, A [4FH]
 Flag Register

Sign Flag
• Parity Flag
• Set – AL operation
• Signed Numbers
Set – result has even number of 1s
• Auxiliary Flag • D7 bit of the result is 1
• Set – Carry by D3 to D4 • Carry Flag
Zero Flag
• Used internally for BCD Set – AL
– operation
Arithmetic
operations • =0 operation
• results
Modifiedin ifa contents
carry in
• Unavailable for the programmer
• Also
• Aborrow for subtraction
& registers change

S Z AC P CY

1
 Instruction Format

Add
Operation Code Operand Address
Mode

Add Operand Address Operand Address

Operation Code
Mode 1 2

Add Operand Operand Result

Operation Code
Mode Address 1 Address 2 Address
 Instruction Format
• Single Byte

• Two Byte

• Three Byte
 Machine cycles and Bus timings

• 74 different instructions type

• Instruction = Opcode + Operand

• Opcode : Command (Add, Sub, CPI…)

• Operand: Object to be operated on (Byte / Contents of

register)
 Timings of operations

• Instruction Cycle

• Machine Cycle

• T state
 Machine Cycles
8085 has seven machine cycles

1. Opcode Fetch

2. Memory Read

3. Memory Write

4. I/O Read

5. I/O Write

6. Interrupt Acknowledge

7. Bus Idle
 Instruction Cycle

• Time required to complete the execution of an instruction

• Consists of 1 – 6 Machine Cycles

 Machine Cycle

• Time required to complete one operation of

• Accessing memory
• Accessing I/O
• Acknowledging an external request

• Consists of 3 – 6 T states
 T States

• One subdivision of the operation performed in one clock

period

• Each T state is equal to one clock period

External Communication functions

External Communication
Memory R/W

I/O – R/W

Request
Acknowledge
 Opcode Fetch Machine Cycle

• First operation in any instruction

• Called M1 cycle

• 4 T states
• 3 T – fetch the opcode
• 1T – decode and execute the opcode
Timing Diagram
Opcode Fetch
Timing Diagram
Timing Diagram
Introduction to Microprocessor and Buses: 8085
Hardware Architecture, 8085 Pin out, register
organization, instruction format, addressing
modes, instruction set, programming 8085.
 Question 1

Multiplexing of data bus and address is done to

1. Increase speed of microprocessor

2. Reduce number of pins

3. Connect more peripherals

4. All of the above

 Question 1

T states required for Opcode fetch, MR and MW are

1. 4, 3, 3

2. 3, 3, 3

3. 3, 4, 3

4. 3, 3, 4
The flags get affected after

1. Arithmetic Operation

2. Logical Operation

3. Both (1) and (2)

4. Data Transfer operation

 Recap

• Instruction cycle
• Machine Cycle
• T state
• Timing Diagram
CALL 16-bit address (Call a subroutine)

1.Opcode Fetch
2.Memory Read (Low byte of address)
3.Memory Read (High byte of address)
4.Stack Write (Low byte of PC)
5.Stack Write (High byte of PC)
6.Memory Read (Opcode at subroutine location)
Timing Diagram – MVI A, 32 H
 Calculation of execution times

• Clock frequency (f) = 2MHz

• T state = Clock Period (1/f) = 0.5µs
• Opcode Fetch : 4T = 4 X 0.5µs = 2µs
• Memory Read : 3T = 3 X 0.5µs = 1.5µs
• Execution time for instruction : 7T = 7 X 0.5µs = 3.5µs
Assume A = 55 H