SCHOOL OF COMPUTER SCIENCES
SEMESTER 2 ACADEMIC SESSION 2024/2025
Course Planner
Course Code CST236
Course Title Digital Systems Design
E-Learning Portal http://elearning.usm.my
Course Instructors 1. Dr. Mohd Nadhir Ab Wahab (Room 525)
2. Dr. Azman Ab Malik (Room 526)
E-Mail
[email protected] [email protected]Course Units 3
Unit Division Meeting Hours
Lectures 2 2 hours x 14 weeks
Labs/Tutorials 1 2 hours/1 hour x 14 weeks
Examinations 50% (2 hours)
Breakdown of Assessments
Coursework 50%
Coursework Evaluation Basis Assignments, Tests and Pactical Test
Type of Course Elective (Core)
Prerequisite (if any) -
Objective This course aims are to make sure student able to analyze, design, and evaluate digital system
circuits, of medium complexity, that are based on microcontroller interfacing with Hardware
Development Kit and related electronic devices to construct a functional digital system
Learning Outcomes At the end of this course the students will be able to:
1. Distinguish the fundamentals needed in designing a digital system. [PLO1, C4]
2. Construct a working digital system. [PLO2, P4, CTPS1]
3. Apply suitable techniques to design a digital system. [PLO3, C3, CTPS1]
Main References 1. J. F. Wakerly, Digital Design: Principles and Practices, 5th Ed., Pearson, 2018, ISBN-13:
978-0134460093
Additional References 1. D. Harris & S. Harris, Digital Design and Computer Architecture, 2nd Ed., Elsevier,
2013, ISBN-13: 978-0123944245
2. T. L. Floyd, Digital Fundamentals, 11th Ed., Pearson, 2016, ISBN-13: 978-1292075983
3. M. M. R. Mano & M. D. Ciletti, Digital Design: With an Introduction to the Verilog HDL,
VHDL, and SystemVerilog, 6th Ed., Pearson, 2018, ISBN-13: 978-0134549897
BLS - Course Syllabus and Planner
Weeks Topics Ref P&P SLT
F2F NF2F
Fizikal Sync (Online)
Lect. Lab/Tut Lect. Lab/Tut Async. (Online)
1 Review of Number Chap. 2.1, 2.3, 3 4
Systems and Codes 2.4,2.8, 2.9
1.1 Introduction to
Digital Design
1.2 Positional Number
Systems
1.3 General Positional-
Number-System
Conversions
1.4 Addition and
Substraction of
Nondecimal Numbers
1.5 Binary
Multiplication
1.6 Binary Division
2 Review of Boolean Chap. 3.2, 3.3 3 4
Algebra and Logic
Functions
2.1 Laws of Boolean
2.2 Boolena Algebra
Truth Tables
2.3 Boolean Algebra
Examples
2.4 Logic AND Function
2.5 Logic OR Function
2.6 Logic NOT Function
2.7 Logic NAND
Function
2.8 Logic NOR Function
3 Review of Logic 1 3 4
Families
3.1 Introduction to Assignment 1
Logic Families [Week 3]
3.2 Bipolar Logic
Family
3.3 Unipolar Logic
Family
3.4 Classicfication of
Logic Family
4,5 Combinational Chap. 4.1, 4.2, 2 2 2 6
Functions 4.3, 4.4
4.1 Combinational
Logic Design Principles
Circuit Descriptions
and Designs
4.2 Circuit
Manipulations
4.3 Karnaugh Maps
(KMAP)
4.4 Timing Hazards
6,7 Analysis of Sequential Chap. 6.1, 6.4, 2 2 2 6
Circuits 6.5, 6.7, 6.9,
5.1 Gate Symbols and 6.11 Assignment 1 12
Buses Due
5.2 Decoders and [Week 6] 4
Encoders
5.3 Multiplexers Test 2 (1 hour)
5.4 Comparators [Week 7]
5.5 Combination
Multipliers
BREAK
9,10 Finite State Chap. 7.2, 7.3, 2 2 2 6
Machines 7.4, 7.5, 7.8,
6.1 Latches and Flip- 8.1 Assignment 2 10
Flops
[Week 10]
6.2 Clocked
Synchronous State
Machines
6.3 State Diagrams
6.4 State Machine
Decomposition
6.5 Standards for
Specifying State
Machine Descriptions
11,12 Designing with Chap. 8.2, 8.3, 2 2 2 6
Sequential MSIs 8.4, 8.5, 8.6
7.1 Multibit Registers Assignment 2
and Latches Due
7.2 Sequential PLD
[Week 12]
7.3 Counters
7.4 Shift Registers
7.5 Iterative vs
Sequential Circuits
13,14,15 Design of Digital Chap. 8.7, 8.8, 2 4 4 10
Systems 8.9, 9.1, 9.2,
8.1 Synchronous Design 9.3, 9.4, 9.5 Test 2 (1 hour) 3
Methodology [Week 14]
8.2 Impediments to
Synchronous Design
Practical Test 35
8.3 ROM (1 hour)
8.4 RWM [Week 15]
8.5 CPLD
Total Contact Hours (SLT) 0 28 18 46
% eLearn element # SLT
40 Content 8 16 Lectures
20 Activities 5 10 Lab Sessions
Assessment
40 5 5 Assignments Tests Pratical Test
(formative)
100 TOTAL 18 31
