US007961 132B1

(12) United States Patent (10) Patent No.: US 7.961,132 B1

Perry et al. (45) Date of Patent: Jun. 14, 2011
(54) SAMPLING SWITCH AND CONTROLLER (56) References Cited
U.S. PATENT DOCUMENTS
(75) Inventors: Raymond T. Perry, South San 6,144,330 A * 1 1/2000 Hoffman et al. .............. 341,166
Francisco, CA (US); Jesper 6,667,707 B2* 12/2003 Muecket al. ...... ... 341,172
Steensgaard-Madsen, San Jose, CA 7.450,041 B2 * 1 1/2008 Lin et al. ....................... 341,118
(US) * cited by examiner
Primary Examiner — Peguy JeanPierre
(73) Assignee: Linear Technology Corporation, (74) Attorney, Agent, or Firm — Patent Law Group LLP:
Milpitas, CA (US) Brian D. Ogonowsky
(57) ABSTRACT
(*) Notice: Subject to any disclaimer, the term of this In one embodiment, an A/D converter samples an analog
patent is extended or adjusted under 35 input signal voltage by applying, the input signal to a first
U.S.C. 154(b) by 5 days. capacitor terminal, while a second capacitor terminal is con
nected to ground via an NMOS sampling Switch, to charge the
capacitor to the input signal Voltage. During an analog-to
(21) Appl. No.: 12/699,794 digital conversion process, the second capacitor terminal may
Swing in a Voltage range that extends below ground. A con
(22) Filed: Feb. 3, 2010 troller circuit provides bias Voltage signals to a gate terminal
and to a p-well of the NMOS sampling switch, to selectively
turn the sampling Switch on and off. In a first step of a
multi-step sampling process, the controller very quickly dis
(51) Int. Cl. charges the gate terminal to ground to isolate a quantity of
charge on the second capacitor plate. In a Subsequent step of
H03M I/2 (2006.01) the sampling process, the controller circuit applies a negative
(52) U.S. Cl. ........................................ 341/172: 341/155 Voltage to the gate terminal and p-well to ensure that the
(58) Field of Classification Search .................. 341/155, quantity of change is substantially preserved during the ensu
341 / 172 122, 134, 136. 139 63 ing analog-to-digital conversion process.
See application file for complete search history. 30 Claims, 4 Drawing Sheets

VREF

VSS Controller VDD

U.S. Patent Jun. 14, 2011 Sheet 1 of 4 US 7.961,132 B1

VREF
VSS

Vinp

Vinn

VSS
VREF
U.S. Patent Jun. 14, 2011 Sheet 2 of 4 US 7.961,132 B1

SWG

VSS VDD PW VSS 8

R CIN
MS2
| P: N+ P. N. N--
S46 S42 N3s N32 33

Fig. 4
U.S. Patent Jun. 14, 2011 Sheet 3 of 4 US 7.961,132 B1

WDD
MS5

CONTROL IN

MC3

Fig. 5

2.5V - - - - - 6
CONTROL IN

Time (ins)
Fig. 6
 US 7,961,132 B1
1. 2
SAMPLING SWITCH AND CONTROLLER will not be formed in a p-doped region between the n-doped
drain and source regions. These requirements may be difficult
FIELD OF THE INVENTION to meet when the sampling Switch is subject to Voltage Swings
that may exceed an upper and/or a lower boundary of a power
This invention relates to analog-to-digital (A/D) converters Supply Voltage range.
and, in particular, to a sampling Switch in an A/D converter What is needed is a sampling switch that can be used to
and its controller, wherein the sampling Switch can be con accurately sample an analog input signal Voltage and remain
trolled to be substantially non-conductive for a Voltage range Substantially non-conductive during a period of time when an
that exceeds a power Supply Voltage range. integrated circuit performs a certain function, for example an
10 analog-to-digital conversion process. What is needed is a
BACKGROUND sampling Switch that can be turned off very quickly, and be
controlled to be substantially non-conductive with respect to
In a successive approximation register (SAR) analog-to a predefined Voltage range that exceeds a boundary of a power
digital converter, capacitors in a capacitor array are charged to Supply Voltage range.
an instantaneous value of an analog input signal Voltage at a 15
sampling instant by operation of a sampling Switch. To lockin SUMMARY
the value of the analog input signal Voltage at the sampling
instant, the sampling Switch is opened. The locked-in value of A sampling Switch and its controller are described in a
the analog input signal Voltage may be referred to as the context of a Successive-approximation-register (SAR) ana
sampled analog input Voltage. During a Subsequent analog log-to-digital converter. The invention also applies to other
to-digital conversion process, a plurality of conversion types of analog-to-digital converters, and more generally to
Switches connected to the capacitors are controlled to effec any type of sampled-data analog signal processing circuit.
tively generate a series of comparison Voltages. The compari An analog input signal Voltage is applied via an input
son Voltages are successively selected, generated, and com terminal across a capacitor during a tracking mode of opera
pared to the sampled analog input Voltage to determine 25 tion when a sampling control signal is low. A sampling Switch
whether the sampled analog input voltage is higher or lower is opened at a sampling instant, marked by a triggering (tran
than each generated comparison Voltage. Each new compari sition from low to high) of the sampling control signal, which
son Voltage in a series of comparison Voltages is based on samples (locks in) an instantaneous value of the analog input
comparisons made of the sampled analog input Voltage and signal Voltage. The instantaneous value of the analog input
previous comparison Voltages in the series. A series of com 30 signal Voltage may be referred to as the sampled analog input
parison Voltages may start with a first comparison Voltage that Voltage. At (or shortly after) the sampling instant, an input
is in the middle of the highest and lowest values within a switch is opened to substantially isolate the capacitor from
nominal analog input Voltage range. For example, if the the input terminal, and an analog-to-digital conversion pro
sampled analog input Voltage is detected as being higher than cess of the sampled analog input Voltage is then initiated. At
the first comparison Voltage, a first bit of a digital code is set 35 the time of triggering the sampling control signal, a function
to a one, and a second comparison Voltage in the series of of the sampling Switch is to open (to become Substantially
comparison Voltages may be generated as the first compari non-conductive) to effectively isolate, or lockin, a quantity of
son voltage increased by one fourth (4) of the span of the charge on a plate of the capacitor. The quantity of charge
nominal analog input Voltage range. Continuing the example, represents the sampled analog input Voltage, and it must be
if the sampled analog input Voltage Subsequently is detected 40 Substantially preserved (isolated) during an analog-to-digital
as being lower than the second comparison Voltage, a second conversion process. The requirement of isolating the quantity
bit in the digital code is set to Zero, and a third comparison of charge may be difficult to meet when the plate of the
Voltage in the series of comparison Voltages may be generated capacitor on which the charge is located may swing in a
as the second comparison Voltage decreased by one eighth Voltage range that exceeds an upper and/or a lower boundary
(/s) of the span of the nominal analog input Voltage range. By 45 of a power Supply Voltage range. Such voltage Swings may
using a successive-approximation algorithm repeatedly (se occur during the analog-to-digital conversion process, for
lecting, generating and comparing a series of comparison example, if the capacitor is coupled between the input termi
Voltages to Successively approximate a sampled analog input nal and a power Supply Voltage rail during the tracking mode
Voltage) a digital representation of the sampled analog input of operation. Coupling the capacitor between the input termi
Voltage can be made to have substantially any resolution. 50 nal and a power Supply Voltage rail may be preferable for
The sampling Switch must be substantially non-conductive implementing low-power analog-to-digital converters that
during the Successive-approximation analog-to-digital con consume very little power (ideally Zero power) during the
version process, so that the sampled analog input Voltage can tracking mode of operation.
be preserved and compared accurately to each Voltage in the In the event the sampling Switch becomes Substantially
series of comparison Voltages. If a junction-isolated MOS 55 conductive during the analog-to-digital conversion process,
FET transistor is used as a sampling Switch, its pnjunction the isolated quantity of charge may be affected, and the ana
diodes must not become forward-biased enough to cause log-to-digital conversion process may yield an inaccurate
Substantial conduction when the sampling Switch is open, or result.
else the analog-to-digital conversion process may yield an In one embodiment of the invention, the sampling Switch is
inaccurate result. For example, if the sampling Switch is 60 implemented as a junction-isolated NMOS transistor imple
implemented as a junction-isolated NMOS transistor, a pn mented in a p-well that can be biased at a Voltage that may be
junction diode formed by a p-doped Substrate (or a p-doped substantially different than a voltage that a silicon substrate is
well) and an n-doped drain or source region must not become biased at. A controller circuit provides biasing Voltage signals
Substantially forward-biased during the conversion process. to a gate terminal of the NMOS transistor and also to the
Furthermore, during the analog-to-digital conversion pro 65 p-well. The biasing Voltage signals provided by the controller
cess, a gate Voltage applied to the NMOS sampling Switch exceed a power Supply Voltage range (a range of Voltages
must be sufficiently low to ensure that a conductive channel limited by a low power Supply Voltage and a high power
 US 7,961,132 B1
3 4
Supply Voltage used to power the analog-to-digital converter), p-well bias voltage signals to control an NMOS sampling
in order to prevent a pnjunction diode from becoming Sub switch in accordance with one embodiment of the invention.
stantially conductive, and also to prevent a Substantially con FIG. 4 is a cross-sectional view of a junction-isolated
ductive channel from forming under the gate terminal. NMOS transistor that may be used as a sampling switch in
A drain terminal and a source terminal of the NMOS tran 5 accordance with one embodiment of the invention.
sistor are each one of two Switch terminals of the sampling FIG. 5 is a schematic of a controller that provides gate and
Switch. During the tracking mode of operation, each of the p-well bias voltage signals to control an NMOS sampling
Switch terminals are biased at Voltages that are substantially switch in accordance with one embodiment of the invention.
the same as the low power Supply Voltage. In the tracking 10
FIG. 6 illustrates simplified waveforms of a control signal
mode of operation, the controller couples the gate terminal of and gate and p-well bias Voltage signals generated by the
the NMOS transistor to the high power supply voltage rail to controller of FIG. 5 in accordance with one embodiment of
establish a conductive channel between the switch terminals. the invention.
The controller implements a multi-step sampling process. FIG. 7 illustrates the controller of FIG. 5 along with
In a first step of the sampling process, the gate terminal of the 15 approximate Voltage levels during a tracking mode of opera
NMOS transistor is switched very quickly from the high tion when the sampling Switch is on.
power Supply Voltage to the low power Supply Voltage, caus FIG. 8 illustrates the controller of FIG. 5 along with
ing the conductive channel to Substantially disappear (mak approximate Voltage levels during a conversion mode of
ing the sampling Switch Substantially non-conductive). The operation when the sampling Switch is off.
input Switch is opened to Substantially isolate the capacitor Elements that are the same or equivalent are labeled with
from the input terminal. In a Subsequent step of the sampling the same numeral.
process, which occurs before the sampling Switch terminals
become subject to Voltages that may substantially exceed the DETAILED DESCRIPTION
power Supply Voltage range, the controller applies a low bias
voltage to the gate terminal and to the p-well of the NMOS. 25 FIG. 1 illustrates a SAR analog-to-digital converter I0 in
The low bias voltage (below the low power supply voltage) is accordance with one embodiment of the invention. Many
applied to ensure that the sampling Switch will remain Sub different types of analog-to-digital converter principles and
stantially non-conductive with respect to a nominal range of methods may be used with the inventive sampling Switch and
Voltages (exceeding the power Supply Voltage range) that the controller.
Switch terminals may become Subject to during the analog 30 The general operation of SAR analog-to-digital converters
to-digital conversion process. is well known and extensively described in many publica
The first step of the sampling process may be completed tions. Accordingly, only a general description of the operation
very quickly (as quickly as the semiconductor process, and of a SAR analog-to-digital converter is presented below to
other engineering aspects, reasonably allow for) to ensure provide context for the inventive sampling Switch and con
that the quantity of charge isolated on the capacitor will 35 troller.
represent the instantaneous analog input Voltage with Suffi In a tracking mode of operation of the analog-to-digital
cient accuracy. The speed at which the low bias Voltage is converter 10 shown in FIG. 1, an analog input signal Voltage
subsequently applied to the NMOS switch may not be critical YIN is applied across a capacitor CIN via an input switch SI
for the overall accuracy of the conversion process, as long as and a sampling Switch S2. Input Switch S1 selectively couples
it is done before the switch terminals are made subject to 40 an input plate of capacitor CIN to an input terminal. Sampling
Voltages that may otherwise have caused a material change in switch S2 selectively couples a second plate of capacitor CIN
the quantity of charge isolated on the capacitor. Propertiming to a low power supply voltage rail (VSS-OV). The analog
may be used to coordinate the sampling process with the input signal voltage VIN is defined from the input terminal to
analog-to-digital conversion process, to ensure that a digital the low power Supply Voltage rail (may also be referred to as
code provided by the analog-to-digital converter is accurate 45 ground, VSS, or OV).
to within one least significant bit (LSB). In a process of sampling an instantaneous value of the
The sampling switch may also be a PMOS transistor or analog input signal Voltage VIN, the sampling Switch S2 is
another type of semiconductor device. When using a PMOS opened at a sampling instant, which Substantially isolates
sampling switch, the circuit may be implemented in a CMOS (locks in) a quantity of charge on the second plate of capacitor
process based on a p-doped Substrate and providing n-doped 50 CIN. The instantaneous value of the analog input signal Volt
wells in the p-doped substrate for the implementation of the age at the sampling instant may be referred to as the sampled
PMOS sampling switch. analog input Voltage. At (or shortly after) the sampling
The invention is also advantageous for controlling a gate instant, input Switch S1 is opened to Substantially isolate
terminal of a MOSFET sampling switch implemented in a capacitor CIN from the input terminal. A conversion switch
silicon-on-insulator (SOI) semiconductor process. 55 C1 is then closed to Successively apply a series of comparison
voltages VDAC to the input plate of capacitor CIN as part of
BRIEF DESCRIPTION OF THE DRAWINGS a successive-approximation analog-to-digital conversion
process.
FIG. 1 is a schematic of one type of SAR analog-to-digital At the end of the analog-to-digital conversion process, a
converter employing the sampling Switch and controller in 60 digital circuit 14 (that for simplicity and general practice will
accordance with one embodiment of the invention. be referred to as a successive-approximation-register or SAR)
FIG. 2 illustrates in more detail an analog section of a provides a digital code representing the sampled analog input
differential SAR analog-to-digital converter employing the Voltage with a certain resolution. The resolution may be char
sampling Switch and controller in accordance with one acterized by a size of a least significant bit (LSB). A maxi
embodiment of the invention. 65 mum digital code represents a high-end boundary of a nomi
FIG. 3 illustrates the SAR analog-to-digital converter of nal full-scale input Voltage range, which substantially equals
FIG. 1 with a controller that may be used to provide gate and a reference voltage VREF. A minimum digital code repre
 US 7,961,132 B1
5 6
sents a low-end boundary of the nominal full-scale input to be inaccurate if it differs from an ideal digital code by more
voltage range, which substantially equals VSS-OV. than 1 LSB. An aspect of one embodiment of the invention is
The analog-to-digital conversion process involves a series that sampling Switch S2 will remain substantially non-con
ofevaluations whereby each Voltage in a series of comparison ductive when the terminals of sampling Switch S2 Swing in
Voltages is effectively compared to the sampled analog input the voltage range from -VREF/2 to +VREF/2. This aspect is
Voltage. Each series of comparison Voltages is selected and an important feature for its use in analog-to-digital converters
controlled by the SAR circuit 14. The first voltage in each wherein (as shown in FIG. 1) the sampling switch is biased at
series of comparison Voltages may be a default initial value a power Supply Voltage during a tracking mode of operation.
VREF/2. The second voltage in a series of comparison volt DAC 16, SAR14, and comparator 12 may be in a power-down
ages depends on the first voltage in the series and an outcome 10 (or sleep) mode during the tracking mode of operation,
of an evaluation performed by a comparator circuit 12. For whereby the entire circuit 10 may consume very little (sub
example, if comparator circuit 12 determines that the sampled stantially Zero) power when it is tracking the input signal VIN.
analoginput Voltage is higher that the first Voltage in the series A low-power mode of operation may also be used.
of comparison voltages, then SAR 14 will select a second Those who are skilled in the art will recognize that capaci
Voltage in the series that is higher than the first Voltage. In the 15 tor CIN may be implemented as a plurality of capacitors and
alternate case, if comparator circuit 12 determines that the that DAC 16 and conversion switch C1 may be a plurality of
sampled analog input Voltage is lower than the first Voltage in Switches controlled to connect individual capacitors in the
the series of comparison voltages, then SAR 14 will select a plurality of capacitors to either the reference voltage VREF or
second Voltage in the series that is lower than the first Voltage. VSS-OV. It will also be recognized that the analog-to-digital
The process continues for a number of Successive steps of converter 10 may easily be generalized to a fully differential
iteration/approximation, wherein SAR14 selects a third com circuit structure and/or modified in a number of other ways.
parison Voltage based on an evaluation of the selected second FIG. 2 illustrates an analog section of a 6-bit fully differ
comparison Voltage and the sampled analog input Voltage; ential SAR analog-to-digital converter, having a non-invert
SAR 14 then selects a fourth comparison voltage based on an ing input terminal Vinp and an inverting input terminal Vinn.
evaluation of the selected third comparison Voltage and the 25 The analog input signal voltage VIN is fully differential,
sampled analog input Voltage; the approximation process VIN=Vinp-Vinn, having a common-mode Voltage compo
continues in this manner for a number of steps. SAR 14 may nent, VCM=(Vinp+Vinn)/2, that is substantially constant and
use a step size (difference between one comparison Voltage nominally equal to VREF/2. Each of the two input terminals
and the next comparison Voltage in a series) that is a progres are coupled to an array of binary-weighted capacitors; each
sively smaller quantity for each step in the approximation 30 array comprises 7 individual capacitors with relative weights
process. For example, the step size may be VREF/4 in a first of respectively C/2, C/4, C/8, C/16, C/32, C/64, and C/64. A
step, VREF/8 in a second step, VREF/16 in a third step, and so total capacitance of each array is C. A first array of capacitors
on. Accordingly, SAR 14 controls a Successive-approxima is coupled to the non-inverting input terminal Vinp via a first
tion analog-to-digital conversion process (Successively array of input Switches 20. A second array of capacitors is
reducing a nominal worst-case absolute difference between 35 coupled to the inverting input terminal Vinn via a secondarray
the sampled analog input Voltage and each Voltage in a series of input switches 22. Input switches 20.22, serve substantially
of comparison Voltages), to determine a digital representation the same function as input switch S1 in FIG. 1 does. The first
of the sampled analog input Voltage. SAR 14 may implement array of capacitors is connected to a first array of conversion
any one of a variety of more-or-less advanced successive Switches 24. The second array of capacitors is connected to a
approximation algorithms. Specific details of Such algo 40 second array of conversion switches 26. The conversion
rithms are not important for understanding and/or utilizing switches 24, 26 are used to selectively couple individual
this invention. capacitors in the two arrays of capacitors to either the refer
A digital-to-analog converter (DAC) 16 generates the com ence voltage VREF or VSS=OV. Conversion switches 24, 26
parison Voltages VDAC selected by SAR 14. A conversion serve substantially the same function as switch C1 and DAC
Switch C1 is closed during the analog-to-digital conversion 45 16 in FIG. 1 do. A commonplate of the first array of capacitors
process (prefix“C” is used to identify switches that are closed and a common plate of the second array of capacitors can be
during the analog-to-digital conversion process, and prefix selectively connected to one another and to VSS via a plural
“S” is used to identity switches that are closed during the ity of sampling Switches marked S in FIG. 2. Sampling
tracking mode of operation). A comparison Voltage VDAC is switches S in FIG. 2 serve substantially the same function as
applied via conversion Switch C1 to the input plate of capaci 50 sampling switch S2 in FIG. 1 does. A comparator 28 in FIG.
tor CIN, and a polarity of a voltage VX (defined with respect 2 serves Substantially the same function as comparator 12 in
to VSS-OV) of the second plate of capacitor CIN is indicative FIG. 1 does. A SAR circuit (not shown in FIG. 2) controls
of a difference between the comparison voltage VDAC and conversion switches 24, 26 to effectively apply a series of
the sampled analog input Voltage. Specifically, if comparison differential comparison Voltages across the first and second
Voltage VDAC is higher than the sampled analog input Volt 55 arrays of capacitors. During an analog-to-digital conversion
age, then comparator 12 will detect that voltage VX is higher process, Sampling Switches S will be subject to terminal Volt
than VSS. SAR 14 uses this determination to select a next ages that may Swing in a nominal Voltage range Substantially
comparison Voltage. from -VREF/2 to +VREF/2. Sampling switches S are imple
For an input signal voltage VIN within a full-scale input mented according to the present invention to facilitate that
voltage range from OV to VREF, Voltage VX may swing 60 they are Substantially non-conductive when made Subject to
substantially in a voltage range from -VREF/2 to +VREF/2 Such terminal Voltages during the analog-to-digital conver
during the analog-to-digital conversion process. In the event sion process. Further details regarding the operation of a
sampling Switch S2 becomes Substantially conductive during differential SAR A/D converter is provided in U.S. Pat. No.
the conversion process, the quantity of charge nominally iso 6,667.707, incorporated herein by reference.
lated on the second plate of capacitor CIN may change, and 65 There are several other types of analog-to-digital convert
the analog-to-digital conversion process may yield an inac ers than those described above. FIGS. 1 and 2 are merely
curate digital code (result). A digital code may be considered examples of circuits in which the present invention may be
 US 7,961,132 B1
7 8
incorporated advantageously. Sampling Switches are also voltage VSS-OV. Furthermore, during tracking mode of
used in many sampled-data analog signal-processing circuits operation, a charge pump capacitor CP is charged to the
that do not perform a data conversion process (for example, a power supply voltage VDD. A positively-charged plate of
Switched-capacitor filter). Accordingly, sampling Switches, charge pump capacitor CP is coupled to the high power Sup
S2 in FIG. 1, and S in FIG. 2, and their controller, are in 5 ply voltage rail VDD via a switch S4, which is closed during
accordance with the present invention. The invention may be tracking mode of operation. A negatively-charged plate of
incorporated in many different types of circuits and applica charge pump capacitor CP is connected to node PW, which is
tions. coupled to VSS via switch S3 during tracking mode of opera
FIG.3 illustrates the analog-to-digital converter 10 of FIG. tion. When a control signal (not shown) is triggered, a sam
1, wherein sampling switch S2 is implemented as an NMOS 10 pling process occurs followed by an analog-to-digital conver
transistor MS2. A gate terminal of NMOS MS2 is connected sion process. The sampling process may be described as a
to a node SWG. NMOS MS2 is implemented in a p-well three-step process. In a first step of the sampling process,
connected to a node PW. A controller circuit 30 applies bias switch S5 is opened and a switch C3 closed, which very
voltage signals to nodes SWG and PW to selectively turn quickly changes the bias voltage at node SWG from substan
NMOS sampling switch MS2 on and off. 15 tially VDD to substantially VSS. In a second step of the
FIG. 4 shows a cross-sectional view of NMOS transistor sampling process, switch S3 is opened, whereby nodes PW
MS2. NMOS MS2 has a source region 32 that is strongly and SWG are effectively connected to the negatively-charged
doped n-type, and a drain region 33 that is strongly doped plate of charge-pump capacitor CP. In the second step of the
n-type. The source and drain regions 32, 33 are formed in a sampling process, bias voltages at nodes PW and SWG are
p-well 36 that is lightly doped p-type. The p-well 36 may be 20 substantially the same (because switch C3 is closed) and
formed in any region doped n-type, including an n-type semi approximately OV. In a third step of the sampling process,
conductor substrate. FIG. 4 shows that p-well 36 may be switch S4 is opened and a switch C2 is closed to change the
implemented in an n-well 40 that is lightly doped n-type. bias Voltage of the positively-charged plate of charge-pump
N-well 40 is implemented in a p-type substrate 44 that is capacitor CP substantially from VDD to VSS. The negatively
lightly doped p-type. In the application (FIG. 3), source 25 charged plate of capacitor CP will thereby transition from
region 32 is connected to VSS-OV. and drain region 33 is substantially VSS to a negative bias voltage (below
connected to capacitor CIN. P-well 36 has a contact region 38 VSS-OV). The negative bias voltage depends on the power
that is strongly doped p-type, which couples p-well 36 to node Supply Voltage VDD and also a capacitive loading repre
PW. N-well 40 has a contact region 42 that is strongly doped sented by nodes PW and SWG relative to a capacitance of
n-type, which couples n-well 40 to the high power supply 30 charge pump capacitor CP. For example, if the capacitive
voltage rail (VDD). P-type substrate 44 has a contact region loading represented by nodes PW and SWG is negligible, the
46 that is strongly doped p-type, which couples substrate 44 negative bias voltage may be substantially minus the power
to the low power supply voltage rail (VSS-OV). A gate ter supply voltage (-VDD). For simplicity, and without loss of
minal (plate) 48 is Substantially isolated from an underlying generality, it will be assumed that the capacitive loading of CP
channel region. If gate 48 is biased at a Voltage that is high 35 is negligible. Those who are skilled in the art know how to
enough to invert the channel region, a conductive channel will design a charge pump circuit to provide a Suitable negative
beformed between the source and drain regions 32.33 (effec bias Voltage to meet specific needs of specific applications.
tively turning on the sampling switch NMOS MS2). This exemplary embodiment describes a specific charge
To ensure accurate analog-to-digital conversion results, a pump structure that is suitable for this embodiment, as well as
quantity of charge that is being Substantially isolated on the 40 many other embodiments. Specifically, the charge pump pro
second plate of capacitor CIN (connected to drain region33) vides a negative bias voltage of approximately-VDD, which
by the sampling process must be preserved during the ensuing may be sufficiently low to ensure that the isolated quantity of
analog-to-digital conversion process. The isolated quantity of charge is preserved with Sufficient accuracy for reference
charge may be detrimentally affected (causing a loss of over voltages VREF of up to 2VDD. In one embodiment, VDD
all accuracy) if a pn junction diode in an interface region 45 may be 2.5V and VREF may be 4.096V.
between p-well 36 and n-type drain region 33 becomes sub The three-step sampling process facilitates Substantially
stantially forward-biased during the conversion process. To accurate sampling of the analog input signal Voltage VIN. The
substantially prevent (or limit to an acceptable level) such sampling Switch MS2 becomes Substantially non-conductive
forward-biasing, node PW and thereby p-well 36 is biased at during the first step of the sampling process, which advanta
a negative bias voltage (below VSS-OV) during the analog- 50 geously may complete in a very short period of time (for
to-digital conversion process. The isolated quantity of charge example, a hundred pico seconds, or even faster for some very
may also be detrimentally affected (causing a loss of overall fast semiconductor technologies). A quantity of charge is
accuracy) if a Substantially conductive channel is established thereby substantially isolated on the second plate of capacitor
between source and drain regions 32, 33 during the conver CIN. The second and third steps of the sampling process need
sion process. To prevent a conductive channel from forming, 55 not occur similarly fast, as long as they are completed before
node SWG and thereby gate 48 is biased at the negative bias the drain and/or source terminals of sampling switch MS2 are
Voltage during the conversion process. The objective of made Subject to Voltages that may otherwise have caused a
applying negative voltages to nodes SWG and PW is to pre material change in the quantity of charge isolated on CIN. A
serve the isolated quantity of charge to a degree where any timing strategy may be used to limit/reduce worst-case Volt
change of Such charge will not affect a resulting digital code 60 age Swings that may occur at node VX, to ensure that the
by more than 1 least significant bit (LSB). quantity of charge is Substantially isolated until the end of the
Controller 30 in FIG. 3 applies bias voltage signals to analog-to-digital conversion process. For example, it may be
nodes SWG and PW to control sampling switch MS2. During advantageous to openinput Switch S1 immediately after (with
tracking mode of operation, a switch S5 is closed to bias node only little delay) the first step of the sampling process. It may
SWG substantially at the high power supply voltage (VDD). 65 also be advantageous to delay the analog-to-digital conver
Likewise, during tracking mode of operation, a Switch S3 is sion process (applying comparison Voltages by closing
closed to bias node PW substantially at the low power supply Switch C1) until after the three-step sampling process has
 US 7,961,132 B1
10
completed. Depending on specific needs, the three-step Sam is initiated by a transition of CONTROL IN from low to high
pling process may be designed to complete relatively quickly (VSS to VDD). When CONTROL INgoes high, at time 0 in
(in a fraction of a nanosecond), or at a more modest pace (for FIG. 6, PMOS MS5 is turned off and NMOS MC3 is turned
example, 5 to 10 nanoseconds). on. An output voltage at node n1 provided by inverter 38 does
During the analog-to-digital conversion process, Switches not change substantially until after node SWG transitions to
C1, C2, and C3 are on, and Switches S1, S3, S4, and S5 are off. below a threshold voltage. Accordingly, in this first step of the
Nodes SWG and PW are biased at a negative bias voltage, sampling process, MS5 is turned off, MS3 remains on, and
which is sufficiently low to ensure that sampling switch MS2 MC3 is conductive pulling node SWG towards the low power
is substantially non-conductive during the analog-to-digital supply voltage rail (via NMOS MS3). NMOS transistors
conversion process. 10 MC3 and MS3 may be sized such that node SWG will tran
FIG. 5 shows a detailed implementation of controller 30, sition very quickly from VDD to approximately VSS in the
incorporated in the analog-to-digital converter 10 of FIG. 3. first step of the sampling process.
Now comparing FIGS. 3 and 5: switch S5 is implemented as Transistors M4 and M5 effectively implement the function
a PMOS transistor MS5; switch C3 is implemented as an of a traditional inverter circuit as long as node PW is biased at
NMOS transistor MC3; switch S3 is implemented as an 15 approximately OV. Node n2 will, therefore, transition from
NMOS transistor MS3; switch S4 is implemented as a PMOS substantially VDD to VSS a short delay after node SWG
transistor MS4; switch C2 is implemented as an NMOS tran transitions from VDD to VSS. The short delay is sufficiently
sistor MC2. An applied control signal CONTROL IN, a first long to allow node SWG to substantially reach a voltage of
inverter circuit 38, PMOS M4, NMOS M5, and a second VSS, thus completing the first step of the sampling process.
inverter circuit 40 are used to provide bias voltages to control Transistors MC3 and MS3 couple node SWG to node VSS
transistors MS5, MC3, MS3, MS4, and MC2 to provide the during the first step of the sampling process. After the short
described function of switches S5, C3, S3, S4, and C2. delay, node n2 transitions substantially from VDD to VSS,
The operation of controller 30 may be learned more easily thereby turning off MS3 and completing the second step of
by studying FIGS. 3, 5 and 6 in conjunction. FIG. 6 shows the three-step sampling process. Inverter 40 will then change
simplified waveforms of control signal CONTROL IN and 25 state and drive node n3 to substantially VDD, thereby turning
bias voltage signals at nodes SWG and PW in the controller off PMOS MS4 and turning on NMOS MC2. NMOS MC2
30. The low power supply voltage VSS is selected as a refer pulls the positively-charged plate of capacitor CP (node na)
ence potential defining OV, and the high power Supply Voltage substantially from VDD to VSS-OV. causing node PW (con
rail VDD is assumed to be 2.5 volts (expressed with respect to nected to the negatively-charge plate of capacitor CP) to
VSS=OV). 30 transition to a negative bias voltage. MC3 and M5 are con
Control signal CONTROL IN is low (substantially ductive during the third step of the sampling process, and
VSS=OV) during the analog-to-digital converter's 10 track nodes SWG and n2 will substantially track the voltage at node
ing mode of operation, and it is high (Substantially PW as it gradually transitions substantially from VSS to the
VDD=2.5V) during the analog-to-digital conversion process. negative bias Voltage.
CONTROL IN transitions from low to high to start the sam 35 FIG. 8 shows the control circuit 30 of FIG. 5 with addi
pling process. A time axis in FIG. 6, using nanoseconds as a tional text labels identifying approximate Voltages (enclosed
unit of time, defines the sampling instant in time as 0. by “(“and”)') at individual nodes in a steady state after the
FIG. 7 shows the control circuit 30 of FIG. 5 with addi sampling process when CONTROL IN has been high for
tional text labels identifying approximate Voltages (enclosed period of time (conversion mode of operation). The negative
by “(“and”)') at individual nodes in a steady state when 40 bias voltage is assumed to be -VDD=-2.5V, reflecting a
CONTROL IN has been low for a period of time (tracking negligible capacitive loading by nodes PW and SWG.
mode of operation). CONTROL IN=OV turns on PMOS The waveforms shown in FIG. 6 reflect that the sampling
MSS, which will charge node SWG to substantially VDD. switch MS2 may be turned off very quickly (providing a
Inverter 38 translates node SWG as a high input, and drives well-defined and accurate sampling of the value of the analog
node n1 to a low level of substantially VSS=OV. The low level 45 input signal Voltage at the sampling instant), by ensuring that
at node n1 turns on PMOS M4, which will charge node n2 to the first step in the sampling process happens very quickly. In
substantially VDD. Node n2 is connected to a gate terminal of FIG. 6, the first step of the sampling process takes 250 pico
NMOS MS3, which turns on MS3 and thereby bias node PW seconds to complete (from the transition of CONTROL IN),
at substantially VSS=OV. NMOS MC3 and M5 are off (each and the overall sampling process is shown to take approxi
device having a gate-to-source Voltage of Substantially OV). 50 mately 2 nanosecond (8 times as long, but only a small frac
Inverter 40 translates node n2 as a high input, and drives node tion of the duration of the analog-to-digital conversion pro
n3 to a low level of substantially VSS=OV. PMOS MS4 is on, cess). A timing of the sampling process can be optimized to
and NMOSMC2 is off, biasing node na (positively-charged meet specific requirements and objectives for different appli
plate of capacitor CP) at substantially VDD. Accordingly, cations.
node SWG is biased at substantially VDD=2.5V, which is 55 Inverter 38 provides a CMOS logic signal at node n1 that
sufficient to turn on sampling switch MS2 (shown in FIG.3), may be used to control input switch S1 (shown in FIG. 3),
while the drain and source terminals of MS2 are biased at such that S1 opens shortly after the first step of the sampling
substantially OV. Furthermore, node PW is biased at substan process. Nodena is a CMOS logic signal that may be used to
tially OV, which will establish a voltage of approximately OV control the conversion switches (C1 in FIG. 3) and/or SAR
across pn junction diodes (p-well 36 to n-type drain and 60 14. Such that the first comparison Voltage is not applied until
source regions 32, 33 in FIG. 4) that are associated with after SWG and PW have reached the negative bias voltage to
NMOS sampling switch MS2 shown in FIG.3 (making the pn ensure that the sampling switch (MS2 in FIG. 3) will remain
junctions Substantially non-conductive). Charge-pump Substantially non-conductive during the analog-to-digital
capacitor CP is being charged to the power Supply Voltage conversion process.
VDD via PMOS MS4 and NMOS MS3. 65 Control signal CONTROL IN goes low after the analog
As described, FIG. 7 reflects a set of initial conditions for to-digital conversion process is completed, turning on PMOS
control circuit 30, just before the three-step sampling process MS5 and gradually charging node SWG to a voltage of sub
 US 7,961,132 B1
11 12
stantially VDD. MS5 may also charge node PW partially via junction diode having a first junction terminal and a
NMOS MC3, but MC3 becomes substantially non-conduc second junction terminal, the first junction terminal
tive when node PW has been charged to a voltage that is a being coupled to the second capacitor terminal; and
threshold voltage below VSS-OV. Inverter 38 changes state, a controller circuit controlling the sampling Switch, the
providing a low output Voltage at node n1, which will turn on controller circuit comprising a charge pump coupled to
M4 and turn off M5. M4 couples the gate terminal of MS3 the second junction terminal, the charge pump config
(node n2) to VDD, turning on MS3 and thereby coupling node ured for providing a second Voltage to the second junc
PW to VSS=OV. The high level at node n2 causes inverter 40 tion terminal during at least a portion of the analog-to
to drive node n3 to substantially VSS-OV, turning on MS4 digital conversion process when the analog-to-digital
and turning off MC2. Accordingly, the charge-pump capaci 10
converter is evaluating the sampled analog input signal
tor is being charged between VDD (via MS4) and VSS (via value, to prevent the pnjunction diode from becoming
MS3). Substantially conductive so as not to Substantially affect
A body terminal of NMOS transistors MC3, MS3, and M5 an accuracy of the digital code representing the sampled
is connected to node PW. These devices may be implemented analog input signal value.
using the junction-isolation structure also used for NMOS 15
MS2 (shown in FIG. 4). The body terminal is a representation 2. The analog-to-digital converter of claim 1 wherein the
of the p-well 36 which is biased via contact region 38. The analog-to-digital converter is a Successive approximation reg
junction-isolation structure may be simplified in another ister analog-to-digital converter, and wherein the capacitor is
embodiment wherein the sampling switch may be a PMOS one of a plurality of capacitors connected to the sampling
transistor, and the overall system may be implemented in a switch.
CMOS process based on a p-type substrate in which n-wells 3. The analog-to-digital converter of claim 1 wherein a
are created for the implementation of PMOS devices. Sub circuit that is used to evaluate an analog signal during the
stantially all Voltages and doping polarities would be reversed analog-to-digital conversion process is controlled to be in a
in Such an alternative embodiment. power-down mode during the tracking period.
It will be understood that while the sampling process is 25 4. The analog-to-digital converter of claim 1 wherein the
described herein as a series of three steps (to teach the inven sampling switch comprises a MOSFET transistor, and
tion efficiently) the exact same sampling process can be wherein the pnjunction diode is formed by a well region of a
described using fewer or more steps. The number of steps first doping polarity and a drain region of a second doping
used to describe the sampling process, therefore, should not polarity different from the first doping polarity.
be construed as limiting the invention, as it can be described 30 5. The analog-to-digital converter of claim 1 wherein the
and/or modified in any number of ways without departing analog-to-digital converter receives power from a power
from the true spirit and scope of the invention. source providing a first power supply voltage and a second
While particular embodiments of the present invention power Supply Voltage, and wherein said first Voltage is Sub
have been shown and described, it will be obvious to those stantially the same as the first power Supply Voltage, and said
skilled in the art that changes and modifications may be made 35 second Voltage exceeds a power Supply Voltage range limited
without departing from this invention in its broader aspects. by the first power Supply Voltage and the second power Supply
Without limitation, such modifications may include incorpo Voltage.
rating one or more instances of the invention in analog-to 6. The analog-to-digital converter of claim 5 wherein the
digital converters based on various conversion methods and sampling Switch comprises a gate terminal that is biased at a
algorithms (delta-sigma, pipeline, multi-stage, dual-slope, 40 third Voltage during at least a portion of the analog-to-digital
multi-slope, incremental, and so on), and/or incorporating the conversion process when the analog-to-digital converter is
invention in other types of Sampled-data analog signal pro evaluating the sampled analog input signal value, and
cessing circuits that may not perform an analog-to-digital wherein the third Voltage exceeds the power Supply Voltage
conversion (for example, an amplifier or a filter). The inven range.
tion may be implemented in various types of semiconductor 45 7. The analog-to-digital converter of claim 5 wherein the
processes (CMOS, DMOS, BJT, IGBJT, IGFET, JFET, BCD, charge pump comprises a charge-pump capacitor having a
and so on), whether or not such processes utilize junction first charge-pump capacitor terminal and a second charge
isolation to isolate individual devices (including, without pump capacitor terminal, where the first charge-pump capaci
limitation, silicon-on-insulator technologies), and whether or tor terminal is coupled to the first power Supply Voltage and
not such processes are based on a silicon (or, for example, a 50 the second charge-pump capacitor terminal is coupled to the
III-V compound) substrate. The appended claims are to second power Supply Voltage during at least a portion of the
encompass within their scope all Such changes and modifica tracking period, and where said second Voltage is provided by
tions as fall within the true spirit and scope of this invention. coupling the first charge-pump capacitor terminal to the sec
What is claimed is: ond junction terminal.
1. An analog-to-digital converter configured for sampling 55 8. The analog-to-digital converter of claim 1 wherein the
an analog input signal and performing an analog-to-digital analog-to-digital converter comprises a comparator circuit
conversion process to generate a digital code representing a that is in a low-power mode during the tracking period, where
sampled analog input signal value, the analog-to-digital con a power consumption of the comparator circuit in the low
Verter comprising: power mode is at least a factor of ten less than a power
a capacitor having a first capacitor terminal and a second 60 consumption of the comparator circuit when it is in an active
capacitor terminal, the analog input signal being selec mode during the analog-to-digital conversion process.
tively coupled to the first capacitor terminal and a first 9. The analog-to-digital converter of claim 1 wherein the
Voltage being selectively coupled to the second capaci sampling switch comprises a MOSFET transistor compris
torterminal during a tracking period to acquire the ana ing:
log input signal to be sampled on the capacitor, 65 a first semiconductor region of a first doping polarity;
a sampling Switch controlled to lock in the sampled analog a second semiconductor region of a second doping polarity
input signal value, the sampling Switch comprising a pn formed in the first semiconductor region, the second
 US 7,961,132 B1
13 14
semiconductor region being a well region connected to 16. The method of claim 15 wherein the step d comprises
the second junction terminal; the step of
a source region of the first doping polarity formed in the applying a series of comparison Voltages causing the sec
second semiconductor region, the source region being ond plate of the capacitor to Swing in a Voltage range that
biased at the first Voltage during the tracking period; exceeds the power Supply Voltage range for at least some
a drain region of the first doping polarity formed in the analog Voltage signal values within a nominal input
second semiconductor region, the drain region being range.
connected to the first junction terminal; and 17. The method of claim 16 wherein the sampling switch
a gate plate proximate to a channel region in the second and the control bias Voltage are selected to ensure that an error
semiconductor region between the source region and the 10
resulting from a detrimental change in the quantity of charge
drain region. corresponds to a change in the digital code of at most one least
10. The analog-to-digital converter of claim 1 wherein the significant bit.
sampling switch comprises an NMOS transistor, and wherein 18. The method of claim 14 wherein
the second Voltage is lower than any Voltage provided by a step a comprises the step of charging a second capacitor by
power source providing power to the analog-to-digital con 15
Verter. Selectively coupling a first terminal of the second capaci
11. The analog-to-digital converter of claim 1 wherein the tor to the first power supply voltage rail and selectively
sampling Switch comprises a semiconductor device having a coupling a second terminal of the second capacitor to the
gate terminal, and wherein second power Supply Voltage rail; and wherein
a first path with controllable conductivity selectively step c comprises the step of coupling the first terminal of
couples the gate terminal to a first power Supply Voltage the second capacitor to the control terminal.
to lock in the sampled analog input signal value; and 19. The method of claim 18 wherein step c comprises the
wherein the first path with controllable conductivity is step of coupling the second terminal of the second capacitor
Substantially non-conductive during at least a portion of to the first power Supply Voltage rail.
the analog-to-digital conversion process when the ana 25 20. The method of claim 14 wherein the first plate of the
log-to-digital converter is evaluating the sampled analog capacitoris Substantially isolated from the input terminal in a
input signal value. step initiated in response to completing step b.
12. The analog-to-digital converter of claim 11 wherein the 21. The method of claim 14 wherein step c further com
first path with controllable conductivity is substantially con prises the step of providing a junction bias Voltage to a first
ductive during a short period of time, where a duration of the 30
junction terminal to Substantially prevent apnjunction diode
short period of time is less than five percent of a minimum configured between the first junction terminal and the second
period of time used to complete the analog-to-digital conver capacitor plate from becoming Substantially forward-biased.
sion process to provide the digital code representing the
sampled analog input signal value. 22. The method of claim 14 further comprising the step of
13. The analog-to-digital converter of claim 11 wherein the 35 providing a series connection of a first semiconductor device
analog-to-digital conversion process is initiated at a time of a first polarity and a second semiconductor device of the
when the first path with controllable conductivity is substan first polarity to selectively couple the control terminal to the
tially non-conductive. first power Supply Voltage rail, wherein the first semiconduc
14. A method for processing an analog Voltage signal tor device is Substantially conductive during step a and step b
applied at an input terminal, the method comprising the steps 40 of the method, and wherein the second semiconductor device
of: is Substantially conductive during step b and step c of the
Stepa, selectively coupling the input terminal to a first plate method.
of a capacitor, and selectively coupling a second plate of 23. The method of claim 22 further comprising the step of
the capacitor to a first power Supply Voltage rail via a providing a third semiconductor device of a second polarity
sampling Switch having a control terminal selectively 45 different from the first polarity, where the third semiconduc
coupled to a second power Supply Voltage rail; tor device is configured to selectively couple the control ter
step b, after step a, applying a control signal to the control minal to the second power Supply Voltage rail, and where a
terminal to Substantially isolate a quantity of charge on gate terminal of the third semiconductor device is coupled to
the second plate of the capacitor while a Voltage poten a gate terminal of the second semiconductor device.
tial of the second plate of the capacitor is substantially 50 24. The method of claim 14 wherein step a comprises the
restricted to be within a power Supply Voltage range step of placing an analog circuit in a power-down mode, and
having boundaries corresponding to the first power Sup wherein the method further comprises the step of activating
ply Voltage rail and the second power Supply Voltage rail; the analog circuit to evaluate the quantity of charge isolated
and on the second plate of the capacitor.
step c, after step b, applying a control bias Voltage to the 55 25. An analog-to-digital converter configured for sampling
control terminal to continue to isolate the quantity of an analog input signal and performing a successive-approxi
charge on the second plate of the capacitor while it may mation analog-to-digital conversion process to generate a
Swing in an expanded Voltage range exceeding the digital code representing a sampled analog input signal value,
power Supply Voltage range, the control bias Voltage the analog-to-digital converter comprising:
being outside the power Supply Voltage range; 60 a first capacitor having a first capacitor terminal and a
whereby the quantity of charge isolated on the second plate second capacitor terminal,
of the capacitor represents an instantaneous value of the an input Switch configured to selectively couple the analog
analog Voltage signal at a sampling instant. input signal to said first capacitor terminal during a
15. The method of claim 14 further comprising a step d of tracking period;
performing an analog-to-digital conversion process to pro 65 a sampling Switch configured to selectively couple the
vide a digital code representing the instantaneous value second capacitor terminal to a first power Supply Voltage
of the analog Voltage signal at the sampling instant. during the tracking period;
 US 7,961,132 B1
15 16
a controller configured to apply a bias Voltage signal to the 28. The analog-to-digital converter of claim 25 wherein the
sampling Switch to control a multi-step sampling pro capacitor is comprised in an array of capacitors, wherein
cess, the controller comprising: individual capacitors in the array of capacitors are Switched
a sampling control terminal coupled to the sampling Switch selectively to a reference Voltage.
for providing the bias Voltage signal; 29. The analog-to-digital converter of claim 25 further
a circuit comprising Switches for selectively coupling the comprising a comparator circuit, the comparator circuit being
sampling control terminal to the first power Supply Volt in an active mode during the Successive-approximation ana
age as a step in a multi-step sampling process; and log-to-digital conversion process, and the comparator circuit
a charge-pump circuit for pumping the bias Voltage signal being in a power-down mode during the tracking period.
to a Voltage exceeding a power Supply Voltage range in 10 30. The analog-to-digital converter of claim 25 wherein the
another step of the multi-step sampling process. power Supply Voltage range is a range of Voltages limited by
26. The analog-to-digital converter of claim 25 wherein the the first power Supply Voltage and a second power Supply
sampling switch comprises a MOSFET transistor having a Voltage; the analog-to-digital converter Substantially being
gate terminal receiving the bias Voltage signal.
27. The analog-to-digital converter of claim 25 wherein the powered by the first and second power Supply Voltages.
sampling switch comprises a MOSFET transistor imple 15
mented in a semiconductor well of a first doping polarity, the
bias Voltage signal being applied to the semiconductor well.