CPU

Organisation
1.1 Introduction
We know that a computer has five main components
1. Input unit

This unit contains devices with the help of which we enter data into computer.
For example, keyboard, mouse etc.
2. Arithmetic and logic unit (ALU)
This unit performs the arithmetic operations like addition,subtraction etc. and
logical operations like comparison, selection etc.
3. Memory unit
This unit stores instructions, data and intermediate results.
4. Control unit
This unit controls the operations of all parts of computer.
5. Output unit
This unit consists of devices with the help of which we get the information
from computer. For example, monitor, printers etc.
CPU(Central Processing Unit) is the heart of the computer which consists of
arithmetic and logic unit, control unit, register and decoders etc. CPUis connected
with various WO devices and memories by sets of wires called buses) A single bus
computer architecture is shown in figure 11.1
inalout
The purpose of CPUis to execute the instructions stored in the main memory.
Therefore,question arises, how these instructions will be exécuted by the CPU?
This chapter answer this question. In this chapter, we will discuss the basic
structures of CPU, the instruction cycle, instruction formats and addressing modes.
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 CPU
Registers

O-O ALU
Main Memory

Control unit

Bus

Device Device
Controller Controller

Input devices Output devices

FIGURE 11.1

K.2 Bus
In a microcomputer, all the above mentioned units are linked to one another via
buses. A Bus is basically a set of wires that carry data bits and act as a
communication path between the processing unit and peripherals. Wires are used
to connect Register together. To connect n-registers we need n(n-1) wires, to
manage these wires is very difficult, moreover more wires causes more problems.
So in place of wires a Bus is used. Bus is a fast and safe mnedium of data transfer
from one place to other.
Two way of Data Transfer Occur :
()/Unidirectional Bus : Ad
Where bus is used to transfer data in one direction called Unidirectional. e.g.
Address Bus. Transfer is controlled by control signals.
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(i) Bidirectional Bus :
Where Bus is used to transfer data in both irections, each direction is
controlled by a control switch. This bus is called Bidirectional. e.g. control,
Data Bus.

Abus is a group of wires which are used to transmit electrical signals. In a typical
eomputer, there are basically three types of buses namely address bus, data bus
and control bus.

Address Bus

This bus is used to carry address of the device to which microprocessor wants to
interact. For example, if a microprocessor has to retrieve the contents of a memory
location whose address is 3000H then it willtrarsihit the address, 3000H on the
address bus. This address is received by all the devices connected to it but only
the device whose address is on address bus responds.

Data Bus

This bus is used to transmit data from one device to another and vice versa. For
example, the contents of the above addressed memory location will be sent to the
processor via data bus. Similarly data from memory may be transmited to output
unit on the same bus.

Control Bus
ToSoo'
This bus is used to transmit and receive control signals between the microprocessor
and various devices attached to itJFor example when ALUhas finished a particular
computations it sends a contol signal to the microprocessor to tell this fact.

Width
Pardt
(The width of a bus is defined as the no. of wires that constitutes it)8-bjt
microprocessor has bit-wide data bus. This means that 8 bits of information can
be transmitted in parallel over the data bus.
Calcu lae
The width of the address bus can be used to compute the totalamount of memory
that can be directly accessed by the processor. If width of an adders bus is 16 then
216 memory locations can be accessed by processor.
The arrangement of the three types of buses in a typical computer system is shown
in fig. 11.2

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 ADDRESS BUS

Central Input Output

Processing Memory Devices(s) Devicés(s)
Unit
(CPU)
DATA BUS

Control
MEMRW y Signal - WO Read/Write
CONTROL BäS

FIGURE 11.2

Here CPU, memory chips and /O devices are connected via address bus, data
bus and a set of control signals. If it is required to read the contents of a particular
memory location,the CPUfirst sends out the address of thà location on the address
bus and a memory read control ignal on the control bus. The memory responds by
outputting the stored data. from the addressed location onto the data bus. On the
data bus, first the data i_ read from the memory into one of the registers of CPU.
and later written from the CPUto the designated /Odevice.

M.3Instruction Set
An instruction set is a collection of all the instructions a CPU can execute. Each
instruction consists of several elements. An instruction element is a unit of information
required by the CPUfor execution.

11.3.1 Elements of an instruction

An instruction has the following elements :
An operation code also termed as epcede which specifies the operation is to
be performed.
a (iDAreferene to the operands on which data processing is to performed. For
example, £n address of an operand.
i) Areference to the operands which m¡y store the results of data processing
operation performed by the instruction.
ty) Areference for the next instruction, to be fetched and executed.
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1.32 How is an instruction
represented ?
Instructions are represented as sequence of bits. An
of fields. Each of these fields
are corresponds to a
instruction is divided into number
Alayout of instruction is constituent element of instruction.
termed as instruction format. fiqure 11.3 shows a instruction
format for a computer. It uses four bits for
are pravided here. In this opcode and only two operand
format, no explicit references
instruction to be executed. reference is provided for the next

3
15
Opcode
Reference to Reference to
mode operand 1 operand 2

4 bits 6 bits 6 bits

Most significant bit

-
Least significant bit

FIGURE 11.3

11.4Factors for Selection/Designing of instruction set for a

machine
The instruction set plays important role in design of the CPU as it
defines many
functions of it. Since instruction sets are the means by which a
programmer can
cortrol the CPU, therefore, users view must be considered while designing the
instruction set. Some of the important factors which play important role for selection/
designingof instruction set for a machine are:
How many and what operations to be provided ?
ty What are the operand data types to be provided ?
fii) What should be the instruction format ? This includes issues like: instruction
length, number of address, length of various elements of instructions etc.
(i What is the number of registers which can be referenced by an instruction
and how are they used ?
() What are the modes of specitying an operand address ?
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 11.5 Fypes of Instructions
The instructions can be categorised as
Data Processing Instructions : These instructions are used for arithmetic
in a machine. Examples of these instructions r
and logic operations string processing instructions
Arithmetic, boolean, shift, character and
Since the data processing operations
()Data Storage/ Retrieval Instructions : in CPUregisters. Thus, we po
stored
are normally performed on the data
an instruction to bring d¡ta to and from memory to registerS. hese are caller
Examples of these instructions are I
Data Storage/ retrieval instructions.
and store instructions.
input output instructione
fiiY Data Movement Instructions :These are basically data from various devicee
These are required to bring in programs' and
Output devices. Exampla
memory or to communicate the results to the Inputt
Output, TEST Inot
of these instructions are : Start Input Output, Halt Input
Output etc.
Ai Control Instructions : These instructions are_used for testing the status of
such
computation through Processor Status Word (PSW). Another of
instruction is the branch instruction used for transfer of control.
(V Miscellaneous Instructions: These instructions do not fit in any of theabove
category. Some of these instructions are : interYrupt or supervisory call.
swapping return from interrupt, Halt instruction or some privileged instruction
of operating systems.
feleh
A,× BASICStructure of CPU
to execute an instruction, CPUundergoes a sequence of operations which are
Used in processing the instruction called the instruction cycle. The instruction
.cycle constitutes two cycles :fetch cycle and the execution cycle. During the fetch
cycle, the CPUfetches the instruction to be executed, from the main memory. In
the execution cycle, decoding of the fetched instryction is done to perform the
operation specified by.the opcode of the instruction.
Duringthe program execution, firstly the required operands are transferred from
main memory to CPUregisters and then after computingthese in CPU,the desired
result is transferred back to the main memory. In CPU, 'Accumulator is the key
register for execution of most of the instructions as it plays a central role in storing
the input or output operand for ALU. |
ACPU structure of the IAScomputer (firstly proposed by Johnvon Neumann and
his colleagues) is shown in figure 11.4 which is still used in some mini and micro
computers. This was having minimal number of registers and a small instruction
set.

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 Data Processing Unit

ALU AC

To/trom MBR
main
memory
&
/O MAR CONTROL
PC IR
Devices UNIT

cONTROL SIGNALS

Program Control Unit

FIGURE 11.4

The various registers available in this structure are :

1. Accumulator Register (AC)
This register holds the initial data to be operated upon, the intermediate results
and also the final results. of processing operations. It is used during the
executions of most instructions. The results of arithmetic operations are
returned to the accumulator register for transfer to main storage through the
memory buffer register. In many computers there are more than one
accumulator registers.
2. Memory Buffer Register (MBR)
It holds the contents of the memory word read from, or written in memory. An
instruction word placed in this register is transferred to the instruction register.
A data word placed in this register is accessible for operation with the
accumulator register or for transfer to the /O register.A wordto be stored in a
memory location must first be transferred to the MBR, from where it is written
in memory. This register is also known as Data Register (DR).
3. Program Counter (PC)
It is a part of control unit and is used to hold the address of the next instruction
to be read from memory after the current instruction is fetched and executed.
This register goes through a counting sequence and, therefore, is automatically
incremented after arn instruction is fetched by causing the computer to read
previously stored instructions in a sequential manner.
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 4. Instruction Register (R)
executed. As SOon as h.
It holds the current instruction that is being
instructions are stored in this register, the operation part and the address part
of the instructions are seperated. The address part of the instruction is sent to
the MAR while its operation part is sent tothe control section whereit is decoded
and interpretedand ultimately command signals are generated to carry out
the task specified by the instruction.
5. Memory Address Register (MAR)
give the addrese at
MARis directly connected tothe address bus. It isused to
memory location from where data is retrjeved or to which data is to be stored.
role in the transfer of dat
Both MAR and MBR register play an important
between CPUandthe memory.
more powerful by addine
This simple structure of CPUcan be extended to make it
capabilities
more number of general purpose registers,by increasing the arithrnetic of
of ALU and byincluding some special registers to check the status
and transfer
Control duringprogram execution. Extra Registers are
Snale 1. General Purpose Register 6
functions desired by the
A general purpose register can be used for various
processor, like either to contain an operand or an address of an operand for
any opcode of an instruction. In modern day systems, concept of dedicated
registers is aiso put in use where some registers may be dedicated to floating
point operations.
2. Condition Codes Registers
123}rhIt These registers are used to contain the condition codes calledfiags and are
partially available to the programmers. These flags are set by the CPU while
performing an operation. Some of the common condition codes or flags are:
Zero flag: To indicate whether the content of last arithmetic operation
Was.zero.

Sign flag:To indicate whether the content of last arithmetic operation

was positive or negative.
Carry flag To indicatethecarry (borrow) from the addition (substraction)
of the highest order bits.
Equal flag:To indicate whether the result of last logic operation was
equal.
Overflow flag : To indicate the condition of arithmetic overflow.
Interrupt nable/ disable flag : For enabling or disabling the interrupts.
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 3. Status and Control Registers ttah
During a subroutine calloperation or interrupt handling routine, it is required
that the status information (such as condition codes) and other register
information be saved and after the execution of these routines, restores back.
Astatus register often known as Program Status Word (PSW) serves the
purpose to contain the condition code and other status information. Similarly,
Interrup Vector Register and Stack Pointer are the other status and control
registers, respectively.

1.7 Instruction Formats

There are various instruction formats depending upon the architecture of the
computer. The formats of commonly used instructions are :
1. 4-address instruction
2. 3-address instruction
3 2-address instruction
4. 1-address instruction
5. 0-address instruction
1. 4-address instruction :
Afour address instruction consists of the following parts :
Operation code
(i) Two address for two operands.
(iü) Address of the memory locationwhere the result of the operation is to be
stored.
(iv) Address of the memory location containing the next instruction.
Ageneral form ofa 4-address function is

op-code address-1|address-2 address address of

of resultnext instruction

These four address instructions have become obsolete now beçause execution
of these instructions is very slow.
2. 3-address instructions :
To reduce the length of an instruction, a register called Program Counter (PC)
is used to compute the address of the next instruction. Hence a three address
instructionconsists of the following parts operation code.
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 () Operation code
() Two addresses for two operands.
(ii) Address of the memory location where the result of the operation is to be
stored.
The general form of a three address instruction is

op-code address-1 address-2 address

of result

3. 2-address instructions
An improvement over three address instructions was achieved by using two
address instructions.
in 2-address instructions both operand address are specified. The resuit is
placed in ane of the specified address. The general form of a two address
instruction is.

op-code address-1 address-2

ccumulat
1-address instruction
In 1-address instruction only one operand address is specified in the
instruction, the other operand is stored in accumulater, The results of operation
are left in the accumulator itself, from where these can be moved to main memory
by another instruction. The general form of single address instruction is.

op-code address-1

5. 0-address instruction
The zero address instruction do not contain any operandaddress. The operand
addresses are implied. These zero address instructions are also called stack
instructions. The general form of zero address instructions is

op-code

264]
The
number of address in the instruction depends upon the register organization of
into the one of the three
thecomputer. From this point of view, most Computers fall
typesof CPU organization :-
Single accumulator organizations
(2) General register organizations
(3) Stack organization
) Single accumulator organization (1-address instruction)
Most of the instructions ofan accumulator based machine contain one operand
address. The other operand is implied and it is in the accumulator. For example,
the instruction that specifies an arithmetic addition is defined by one address
instruction
ADD X
Where Xis the address of the operand. Meaning of this instruction is
AC -AC + M[X]
M[X] symbolizes the memory word located at address X and AC is the
accumulator register.
Intel 8080.and
8085 are mainly one-address processors using a single 8-bit
accumulator.

(2) General register organization (2 or 3-address instruction)

Machines of this type have aset oflgeneral purpose registers which are used
for arithmetic, logical and comparsion operations. Their instructions contain
two or three addresses. The three address instruction for an arithmeticaddition
may be written as
ADD R1, R2, R3
to denotetheoperation R1 R2+R3. Where R1, R2, R3 are general purpose
registers. The two address instructions may be written on
ADD R1, R2
to denote the operation R1 R1 + R2
General register type computers employ two or three address fields in their
instruction format. Each address field may specify a processor register or a
memory word. Consider an instruction.
ADD R1, X (2 Aolel)
This instruction would specify the operation
R1 R1 +MX]
This type of structure was employed in the second generation maintrame
computers (|BM) 360/370), minicomputers (DEC, PPP-11) and
microprocessors (Zlog Z8000, motorala 68000). Intel 8086 and 8089 are mainly
a two address processor with general register.
[265)
(3) Stack organization (0-address instruction)
Astack-oriented machine contains only a stack pointer (SP) which pointe
the stacktop. Such machines contain neither accumulator norgeneral-purpose
registers. Computers with stack organization would have PUSH and POP
instruction which requires an address field. Thus the instructions.
PUSH X

Willpush the word al address Xto the top of the stack. Operation type instruction
do not needan address field in stack organized computers. For example the
instruction.
ADD
Pops two top operands from the stack, adds them and pushes the result back
into the stack. There is no need to specify operands with an address field
since all operands are implied to be in the stack. We willuse the symbols.
LADD, SUB, MUL and DIV for the four arithmetic operations, MOV for the
transfer operation and LOAD andSTORE for transfers to and from memory
and AC register.

Example 11.1
Compare zero, one, two and three address instructions by writing program to
complete
F= (R+ S) *(U+ V)
Solution:
() Three-Address Instructions
Ac
The program is as follows : 2 -3
ADD R1, R, S R1 -MR] + M[S]
ADD R2, Ú, V R2M[U] + M[V] PuSH, poP
MUL F, R1, R2 M[F] R1 + R2
(ii) Two-Address Instructions
The program is as follows :
MOV R1, R R1-M[R]
ADD R1, S R1 R1 + M[Sj
MOV R2, U R2 4- M[U]
ADD R2, V R2 4-R2+ M[V]
MUL R1, R2 R1 R1 * R2
MOV F, R1 MIF]R1
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 ACuulator
One-Address Instructions
The program iS
as follows :
LOAD R AC+ MIR]
ADD AC AC+M[S)
STORE_T M[T]e-AC
LOAD U AC MU)
ADD ACAC + M[V)
MUL "ACAÇ*M[T]
STOREF M[F]-AC
required for storing
In the above program, T is address of a temporary location
the intermediate result.
Zero Address Instructions
(iv)
The program is as follows (TOS stands for top of stack)
PUSH TOS R
PUSH TOS S
ADD TOS (R+S)
PUSH U TOSU
PUSH V TOS V
ADD TOS (U+ )
MUL TOS (R+S)*(U+V)
POP F M[F]TOS

11.8Addressing modes (Th

The addressing mode of an instruction refers to a rule by which the
effective address
of an operand for that instruction is calculated. Effective Address refers to a inphysical
virtual 341'
address in a non-virtual memory environment and refers to a register
menory address environment. This register address is then mapped to physical
memory address.
An instruction with the use of addressing modes has certain advantages.
With a lesser number of bits in the address field of the instruction, a larger
address space may be addressed.
It helps to make programming easier, programs more efficiert and less prone
to errors.
(ii) The base register mode of addressing allows programs or data to be relocated
from one part of the memory to another.
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 Various addressing modes are:
(i) Immediate mode
In this mode, the operand va<ue, is specified as part of an instruction. Thus.
the operand is fetched along with the instruction and no seperate memory
required for the operand fetch.However, the number of bits of
access is limited and hence th
instruction available to store the immediate operand is
mode instructions are useful 6
range of its value is also limited. Immediate
initializing registers to a constant value.
Example 11.2
26 H AC AC + 26 H
() ADD
56 H AC AC- 56 H
(ii) SUB
Implied mode
The address field is not required for this type of instruction, because the address
instructions in2
Jhatuhòh of the operand is implied by the op-code itself. Zero-address
stack-organized computer are implied-mode instructions since the operande
are implied to be on top of the stack. Tos
i i Register Mode
When the operand for any operation are in general purposeregister, then only
registers are to be specified.
Example 11.3
ADD B AC AC+B
MOV A, AC B
SUB C AC AC -
(iv) Register Indirect Mode
In this mode the instruction specifies a register in the CPU whose contents
give the address of the operand in memory. In other words, the selected register
contains the address of the operand rather than the operand itself. The
advantage of a register indirect mode instruction is that the address field of the
instruction uses fewer bits to select register than would have been requiredto
specify a memory address directly.
(v) Direct Address Mode
In this mode the effective address is equal to the address part of the
instYuction The operand resides in memory and its address is given directly
by the address field of the instruction. Inabranch-type instruction the address
field specifies the actual branch address.
Note that Mode bit Ois used for direct address mode and 1 for indirect address
mode.

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 Memory
ADD 234

Mode blt

234 Operand

AC

FIGURE11.5

\(vi) Indirect Access Mode

In this mode the address field of the instruction gives the address where the
effective address is stored in memony Control fetches the instruction from
memory and uses its address part to access memory again to read the effective
adaress.

Memory
ADD 234

Mode bit

234 1008

1008 Operand

AC

FIGURE11.6
( 269 ]
(vii) Relative Address Mode
this type of
Thisis also called PC(Progam Counter) addressing. Incontents
CPU inadds
given thethe
cOunter to the
contents oroftoprogram
instruction
of addressi
the ng
address
the contents given in the instruction to find the
effective address of the operand.
PC+Contents of address field
Effective address = contents of
or Relative.
A new address is generated called
For example: ADD*+100
ADD$+100
here * or $represents contents of PC and this instruction implies that add the
contents of PC tothe value given in theinstruction (100) tofind the final address
of the operand.
vi) Indexed Addressing Mode
The indexed address can be any general purpose register in the CPU. The
purpose lo
CPU design may set aside a separate set of registers for indexing
the mode the effective address is computed by adding the contents of the
address given to the contents of indexed register. This mode is generally
used for address modification in calculations.

Effective Address =Address field Contents+Contents of index register

For Example ADD 100, X
here 'X' indicates the address of the indexed register Computer adds the
contents of the indexed register to 100 to calculate effective address.
Wix) Autoincrement Mode
In this mode, address is automatically incremented by 1 (one).
.ut
For example : In insetiorn (PUSH) operation in stack, the address of Stack
Pointer Register is automatically incremented by 1.
If A = 56H
next A = 57H

(x) Autodecrement Mode

in this mode, address is automaticaly decrermented by 1.
For example:During Pop operation, in the stack the contents ofStack Pointer
Register is decremented by 1.
A = 58H
then A = 57H
 (xi) Base Register Addressing Mode:
In this mode the content ofa base register is added to the address part of the
instruction to obtain the effective address. This is similar to the indexed
addressingmode except that the register is now called a base register instead
of an index register.
Effective address = Address field contents + Contents of Base Register
The base register addressing mode is used in computers to facilitate the
relocation of programs in menory.When programs and data are moved from
one segment of memory to another, as required in multiprograrnming system_,
the address values of instructions must reflect this change of position.
11.9 Instruction cycles
A simple instruction cycle will consist of the following steps:
fetching the instruction from the memory. This is also termed as fetch-cycle.
decode the instruction eol
find out the effective address of the operand (Cohee hto moh
(iy execute the instructions. This is also termed as execute cycle. aquae.
Normally decoding is also performed in this cycle/
decode
Upon the completion of siep (iv), the control goes back to step () to fetch, aHALT
and execute the next instruction. This process Continues indefinitely unless
instruction is encountered.
An instruction cycle may consist of these sub-cycles. These three cycles are :

11.9.1 Fetch Cycie CPU -{e-teh

During this cycBe the instruction which is to. be executèd next is brought from the
memory to the CPU. Steps are
(i) The next instruction address is transferred from PC to MAR.
MAR PC
(ii) MAR puts this signalon the address bus for the main memory location selection,
whereas the control unit uses a memory read signal. Theresultant so obtained
is placed on the data where it is accepted by the Data register DR.
DR (M) (where M represents a memory read)
(ii) The PC is incremented by one memory word length
PC PC +1
Thís operation can be carried out in parallel to the above operation.
(iv) The instruction so obtained is transferred to the Instruction Register.
IR DR

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11.9.2 Indirect Cycle
Once the instruction is fetched, the next step is to determine whether it
requires
memory reference or a register reference or it is an input/ output instruction. a
instruction can use several
However, the memory
Depending on the
reference
type of addressing the effective address (EA) addressing
of operands
calculation of effective
modes,
in the
memory are calculated. In certain cases, the address inrequire
one memory reference (for example in the case of
indirect
addressing)
to direct Such
cases a special cycle which converts all the indirect addresses
required. This cycle is termed as an indirect cycle. address is
The steps of indirect cycleare:
() transfer the address bitsof instruction to the MAR. This transfer o ,
achieved using DR only as DR and lR at this point of time Contains
value. same
MAR DR(Address)
(i) Once again a memory read operation as done in fetch cycle is performed and
the desired address of the operand is obtained in the DH. or memory bufter
register (MBR)
DR -(M)
(ii) transfer the address pat so obtained in DR as the address part of instruction
IR (Address) DR (Address)

11.9.3 Execute Cycle

After the fetch and indirect cycle (if required) an instruction is ready to be executed.
h the execute cycle the instruction get actually executed. An, execute cycle depends
on the opcode. Adifferent opcode wil require ifferent sequence of steps for the
execute cycle.Therefore, let us discuss one example of execute cycle of some
simple instruction for the purpose of identifying some of the steps needed during
this cycle. Suppose, we have an instruction :Add Awhich adds the content of
memory location Ato AC storing the result in AC. This instruction will be executed
in the following steps:
() Transfer the address portion (this address in symbolic form is A) of the
instruction to the MAR.
MAR IR (Address)
(i) Read the memory location A and bring the operand in the DR.
DR (M)
(iii) Add the DR with AC using ALU and bring the results back to AC.
AC AC +DR

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