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4 Channel DAC SPI Protocol

The DAC81404 and DAC61404 are quad-channel, high-voltage-output digital-to-analog converters with 16-bit and 12-bit resolutions, respectively, featuring a 2.5-V internal reference and specified monotonicity. They support a variety of output voltage configurations and include integrated reliability features such as short-circuit protection and a CRC error check. Communication is facilitated through a 50-MHz SPI-compatible serial interface, and the devices operate over a temperature range of -40°C to +125°C.

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4 Channel DAC SPI Protocol

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DAC81404, DAC61404

SLASEH2A – NOVEMBER 2020 – REVISED MAY 2021

DACx1404 Quad, 16-Bit and 12-Bit, High-Voltage-Output DACs

With Internal Reference

1 Features 3 Description
• Performance: The 16-bit DAC81404 and 12-bit DAC61404
– Specified monotonic at 16-bit resolution (DACx1404) are pin-compatible, quad-channel,
– INL: ±1 LSB maximum at 16-bit resolution buffered, high-voltage-output, digital-to-analog
– TUE: ±0.05% FSR, maximum converters (DACs). These devices include a low-drift,
• Integrated output buffer 2.5-V internal reference that eliminates the need for
– Full-scale output voltage: ±5 V, ±10 V, ±20 V, an external precision reference in most applications.
5 V, 10 V, 20 V, 40 V The devices are specified monotonic and provide
– High drive capability: ±15 mA high linearity of ±1 LSB INL. Additionally, the devices
– Per channel sense pins implement per channel sense pins to eliminate IR
• Integrated 2.5-V precision reference drops and sense up to ±12 V of ground bounce.
– Initial accuracy: ±2.5 mV, maximum A user-selectable output configuration enables full-
– Low drift: 10 ppm/°C, maximum scale bipolar output voltages of ±20 V, ±10 V, and
• Reliability features: ±5 V; and full-scale unipolar output voltages of 40 V,
– CRC error check 20 V, 10 V and 5 V. The full-scale output range for
– Short circuit limit each DAC channel is independently programmable.
– Fault pin The integrated DAC output buffers can sink or source
• 50-MHz, SPI-compatible serial interface up to 15 mA, thus limiting the need for additional
– 4-wire mode, 1.7-V to 5.5-V operation operational amplifiers.
– Readback and daisy-chain operations The DACx1404 incorporate a power-on-reset circuit
• Temperature range: –40°C to +125°C that connects the DAC outputs to ground at power
• Package: 5-mm × 5-mm, 32-pin QFN up. The outputs remain in this mode until the device
2 Applications is properly configured for operation. These devices
include additional reliability features, such as a CRC
• Semiconductor test error check, short-circuit protection, and a thermal
• Lab and field Instrumentation alarm.
• Analog output module
• Data acquisition (DAQ) Communication to the devices is performed through
• LCD test a 4-wire serial interface that supports operation from
• Servo drive control module 1.7 V to 5.5 V.
IOVDD DVDD FAULT REFIO AVDD
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
Internal Reference

DAC81404
VQFN (32) 5.00 mm × 5.00 mm
Power On REF
SCLK Reset BUF
DAC61404
SDIN
REF
SYNC

SDO
Buffer Active DAC
+ CCOMP[A:D] (1) For all available packages, see the package option
SPI

Register Register Ladder

LDAC
OUT[A:D]
addendum at the end of the data sheet.
–
RST 40 k
AVDD
CLR 40 k SENSEP[A:D]
Channel 40 k – SENSEN[A:D]
A
+ 40 k
CCOMP

Resistor Gain
REF Network REF DAC CCOMPX
Ladder + R
Current Limit
OUTX
-
40 k
RLOAD

40 k
GND AGND REFGND AVSS 40 k -
+ 40 k AVSS
SENSEPX GND
Functional Block Diagram Resistor Gain
Network SENSENX
REF

REFGND

High Current Drive (1 A) Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC81404, DAC61404
SLASEH2A – NOVEMBER 2020 – REVISED MAY 2021 www.ti.com

Table of Contents
1 Features............................................................................1 7.13 Typical Characteristics............................................ 17
2 Applications..................................................................... 1 8 Detailed Description......................................................25
3 Description.......................................................................1 8.1 Overview................................................................... 25
4 Revision History.............................................................. 2 8.2 Functional Block Diagram......................................... 25
5 Device Comparison Table...............................................3 8.3 Feature Description...................................................26
6 Pin Configuration and Functions...................................3 8.4 Device Functional Modes..........................................30
7 Specifications.................................................................. 5 8.5 Programming............................................................ 31
7.1 Absolute Maximum Ratings ....................................... 5 8.6 Register Map.............................................................34
7.2 ESD Ratings .............................................................. 5 9 Application and Implementation.................................. 41
7.3 Recommended Operating Conditions ........................6 9.1 Application Information............................................. 41
7.4 Thermal Information ...................................................6 9.2 Typical Application.................................................... 41
7.5 Electrical Characteristics ............................................7 10 Power Supply Recommendations..............................43
7.6 Timing Requirements: Write, IOVDD: 1.7 V to 2.7 11 Layout........................................................................... 43
V ................................................................................. 13 11.1 Layout Guidelines................................................... 43
7.7 Timing Requirements: Write, IOVDD: 2.7 V to 5.5 11.2 Layout Example...................................................... 43
V ................................................................................. 13 12 Device and Documentation Support..........................44
7.8 Timing Requirements: Read and Daisy Chain, 12.1 Documentation Support.......................................... 44
FSDO = 0, IOVDD: 1.7 V to 2.7 V ............................... 14 12.2 Receiving Notification of Documentation Updates..44
7.9 Timing Requirements: Read and Daisy Chain, 12.3 Support Resources................................................. 44
FSDO = 1, IOVDD: 1.7 V to 2.7 V ............................... 14 12.4 Trademarks............................................................. 44
7.10 Timing Requirements: Read and Daisy Chain, 12.5 Electrostatic Discharge Caution..............................44
FSDO = 0, IOVDD: 2.7 V to 5.5 V ............................... 15 12.6 Glossary..................................................................44
7.11 Timing Requirements: Read and Daisy Chain, 13 Mechanical, Packaging, and Orderable
FSDO = 1, IOVDD: 2.7 V to 5.5 V ............................... 15 Information.................................................................... 44
7.12 Timing Diagrams..................................................... 16

4 Revision History
Changes from Revision * (November 2020) to Revision A (May 2021) Page
• Added DAC61404 and associated content.........................................................................................................1

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5 Device Comparison Table

DEVICE RESOLUTION
DAC81404 16-bit
DAC61404 12-bit

6 Pin Configuration and Functions

RE FGND
FA ULT

RE FIO
AGND
DV DD

AVDD

AVSS
RS T

25
32

27
OUTA 1 24 OUTD

CCOMPA 2 23 CCOMPD

SENSEPA 3 22 SENSEPD

SENSENA 4 21 SENSEND
Th ermal pad
SENSENB 5 20 SENSENC

SENSEPB 6 19 SENSEPC

CCOMPB 7 18 CCOMPC

OUTB 8 17 OUTC
15

16
10

14
9

CL R
SDO

SCLK

SYNC

LDAC

GND

IOVDD
SDIN

No t to scale

Figure 6-1. RHB (32-pin VQFN) Package, Top View

Table 6-1. Pin Functions

PIN
TYPE DESCRIPTION
NO. NAME
1 OUTA Output Channel-A analog output voltage.
Channel-A external compensation capacitor connection.
The addition of an external capacitor improves the output buffer stability with high capacitive
2 CCOMPA Input
loads at the OUTA pin by reducing the bandwidth of the output amplifier at the expense of
increased settling time.
3 SENSEPA Input Channel-A sense pin for the positive voltage output load connection.
4 SENSENA Input Channel-A sense pin for the negative voltage output load connection.
5 SENSENB Input Channel-B sense pin for the negative voltage output load connection.
6 SENSEPB Input Channel-B sense pin for the positive voltage output load connection.
Channel-B external compensation capacitor connection pin.
The addition of an external capacitor improves the output buffer stability with high capacitive
7 CCOMPB Input
loads at the OUTB pin by reducing the bandwidth of the output amplifier at the expense of
increased settling time.
8 OUTB Output Channel-B analog output voltage.
Serial interface data output.
The SDO pin must be enabled before operation by setting the SDO-EN bit. Data are clocked out
9 SDO Output
of the input shift register on either rising or falling edges of the SCLK pin as specified by the
FSDO bit (rising edge by default).

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Table 6-1. Pin Functions (continued)

PIN
TYPE DESCRIPTION
NO. NAME
10 SCLK Input Serial interface clock.
Serial interface data input. Data are clocked into the input shift register on each falling edge of the
11 SDIN Input
SCLK pin.
Active low serial data enable. This input is the frame synchronization signal for the serial data.
12 SYNC Input
The serial interface input shift register is enabled when SYNC is low.
Active low synchronization signal. The DAC outputs of those channels configured in synchronous
13 LDAC Input
mode are updated simultaneously when the LDAC pin is low. Connect to IOVDD if unused.
14 GND Ground Digital ground reference point.
15 IOVDD Power IO supply voltage. This pin sets the digital I/O operating voltage for the device.
Active-low clear input. Logic low on this pin clears all outputs to their clear code. Connect to
16 CLR Input
IOVDD if unused.
17 OUTC Output Channel-C analog output voltage.
Channel-C external compensation capacitor connection pin.
The addition of an external capacitor improves the output buffer stability with high capacitive
18 CCOMPC Input
loads at the OUTC pin by reducing the bandwidth of the output amplifier at the expense of
increased settling time.
19 SENSEPC Input Channel-C sense pin for the positive voltage output load connection.
20 SENSENC Input Channel-C sense pin for the negative voltage output load connection.
21 SENSEND Input Channel-D sense pin for the negative voltage output load connection.
22 SENSEPD Input Channel-D sense pin for the positive voltage output load connection.
Channel-D external compensation capacitor connection pin.
The addition of an external capacitor improves the output buffer stability with high capacitive
23 CCOMPD Input
loads at the OUTD pin by reducing the bandwidth of the output amplifier at the expense of
increased settling time.
24 OUTD Output Channel-D analog output voltage.
25 REFGND Ground Ground reference point for the internal reference.
Reference input to the device when operating with an external reference. Reference output
26 REFIO Input/Output
voltage pin when using the internal reference. Connect a 150-nF capacitor to ground.
27 AVSS Power Output buffers negative supply voltage.
28 AVDD Power Output buffers positive supply voltage.
29 AGND Ground Analog ground reference point.
30 DVDD Power Digital and analog supply voltage.
FAULT is an open-drain, fault-condition output. An external 10-kΩ pullup resistor to a voltage no
31 FAULT Output
higher than IOVDD is required.
32 RST Input Active-low reset input. Logic low on this pin causes the device to issue a power-on-reset event.
Thermal The thermal pad is located on the package underside. The thermal pad should be connected to
Thermal pad —
Pad any internal PCB ground plane through multiple vias for good thermal performance.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
DVDD to GND –0.3 6
IOVDD to GND –0.3 6
Supply voltage AVDD to GND –0.3 44 V
AVSS to GND –22 0.3
AVDD to AVSS –0.3 44
VOUTX to GND AVSS – 0.3 AVDD + 0.3
VSENSEPX to GND AVSS – 0.3 AVDD + 0.3
VSENSENX to GND AVSS – 0.3 AVDD + 0.3
VREFIO to GND –0.3 DVDD + 0.3
Pin voltage V
VREFGND to GND –0.3 +0.3
Digital inputs to GND –0.3 IOVDD + 0.3
SDO to GND –0.3 IOVDD + 0.3
FAULT to GND –0.3 6
Input current Current into any digital pin –10 10 mA
TJ Junction temperature –40 150 °C
Tstg Storage temperature –60 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/
±1000
ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per
±500
JEDEC specification JESD22-C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
DVDD to GND 4.5 5.5
IOVDD to GND 1.7 5.5
Supply voltage AVDD to GND 4.5 41.5 V
AVSS to GND –21.5 0
AVDD to AVSS 4.5 43
Pin voltage VSENSENX to GND –12 12 V
TA Ambient temperature –40 125 °C

7.4 Thermal Information

DACx1404
THERMAL METRIC(1) RHB (VQFN) UNIT
32 PINS
RΘJA Junction-to-ambient thermal resistance 29.3 ℃/W
RΘJC(top) Junction-to-case (top) thermal resistance 17.0 ℃/W
RΘJB Junction-to-board thermal resistance 9.5 ℃/W
ΨJT Junction-to-top characterization parameter 0.2 ℃/W
ΨJB Junction-to-board characterization parameter 9.5 ℃/W
RΘJC(bot) Junction-to-case (bottom) thermal resistance 1.1 ℃/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.5 Electrical Characteristics

all minimum/maximum specifications at TA = –40°C to +125°C and all typical specifications at TA = 25°C, AVDD = 4.5 V to
41.5 V, AVSS = –21.5 V to 0 V, DVDD = 5.0 V, internal reference enabled, IOVDD = 1.7 V, VSENSENX = 0 V, CCOMPX floating,
DAC outputs unloaded, and digital inputs at IOVDD or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
DAC81404 16
Resolution Bits
DAC61404 12
DAC81404. All ranges, except 0-V to
–1 1
40-V and overranges
INL Relative accuracy(1) LSB
DAC81404. 0-V to 40-V range –2 2
DAC61404 –1 1
DNL Differential nonlinearity(1) –1 1 LSB
Unipolar ranges, AVSS = 0 V –0.07 0.07
Unipolar ranges, AVSS = 0 V,
TUE Total unadjusted error(1) –0.05 0.05 %FSR
0°C ≤ TA ≤ 50°
Bipolar ranges, –21.5 V ≤ AVSS < 0 V –0.05 0.05
Unipolar ranges, AVSS = 0 V
Offset error(1) –0.05 0.05 %FSR
Bipolar ranges, –21.5 V ≤ AVSS < 0 V
Unipolar ranges, AVSS = 0 V
Offset error temperature coefficient ±2 ppmFSR/°C
Bipolar ranges, –21.5 V ≤ AVSS < 0 V
All unipolar ranges, AVSS = 0 V 0.15
Zero-code (negative full scale) error All bipolar ranges, %FSR
0.05
–21.5 V ≤ AVSS < 0 V
All unipolar ranges, AVSS = 0 V
Zero-code (negative full scale) error ppm of
All bipolar ranges, ±2
temperature coefficient FSR/°C
–21.5 V ≤ AVSS < 0 V
Full-scale error(2) –0.06 0.06 %FSR
Full-scale error temperature ppm of
±3
coefficient(2) FSR/°C
Gain error(1) –0.06 0.06 %FSR
ppm of
Gain error temperature coefficient ±2
FSR/°C
All bipolar ranges,
Bipolar-zero (midscale) error –0.03 0.03 %FSR
–21.5 V ≤ AVSS < 0 V
Bipolar-zero (midscale) error All bipolar ranges, ppm of
±2
temperature coefficient –21.5 V ≤ AVSS < 0 V FSR/°C
TA = 40°C, DAC code = full scale,
Output voltage drift over time ±6 ppm FSR
1000 hours

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7.5 Electrical Characteristics (continued)

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7.5 Electrical Characteristics (continued)

all minimum/maximum specifications at TA = –40°C to +125°C and all typical specifications at TA = 25°C, AVDD = 4.5 V to
41.5 V, AVSS = –21.5 V to 0 V, DVDD = 5.0 V, internal reference enabled, IOVDD = 1.7 V, VSENSENX = 0 V, CCOMPX floating,
DAC outputs unloaded, and digital inputs at IOVDD or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE
5-V span, 1/4 to 3/4 scale and 3/4 to
7
1/4 scale, settling time to ±2 LSB
10-V span, 1/4 to 3/4 scale and 3/4 to
8
1/4 scale, settling time to ±2 LSB
µs
20-V span, 1/4 to 3/4 scale and 3/4 to
12
1/4 scale, settling time to ±2 LSB
40-V span, 1/4 to 3/4 scale and 3/4 to
22
1/4 scale, settling time to ±2 LSB
5-V span, 1/4 to 3/4 scale and 3/4 to
Output voltage settling time 1/4 scale, settling time to ±2 LSB, 0.6
CL = 1 µF, CCOMPX = 500 pF to VOUTX
10-V span, 1/4 to 3/4 scale and 3/4 to
1/4 scale, settling time to ±2 LSB, 0.6
CL = 1 µF, CCOMPX = 500 pF to VOUTX
ms
20-V span, 1/4 to 3/4 scale and 3/4 to
1/4 scale, settling time to ±2 LSB, 0.6
CL = 1 µF, CCOMPX = 500 pF to VOUTX
40-V span, 1/4 to 3/4 scale and 3/4 to
1/4 scale, settling time to ±2 LSB, 1.2
CL = 1 µF, CCOMPX = 500 pF to VOUTX
0-V to 5-V range (10% to 90% of full-
0.8
scale range)
All other output ranges except 40-V
4
span (10% to 90% of full-scale range)
Slew rate V/µs
0-V to 5-V range, CL = 1 µF,
0.04
CCOMPX = 500 pF to VOUTX
All other ranges, CL = 1 µF,
0.04
CCOMPX = 500 pF to VOUTX
AVSS and AVDD ramped symmetrically,
Power-on glitch magnitude ramp rate = 18 V/ms, output unloaded, 0.1 V
internal reference
AVSS and AVDD ramped, output
Output enable glitch magnitude 0.35 V
unloaded, internal reference, gain = 1x
0.1 Hz to 10 Hz, DAC code at
midscale, 5-V span, external reference 25
= 2.5 V, output unloaded
Output noise µVPP
0.1 Hz to 10 Hz, DAC code at
midscale, 5-V span, internal reference 30
= 2.5 V, output unloaded
1 kHz, DAC code at midscale, 5-
V span, output unloaded, external 115
reference
Output noise density nV/√Hz
10 kHz, DAC code at midscale, 5-
V span, output unloaded, external 105
reference
1-kHz sine wave on VOUTX, output
THD Total harmonic distortion 88 dB
unloaded, DAC update rate = 400 kHz
VOUTX = 0 V (midscale), output
unloaded, ±10-V output,
PSRR-AC Power supply ac rejection ratio frequency = 60 Hz, 75 dB
amplitude 200 mVPP,
superimposed on AVDD, DVDD or AVSS

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7.5 Electrical Characteristics (continued)

all minimum/maximum specifications at TA = –40°C to +125°C and all typical specifications at TA = 25°C, AVDD = 4.5 V to
41.5 V, AVSS = –21.5 V to 0 V, DVDD = 5.0 V, internal reference enabled, IOVDD = 1.7 V, VSENSENX = 0 V, CCOMPX floating,
DAC outputs unloaded, and digital inputs at IOVDD or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUTX = 0 V (midscale), ±10-V output,
DVDD = 5 V, AVDD = 15 V ± 20%, 5
AVSS = –15 V, output unloaded
µV/V
VOUTX = 0 V (midscale), ±10-V output,
PSRR-DC Power supply dc rejection ratio DVDD = 5 V, AVDD = 15 V, 10
AVSS = –15 V ± 20%, output unloaded
VOUTX = 0 V (midscale), ±10-V output,
DVDD = 5 V ± 5%, AVDD = 15 V, 0.2 mV/V
AVSS = –15 V, output unloaded
1-LSB change around midscale,
1
0-V to 5-V range, output unloaded
1-LSB change around midscale,
2
0-V to 10-V range, output unloaded
Code change glitch impulse 1-LSB change around midscale, nV-s
2
–5-V to +5-V range, output unloaded
1-LSB change around midscale,
–10-V to +10-V range, output 4
unloaded
1-LSB change around midscale,
0-V to 5-V, 0-V to 10-V, –5-V to +5-
Code change glitch amplitude ±10 mV
V and –10-V to +10-V ranges, output
unloaded
10-V span, full-scale swing on all
Channel-to-channel ac crosstalk other channel, measured channel at 1 nV-s
midscale, output unloaded
10-V span, full-scale swing on all
Channel-to-channel dc crosstalk other channel, measured channel at 1 LSB
midscale, output unloaded
10-V span, full-scale swing on all
Digital crosstalk other input buffer, measured channel 1 nV-s
at midscale, output unloaded
DAC code at midscale, fSCLK = 1 MHz,
Digital feedthrough 1 nV-s
output unloaded

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7.5 Electrical Characteristics (continued)

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7.5 Electrical Characteristics (continued)

(1) End point fit between codes. 16-bit: 512 to 65024 for AVDD ≥ 5.5 V, 512 to 63488 for AVDD ≤ 5.5 V, 0.2-V headroom between VREFIO
and AVDD; 12-bit: 32 to 4064 for AVDD ≥ 5.5 V, 32 to 3968 for AVDD ≤ 5.5 V, 0.2-V headroom between VREFIO and AVDD.
(2) Full-scale code written to the DAC for AVDD ≥ 5.5 V. 16-bit: code 63488 written to the DAC for AVDD ≤ 5.5 V; 12-bit: code 3968 written
to the DAC for AVDD ≤ 5.5 V.
(3) Temporary overload condition protection. junction temperature can be exceeded during current limit. operation above the specified
maximum junction temperature may impair device reliability.
(4) Specified by design and characterization, not production tested.
(5) AVDD = +15 V, AVSS = –15 V, DVDD = 5 V, SPI static, 10-V output span, all DAC at full scale, VOUTX unloaded.

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7.6 Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V

all specifications at TA = –40°C to +125°C, input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed
from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, 1.7 V ≤ IOVDD < 2.7 V
PARAMETER MIN NOM MAX UNIT
fSCLK SCLK frequency 25 MHz
tSCLKHIGH SCLK high time 20 ns
tSCLKLOW SCLK low time 20 ns
tSDIS SDIN setup 10 ns
tSDIH SDIN hold 10 ns
tCSS SYNC to SCLK falling edge setup 30 ns
tCSH SCLK falling edge to SYNC rising edge 10 ns
tCSHIGH SYNC high time 50 ns
tDACWAIT Sequential DAC update wait time 2.4 µs
tBCASTWAIT Broadcast DAC update wait time 4 µs
tLDACAL SYNC rising edge to LDAC falling edge 80 ns
tLDACW LDAC low time 20 ns
tCLRW CLR low time 20 ns
tRSTW RST low time 20 ns

7.7 Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V

all specifications at TA = –40°C to +125°C, input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed
from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, 2.7 V ≤ IOVDD ≤ 5.5 V
PARAMETER MIN NOM MAX UNIT
fSCLK SCLK frequency 50 MHz
tSCLKHIGH SCLK high time 10 ns
tSCLKLOW SCLK low time 10 ns
tSDIS SDIN setup 5 ns
tSDIH SDIN hold 5 ns
tCSS SYNC to SCLK falling edge setup 15 ns
tCSH SCLK falling edge to SYNC rising edge 5 ns
tCSHIGH SYNC high time 25 ns
tDACWAIT Sequential DAC update wait time 2.4 µs
tBCASTWAIT Broadcast DAC update wait time 4 µs
tLDACAL SYNC rising edge to LDAC falling edge 40 ns
tLDACW LDAC low time 20 ns
tCLRW CLR low time 20 ns
tRSTW RST low time 20 ns

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7.8 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
all specifications at TA = –40°C to +125°C, input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed
from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, 1.7 V ≤ IOVDD < 2.7 V
PARAMETER MIN NOM MAX UNIT
fSCLK SCLK frequency 12.5 MHz
tSCLKHIGH SCLK high time 33 ns
tSCLKLOW SCLK low time 33 ns
tSDIS SDIN setup 10 ns
tSDIH SDIN hold 10 ns
tCSS SYNC to SCLK falling edge setup 30 ns
tCSH SCLK falling edge to SYNC rising edge 10 ns
tCSHIGH SYNC high time 50 ns
tSDOZ SDO driven to tri-state mode 0 30 ns
tSDODLY SDO output delay from SCLK rising edge 0 30 ns

7.9 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
all specifications at TA = –40°C to +125°C, input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed
from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, 1.7 V ≤ IOVDD < 2.7 V
PARAMETER MIN NOM MAX UNIT
fSCLK SCLK frequency 25 MHz
tSCLKHIGH SCLK high time 20 ns
tSCLKLOW SCLK low time 20 ns
tSDIS SDIN setup 10 ns
tSDIH SDIN hold 10 ns
tCSS SYNC to SCLK falling edge setup 30 ns
tCSH SCLK falling edge to SYNC rising edge 10 ns
tCSHIGH SYNC high time 50 ns
tSDOZ SDO driven to tri-state mode 0 30 ns
tSDODLY SDO output delay from SCLK rising edge 0 30 ns

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7.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
all specifications at TA = –40°C to +125°C, input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed
from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, 2.7 V ≤ IOVDD ≤ 5.5 V
PARAMETER MIN NOM MAX UNIT
fSCLK SCLK frequency 20 MHz
tSCLKHIGH SCLK high time 25 ns
tSCLKLOW SCLK low time 25 ns
tSDIS SDIN setup 5 ns
tSDIH SDIN hold 5 ns
tCSS SYNC to SCLK falling edge setup 20 ns
tCSH SCLK falling edge to SYNC rising edge 5 ns
tCSHIGH SYNC high time 25 ns
tSDOZ SDO driven to tri-state mode 0 20 ns
tSDODLY SDO output delay from SCLK rising edge 0 20 ns

7.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
all specifications at TA = –40°C to +125°C, input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed
from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, 2.7 V ≤ IOVDD ≤ 5.5 V
PARAMETER MIN NOM MAX UNIT
fSCLK SCLK frequency 35 MHz
tSCLKHIGH SCLK high time 14 ns
tSCLKLOW SCLK low time 14 ns
tSDIS SDIN setup 5 ns
tSDIH SDIN hold 5 ns
tCSS SYNC to SCLK falling edge setup 20 ns
tCSH SCLK falling edge to SYNC rising edge 5 ns
tCSHIGH SYNC high time 25 ns
tSDOZ SDO driven to tri-state mode 0 20 ns
tSDODLY SDO output delay from SCLK rising edge 0 20 ns

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7.12 Timing Diagrams

tCSHIGH tCSS tCSH

SYNC

tSCLKLOW
SCLK
tSCLKHIGH

tSDIS tSDIH

SDIN Bit 23 Bit 1 Bit 0

LDAC(A)

LDAC(B)
tCLRW
tLDACAL tLDACW

CLR

tRSTW

RST

A. Asynchronous update.
B. Synchronous update.

Figure 7-1. Serial Interface Write Timing Diagram

tCSHIGH
tCSS tCSH

SYNC

tSCLKLOW
SCLK
tSCLKHIGH

FIRST READ COMMAND ANY COMMAND

SDIN Bit 23 Bit 22 Bit 0 Bit 23 Bit 22 Bit 0

tSDIS tSDIH
DATA FROM FIRST
READ COMMAND
SDO
Bit 23 Bit 22 Bit 0
tSDOZ
tSDODLY

Figure 7-2. Serial Interface Read Timing Diagram

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7.13 Typical Characteristics

at TA = 25°C, DVDD = 5.0 V, IOVDD = 1.8 V, internal reference enabled, unipolar ranges: AVSS = 0 V and AVDD ≥ VMAX + 1.5
V for the DAC range, bipolar ranges: AVSS ≤ VMIN − 1.5 V and AVDD ≥ VMAX + 1.5 V for the DAC range, and DAC outputs
unloaded (unless otherwise noted)

Figure 7-3. DAC81404 INL vs Digital Input Code Figure 7-4. DAC81404 INL vs Digital Input Code
(Bipolar Outputs) (Unipolar Outputs)

Figure 7-5. DAC81404 DNL vs Digital Input Code Figure 7-6. DAC81404 DNL vs Digital Input Code
(Bipolar Outputs) (Unipolar Outputs)

Figure 7-7. DAC81404 TUE vs Digital Input Code Figure 7-8. DAC81404 TUE vs Digital Input Code
(Bipolar Outputs) (Unipolar Outputs)

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7.13 Typical Characteristics (continued)

Figure 7-9. DAC61404 INL vs Digital Input Code Figure 7-10. DAC61404 INL vs Digital Input Code
(Bipolar Outputs) (Unipolar Outputs)

Figure 7-11. DAC61404 DNL vs Digital Input Code Figure 7-12. DAC61404 DNL vs Digital Input Code
(Bipolar Outputs) (Unipolar Outputs)

Figure 7-13. DAC61404 TUE vs Digital Input Code Figure 7-14. DAC61404 TUE vs Digital Input Code
(Bipolar Outputs) (Unipolar Outputs)

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7.13 Typical Characteristics (continued)

Figure 7-15. DAC81404 INL vs Temperature Figure 7-16. DAC81404 DNL vs Temperature

Figure 7-17. DAC61404 INL vs Temperature Figure 7-18. DAC61404 DNL vs Temperature

Figure 7-19. TUE vs Temperature Figure 7-20. Unipolar Offset Error vs Temperature

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7.13 Typical Characteristics (continued)

Figure 7-21. Unipolar Zero Code Error vs Temperature Figure 7-22. Bipolar Zero Code Error vs Temperature

Figure 7-23. Bipolar Zero Error vs Temperature Figure 7-24. Gain Error vs Temperature

Figure 7-25. Full-Scale Error vs Temperature Figure 7-26. Supply Current (DIDD)
vs Digital Input Code

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7.13 Typical Characteristics (continued)

Figure 7-27. Supply Current (AIDD, AISS) Figure 7-28. Supply Current (IIOVDD)
vs Digital Input Code vs Supply Voltage

DAC range: ±20 V DAC range: ±20 V

Figure 7-29. Supply Current vs Temperature Figure 7-30. Power-Down Current vs Temperature

Figure 7-31. Headroom and Footroom from Supply Figure 7-32. Source and Sink Capability
vs Output Current

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7.13 Typical Characteristics (continued)

DAC range: ±10 V DAC range: ±10 V

Figure 7-33. Full-Scale Settling Time, Rising Edge Figure 7-34. Full-Scale Settling Time, Falling Edge

DAC range: ±20 V DAC range: ±10 V

Figure 7-35. DAC Output Enable Glitch Figure 7-36. Glitch Impulse, 1 LSB Step,
Rising Edge

DAC range: ±10 V

Figure 7-37. Glitch Impulse, 1 LSB Step,
Falling Edge Figure 7-38. Power-Up Response

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7.13 Typical Characteristics (continued)

DAC range: ±20 V

Figure 7-39. Power-Down Response Figure 7-40. Clear Command Response

DAC range: 0 V to 5 V DAC range: 0 V to 5 V

Midscale code Midscale code

Figure 7-41. DAC Output Noise Density vs Frequency Figure 7-42. DAC Output Noise

Figure 7-43. Internal Reference Voltage vs Temperature Figure 7-44. Internal Reference Voltage
vs Supply Voltage

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7.13 Typical Characteristics (continued)

Figure 7-45. Internal Reference Voltage vs Time Figure 7-46. Internal Reference Noise Density vs Frequency

Figure 7-47. Internal Reference Noise Figure 7-48. Internal Reference Temperature Drift Histogram

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8 Detailed Description
8.1 Overview
The 16-bit DAC81404 and 12-bit DAC61404 (DACx1404) are pin-compatible, quad-channel, high-voltage output,
digital-to-analog converters (DACs). The DACx1404 consist of an R-2R-based ladder followed by an output
buffer. The devices also include a precision reference and a reference buffer. The R-2R-based ladder is
production trimmed to provide monotonicity and a linearity of ±1 LSB. The devices are also optimized to reduce
the code-to-code change glitch to less than 2 nV-s.
The DACx1404 output amplifier provides bipolar voltage outputs up to ±20 V, and unipolar voltage outputs up to
40 V. Each output channel includes sense pins to eliminate the IR drop across load connections, and sense a
difference of up to ±12 V between the load and DAC grounds. Alternatively, the sense pins can also be used for
output offset adjustment. An external capacitor compensation pin is also provided to stabilize the output amplifier
for high capacitive loads.
Communication to the DACx1404 is performed through a 4-wire serial interface that supports stand-alone and
daisy-chain operation. An optional frame-error check provides added robustness to the device serial interface.
The DACx1404 incorporate a power-on-reset circuit that connects the DAC outputs to ground at power up. The
outputs remain in this mode until the device is properly configured for operation. The devices include additional
reliability features such as short-circuit protection and a thermal alarm.
8.2 Functional Block Diagram
IOVDD DVDD FAULT REFIO AVDD

Internal Reference

Power On REF
SCLK Reset BUF

SDIN
REF
SYNC
Buffer Active DAC CCOMP[A:D]
SDO +
SPI

Register Register Ladder

OUT[A:D]
LDAC
–
RST 40 k
CLR 40 k SENSEP[A:D]
Channel 40 k – SENSEN[A:D]
A
+ 40 k

Resistor Gain
REF Network

GND AGND REFGND AVSS

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8.3 Feature Description

Each output channel in the device consists of an R-2R ladder digital-to-analog converter (DAC) with dedicated
reference and ground buffers, and an output buffer amplifier capable of rail-to-rail operation. The device also
includes an internal 2.5-V reference. Figure 8-1 shows a simplified diagram of the device architecture.
IOVDD DVDD REFIO

Internal REF
Reference BUF

REF

Buffer Active DAC

AVDD
(async mode)
+ CCOMPX
LDAC Trigger Clear Signal OUTX
(synchronous mode)
- AVSS
40 k
40 k SENSEPX
40 k
- SENSENX
+ 40 k

Resistor Gain
REF Network

GND AGND REFGND

Figure 8-1. Device Architecture

8.3.1 R-2R Ladder DAC

The DAC architecture consists of a voltage-output, segmented, R-2R ladder as shown in Figure 8-2. The device
incorporates a dedicated reference buffer per output channel that provides constant input impedance with code
at the REFIO pin. The output of the reference buffers drives the R-2R ladders. A production trim process
provides excellent linearity and low glitch.

Output
Amplifier
R R R R
OUTX
Internal
2R

Reference
SW

REFIO

Reference
Buffer
REFGND

Figure 8-2. R-2R Ladder

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8.3.2 Programmable-Gain Output Buffer

The voltage output stage as conceptualized in Figure 8-3 provides the voltage output according to the DAC code
and the output range setting.
REFIO
AVDD
DAC CCOMPX
Ladder +
OUTX
- AVSS
40 k
40 k SENSEPX
- SENSENX
+
40 k
40 k

REFIO

Resistor Gain
Network REFGND

Figure 8-3. Voltage Output Buffer

For unipolar output mode, the output range can be programmed as:
• 0 V to 5 V
• 0 V to 10 V
• 0 V to 20 V
• 0 V to 40 V
For bipolar output mode, the output reange can be programmed as:
• ±5 V
• ±10 V
• ±20 V
In addition, 20% overrange is available on all ranges except for 0 V to 40 V and ±20 V.
The input data are written to the individual DAC data registers in straight-binary format for all output ranges. The
output voltage (VOUTX) can be expressed as Equation 1 and Equation 2.
For unipolar output mode

CODE
VOUTX VREFIO u GAIN u
2N (1)

For bipolar output mode

CODE VREFIO
VOUTX VREFIO u GAIN u GAIN u
2N 2 (2)
where:
• CODE is the decimal equivalent of the binary code loaded to the DAC data register.
• N is the DAC resolution in bits.
• VREFIO is the reference voltage (internal or external).
• GAIN is the gain factor assigned to each output voltage output range as shown in Table 8-1.

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Table 8-1. Voltage Output Range vs Gain Setting

MODE VOLTAGE OUTPUT RANGE GAIN
5V 2.0
6 V (20% overrange) 2.4
10 V 4.0
Unipolar 12 V (20% overrange) 4.8
20 V 8.0
24 V (20% overrange) 9.6
40 V 16.0
±5 V 4.0
±6 V (20% overrange) 4.8
Bipolar ±10 V 8.0
±12 V (20% overrange) 9.6
±20 V 16.0

The output amplifiers can drive up to ±15 mA with 1.5-V supply headroom while maintaining the specified TUE
specification for the device. The output stage has short-circuit current protection that limits the output current
to 40 mA. The device is able to drive capacitive loads up to 1 µF. For loads greater than 2 nF, an external
compensation capacitor must be connected between the CCOMPx and OUTx pins to keep the output voltage
stable, but at the expense of reduced bandwidth and increased settling time.
8.3.2.1 Sense Pins
The SENSEPx pins are provided to enable sensing of the load by connecting to points electrically closer to
the load. This configuration allows the internal output amplifier to make sure that the correct voltage is applied
across the load, as long as headroom is available on the power supply. The SENSEPx pins are used to correct
for resistive drops on the system board, and are connected to VOUTX at the pins. In some cases, both VOUTX and
VSENSEPX are brought out through separate lines and connected remotely together at the load. In such cases, if
the VSENSEPX line is cut, then the amplifier loop is broken; use a 5-kΩ resistor between the OUTx and SENSEPx
pins to maintain proper amplifier operation.
The SENSENx pins are provided as remote ground sense reference outputs from the internal VOUTX amplifier.
The output swing of the VOUTX amplifier is relative to the voltage seen at these pins. The voltage difference
between VSENSENX and the device ground must be lower than ±12 V.
At device start up, the power-on-reset circuit makes sure that all registers are at default values. The voltage
output buffer is in a Hi-Z state; however, the SENSEPx pins connect to the amplifier inputs through an internal
40-kΩ feedback resistor (Figure 8-3). If the OUTx and SENSEPx pins are connected together, the OUTx pins are
also connected to the same node through the feedback resistor. This node is protected by internal circuitry and
settles to a value between GND and the reference input.

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8.3.3 DAC Register Structure

Data written to the DAC data registers is initially stored in the DAC buffer registers. The transfer of data from the
DAC buffer registers to the active registers can be configured to occur immediately (asynchronous mode) or be
initiated by a DAC trigger signal (synchronous mode). After the active registers are updated, the DAC outputs
change to the new values.
After a power-on or reset event, all DAC registers set to zero code, the DAC output amplifiers power down, and
the DAC outputs connect to ground.
8.3.3.1 DAC Output Update
The DAC double-buffered architecture enables data updates without disturbing the analog outputs. Data updates
can be performed either in synchronous or asynchronous mode. The device offers both software and hardware
data update control.
The update mode for each DAC channel is determined by the status of the corresponding SYNC-EN bit. In both
update modes, a minimum wait time of 2.4 μs is required between DAC output updates.
8.3.3.1.1 Synchronous Update
In synchronous mode, writing to the DAC data register does not automatically update the DAC output. Instead
the update occurs only after a trigger event. A DAC trigger signal is generated eigher through the SOFT-LDAC
bit or by the LDAC pin. The synchronous update mode enables simultaneous update of multiple DAC outputs.
8.3.3.1.2 Asynchronous Update
In asynchronous mode, a DAC data register write results in an immediate update of the DAC active register and
DAC output on a SYNC rising edge.
8.3.3.2 Broadcast DAC Register
The DAC broadcast register enables a simultaneous update of multiple DAC outputs with the same value with a
single register write.
Each DAC channel can be configured to update or remain unaffected by a broadcast command by setting
the corresponding DAC-BRDCAST-EN bit. A register write to the BRDCAST-DATA register forces those DAC
channels that have been configured for broadcast operation to update their DAC buffer registers to this value.
The DAC outputs update to the broadcast value according to their synchronous mode configuration.
8.3.3.3 Clear DAC Operation
The DAC outputs are set in clear mode either through the CLR pin or the SOFT-CLR bit. In clear mode, each
DAC data register is set to either zero code (if configured for unipolar range operation) or midscale code (if set
for bipolar range operation). A clear command forces all DAC channels to clear the contents of their buffer and
active registers to the clear code regardless of their synchronization setting.

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8.3.4 Internal Reference

The device includes a precision 2.5-V band-gap reference with a maximum temperature drift of 10 ppm/°C. The
internal reference is in power-down mode by default.
The internal reference voltage is available at the REFIO pin and can source up to 5 mA. To filter noise, place a
minimum 150-nF capacitor between the reference output and ground.
External reference operation is also supported. The external reference is applied to the REFIO pin. If using an
external reference, power down the internal reference.
8.3.5 Power-On Reset (POR)
The device incorporates a power-on-reset function. After the supplies reach their minimum specified values, a
POR event is issued. Additionally, a POR event can be initiated by the RST pin or a SOFT-RESET command.
A POR event causes all registers to initialize to default values, and communication with the device is valid only
after a 1 ms POR delay. After a POR event, the device is set to power-down mode, where all DAC channels and
internal reference are powered down and the DAC outputs are connected to ground through a 10-kΩ internal
resistor.
8.3.5.1 Hardware Reset
A device hardware reset event is initiated by a minimum 20-ns logic low on the RST pin.
8.3.5.2 Software Reset
The device implements a software reset feature. A device software reset is initiated by writing reserved code
0x1010 to SOFT-RESET in the TRIGGER register. The software reset command is triggered on the SYNC rising
edge of the instruction.
8.3.6 Thermal Alarm
The device incorporates a thermal shutdown that is triggered when the die temperature exceeds 140°C. A
thermal shutdown sets the TEMP-ALM bit, and causes all DAC outputs to power-down; however, the internal
reference remains powered on. The FAULT pin can be configured to monitor a thermal shutdown condition by
setting the TEMPALM-EN bit. After a thermal shutdown is triggered, the device stays in shutdown even after the
device temperature lowers.
The die temperature must fall to less than 140°C before the device can be returned to normal operation.
To resume normal operation, the thermal alarm must be cleared through the ALM-RESET bit while the DAC
channels are in power-down mode.
8.4 Device Functional Modes
8.4.1 Power-Down Mode
The device output amplifiers and internal reference power-down status can be individually configured and
monitored though the PWDWN registers. Setting a DAC channel in power-down mode disables the output
amplifier and clamps the output pin to ground through an internal 10-kΩ resistor.
The DAC data registers are not cleared when the DAC goes into power-down mode. Therefore, upon return to
normal operation, the DAC output voltages return to the same respective voltages prior to the device entering
power-down mode. The DAC data registers can be updated while in power-down mode, which allows for
changing the power-on voltage, if required.
After a power-on or reset event, all the DAC channels and the internal reference are in power-down mode. The
entire device can be configured into power-down or active modes through the DEV-PWDWN bit.

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8.5 Programming
The device is controlled through an SPI-compatible, flexible, four-wire, serial interface. The interface provides
access to the device registers, and can be configured to daisy-chain multiple devices for write operations.
The device incorporates an optional error-checking mode to validate SPI data communication integrity in noisy
environments.
8.5.1 Stand-Alone Operation
A serial interface access cycle is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be a
continuous or gated clock. SDIN data are clocked on SCLK falling edges. A regular serial interface access cycle
is 24 bits long with error checking disabled and 32 bits long with error checking enabled. Therefore, the SYNC
pin must stay low for at least 24 or 32 SCLK falling edges. The access cycle ends when the SYNC pin is
deasserted high. If the access cycle contains less than the minimum clock edges, the communication is ignored.
If the access cycle contains more than the minimum clock edges, only the first 24 or 32 bits are used by the
device. When SYNC is high, the SCLK and SDIN signals are blocked, and SDO is in a Hi-Z state.
Table 8-2 describes the format for an error-checking-disabled access cycle (24-bits long). The first byte input to
SDIN is the instruction cycle. The instruction cycle identifies the request as a read or write command and the
6-bit address that is to be accessed. The last 16 bits in the cycle form the data cycle.
Table 8-2. Serial Interface Access Cycle
BIT FIELD DESCRIPTION
Identifies the communication as a read or write command to the address
register:
23 RW
R/W = 0 sets a write operation.
R/W = 1 sets a read operation
22 x Don't care bit
Register address — specifies the register to be accessed during the read or
21-16 A[5:0]
write operation
Data cycle bits:
If a write command, the data cycle bits are the values to be written to the
15-0 DI[15:0]
register with address A[5:0]
If a read command, the data cycle bits are don't care values

Read operations require that the SDO pin is first enabled by setting the SDO-EN bit. A read operation is initiated
by issuing a read command access cycle. After the read command, a second access cycle must be issued to get
the requested data. The output data format is shown in Table 8-3. Data are clocked out on the SDO pin either on
the falling edge or rising edge of SCLK according to the FSDO bit.
Table 8-3. SDO Output Access Cycle
BIT FIELD DESCRIPTION
23 RW Echo RW from previous access cycle
22 x Echo bit 22 from previous access cycle
21-16 A[5:0] Echo address from previous access cycle
15-0 DO[15:0] Readback data requested on previous access cycle

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8.5.2 Daisy-Chain Operation

For systems that contain several devices, the SDO pin can be used to daisy-chain the devices together.
Daisy-chain operation is useful in reducing the number of serial interface lines.The SDO pin must be enabled by
setting the SDO-EN bit before initiating daisy-chain operation.
The first falling edge on the SYNC pin starts the operation cycle (see Figure 8-4). If more than 24 clock pulses
are applied while the SYNC pin is kept low, the data ripple out of the shift register and are clocked out on
the SDO pin, either on the falling edge or rising edge of SCLK according to the FSDO bit. By connecting the
SDO output of the first device to the SDIN input of the next device in the chain, a multiple-device interface is
constructed.
Each device in the daisy-chain system requires 24 clock pulses. As a result the total number of clock cycles
must be equal to 24 × N, where N is the total number of devices in the daisy chain. When the serial transfer to all
devices is complete, the SYNC signal is taken high. This action transfers the data from the SPI shift registers to
the internal register of each device in the daisy chain, and prevents any further data from being clocked into the
input shift register.

SYNC

1 8 9 24 25 48 49 72

SCLK

Device A command Device B command NOP

SDIN D23 D16 D15 D0 D23 ± D1 D0 D23 ± D1 D0

SDO Device A command Device B command

Figure 8-4. Serial Interface Daisy-Chain Write Cycle

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8.5.3 Frame Error Checking

If the device is used in a noisy environment, error checking can be used to check the integrity of SPI data
communication between the device and the host processor. This feature is enabled by setting the CRC-EN bit.
The error checking scheme is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (that is, 100000111).
When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data are
appended with an 8-bit CRC polynomial by the host processor before feeding the data to the device. In all serial
interface readback operations, the CRC polynomial is output on the SDO pin as part of the 32-bit cycle.
Table 8-4. Error Checking Serial Interface Access Cycle
BIT FIELD DESCRIPTION
Identifies the communication as a read or write command to the address
register.
31 RW
R/W = 0 sets a write operation.
R/W = 1 sets a read operation.
30 CRC-ERROR Reserved bit. Set to zero.
Register address. Specifies the register to be accessed during the read or
29-24 A[5:0]
write operation.
Data cycle bits.
If a write command, the data cycle bits are the values to be written to the
23-8 DI[15:0]
register with address A[5:0].
If a read command, the data cycle bits are don't care values.
7-0 CRC 8-bit CRC polynomial.

The device decodes the 32-bit access cycle to compute the CRC remainder on SYNC rising edges. If no error
exists, the CRC remainder is zero and data are accepted by the device.
A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a
second access cycle can be issued to determine the error checking results (CRC-ERROR bit) on the SDO pin.
If there is a CRC error, the CRC-ALM bit of the status register is set to 1. The FAULT pin can be configured to
monitor a CRC error by setting the CRCALM-EN bit.
Table 8-5. Write Operation Error Checking Cycle
BIT FIELD DESCRIPTION
31 RW Echo RW from previous access cycle (RW = 0).
30 CRC-ERROR Returns a 1 when a CRC error is detected; otherwise, returns a 0.
29-24 A[5:0] Echo address from previous access cycle.
23-8 DO[15:0] Echo data from previous access cycle.
7-0 CRC Calculated CRC value of bits 31:8.

A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The
error check result (CRC-ERROR bit) from the read command is output on the SDO pin.
As in the case of a write operation failing the CRC check, the CRC-ALM bit of the status register is set to 1, and
the ALMOUT pin, if configured for CRC alerts, is set low.
Table 8-6. Read Operation Error Checking Cycle
BIT FIELD DESCRIPTION
31 RW Echo RW from previous access cycle (RW = 1).
30 CRC-ERROR Returns a 1 when a CRC error is detected; otherwise, returns a 0.
29-24 A[5:0] Echo address from previous access cycle.
23-8 DO[15:0] Readback data requested on previous access cycle.
7-0 CRC Calculated CRC value of bits 31:8.

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8.6 Register Map

Table 8-7 lists the memory-mapped registers for the device. All register addresses not listed should be considered as reserved locations and the register
contents should not be modified.
Table 8-7. Register Map
ADDR RESET BIT DESCRIPTION
REGISTER TYPE
(HEX) (HEX) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00 NOP W 0000 NOP[15:0]
0A60(1)
01 DEVICEID R or DEVICEID[13:0] VERSIONID[1:0]
0920(2)
DAC- TEMP-
02 STATUS R 0000 RESERVED CRC-ALM
BUSY ALM
TEMPALM- DACBUSY- CRCALM- DEV-
03 SPICONFIG R/W 0AA4 RESERVED RESERVED CRC-EN RSVD SDO-EN FSDO RSVD
EN EN EN PWDWN
REF-
04 GENCONFIG R/W 4000 RSVD RESERVED
PWDWN
DACD- DACC- DACB- DACA-
05 BRDCONFIG R/W 000F RESERVED BRDCAST BRDCAST BRDCAST BRDCAST
-EN -EN -EN -EN
DACD- DACC- DACB- DACA-
06 SYNCCONFIG R/W 0000 RESERVED
SYNC-EN SYNC-EN SYNC-EN SYNC-EN
DACD- DACC- DACB- DACA-
09 DACPWDWN R/W FFFF RESERVED
PWDWN PWDWN PWDWN PWDWN
0A DACRANGE W 0000 DACD-RANGE[3:0] DACC-RANGE[3:0] DACB-RANGE[3:0] DACA-RANGE[3:0]
ALM- SOFT-
0E TRIGGER R/W 0000 RESERVED SOFT-CLR RESERVED SOFT-RESET[3:0]
RESET LDAC
0F BRDCAST W 0000 BRDCAST-DATA[15:0]
10 DACA W 0000 DACA-DATA[15:0]
11 DACB W 0000 DACB-DATA[15:0]
12 DACC W 0000 DACC-DATA[15:0]
13 DACD W 0000 DACD-DATA[15:0]

(1) Reset code for DAC81404.

(2) Reset code for DAC61404.

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8.6.1 NOP Register (address = 00h) [reset = 0000h]

Return to Register Map.
Figure 8-5. NOP Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOP[15:0]
W-0000h

Table 8-8. NOP Register Field Descriptions

Bit Field Type Reset Description
15-0 NOP[15:0] W 0000h No operation. Write 0000h for proper no-operation command.

8.6.2 DEVICEID Register (address = 01h) [reset = 0A60h or 0920h]

Return to Register Map.
Figure 8-6. DEVICEID Register
15 14 13 12 11 10 9 8
DEVICEID[13:6]
R
7 6 5 4 3 2 1 0
DEVICEID[5:0] VERSIONID[1:0]
R R-0h

Table 8-9. DEVICEID Register Field Descriptions

Bit Field Type Reset Description
15-2 DEVICEID[13:0] R 0298h DAC81404 device ID.
0248h DAC61404 device ID.
1-0 VERSIONID[1:0] R 0h Version ID. Subject to change.

8.6.3 STATUS Register (address = 02h) [reset = 0000h]

Return to Register Map.
Figure 8-7. STATUS Register
15 14 13 12 11 10 9 8
RESERVED
R-00h
7 6 5 4 3 2 1 0
RESERVED CRC-ALM DAC-BUSY TEMP-ALM
R-00h R-0h R-0h R-0h

Table 8-10. STATUS Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R 0000h Reserved for factory use
2 CRC-ALM R 0h CRC-ALM = 1 indicates a CRC error.
1 DAC-BUSY R 0h DAC-BUSY = 1 indicates DAC registers are not ready for updates.
0 TEMP-ALM R 0h TEMP-ALM = 1 indicates die temperature is over 140°C. A thermal
alarm event forces the DAC outputs to go into power-down mode.

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8.6.4 SPICONFIG Register (address = 03h) [reset = 0AA4h]

Return to Register Map.
Figure 8-8. SPICONFIG Register
15 14 13 12 11 10 9 8
RESERVED TEMPALM-EN DACBUSY-EN CRCALM-EN RESERVED
R-0h R/W-1h R/W-0h R/W-1h R-0h
7 6 5 4 3 2 1 0
RESERVED DEV-PWDWN CRC-EN RESERVED SDO-EN FSDO RESERVED
R-1h R-0h R/W-1h R/W-0h R-0h R/W-1h R/W-0h R-0h

Table 8-11. SPICONFIG Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R 0h Reserved for factory use
11 TEMPALM-EN R/W 1h When set to 1, a thermal alarm triggers the FAULT pin.
10 DACBUSY-EN R/W 0h When set to 1, the FAULT pin is set between DAC output updates.
Contrary to other alarm events, this alarm resets automatically.
9 CRCALM-EN R/W 1h When set to 1, a CRC error triggers the FAULT pin..
8-6 RESERVED R 2h Reserved for factory use
DEV-PWDWN = 1 sets the device in power-down mode.
5 DEV-PWDWN R/W 1h
DEV-PWDWN = 0 sets the device in active mode.
4 CRC-EN R/W 0h When set to 1, frame error checking is enabled.
3 RESERVED R 0h Reserved for factory use
2 SDO-EN R/W 1h When set to 1, the SDO pin is operational.
1 FSDO R/W 0h Fast SDO bit (half-cycle speedup).
When 0, SDO updates on SCLK rising edges.
When 1, SDO updates on SCLK falling edges.
0 RESERVED R 0h Reserved for factory use

8.6.5 GENCONFIG Register (address = 04h) [reset = 4000h]

Return to Register Map.
Figure 8-9. GENCONFIG Register
15 14 13 12 11 10 9 8
RESERVED REF-PWDWN RESERVED
R-0h R/W-1h R-00h
7 6 5 4 3 2 1 0
RESERVED
R-00h

Table 8-12. GENCONFIG Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R 0h Reserved for factory use
14 REF-PWDWN R/W 1h REF-PWDWN = 1 powers down the internal reference.
REF-PWDWN = 0 activates the internal reference.
13-0 RESERVED R 0000h Reserved for factory use

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8.6.6 BRDCONFIG Register (address = 05h) [reset = 000Fh]

Return to Register Map.
Figure 8-10. BRDCONFIG Register
15 14 13 12 11 10 9 8
RESERVED
R-00h
7 6 5 4 3 2 1 0
RESERVED DACD- DACC- DACB- DACA-
BRDCAST_EN BRDCAST-EN BRDCAST-EN BRDCAST-EN
R-0h R/W-1h R/W-1h R/W-1h R/W-1h

Table 8-13. BRDCONFIG Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R 000h Reserved for factory use
3 DACD-BRDCAST-EN R/W 1h When set to 1, the corresponding DAC is set to update the output to
the value set in the BDCAST register.
2 DACC-BRDCAST-EN R/W 1h
When cleared to 0, the corresponding DAC output remains
1 DACB-BRDCAST-EN R/W 1h unaffected by a BRDCAST command.
0 DACA_BRDCAST-EN R/W 1h

8.6.7 SYNCCONFIG Register (address = 06h) [reset = 0000h]

Return to Register Map.
Figure 8-11. SYNCCONFIG Register
15 14 13 12 11 10 9 8
RESERVED
R-00h
7 6 5 4 3 2 1 0
RESERVED DACD-SYNC- DACC-SYNC- DACB-SYNC- DACA-SYNC-
EN EN EN EN
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-14. SYNCCONFIG Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R 000h Reserved for factory use
3 DACD_SYNC_EN R/W 0h When set to 1, the corresponding DAC is set to update in response
to an LDAC trigger (synchronous mode).
2 DACC_SYNC_EN R/W 0h
When cleared to 0, the corresponding DAC output is set to update
1 DACB_SYNC_EN R/W 0h immediately on SYNC rising edge (asynchronous mode).
0 DACA_SYNC_EN R/W 0h

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8.6.8 DACPWDWN Register (address = 09h) [reset = FFFFh]

Return to Register Map.
Figure 8-12. DACPWDWN Register
15 14 13 12 11 10 9 8
RESERVED
R-FFh
7 6 5 4 3 2 1 0
RESERVED DACD-PWDWN DACC-PWDWN DACB-PWDWN DACA-PWDWN
R-Fh R/W-1h R/W-1h R/W-1h R/W-1h

Table 8-15. DACPWDWN Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R FFFh Reserved for factory use
3 DACD-PWDWN R/W 1h When set to 1, the corresponding DAC is in power-down mode, and
the output is connected to ground through a 10-kΩ internal resistor.
2 DACC-PWDWN R/W 1h
1 DACB-PWDWN R/W 1h
0 DACA-PWDWN R/W 1h

8.6.9 DACRANGE Register (address = 0Ah) [reset = 0000h]

Return to Register Map.
Figure 8-13. DACRANGE Register
15 14 13 12 11 10 9 8
DACD-RANGE[3:0] DACC-RANGE[3:0]
W-0h W-0h
7 6 5 4 3 2 1 0
DACB-RANGE[3:0] DACA-RANGE[3:0]
W-0h W-0h

Table 8-16. DACRANGE Register Field Descriptions

Bit Field Type Reset Description
15-12 DACD-RANGE[3:0] W 0h Sets the output range for the corresponding DAC.
0000: 0 V to 5 V
11-8 DACC-RANGE[3:0] W 0h
1000: 0 V to 6 V
7-4 DACB-RANGE[3:0] W 0h 0001: 0 V to 10 V
3-0 DACA-RANGE[3:0] W 0h 1001: 0 V to 12 V
0010: 0 V to 20 V
1010: 0 V to 24 V
0011: 0 V to 40 V
0101: –5 V to +5 V
1101: –6 V to +6 V
0110: –10 V to +10 V
1110: –12 V to +12 V
0111: –20 V to +20 V
All others: invalid

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8.6.10 TRIGGER Register (address = 0Eh) [reset = 0000h]

Return to Register Map.
Figure 8-14. TRIGGER Register
15 14 13 12 11 10 9 8
RESERVED SOFT-CLR ALM-RESET
W-00h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED SOFT-LDAC SOFT-RESET[3:0]
W-0h W-0h W-0h

Table 8-17. TRIGGER Register Field Descriptions

Bit Field Type Reset Description
15-10 RESERVED W 00h Reserved for factory use
9 SOFT-CLR W 0h Set this bit to 1 to clear all DAC outputs.
8 ALM-RESET W 0h Set this bit to 1 to clear an alarm event. Not applicable for a DAC-
BUSY alarm event.
7-5 RESERVED W 0h Reserved for factory use
4 SOFT-LDAC W 0h Set this bit to 1 to synchronously load the DACs that have been set
in synchronous mode in the SYNCCONFIG register.
3-0 SOFT_RESET[3:0] W 0h Set these bits to reserved code 1010 to reset the device to the
default state.

8.6.11 BRDCAST Register (address = 0Fh) [reset = 0000h]

Return to Register Map.
Figure 8-15. BRDCAST Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRDCAST-DATA[15:0]
W-0000h

Table 8-18. BRDCAST Register Field Descriptions

Bit Field Type Reset Description
15-0 BRDCAST_DATA[15:0] W 0000h Writing to the BRDCAST register forces the DAC channels that have
been set to broadcast in the BRDCONFIG register to update the data
register data to BRDCAST-DATA.
Data are MSB aligned in straight-binary format:
DAC81404: { DATA[15:0] }
DAC61404: { DATA[11:0], x, x, x, x }
x − Don't care bits

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8.6.12 DACn Register (address = 10h to 13h) [reset = 0000h]

Return to Register Map.
Figure 8-16. DACn Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACn-DATA[15:0]
W-0000h

Table 8-19. DACn Register Field Descriptions

Bit Field Type Reset Description
15-0 DACn-DATA[15:0] W 0000h Stores the data to be loaded to DACn in MSB-aligned, straight-binary
format:
DAC81404: { DATA[15:0] }
DAC61404: { DATA[11:0], x, x, x, x }
x − Don't care bits

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

A primary application of this device is programmable power supplies commonly used in automated test and
laboratory equipment, where high precision and programmable voltage ranges are important considerations.
This device, with an excellent linearity of ±1 LSB INL and inherently monotonic design, meets the criteria for
these applications. Apart from class-leading noise and drift performance, the per-channel programmable output
ranges make this device an excellent choice for a wide range of programmable power-supply designs.
9.2 Typical Application
Programmable power supplies are important building blocks in automated test equipments, semiconductor test
and bench top instrumentation units. The DAC is used to set the programmable voltage and a power stage is
designed to handle the output current requirements in these systems. Figure 9-1 shows a simplified diagram to
design such a programmable power supply unit.

VCC

T1
AVDD

D1
VSENSE
SENSEP OUTSENSE
Digital Control RSENSE
FPGA DAC81404 OUTFORCE
SPI ISENSE
SENSEN GNDFORCE
D2
GNDSENSE

ISENSE AVSS T2 GND

ADC VSENSE

VEE

Figure 9-1. Programmable Power Supply

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9.2.1 Design Requirements

• Voltage range : ±10 V, ±20 V, 0 V to 40 V
• Current range : 200 mA
9.2.2 Detailed Design Procedure
The DAC81404 is an excellent choice for this application because of the device exceptional linearity and noise
performance. The maximum bipolar output voltage requirement is ±20 V; therefore, set the AVDD and AVSS
supplies to 21 V and −21 V, respectively. For a unipolar output range, set the AVDD supply to 41 V for a full-scale
output voltage of 40 V. In unipolar designs, the AVSS supply can be tied to ground. In all cases, the supply
voltages must be selected so that the AVDD − AVSS voltage does not exceed 41.5 V.
The output stage is designed as a standard class AB output because of the design simplicity. A current limit
stage can be designed to limit the current in the output stage during a short-circuit event.
A simple diode-and-resistor-based biasing is chosen for the class AB output stage. A small constant current
flows through the series circuit of R1, D1, D2 and R2, producing symmetrical voltage drops on either side of the
input. With no input voltage applied, the point between the two diodes is 0 V. As current flows through the chain,
there is a forward-bias voltage drop of approximately 0.7 V across the diodes that are applied to the base-emitter
junctions of the switching transistors. Therefore, the voltage drop across the diodes biases the base of transistor
T1 to approximately 0.7 V, and the base of transistor T2 to approximately −0.7 V. Therefore, the two silicon
diodes provide a constant voltage drop of approximately 1.4 V between the two bases biasing them above cutoff.
Current and voltage is sensed and fed to an ADC to close the loop for the completion of the circuit. The device
has sense connections for sensing the output and load ground voltages. One of the key features of this device
is load-ground voltage compensation, which can be used in this design. The load ground and device ground
difference must be within ±12 V.
The R1 and R2 values are decided by how much quiescent current is required by the design biasing scheme.
Figure 9-2 and Figure 9-3 show simulation results of the output voltage programmed from −10 V to +10 V, while
providing a constant 100 mA current to the load.
9.2.3 Application Curves

Figure 9-2. DAC Code Sweep From −10 V to +10 V Figure 9-3. Output Error vs DAC Code

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10 Power Supply Recommendations

The device requires four power-supply inputs: IOVDD, DVDD, AVDD, and AVSS. A 0.1-µF ceramic capacitor
must be connected close to each power-supply pin. In addition, a 4.7-µF or 10-µF bulk capacitor is
recommended for each power supply. Tantalum or aluminum types can be chosen for the bulk capacitors.
There is no sequencing requirement for the power supplies. The DAC output range is configurable; therefore,
sufficient power-supply headroom is required to achieve linearity at codes close to the power-supply rails. When
sourcing or sinking current from or to the DAC output, make sure to account for the effects of power dissipation
on the temperature of the device, and ensure the device does not exceed the maximum junction temperature.
11 Layout
11.1 Layout Guidelines
Printed circuit board (PCB) layout plays a significant role in achieving desired ac and dc performance from the
device. The device has a pinout that supports easy splitting of the noisy and quiet grounds. The digital and
analog signals are available on separate sides of the package for easy layout. Figure 11-1 shows an example
layout where the different ground planes have been clearly demarcated, as well as the best position for the
single-point shorts between the planes.
For best power-supply bypassing, place the bypass capacitors close to the respective power-supply pins.
Provide unbroken ground reference planes for the digital signal traces, especially for the SPI and LDAC signals.
The RST and FAULT signals are static lines; therefore these lines can lie on the analog side of the ground plane.
11.2 Layout Example

Figure 11-1. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, BP-DAC81404EVM, BP-DAC61402EVM user's guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DAC61404RHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D61404

DAC61404RHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D61404

DAC81404RHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D81404

DAC81404RHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D81404

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
PACKAGE OPTION ADDENDUM

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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC61404RHBR VQFN RHB 32 3000 330.0 12.4 5.25 5.25 1.1 8.0 12.0 Q2
DAC61404RHBT VQFN RHB 32 250 180.0 12.5 5.25 5.25 1.1 8.0 12.0 Q2
DAC81404RHBR VQFN RHB 32 3000 330.0 12.4 5.25 5.25 1.1 8.0 12.0 Q2
DAC81404RHBT VQFN RHB 32 250 180.0 12.5 5.25 5.25 1.1 8.0 12.0 Q2

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PACKAGE MATERIALS INFORMATION

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC61404RHBR VQFN RHB 32 3000 338.0 355.0 50.0
DAC61404RHBT VQFN RHB 32 250 205.0 200.0 33.0
DAC81404RHBR VQFN RHB 32 3000 338.0 355.0 50.0
DAC81404RHBT VQFN RHB 32 250 205.0 200.0 33.0

Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32 VQFN - 1 mm max height
5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224745/A

www.ti.com
PACKAGE OUTLINE
RHB0032E SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

5.1 B
A
4.9

PIN 1 INDEX AREA

5.1 (0.1)
4.9

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS
20.000

C
1 MAX

SEATING PLANE
0.05
0.00 0.08 C
2X 3.5
3.45 0.1 (0.2) TYP
9 16 EXPOSED
THERMAL PAD
28X 0.5
8
17 SEE SIDE WALL
DETAIL

2X SYMM
33
3.5

0.3
32X
0.2
24 0.1 C A B
1
0.05 C

32 25
PIN 1 ID SYMM
(OPTIONAL) 0.5
32X
0.3
4223442/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 3.45)

SYMM
32 25
32X (0.6)

1 24

32X (0.25)

(1.475)
28X (0.5)

33 SYMM

(4.8)
( 0.2) TYP
VIA

8 17

(R0.05)
TYP

9 16
(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4223442/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)
(R0.05) TYP (0.845)
32 25
32X (0.6)

1 24

32X (0.25)

28X (0.5)
(0.845)
SYMM
33

(4.8)

8 17

METAL
TYP

9 16
SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

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