Data Storage

Semiconductor Memory Basics

• Memory is the portion of a computer or other system that stores binary
data
• Units of Binary Data: Bits, Bytes, Nibbles, and Words
• The Basic Memory Array:
• Each storage element in a memory can retain either a 1 or a 0 and is
called a cell
• Memories are made up of arrays of cells
 Semiconductor Memory Basics
• Location of a cell in a memory array can be identified by specifying a row
and a column

The 64-cell array

viewed as either a 64-bit memory or an

8-byte memory
Semiconductor Memory Basics

16 x 4 array A 64 x 1 array

A 16-nibble memory A 64-bit memory

 Semiconductor Memory Basics
• Memory Address and Capacity:
• The location of a unit of data in a memory array is called its address
the address of a bit in the 2- the address of a byte
dimensional array is specified is specified only by
by the row and column the row
 Semiconductor Memory Basics
• The address depends on how the memory is organized into units of data.
• The capacity of a memory is the total number of data units that can be
stored
Memory Banks and Ranks:
• A bank is a section of memory within a single memory array (chip)
• A rank is a group of chips that make up a memory module that stores data
in units such as words or bytes
Semiconductor Memory Basics
 Semiconductor Memory Basics
Basic Memory Operations
• Addressing is the process of accessing a specified location in memory
• The addressing operation, selects the specified memory address.
• The write operation puts data into a specified address in the memory
• The read operation copies data out of a specified address in the memory
• Data units go into the memory and come out of the memory on a set of
lines called the data bus
 Semiconductor Memory Basics
• Address is placed on a set of lines called the address bus
The Write Operation
Semiconductor Memory Basics
 Semiconductor Memory Basics

The Read Operation

 RAMs and ROMs
RAM
• random-access memory
• all addresses are accessible in an equal amount of time and can be selected in
any order for a read or write operation
• All RAMs have both read and write capability
• RAMs are volatile memories.
 RAMs and ROMs
ROM
• read-only memory
• data is stored permanently or semi-permanently
• Data can be read from a ROM, but there is no write operation
• The ROM, like the RAM, is a random-access memory
• Traditionally RAM means a random-access read/write memory
 The Random-Access Memory (RAM)
• The two major categories of RAM are:
• the static RAM (SRAM)
• the dynamic RAM (DRAM)
• SRAMs generally use latches as storage elements - store data indefinitely as
long as dc power is applied.
• DRAMs use capacitors as storage elements – requires refreshing
The RAM Family
 The Random-Access Memory (RAM)
• Both SRAMs and DRAMs will lose stored data when dc power is removed
• Data can be read much faster from SRAMs than from DRAMs
• DRAMs can store much more data than SRAMs for a given physical size and
cost
 Static RAMs (SRAMs)
Memory Cell Static Memory Cell Array

The memory cells in a SRAM are organized in

rows and columns
Static Memory Cell Array
 Basic Asynchronous SRAM Organization
• An asynchronous SRAM is one in which the operation is not synchronized
with a system clock.
Basic Asynchronous SRAM Organization
In the READ mode:
the eight data bits that are stored in a selected
address appear on the data output lines

In the WRITE mode:

the eight data bits that are applied to the
data input lines are stored at a selected
address

The data input and data output lines share the

same lines
 Tri-state Outputs and Buses
• Tri-state buffers in a memory allow the data lines to act as either input or
output lines
• These buffers have three output states:
• HIGH (1),
• LOW (0),
• and HIGH-Z (open).
 Tri-state Outputs and Buses
• A bus is one or more conductive paths that serve to interconnect two or more
functional components of a system or several diverse systems
• A microprocessor is connected to memories and input/output devices by
certain bus structures
• An address bus: - to address the memories
• A data bus: - transfer of data
• A control bus: - control data transfers and timing for the various
components
Read and Write Cycles
Read and Write Cycles
 Dynamic RAM (DRAM) Memory Cells
• Dynamic memory cells store a data bit in a small capacitor rather than in a
latch
• Advantage
• it is very simple
• Allows very large memory arrays to be constructed on a chip at a
lower cost per bit
 Dynamic RAM (DRAM) Memory Cells
• Disadvantage
• storage capacitor cannot hold its charge over an extended period of time
• Charge is refreshed periodically
• Refresh requires additional memory circuitry and complicates the
operation of the DRAM
 Dynamic RAM (DRAM) Memory Cells
• Typical DRAM cell consisting of a single MOS transistor (MOSFET) and a
capacitor
Dynamic RAM (DRAM) Memory Cells
(Write Operation)
 The transistor acts as a switch
 A LOW on the R/W line (WRITE mode) enables the
tri-state input buffer and disables the output buffer
 A 1 to be written into the cell, the DIN line must be
HIGH
 The transistor is turned on by a HIGH on the row
line
 The transistor then connects the capacitor to the bit
line.
 The capacitor to charge to a positive voltage
Dynamic RAM (DRAM) Memory Cells
(Write Operation)
 To store a 0
 A LOW is applied to the DIN line
 If the capacitor is storing a 0, it remains
uncharged, or if it is storing a 1, it discharges
 When the row line is taken back LOW, the
transistor turns off
 This disconnects the capacitor from the bit
line, thus “trapping” the charge (1 or 0) on
the capacitor
Dynamic RAM (DRAM) Memory Cells
(Read Operation)
 R/W (Read/Write) line is made HIGH,
enabling the output buffer and disabling
the input buffer
 The row line is made HIGH
 The transistor turns on and connects the
capacitor to the bit line and to the output
buffer
 The data bit appears on the data-output
line (DOUT).
Dynamic RAM (DRAM) Memory Cells
(Refreshing)
 For refreshing the memory cell, the R/W line is HIGH
 The row line is made HIGH
 The refresh line is made HIGH
 The transistor turns on, connecting the capacitor to
the bit line
 The output buffer is enabled
 The stored data bit is applied to the input of the
refresh buffer
 This produces a voltage on the bit line corresponding
to the stored bit, thus replenishing the capacitor
The Read-Only Memory (ROM)
 The Mask ROM
• It is permanently programmed during the manufacturing process
 Programmable ROMs
• The difference is that PROMs come from the manufacturer unprogrammed
and are custom programmed in the field to meet the user’s needs.
• Once they have been programmed they are the same as mask ROMs.
• A PROM uses a fusing process to store bits, in which a memory link is
burned open or left intact to represent a 0 or a 1
• The fusing process is irreversible
Programmable ROMs

 The fusible links are manufactured into the

PROM between the source of each cell’s
transistor and its column line
 Programming process:
 a sufficient current is injected through the
fusible link to burn it open to create a
stored 0
 The link is left intact for a stored 1.
 Programmable ROMs
• Three basic fuse technologies used in PROMs are:
• metal links,
• silicon links,
• and pn junctions
 EPROMs
• An EPROM is an erasable PROM
• An EPROM can be reprogrammed if an existing program in the memory
array is erased first
• An EPROM uses an NMOSFET array with an isolated-gate structure
• The isolated transistor gate has no electrical connections and can store an
electrical charge for indefinitely
• The data bits in this type of array are represented by the presence or absence
of a stored gate charge
 EPROMs
• Erasure of a data bit is a process that removes the gate charge.
• Types of erasable PROMs are:
• the electrically erasable PROM (EEPROM)
• ultraviolet erasable PROM (UV EPROM).
 EEPROMs
• An electrically erasable PROM
• Erased and programmed with electrical pulses
• The EEPROM can be rapidly programmed and erased in-circuit for
reprogramming.
• Two types of EEPROMs are the floating-gate MOS and the metal nitride-
oxide silicon (MNOS).
 The Flash Memory
• Flash memories are high-density read/write memories
• Flash Memory Cell: A single-transistor cell in a flash memory
 Flash Memory Cell
• The stacked gate MOS transistor consists of:
• a control gate
• a floating gate
• the drain and source
• The floating gate stores electrons
• A 0 is stored when there is more charge and a 1 is stored
when there is less or no charge
 Basic Flash Memory Operation
• There are three major operations in a flash memory:
• the programming operation,
• the read operation,
• and the erase operation
 Programming
• Initially, all cells are at the 1 state because charge was removed from each cell
during erase operation
• The programming operation adds electrons (charge) to the floating gate of
those cells that are to store a 0.
• No charge is added to those cells that are to store a 1.
 Programming
This attracts electrons to the
floating gate

Once programmed, a cell can

retain the charge indefinitely
without any external power.

A sufficient positive voltage to the control gate

with respect to the source
 Read Operation
• A positive voltage is applied to the control gate
• The amount of charge present on the floating gate of a cell determines
whether or not the voltage applied to the control gate will turn on the
transistor.
• If a 1 is stored, the control gate voltage is sufficient to turn the transistor on.
• If a 0 is stored, the transistor will not turn on because the control gate
voltage is not sufficient to overcome the negative charge stored in the
floating gate.
Read Operation
 Erase

 During an erase operation, charge is removed from

all the memory cells

 A sufficient positive voltage is applied to the

transistor source with respect to the control gate.

 This voltage attracts electrons from the floating gate

and depletes it of charge
 Memory Expansion
• Memory can be expanded to:
• increase the word length
• increase the word capacity
• Or Both
• Memory expansion is accomplished by adding an appropriate number of
memory chips
Word-Length Expansion
Word-Length Expansion
Word-Length Expansion
Word-Capacity Expansion
Word-Capacity Expansion
End