A B C D E

1 1

LCFC NM-E111
2 2

JK4A0 MB Schematics Document

Tiger Lake UP3 with DDR4

2021-04
3
REV:1.0 3

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Cover Page
Date: Friday, September 03, 2021 Sheet 1 of 110
A B C D E
 A B C D E

Intel MCP Memory Bus (Channel A) DDR4

SLOT-DIMM(P8,25)

HDMI (DDI 1)
Tiger Lake UP3 28W Memory Bus (Channel B) DDR4
1 1
HDMI Conn. SLOT-DIMM (P9,26)
(P7,50) BGA-1499
45.5mm*25mm USB3.0x1 AOU
eDP x2 USB3.0 Conn
eDP Conn USB2.0x1
(P14,57)
(P7,47)

SATA x1 USB2.0x1 Camera

SATA HDD (P14,47)
(P4,61) TCP
USB2.0x1

SMB Type-C PD CC Type-C Conn

PCI-Express RTS5457V-GR USB3.1 Gen1
NGFF SSD (P59) (P56)
4x Gen4
(P14,63) USB3.0x1 Type-C MUX Type-C Conn
USB2.0x1 RTS5467A (P53) USB3.1 Gen1
(P53)

2
PCIe x1 PCIe x1 Gen2 CONNECTOR (40 PIN) K14 IO BOARD 2

NGFF USB2.0x1
WLAN&BT USB2.0 x1 Fingerprint
(P78)
(P14,71)
USB2.0x2
USB2.0x1 USB2.0 PORT
C C (P78)
O O
SPK Conn. PCI-Express N N HALL Sensor(P78)
(P69) Realtek HD Audio N N
ALC3287
PWR BUTTON/PWR LED
HP&Mic Finger printer diaplay LED
(P66) (P78)
Combo Conn.(P69)

LAN
(P78)
dTPM
(P82)

I2C
Touch Pad SPI
3 (P12,83)
RPMC ROM (32MB) 3
W25R256JVEIN_WSON8
(P27)

SPI(Mirror Code)
ESPI

EC GPIO
IT8227VG-256CX_VFBGA128
(P79)

Int.KBD
(P81,79)

Option

KB Backlight CONN Thermal Sensor

(P81)
F75303M (P77)
4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Block Diagram_EE 1.0
Date: Friday, September 03, 2021 Sheet 2 of 110
A B C D E
 5 4 3 2 1

Richtek +5VALW/10A
SY8370C1TMC_
QFN13_3X4
Converter +5VLP/ 100mA
+5VALW_EN1 EN1
Adaptor 65W +5VALW_EN2 EN2 FOR SYSTEM PGOOD +5VALW_PGD
D D

Silergy +3VLP/ 100mA

SY8386BRHC_
QFN16_2P5X2P5
Converter +3VALW/ 6A
P_+3VALW_EN EN1
P_+3VALW_VIN_S EN2 FOR SYSTEM PGOOD +3VALW_PWRGD

TI
BQ25710RSNR Richtek
B+ LV5116AGQW_ +1.2V/8A
Battery Charger WQFN40_5X5
C C

Switch Mode S5
PMIC +0.6VS/1A
SYSON_VDDQ
S3
FOR SYSTEM
SUSP_N
POK_VDDQ
+5VALW
+0.75VALW/6A
EC_0.75VALW_EN EN
SMBus PGOOD 0.75VALW_PG
BATT+
+5VALW +1.8VALW/3A

EC_ON_1.8VALW EN PGOOD

Battery +3VALW
+2.5V/1A
polymer
EC_VPP_PWREN EN

3S1P/2S2P

B B

Richtek Richtek
RT3613EJGQW_ RT9610CGQW_
WQFN32_4X4 WDFN8_2X2 VCCIN/ TDC 36A / IccMAX 55A
IMVP controller Driver IC
APU_SVI2 VIDs FOR VCCIN
FOR CPU CORE P_VCCIN_EN1_10 EN1
EC_VR_ON EN PGOOD CPU_VR_READY
P_VCCIN_EN2_10 EN2
2Phase

Richtek
RT9610CGQW_
WDFN8_2X2 VCCIN_AUX/ TDC 14A / IccMAX 27A
Driver IC
FOR VCCIN
P_VCCIN_AUX_EN_10 EN1
A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Block Diagram_PWR
Date: Friday, September 03, 2021 Sheet 3 of 110
5 4 3 2 1
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON

Power Plane
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+3VALW +5VS

+5VALW +1.2V +3VS S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
+VCCIO
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
1
V20B+ +3VALW_PCH +2.5V_DDR +VCCSTG
1

+VCCIN
+1.8VALW +VCCST +VCCIN_AUX
+0.6VS

State

HSIO PORT Function

1 USB3.0
S0 O O O O 2 TypeC USB3.0
3 NC
USB3.0
4 NC
S3 O O O X 5 NC
6 NC
1 USB2.0
S3
Battery only O O O X 2
3
TypeC USB2.0
NC
4 USB3.0
2 S5 S4 USB2.0 2

AC Only O O X X 5
6
Camera
Finger Print
7 TypeC Port B
S5 S4
Battery only O X X X 8 NC
9 NC
10 Bluetooth
S5 S4
5~8
AC & Battery X X X X X4
NC
don't exist
9 WLAN
PCIE 10 LAN
SMBUS Control Table
11 SATA HDD

SOURCE BATT Charger PD IT8227VG Memory PCH PMIC SODIMM Thermal WLAN 12 NC
Down Sensor WiMAX 13~16 NC
X4

EC_SMB_CK0 IT8227VG
X X V V X X X X X X
EC_SMB_DA0 +3VL_EC 5V_IN +3VL_EC

EC_SMB_CK1 IT8227VG
3
V V X V X X X X X X 3

EC_SMB_DA1 +3VL_EC +3VL_EC

EC_SMB_CK3 IT8227VG
X X X V X X V X V X
EC_SMB_DA3 +3VL_EC +3VL_EC

PCH_SMB_CLK PCH
X X X X X V X V X X
PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS

EC SMBUS1 Address EC SMBUS2 Address EC SMBUS3 Address PCH SMBUS Address

Device Address Device Address Device Address Device Address
PD Need to update Smart Battery Need to update PMIC Need to update PCH Need to update
Charger Need to update Thermal Sensor(NCT7718W) DDR4 SODIMM Need to update

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR Map/SMBUS/HSIO
Date: Friday, September 03, 2021 Sheet 4 of 110
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

K14-TGL
Issued Date 2021/04/29 Deciphered Date 2021/08/19
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Notes_For VGA
Date: Friday, September 03, 2021 Sheet 5 of 110
5 4 3 2 1
 5 4 3 2 1

Virtual Symbol_Power BOM Structure

Virtual Symbol BOM Structure Description

BOM config

PCB
zzz1

D D
NM-E111
DA80001AP10
PCB@

Vpro CPU Config

UC1 UC1 UC1

TGL_I3 TGL_I5 TGL_I7

SA0000AY370 SA0000AY030 SA0000AY140
SRK07@ SRK03@ SRK1F@
IPU_I3_1115G4_VP IPU_I5_1145G7_VP IPU_I7_1185G7_VP

C C

Non VproCPU Config

UC1
UC1 UC1 UC1 UC1

TGL_I3
TGL_I5 TGL_I5 TGL_I7 TGL_I7
SA0000AY380 SA0000AY280 SA0000AY270 SA0000AWZ80 SA0000AWZ70
SRK08@ SRK05@ SRK04@ SRK02@ SRK01@
NIPU_I3_1115G4_NV NIPU_I5_1135G7_NV IPU_I5_1135G7_NV NIPU_I7_1165G7_NV IPU_I7_1165G7_NV

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Notes_For BOM
Date: Friday, September 03, 2021 Sheet 6 of 110
5 4 3 2 1
 5 4 3 2 1

UC1A

1 OF 21

AC2 AY2
DDIA_TXP_3 TCP0_TXRX_P1
AC1 AY1
D DDIA_TXN_3 TCP0_TXRX_N1 D
AD2 BB1
DDIA_TXP_2 TCP0_TXRX_P0
AD1 BB2
CPU_EDP_TX1_P DDIA_TXN_2 TCP0_TXRX_N0
eDP* Hot Plug Routing: 47 CPU_EDP_TX1_P AF1
DDIA_TXP_1 TCP0_TX_P1
AM5
Recommend 50Ω nominal trace CPU_EDP_TX1_N AF2 AM7
47 CPU_EDP_TX1_N CPU_EDP_TX0_P DDIA_TXN_1 TCP0_TX_N1
impedance 47 CPU_EDP_TX0_P AG2 AT7
CPU_EDP_TX0_N DDIA_TXP_0 TCP0_TX_P0
with reasonable noise isolation 47 CPU_EDP_TX0_N AG1 AT5
DDIA_TXN_0 TCP0_TX_N0
CPU_EDP_AUX_P TCP0_AUX_P
AP7 Type-C Full Function
AJ2 AP5
47 CPU_EDP_AUX_P CPU_EDP_AUX_N DDIA_AUX_P TCP0_AUX
47 CPU_EDP_AUX_N AJ1
DDIA_AUX TCP1_RX1_DP
AT2 TCP1_RX1_DP 56
TCP1_TXRX_P1 TCP1_RX1_DN
DN4 AT1 TCP1_RX1_DN 56
GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 TCP1_RX0_DP
DT6 AU1 TCP1_RX0_DP 56
GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 TCP1_RX0_DN
AU2 TCP1_RX0_DN 56
CPU_EDP_HPD TCP1_TXRX_N0 TCP1_TX1_DP
DR5 AD5 TCP1_TX1_DP 56
47 CPU_EDP_HPD GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1 TCP1_TX1_DN
AD7 TCP1_TX1_DN 56
CPU_HDMI_CLK_P TCP1_TX_N1 TCP1_TX0_DP
50 CPU_HDMI_CLK_P T12 AH7 TCP1_TX0_DP 56
CPU_HDMI_CLK_N DDIB_TXP_3 TCP1_TX_P0 TCP1_TX0_DN
50 CPU_HDMI_CLK_N T11 AH5 TCP1_TX0_DN 56
CPU_HDMI_TX0_P DDIB_TXN_3 TCP1_TX_N0 TCP1_AUX_DP
50 CPU_HDMI_TX0_P Y11 AF7 TCP1_AUX_DP 59
CPU_HDMI_TX0_N DDIB_TXP_2 TCP1_AUX_P TCP1_AUX_DN
50 CPU_HDMI_TX0_N Y9 AF5 TCP1_AUX_DN 59
CPU_HDMI_TX1_P DDIB_TXN_2 TCP1_AUX
50 CPU_HDMI_TX1_P T9
CPU_HDMI_TX1_N DDIB_TXP_1
50 CPU_HDMI_TX1_N P9 BF1
CPU_HDMI_TX2_P DDIB_TXN_1 TCP2_TXRX_P1
50 CPU_HDMI_TX2_P V11 BF2
CPU_HDMI_TX2_N DDIB_TXP_0 TCP2_TXRX_N1
50 CPU_HDMI_TX2_N V9 BE2
DDIB_TXN_0 TCP2_TXRX_P0
BE1
TCP2_TXRX_N0
AB9 BD7
DDIB_AUX_P TCP2_TX_P1
AD9 BD5
DDIB_AUX TCP2_TX_N1
AY5
CPU_HDMI_DDC_CLK TCP2_TX_P0
50 CPU_HDMI_DDC_CLK DM29 AY7
CPU_HDMI_DDC_DATA DK27 GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0
BB5
50 CPU_HDMI_DDC_DATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P
BB7
CPU_HDMI_HPD TCP2_AUX
50 CPU_HDMI_HPD DG43
GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD
BK1
TCP3_TXRX_P1
DG47 BK2
GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1
DJ47 BJ2
GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0
BJ1
TCP3_TXRX_N0
DU8 BM7
GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP3_TX_P1
DV8 BM5
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP3_TX_N1
C BH5 C
TCP3_TX_P0
DF6 BH7
GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0
DD6 BK5
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P
BK7
TCP3_AUX
DN23
GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# TCRCOMP_P RC2 1 2 1/20W_150_1%_0201
DM23 AN2
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P TCRCOMP_N
AN1
TC_RCOMP
DK23
GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO DSI_DE_TE_2 1
DN21 M8 TP3 @
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
DF43 AB1 EDP_COMP
DDIP1_HPD GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
59 DDIP1_HPD DF45
GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK DISP_UTILS
DF47 CE4 1 TP2 @

1
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1
USB2.0 port Power Switch OC USB_OC1_N DH52 RC4
58 USB_OC1_N USB_OC2_N GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
USB3.0 port Power Switch OC 57 USB_OC2_N DK45
GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
DISP_UTILS： 1/20W_150_1%_0201
Recommend 50 ohm nominal trace impedance with reasonable noise isolation.
PCH_ENVDD DM8 Requires level shifting on the platform.
47 PCH_ENVDD

2
PCH_ENBKL EDP_VDDEN
47,79 PCH_ENBKL DN8
PCH_EDP_PWM EDP_BKLTEN
47 PCH_EDP_PWM DG10
EDP_BKLTCTL

@ TGLLAKE-U_BGA1449

2021/07/28

VCC_3P3_1P8_USB_OC +3VALW_PCH
B B
Change RC13,RC15 to 0402, reserve size for 330nF capacitor For Glitch Free
+3VS +1.8VALW_PCH
Cap or pull-down resistor is required depending on panel
PCH_ENVDD RC13 1 2 100K_0402_5% power sequencing spec or power delivery
RPC11 RC8 1 @ 2 0_0201_5%
1 4 CPU_HDMI_DDC_CLK PCH_ENBKL RC15 1 2 100K_0402_5%
2 3 CPU_HDMI_DDC_DATA RC10 1 @ 2 0_0201_5% Option 1:Cap Implementation
PCH_EDP_PWM RC863 1 2 100K_0201_5% 330 nF for 3.3v Ramp Rate from 5-50ms
2.2K_0404_4P2R_5% 33 nF for 3.3V Ramp Rate Less than 5ms
RC7 2 1 10K_0201_5% USB_OC1_N
RC9 2 1 10K_0201_5% USB_OC2_N Option 2:Pull-down Resistor Implementation
100K for 3.3V Signaling Mode
75K for 1.8V Signaling Mode

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DDI/EDP
Date: Friday, September 03, 2021 Sheet 7 of 110
5 4 3 2 1
 5 4 3 2 1

UC1B
D 2 OF 21 D
+3VALW
DDR4 (NIL)/LP4 DDR4/LP4
DDRA_DQ7 CP53 BT42 DDRA_CLK1_P
25 DDRA_DQ7 DDR0_DQ0_7/DDR0_DQ0_7 DDR0_CLK_P1/DDR3_CLK_P DDRA_CLK1_P 25

1
DDRA_DQ6 CP52 BT41 DDRA_CLK1_N
25 DDRA_DQ6 DDRA_DQ5 DDR0_DQ0_6/DDR0_DQ0_6 DDR0_CLK_N1/DDR3_CLK DDRA_CLK1_N 25
25 DDRA_DQ5 CP50 BP52
DDRA_DQ4 DDR0_DQ0_5/DDR0_DQ0_5 NC/DDR2_CLK_P RC21
25 DDRA_DQ4 CP49 BP53
DDRA_DQ3 DDR0_DQ0_4/DDR0_DQ0_4 NC/DDR2_CLK 100K_0402_5%
25 DDRA_DQ3 CU53 CD42
DDRA_DQ2 DDR0_DQ0_3/DDR0_DQ0_3 NC/DDR1_CLK_P
CU52 CD41

2
25 DDRA_DQ2 DDRA_DQ1 DDR0_DQ0_2/DDR0_DQ0_2 NC/DDR1_CLK DDRA_CLK0_P
25 DDRA_DQ1 CU50 CC52 DDRA_CLK0_P 25 CPU_DRAMPG_CNTL 93
DDRA_DQ0 DDR0_DQ0_1/DDR0_DQ0_1 DDR0_CLK_P0/DDR0_CLK_P DDRA_CLK0_N
25 DDRA_DQ0 CU49 CC53 DDRA_CLK0_N 25
DDRA_DQ15 DDR0_DQ0_0/DDR0_DQ0_0 DDR0_CLK_N0/DDR0_CLK +1.2V
25 DDRA_DQ15 CH53
DDRA_DQ14 DDR0_DQ1_7/DDR0_DQ1_7 DDR4/LP4
RC23
25 DDRA_DQ14 CH52 BT45
DDR0_DQ1_6/DDR0_DQ1_6 NC/DDR3_CKE0

1
DDRA_DQ13 CH50 BT47 1K_0402_5% C
25 DDRA_DQ13 DDRA_DQ12 DDR0_DQ1_5/DDR0_DQ1_5 NC/DDR3_CKE1 1 2 DDR_VTT_CNTL_BASE 2
CH49 BN51 QC1
25 DDRA_DQ12 DDRA_DQ11 DDR0_DQ1_4/DDR0_DQ1_4 NC/DDR2_CKE0
CL53 BN53 B MMBT3904WH_SOT323-3
25 DDRA_DQ11 DDRA_DQ10 DDR0_DQ1_3/DDR0_DQ1_3 NC/DDR2_CKE1 E
25 DDRA_DQ10 CL52 CD45

3
DDRA_DQ9 DDR0_DQ1_2/DDR0_DQ1_2 NC/DDR1_CKE0
25 DDRA_DQ9 CL50 CD47
DDRA_DQ8 DDR0_DQ1_1/DDR0_DQ1_1 NC/DDR1_CKE1 DDR_VTT_CNTL
25 DDRA_DQ8 CL49 CA51
DDRA_DQ23 DDR0_DQ1_0/DDR0_DQ1_0 NC/DDR0_CKE0
25 DDRA_DQ23 CT47 CA53
DDR0_DQ2_7/DDR1_DQ0_7 NC/DDR0_CKE1

2
DDRA_DQ22 CV47 @
25 DDRA_DQ22 DDRA_DQ21 DDR0_DQ2_6/DDR1_DQ0_6 DDR4/LP4 DDRA_CKE1
CT45 BU52 RC24
25 DDRA_DQ21 DDRA_DQ20 DDR0_DQ2_5/DDR1_DQ0_5 DDR0_CKE1/DDR2_CA4 DDRA_CKE0 DDRA_CKE1 25
CV45 BL50 10K_0402_5%
25 DDRA_DQ20 DDRA_DQ19 DDR0_DQ2_4/DDR1_DQ0_4 DDR0_CKE0/DDR2_CA5 DDRA_CKE0 25
25 DDRA_DQ19 CT42
DDRA_DQ18 DDR0_DQ2_3/DDR1_DQ0_3 DDR4/LP4 DDRA_CS1_N
25 DDRA_DQ18 CV42 CF42 DDRA_CS1_N 25

1
DDRA_DQ17 DDR0_DQ2_2/DDR1_DQ0_2 DDR0_CS1/DDR1_CA1 DDRA_CS0_N
25 DDRA_DQ17 CT41 CF47 DDRA_CS0_N 25
DDRA_DQ16 DDR0_DQ2_1/DDR1_DQ0_1 DDR0_CS0/NC
25 DDRA_DQ16 CV41
DDRA_DQ31 DDR0_DQ2_0/DDR1_DQ0_0 DDR4/LP4
25 DDRA_DQ31 CK47 CE53
DDRA_DQ30 DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_CA0
25 DDRA_DQ30 CM47 CE50
DDRA_DQ29 DDR0_DQ3_6/DDR1_DQ1_6 NC/DDR0_CA1
25 DDRA_DQ29 CK45 BL53
DDRA_DQ28 DDR0_DQ3_5/DDR1_DQ1_5 NC/DDR2_CS0
25 DDRA_DQ28 CM45 BP47
DDRA_DQ27 DDR0_DQ3_4/DDR1_DQ1_4 NC/DDR3_CA5
25 DDRA_DQ27 CK42 BP42
DDRA_DQ26 DDR0_DQ3_3/DDR1_DQ1_3 NC/DDR3_CA4
25 DDRA_DQ26 CM42 BP45
DDRA_DQ25 DDR0_DQ3_2/DDR1_DQ1_2 NC/DDR3_CA3
25 DDRA_DQ25 DDRA_DQ24
CM41
DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR3_CA2
BP44 2021/07/28
25 DDRA_DQ24 CK41
DDRA_DQ39 DDR0_DQ3_0/DDR1_DQ1_0 DDR4 (NIL)/LP4
DDRA_DQS7_P
25 DDRA_DQ39 BF53 BB44 DDRA_DQS7_P 25
DDRA_DQ38 DDR0_DQ4_7/DDR2_DQ0_7 DDR0_DQSP_7/DDR3_DQSP_1 DDRA_DQS7_N +1.2V
25 DDRA_DQ38 BF52 BD44 DDRA_DQS7_N 25
DDRA_DQ37 DDR0_DQ4_6/DDR2_DQ0_6 DDR0_DQSN_7/DDR3_DQSN_1 DDRA_DQS6_P
25 DDRA_DQ37 BF50 BK44 DDRA_DQS6_P 25
DDRA_DQ36 DDR0_DQ4_5/DDR2_DQ0_5 DDR0_DQSP_6/DDR3_DQSP_0 DDRA_DQS6_N
C
25 DDRA_DQ36 BF49 BH44 DDRA_DQS6_N 25
C

1
DDRA_DQ35 DDR0_DQ4_4/DDR2_DQ0_4 DDR0_DQSN_6/DDR3_DQSN_0 DDRA_DQS5_P
25 DDRA_DQ35 BH53 BA51 DDRA_DQS5_P 25
DDRA_DQ34 DDR0_DQ4_3/DDR2_DQ0_3 DDR0_DQSP_5/DDR2_DQSP_1 DDRA_DQS5_N RC20
25 DDRA_DQ34 BH52 BA50 DDRA_DQS5_N 25
DDRA_DQ33 DDR0_DQ4_2/DDR2_DQ0_2 DDR0_DQSN_5/DDR2_DQSN_1 DDRA_DQS4_P 1/16W_470_1%_0402
25 DDRA_DQ33 BH50 BG51 DDRA_DQS4_P 25
DDRA_DQ32 DDR0_DQ4_1/DDR2_DQ0_1 DDR0_DQSP_4/DDR2_DQSP_0 DDRA_DQS4_N
25 DDRA_DQ32 BH49 BG50 DDRA_DQS4_N 25
DDRA_DQ47 DDR0_DQ4_0/DDR2_DQ0_0 DDR0_DQSN_4/DDR2_DQSN_0 DDRA_DQS3_P
AY53 CK44

2
25 DDRA_DQ47 DDRA_DQ46 DDR0_DQ5_7/DDR2_DQ1_7 DDR0_DQSP_3/DDR1_DQSP_1 DDRA_DQS3_N DDRA_DQS3_P 25
25 DDRA_DQ46 AY52 CM44 DDRA_DQS3_N 25
DDRA_DQ45 DDR0_DQ5_6/DDR2_DQ1_6 DDR0_DQSN_3/DDR1_DQSN_1 DDRA_DQS2_P CPU_DRAMRST_N RC22 1 @ 2 0_0201_5%
25 DDRA_DQ45 AY50 CT44 DDRA_DQS2_P 25 CPU_DRAMRST_N_R 25,26
DDRA_DQ44 DDR0_DQ5_5/DDR2_DQ1_5 DDR0_DQSP_2/DDR1_DQSP_0 DDRA_DQS2_N
25 DDRA_DQ44 AY49 CV44 DDRA_DQS2_N 25
DDRA_DQ43 DDR0_DQ5_4/DDR2_DQ1_4 DDR0_DQSN_2/DDR1_DQSN_0 DDRA_DQS1_P
25 DDRA_DQ43 BC53 CK51 DDRA_DQS1_P 25 1
DDRA_DQ42 DDR0_DQ5_3/DDR2_DQ1_3 DDR0_DQSP_1/DDR0_DQSP_1 DDRA_DQS1_N @
25 DDRA_DQ42 BC52 CK50 DDRA_DQS1_N 25
DDRA_DQ41 DDR0_DQ5_2/DDR2_DQ1_2 DDR0_DQSN_1/DDR0_DQSN_1 DDRA_DQS0_P CC11
25 DDRA_DQ41 BC50 CR51 DDRA_DQS0_P 25
DDRA_DQ40 DDR0_DQ5_1/DDR2_DQ1_1 DDR0_DQSP_0/DDR0_DQSP_0 DDRA_DQS0_N 0.1U_6.3V_K_X5R_0201
25 DDRA_DQ40 BC49 CR50 DDRA_DQS0_N 25
DDRA_DQ55 DDR0_DQ5_0/DDR2_DQ1_0 DDR0_DQSN_0/DDR0_DQSN_0 2
25 DDRA_DQ55 BK47 DDR4/LP4
DDRA_DQ54 DDR0_DQ6_7/DDR3_DQ0_7 DDRA_ODT1
25 DDRA_DQ54 BK45 CF44 DDRA_ODT1 25
DDRA_DQ53 DDR0_DQ6_6/DDR3_DQ0_6 DDR0_ODT1/DDR1_CA0 DDRA_ODT0
25 DDRA_DQ53 BH47 CF45 DDRA_ODT0 25
DDRA_DQ52 DDR0_DQ6_5/DDR3_DQ0_5 DDR0_ODT0/DDR1_CS0
25 DDRA_DQ52 BH45 DDR4/LP4
DDRA_DQ51 DDR0_DQ6_4/DDR3_DQ0_4 DDRA_MA16_RAS_N
25 DDRA_DQ51 BH42 CB47 DDRA_MA16_RAS_N 25
DDRA_DQ50 DDR0_DQ6_3/DDR3_DQ0_3 DDR0_MA16/DDR1_CA4 DDRA_MA15_CAS_N
25 DDRA_DQ50 BK42 CB44 DDRA_MA15_CAS_N 25
DDRA_DQ49 DDR0_DQ6_2/DDR3_DQ0_2 DDR0_MA15/DDR1_CA3 DDRA_MA14_WE_N
25 DDRA_DQ49 BK41 CB45 DDRA_MA14_WE_N 25
DDRA_DQ48 DDR0_DQ6_1/DDR3_DQ0_1 DDR0_MA14/DDR1_CA2 DDRA_MA13
25 DDRA_DQ48 BH41 CF41 DDRA_MA13 25
DDRA_DQ63 DDR0_DQ6_0/DDR3_DQ0_0 DDR0_MA13/DDR1_CS1 DDRA_MA12
25 DDRA_DQ63 BD47 BU53 DDRA_MA12 25
DDRA_DQ62 DDR0_DQ7_7/DDR3_DQ1_7 DDR0_MA12/DDR2_CA1 DDRA_MA11
25 DDRA_DQ62 BB47 BT51 DDRA_MA11 25
DDRA_DQ61 DDR0_DQ7_6/DDR3_DQ1_6 DDR0_MA11/NC DDRA_MA10
25 DDRA_DQ61 BD45 BV42 DDRA_MA10 25
DDRA_DQ60 DDR0_DQ7_5/DDR3_DQ1_5 DDR0_MA10/DDR3_CA1 DDRA_MA9
25 DDRA_DQ60 BB45 BU50 DDRA_MA9 25
DDRA_DQ59 DDR0_DQ7_4/DDR3_DQ1_4 DDR0_MA9/DDR2_CA0 DDRA_MA8
25 DDRA_DQ59 BB42 BY53 DDRA_MA8 25
DDRA_DQ58 DDR0_DQ7_3/DDR3_DQ1_3 DDR0_MA8/DDR0_CA2 DDRA_MA7
25 DDRA_DQ58 BB41 CA50 DDRA_MA7 25
DDRA_DQ57 DDR0_DQ7_2/DDR3_DQ1_2 DDR0_MA7/DDR0_CA4 DDRA_MA6
25 DDRA_DQ57 BD42 BY52 DDRA_MA6 25
DDRA_DQ56 DDR0_DQ7_1/DDR3_DQ1_1 DDR0_MA6/DDR0_CA3 DDRA_MA5
25 DDRA_DQ56 BD41 BY50 DDRA_MA5 25
DDR0_DQ7_0/DDR3_DQ1_0 DDR0_MA5/DDR0_CA5 DDRA_MA4
CD51 DDRA_MA4 25
DDR0_MA4/DDR0_CS0 DDRA_MA3
CD53 DDRA_MA3 25
DDR0_MA3/DDR0_CS1 DDRA_MA2
BV47 DDRA_MA2 25
DDR0_MA2/DDR3_CS0 DDRA_MA1
CE52 DDRA_MA1 25
DDR0_MA1/NC DDRA_MA0
BV41 DDRA_MA0 25
DDR0_MA0/NC
DDR4/LP4
BN50 DDRA_BG1
DDR0_BG1/DDR2_CA2 DDRA_BG0 DDRA_BG1 25
BL52 DDRA_BG0 25
DDR0_BG0/DDR2_CA3
B DDR4/LP4 B
CB42 DDRA_BA1
DDR0_BA1/DDR1_CA5 DDRA_BA0 DDRA_BA1 25
BV44 DDRA_BA0 25
DDR0_BA0/DDR3_CA0
DDR4/LP4
BT53 DDRA_ACT_N
DDR0_ACT#/DDR2_CS1 DDRA_ACT_N 25
DDR4/LP4 DDRA_PAR
BV45 DDRA_PAR 25
DDR0_PAR/DDR3_CS1
DDR4 DDRA_ALERT_N
AU50 DDRA_ALERT_N 25
DDR0_ALERT# DDR_SA_VREFCA
AU49 DDR_SA_VREFCA 25
DDR0_VREF_CA
E52 DDR_VTT_CNTL
DDR_VTT_CTL CPU_DRAMRST_N
DV47
DRAM_RESET# DDR_RCOMP0
C49
DDR_RCOMP
2

@ TGLLAKE-U_BGA1449
RC19
1/20W_100_1%_0201
1

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DDR4-Chanel-A
Date: Friday, September 03, 2021 Sheet 8 of 110
5 4 3 2 1
 5 4 3 2 1

UC1C
3 OF 21

DDR4 (NIL)/LP4 DDR4/LP4

D DDRB_DQ0_7 DDRB_CLK1_DP D
26 DDRB_DQ0_[7:0] AL53 R41 DDRB_CLK1_DP 26
DDRB_DQ0_6 DDR1_DQ0_7/DDR4_DQ0_7 DDR1_CLK_P1/DDR7_CLK_P DDRB_CLK1_DN
AL52 R42 DDRB_CLK1_DN 26
DDRB_DQ0_5 DDR1_DQ0_6/DDR4_DQ0_6 DDR1_CLK_N1/DDR7_CLK
AL50 M52
DDRB_DQ0_4 DDR1_DQ0_5/DDR4_DQ0_5 NC/DDR6_CLK_P
AL49 M53
DDRB_DQ0_3 DDR1_DQ0_4/DDR4_DQ0_4 NC/DDR6_CLK
AP53 AC42
DDRB_DQ0_2 DDR1_DQ0_3/DDR4_DQ0_3 NC/DDR5_CLK_P
AP52 AC41
DDRB_DQ0_1 DDR1_DQ0_2/DDR4_DQ0_2 NC/DDR5_CLK DDRB_CLK0_DP
AP50 Y52 DDRB_CLK0_DP 26
DDRB_DQ0_0 DDR1_DQ0_1/DDR4_DQ0_1 DDR1_CLK_P0/DDR4_CLK_P DDRB_CLK0_DN
AP49 Y53 DDRB_CLK0_DN 26
DDRB_DQ1_7 DDR1_DQ0_0/DDR4_DQ0_0 DDR1_CLK_N0/DDR4_CLK
26 DDRB_DQ1_[7:0] AF53
DDRB_DQ1_6 DDR1_DQ1_7/DDR4_DQ1_7 DDR4/LP4
AF52 R47
DDRB_DQ1_5 DDR1_DQ1_6/DDR4_DQ1_6 NC/DDR7_CKE0
AF50 R45
DDRB_DQ1_4 DDR1_DQ1_5/DDR4_DQ1_5 NC/DDR7_CKE1
AF49 K51
DDRB_DQ1_3 DDR1_DQ1_4/DDR4_DQ1_4 NC/DDR6_CKE0
AH53 K53
DDRB_DQ1_2 DDR1_DQ1_3/DDR4_DQ1_3 NC/DDR6_CKE1
AH52 AC47
DDRB_DQ1_1 DDR1_DQ1_2/DDR4_DQ1_2 NC/DDR5_CKE0
AH50 AC45
DDRB_DQ1_0 DDR1_DQ1_1/DDR4_DQ1_1 NC/DDR5_CKE1
AH49 W51
DDRB_DQ2_7 DDR1_DQ1_0/DDR4_DQ1_0 NC/DDR4_CKE0
26 DDRB_DQ2_[7:0] AR41 W53
DDRB_DQ2_6 DDR1_DQ2_7/DDR5_DQ0_7 NC/DDR4_CKE1
AV42 DDR4/LP4
DDRB_DQ2_5 DDR1_DQ2_6/DDR5_DQ0_6 DDRB_CKE1
AR42 P52 DDRB_CKE1 26
DDRB_DQ2_4 DDR1_DQ2_5/DDR5_DQ0_5 DDR1_CKE1/DDR6_CA4 DDRB_CKE0
AV41 J50 DDRB_CKE0 26
DDRB_DQ2_3 DDR1_DQ2_4/DDR5_DQ0_4 DDR1_CKE0/DDR6_CA5
AR45
DDRB_DQ2_2 DDR1_DQ2_3/DDR5_DQ0_3 DDR4/LP4 DDRB_CS1
AV45 AE42 DDRB_CS1 26
DDRB_DQ2_1 DDR1_DQ2_2/DDR5_DQ0_2 DDR1_CS1/DDR5_CA1 DDRB_CS0
AR47 AE47 DDRB_CS0 26
DDRB_DQ2_0 DDR1_DQ2_1/DDR5_DQ0_1 DDR1_CS0/NC
AV47
DDRB_DQ3_7 DDR1_DQ2_0/DDR5_DQ0_0 DDR4/LP4
26 DDRB_DQ3_[7:0] AJ41 N42
DDRB_DQ3_6 DDR1_DQ3_7/DDR5_DQ1_7 NC/DDR7_CA5
AJ42 N45
DDRB_DQ3_5 DDR1_DQ3_6/DDR5_DQ1_6 NC/DDR7_CA4
AL41 N44
DDRB_DQ3_4 DDR1_DQ3_5/DDR5_DQ1_5 NC/DDR7_CA3
AL42 N47
DDRB_DQ3_3 DDR1_DQ3_4/DDR5_DQ1_4 NC/DDR7_CA2
AJ45 J53
DDRB_DQ3_2 DDR1_DQ3_3/DDR5_DQ1_3 NC/DDR6_CS0
AJ47 AC50
DDRB_DQ3_1 DDR1_DQ3_2/DDR5_DQ1_2 NC/DDR4_CA1
AL45 AC53
DDRB_DQ3_0 DDR1_DQ3_1/DDR5_DQ1_1 NC/DDR4_CA0
AL47
DDRB_DQ4_7 DDR1_DQ3_0/DDR5_DQ1_0 DDR4 (NIL)/LP4 DDRB_DQS7_DP
26 DDRB_DQ4_[7:0] A43 K36 DDRB_DQS7_DP 26
DDRB_DQ4_6 DDR1_DQ4_7/DDR6_DQ0_7 DDR1_DQSP_7/DDR7_DQSP_1 DDRB_DQS7_DN
B43 K38 DDRB_DQS7_DN 26
DDRB_DQ4_5 DDR1_DQ4_6/DDR6_DQ0_6 DDR1_DQSN_7/DDR7_DQSN_1 DDRB_DQS6_DP
D43 G44 DDRB_DQS6_DP 26
DDRB_DQ4_4 DDR1_DQ4_5/DDR6_DQ0_5 DDR1_DQSP_6/DDR7_DQSP_0 DDRB_DQS6_DN
E44 J44 DDRB_DQS6_DN 26
DDRB_DQ4_3 DDR1_DQ4_4/DDR6_DQ0_4 DDR1_DQSN_6/DDR7_DQSN_0 DDRB_DQS5_DP
A46 D39 DDRB_DQS5_DP 26
DDRB_DQ4_2 DDR1_DQ4_3/DDR6_DQ0_3 DDR1_DQSP_5/DDR6_DQSP_1 DDRB_DQS5_DN
C B46 C39 DDRB_DQS5_DN 26
C
DDRB_DQ4_1 DDR1_DQ4_2/DDR6_DQ0_2 DDR1_DQSN_5/DDR6_DQSN_1 DDRB_DQS4_DP
D46 C45 DDRB_DQS4_DP 26
DDRB_DQ4_0 DDR1_DQ4_1/DDR6_DQ0_1 DDR1_DQSP_4/DDR6_DQSP_0 DDRB_DQS4_DN
E47 D45 DDRB_DQS4_DN 26
DDRB_DQ5_7 DDR1_DQ4_0/DDR6_DQ0_0 DDR1_DQSN_4/DDR6_DQSN_0 DDRB_DQS3_DP
26 DDRB_DQ5_[7:0] E38 AJ44 DDRB_DQS3_DP 26
DDRB_DQ5_6 DDR1_DQ5_7/DDR6_DQ1_7 DDR1_DQSP_3/DDR5_DQSP_1 DDRB_DQS3_DN
D38 AL44 DDRB_DQS3_DN 26
DDRB_DQ5_5 DDR1_DQ5_6/DDR6_DQ1_6 DDR1_DQSN_3/DDR5_DQSN_1 DDRB_DQS2_DP
B38 AV44 DDRB_DQS2_DP 26
DDRB_DQ5_4 DDR1_DQ5_5/DDR6_DQ1_5 DDR1_DQSP_2/DDR5_DQSP_0 DDRB_DQS2_DN
A38 AR44 DDRB_DQS2_DN 26
DDRB_DQ5_3 DDR1_DQ5_4/DDR6_DQ1_4 DDR1_DQSN_2/DDR5_DQSN_0 DDRB_DQS1_DP
E41 AG51 DDRB_DQS1_DP 26
DDRB_DQ5_2 DDR1_DQ5_3/DDR6_DQ1_3 DDR1_DQSP_1/DDR4_DQSP_1 DDRB_DQS1_DN
D40 AG50 DDRB_DQS1_DN 26
DDRB_DQ5_1 DDR1_DQ5_2/DDR6_DQ1_2 DDR1_DQSN_1/DDR4_DQSN_1 DDRB_DQS0_DP
B40 AN51 DDRB_DQS0_DP 26
DDRB_DQ5_0 DDR1_DQ5_1/DDR6_DQ1_1 DDR1_DQSP_0/DDR4_DQSP_0 DDRB_DQS0_DN
A40 AN50 DDRB_DQS0_DN 26
DDRB_DQ6_7 DDR1_DQ5_0/DDR6_DQ1_0 DDR1_DQSN_0/DDR4_DQSN_0
26 DDRB_DQ6_[7:0] G42
DDRB_DQ6_6 DDR1_DQ6_7/DDR7_DQ0_7 DDR4/LP4 DDRB_ODT1
G41 AE44 DDRB_ODT1 26
DDRB_DQ6_5 DDR1_DQ6_6/DDR7_DQ0_6 DDR1_ODT1/DDR5_CA0 DDRB_ODT0
J41 AE45 DDRB_ODT0 26
DDRB_DQ6_4 DDR1_DQ6_5/DDR7_DQ0_5 DDR1_ODT0/DDR5_CS0
J42
DDRB_DQ6_3 DDR1_DQ6_4/DDR7_DQ0_4 DDR4/LP4 DDRB_MA16
G45 AA47 DDRB_MA16 26
DDRB_DQ6_2 DDR1_DQ6_3/DDR7_DQ0_3 DDR1_MA16/DDR5_CA4 DDRB_MA15
J45 AA44 DDRB_MA15 26
DDRB_DQ6_1 DDR1_DQ6_2/DDR7_DQ0_2 DDR1_MA15/DDR5_CA3 DDRB_MA14
G47 AA45 DDRB_MA14 26
DDRB_DQ6_0 DDR1_DQ6_1/DDR7_DQ0_1 DDR1_MA14/DDR5_CA2 DDRB_MA13
J47 AE41 DDRB_MA13 26
DDRB_DQ7_7 DDR1_DQ6_0/DDR7_DQ0_0 DDR1_MA13/DDR5_CS1 DDRB_MA12
26 DDRB_DQ7_[7:0] G38 P53 DDRB_MA12 26
DDRB_DQ7_6 DDR1_DQ7_7/DDR7_DQ1_7 DDR1_MA12/DDR6_CA1 DDRB_MA11
G36 N51 DDRB_MA11 26
DDRB_DQ7_5 DDR1_DQ7_6/DDR7_DQ1_6 DDR1_MA11/NC DDRB_MA10
H36 U42 DDRB_MA10 26
DDRB_DQ7_4 DDR1_DQ7_5/DDR7_DQ1_5 DDR1_MA10/DDR7_CA1 DDRB_MA9
H38 P50 DDRB_MA9 26
DDRB_DQ7_3 DDR1_DQ7_4/DDR7_DQ1_4 DDR1_MA9/DDR6_CA0 DDRB_MA8
N36 U53 DDRB_MA8 26
DDRB_DQ7_2 DDR1_DQ7_3/DDR7_DQ1_3 DDR1_MA8/DDR4_CA2 DDRB_MA7
L36 W50 DDRB_MA7 26
DDRB_DQ7_1 DDR1_DQ7_2/DDR7_DQ1_2 DDR1_MA7/DDR4_CA4 DDRB_MA6
L38 U52 DDRB_MA6 26
DDRB_DQ7_0 DDR1_DQ7_1/DDR7_DQ1_1 DDR1_MA6/DDR4_CA3 DDRB_MA5
N38 U50 DDRB_MA5 26
DDR1_DQ7_0/DDR7_DQ1_0 DDR1_MA5/DDR4_CA5 DDRB_MA4
AA51 DDRB_MA4 26
DDR1_MA4/DDR4_CS0 DDRB_MA3
AA53 DDRB_MA3 26
DDR1_MA3/DDR4_CS1 DDRB_MA2
U47 DDRB_MA2 26
DDR1_MA2/DDR7_CS0 DDRB_MA1
AC52 DDRB_MA1 26
DDR1_MA1/NC DDRB_MA0
U41 DDRB_MA0 26
DDR1_MA0/NC
DDR4/LP4 DDRB_BG1
K50 DDRB_BG1 26
DDR1_BG1/DDR6_CA2 DDRB_BG0
J52 DDRB_BG0 26
DDR1_BG0/DDR6_CA3
DDR4/LP4 DDRB_BA1
AA42 DDRB_BA1 26
DDR1_BA1/DDR5_CA5 DDRB_BA0
U44 DDRB_BA0 26
B DDR1_BA0/DDR7_CA0 B

N53 DDRB_ACT_N
DDR1_ACT#/DDR6_CS1 DDRB_ACT_N 26
U45 DDRB_PARITY
DDR1_PAR/DDR7_CS1 DDRB_PARITY 26
AU53 DDRB_ALERT_N
DDR1_ALERT# DDRB_VREF_CA DDRB_ALERT_N 26
AU52 DDRB_VREF_CA 26
DDR1_VREF_CA

@ TGLLAKE-U_BGA1449

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DDR4-Chanel-B
Date: Friday, September 03, 2021 Sheet 9 of 110
5 4 3 2 1
 5 4 3 2 1

UC1D
4 OF 21
UC1U
21 OF 21
DV24
RSVD_2
DW47
PCH_CATERR_N CPU_JTAG_TRST_N RSVD_3
M7 K4 DW49
PCH_PECI CATERR# PROC_TRST# CPU_JTAG_TMS RSVD_4
79 PCH_PECI BK9 B9 A48
RC39 1 2 1/20W_499_1%_0201 H_PROCHOT_N_R PECI PROC_TMS CPU_JTAG_TDO RSVD_5
20,59,79,93 H_PROCHOT_N E2 D12
PCH_H_THRMTRIP_N M5 PROCHOT# PROC_TDO CPU_JTAG_TDI
A12
D THRMTRIP# PROC_TDI CPU_JTAG_TCK D
RC42 1 2 1/20W_49.9_1%_0201PROC_OPI_RCOMP CT39 PROC_TCK
B6 2021/07/28 @ TGLLAKE-U_BGA1449
RC43 1 2 1/20W_49.9_1%_0201PCH_OPI_RCOMP PROC_POPIRCOMP PCH_JTAG_JTAGX
CB9 D8
PCH_OPIRCOMP PCH_JTAGX PCH_JTAG_TMS
CW12 A9
TP_1 PCH_TMS PCH_JTAG_TDO CPU_JTAG_TCK RC48 1 @ 2 0_0201_5% PCH_JTAG_JTAGX
CM39 E12
TP_2 PCH_TDO PCH_JTAG_TDI
B12
DBG_PMODE PCH_TDI PCH_JTAG_TCK CPU_JTAG_TRST_N RC233 1 @ 2 0_0201_5% PCH_JTAG_TRST_N
DF4 A7
DBG_PMODE PCH_TCK PCH_JTAG_TRST_N
H4
PCH_TRST# CPU_JTAG_TMS RC234 1 @ 2 0_0201_5% PCH_JTAG_TMS
DB42
GPP_B4/CPU_GP3 PROC_PREQ_N 1 TP11 @
DB41 C11
GPP_B3/CPU_GP2 PROC_PREQ# PROC_PRDY_N 1 CPU_JTAG_TDO RC235 1 @ 2 0_0201_5% PCH_JTAG_TDO
DF8 D11 TP12 @
EC_PCH_SCI_N DU5 GPP_E7/CPU_GP1 PROC_PRDY#
79 EC_PCH_SCI_N GPP_E3/CPU_GP0 CPU_EAR CPU_JTAG_TDI RC236 1 @ 2 0_0201_5% PCH_JTAG_TDI
G1
GPP_H2 EAR_N/EAR_N_TEST_NCTF
DF31
GPP_H1 GPP_H2
DV32 DT15 GPP_F7
GPP_H0 GPP_H1 GPP_F7
DW32 DR15
GPP_H0 GPP_F9
DT14 GPP_F10 +VCCSTG_TERM
GPP_F10
DJ27
GPP_H19/TIME_SYNC0 RC38 1 2 51_0402_5% PCH_JTAG_TDO
RC40 1 @ 2 51_0402_5% CPU_JTAG_TDI
RC41 1 @ 2 51_0402_5% CPU_JTAG_TMS
@ TGLLAKE-U_BGA1449

+3VALW_PCH RC36 1 2 51_0402_5% CPU_JTAG_TCK

C C
GPP_H0: Boot Strap 1 RC35 1 @ 2 51_0402_5% CPU_JTAG_TRST_N
RC37 1 @ 2 51_0402_5% PCH_JTAG_TCK
GPP_H1: Boot Strap 2
@ @ @ GPP_H2: Boot Strap 3
1/20W_4.7K_5%_0201 1/20W_20K_5%_0201

1/20W_4.7K_5%_0201 1/20W_20K_5%_0201

1/20W_4.7K_5%_0201 1/20W_20K_5%_0201

RC27 RC28 RC29

Boot Strap, Rising edge of RSMRST#
1

These straps has a 20 kohm ± 30% internal

pull-down.
They are bit [3:1] of a total of 4-bit encoded pin straps
for boot configuration.
2

GPP_H0 Refer to Boot Strap 0 (on GPP_C5) for the encoding. GPP_F7 RC50 1 @ 2 1/20W_20K_5%_0201
GPP_H1 Notes: 1. The internal pull-down is disabled after
GPP_H2 RSMRST# de-asserts. GPP_F10 RC49 1 @ 2 1/20W_20K_5%_0201
@ @ @ 2. This signal is in the primary well.
RC31 RC32 RC33
1

GPP_F7 and GPP_F10:

Reserved, Rising edge of RSMRST#
0000 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is enabled This strap has a 20 kohm ± 30% internal pull-down.
0010 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is disabled This strap should sample LOW. There should NOT be any onboard
2

0100 = BIOS on eSPI Peripheral Channel; CSME on master attached SPI device driving it to opposite direction during strap sampling.
1000 = Slave Attached Flash Configuration (BIOS / CSME on eSPI attached device). Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts.
1100 = BIOS on eSPI peripheral Channel; CSME on slave attached SPI. 2. This signal is in the primary well.
B B

+VCCSTG_TERM

RC44 1 2 1K_0201_5% H_PROCHOT_N +VCCSTG_CPU

+VCCST_CPU
+VCCST_CPU

1
RC45 1 2 1K_0201_5% PCH_H_THRMTRIP_N
RC30
+3VS 1K_0201_5% EAR
1

Stall CPU reset sequence

2
RC46 CPU_EAR
1 2 10K_0201_5% EC_PCH_SCI_N until de-asserted:
RC47 1K_0201_5% - 1 = (Default) Normal

1
@
+VCC1.05_OUT_FET RC34 Operation; No stall.
- 0 = Stall;
2

1K_0201_5%
RC25 1 @ 2 1K_0201_5% DBG_PMODE PCH_CATERR_N Follow PDG Page118

2
RC26 1 @ 2 1K_0201_5% PDG Page116，CRB,Page35

A A
DBG_PMODE(Reserved): Rising edge of RSMRST#
This strap has a 20 kohm ± 30% internal pull-up.
This strap should sample high. There should NOT be Security Classification LCFC Highly Confidential Information Title
any on-board device driving it to opposite direction
during strap sampling. Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
Notes:
1. The internal pull-up is disabled after RSMRST# deasserts. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2. This signal is in the primary well. B 1.0
Confirmed with Intel Kaiyin, follow PDG 20200103
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MISC/JTAG
Date: Friday, September 03, 2021 Sheet 10 of 110
5 4 3 2 1
 5 4 3 2 1

UC1E
5 OF 21

PCH_SPI0_CLK R8429 1 2 1/20W_10_1%_0201 SPI0_CLK_C DJ37 DK21 PCH_SMB_CLK

27,82 PCH_SPI0_CLK PCH_SPI0_IO3 SPI0_IO3_C SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA
R8430 1 2 1/20W_10_1%_0201 DG35 DM19
27 PCH_SPI0_IO3 PCH_SPI0_IO2 SPI0_IO2_C SPI0_IO3 GPP_C1/SMBDATA PCH_SMB_ALERT_N
R8431 1 2 1/20W_10_1%_0201 DJ39 DN19
27 PCH_SPI0_IO2 PCH_SPI0_SO 1 2 SPI0_MISO_C SPI0_IO2 GPP_C2/SMBALERT#
R8432 1/20W_10_1%_0201 DJ33
27,82 PCH_SPI0_SO PCH_SPI0_SI SPI0_MOSI_C SPI0_MISO PCH_SML0_CLK
R8433 1 2 1/20W_10_1%_0201 DJ35 DK19
27,82 PCH_SPI0_SI 1 PCH_SPI0_CS1_N SPI0_MOSI GPP_C3/SML0CLK PCH_SML0_DATA
@ TP5907 DF35 DM17
PCH_SPI0_CS0_N SPI0_CS1# GPP_C4/SML0DATA PCH_SML0_ALERT_N
27 PCH_SPI0_CS0_N DG37 DN17
D -SPI_CS2 SPI0_CS0# GPP_C5/SML0ALERT# D
82 -SPI_CS2 DF39
SPI0_CS2# PCH_SML1_CLK
DK17 PCH_SML1_CLK 59
GPP_C6/SML1CLK PCH_SML1_DATA
DJ6
GPP_E11/THC0_SPI1_CLK GPP_C7/SML1DATA
DJ17
PCH_SML1_ALERT_N PCH_SML1_DATA 59 2021/07/28
DN5 CY50
ID1 GPP_E2/THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#
DR9
GPP_E1/THC0_SPI1_IO2 ESPI_CLK_R RC55 2 1 1/20W_49.9_1%_0201
DM6 DN53 LPC_ESPI_CLK 79
GPP_E12/THC0_SPI1_IO1 GPP_A5/ESPI_CLK ESPI_IO3_R RC56 1 2 1/20W_15_5%_0201
DK6 DJ53 LPC_ESPI_IO3 79
GPP_E13/THC0_SPI1_IO0 GPP_A3/ESPI_IO3/SUSACK# ESPI_IO2_R RC57 1 2 1/20W_15_5%_0201
DK8 DH50 LPC_ESPI_IO2 79
GPP_E10/THC0_SPI1_CS# GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK ESPI_IO1_R 1 2
Internal 20K PD @PCH DV11
GPP_E8/SATA_LED# GPP_A1/ESPI_IO1
DP50 RC59 1/20W_15_5%_0201
LPC_ESPI_IO1 79
VIH=0.7VCC @SPI ROM DW9 DP52 ESPI_IO0_R RC61 1 2 1/20W_15_5%_0201
GPP_E6 GPP_E17/THC0_SPI1_INT# GPP_A0/ESPI_IO0 ESPI_CS_N_R LPC_ESPI_IO0 79
DT8 DK52 RC63 1 2 0_0201_5%
GPP_E6/THC0_SPI1_RST# GPP_A4/ESPI_CS# LPC_ESPI_RST_N LPC_ESPI_CS_N 79
DL50 LPC_ESPI_RST_N 79
PLANARID0 GPP_A6/ESPI_RESET#
DN15
GPP_F11/THC1_SPI2_CLK
SPI0_MOSI(PCH_SPI_SI ): DK13
GPP_F15/GSXSRESET#/THC1_SPI2_IO3
Rising edge of RSMRST# PLANARID3 DM13
PLANARID2 GPP_F14/GSXDIN/THC1_SPI2_IO2
External pull-up is required. Recommend 4.7 kohm pull up. DN13
PLANARID1 GPP_F13/GSXSLOAD/THC1_SPI2_IO1
This strap should sample HIGH. There should NOT be any onboard DJ15
GPP_F12/GSXDOUT/THC1_SPI2_IO0
device driving it to opposite direction during strap sampling. DK15
GPP_F16/GSXCLK/THC1_SPI2_CS#
DN10
GPP_F18/THC1_SPI2_INT#
SPI0_IO2 and SPI0_IO3: DV14
GPP_F17/THC1_SPI2_RST#
Rising edge of RSMRST# 2021/07/28
External pull-up is required. DH3
CL_CLK
Recommend 100K if pulled up to 3.3V or 75K if pulled up to 1.8V. DH4
CL_DATA
This strap should sample HIGH. There should NOT be any onboard DF2
CL_RST# +3VALW_PCH +3VS +3VS
device driving it to opposite direction during strap sampling.

+3VALW_PCH @ TGLLAKE-U_BGA1449
@

4
3

4
3
@ QC4A
1/20W_4.7K_5%_0201 2 1 RC74 PCH_SPI0_CS0_N RPC2 2N7002KDWH_SOT363-6 RPC9

2
1/20W_4.7K_5%_0201 1 2 RC70 SPI0_MOSI_C 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
100K_0201_5% 2 1 RC71 SPI0_IO2_C
100K_0201_5% 2 1 RC72 SPI0_IO3_C

1
2

1
2
+3VALW_PCH PCH_SMB_CLK 6 1

S
SMB_CLK_S1 25,26

D
C RPC1 C
PCH_SML0_CLK 1 4 2.2K_0404_4P2R_5%
PCH_SML0_DATA 2 3
R8425 1 2 0_0402_5%

+3VALW_PCH PCH_SML0_ALERT_N RC67 2 @ 1 1/20W_4.7K_5%_0201

5
G
GPP_C5(PCH_SML0_ALERT#):
RC54 1 2 100K_0201_5% GPP_E6 Rising edge of RSMRST#
This signal has a 20K+/-30% internal pull-down.
RC53 1 @ 2 1/20W_4.7K_5%_0201 0 = Enable eSPI. (Default) PCH_SMB_DATA 3 4

S
SMB_DATA_S1 25,26

D
1 = Disable eSPI.
Notes: @ QC4B
2N7002KDWH_SOT363-6
1. The internal pull-down is disabled after RSMRST# de-asserts.
GPP_E6: 2. This signal is in the primary well
JTAG ODT Disable R8426 1 2 0_0402_5%
Rising edge of RSMRST#
This strap does not have an internal pull-up or pull-down.
External pull-up is recommended
0=> JTAG ODT is disabled +3VALW_PCH
1=> JTAG ODT is enabled

PCH_SMB_ALERT_N RC73 2 1 1/20W_4.7K_5%_0201

2021/07/28
GPP_C2(PCH_SMB_ALERT#):
This signal is used to wake the system or generate SMI#. TABLE
SPI0_CLK_C RC65 1 2 100K_0201_5% PLANARID3
External Pull-up resistor is required.Rising edge of RSMRST#
PLANARID2
1 2
This signal has a 20K+/-30% internal pull-down.
CC1 5P_50V_B_NPO_0402 PLANARID1
0 = Disable Intel ME Crypto Transport Layer Security (TLS) PLANARID0
LEVEL PLANARID[3:0]
cipher suite (no confidentiality). (Default)
Follow PDG P191 EMC_NS@
1 = Enable Intel ME Crypto Transport Layer Security (TLS)
cipher suite (with confidentiality). Must be
EVT 0000b
Glitch Free Requirements:
Cap or pull-down resistor is required pulled up to support Intel AMT with TLS.

2
Notes: FVT 0001b
100K for 3.3V Signaling Mode 1. The internal pull-down is disabled after RSMRST# de-asserts. @ @ @ @
B B
75K for 1.8V Signaling Mode 2. This signal is in the primary well. RC9115 RC9114 RC9113 RC9112
0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% SIT 0100b

1
SVT 1111b
+3VALW_PCH

+1.8VALW_PCH
PCH_SML1_CLK RC62 2 1 1/20W_4.7K_5%_0201
PCH_SML1_DATA RC75 2 1 1/20W_4.7K_5%_0201
RC51 1 @ 2 1K_0201_5% LPC_ESPI_CS_N

RC52 1 @ 2 1/20W_75K_5%_0201
+3VALW_PCH
+3VALW_PCH

PCH_SML1_ALERT_N RC76 2 @ 1 1/20W_150K_5%_0201

FP ID

1
RC77 2 @ 1 1/20W_20K_5%_0201
FP@
RC254 Status GPP_E1
Glitch Free Requirements P163 Site for cap or pull-down resistor only. 100K_0201_5%
GPP_B23 /SML1_ALERT# /PCHHOT#:

2
LPC_ESPI_RST_N RC64 1 2 1/20W_75K_5%_0201 CPUNSSC Clock Frequency
ID1
FP 1 (RC254)
Rising edge of RSMRST#
This strap has a 20 kohm ± 30% internal pull-down.
0 = 38.4 MHz clock (direct from crystal) (default) NFP 0 (RC262)
1 = 19.2 MHz clock (derived from 38.4 MHz crystal)
Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts.
2. When used as PCHHOT# and strap low, a 150K pull-up is needed

1
to ensure it does not override the internal pull-down strap sampling. NFP@
3. This signal is in the primary well. RC262
100K_0201_5%
A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. SPI/ESPI/SMB/CL
Date: Friday, September 03, 2021 Sheet 11 of 110
5 4 3 2 1
 5 4 3 2 1

RC9121 1 2 0_0201_5% UC1F

79 TOP_SWAP_EN
6 OF 21

PCH_TP_INT_N DC53 DR27

79,83 PCH_TP_INT_N GPP_B18 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD PCH_ECLPM_BREAK
DA51 DW27 PCH_ECLPM_BREAK 79
PCH_WLAN_PERST_N GPP_B18/GSPI0_MOSI GPP_D13/ISH_UART0_RXD
71 PCH_WLAN_PERST_N DC49 DV25
PCH_BEEP GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#
66 PCH_BEEP DC50 DT25
PCH_WLAN_OFF_N GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1# GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5
71 PCH_WLAN_OFF_N DC52
D GPP_B15/GSPI0_CS0# D
DB45
GPP_B6/ISH_I2C0_SCL
CY49 DB44
GPP_B20/GSPI1_CLK GPP_B5/ISH_I2C0_SDA
CY53
GPP_B22/GSPI1_MOSI
CY52
GPP_B21/GSPI1_MISO GPP_B8/ISH_I2C1_SCL
CY39 2021/07/28
DA50 DB47
GPP_B19/GSPI1_CS0# GPP_B7/ISH_I2C1_SDA
DV21 DD47
GPP_C9/UART0_TXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL
DT21 DD44
GPP_C8/UART0_RXD GPP_B9/I2C5_SDA/ISH_I2C2_SDA
DR21
2021/07/28 GPP_C11/UART0_CTS# FP_RESETN RC88 1 @ 2 0_0201_5%
DW21 DJ8 FP_RESETN_R 78
GPP_C10/UART0_RTS# GPP_E16/ISH_GP7 FPR_DELINK RC293 1 2 0_0201_5% 1
DR7
GPP_E15/ISH_GP6 PLANARID4 @ TP5908 @
DV19 DR24
RC856 1 @ 2 0_0201_5% PCH_CAPS_LED_N GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_D18/ISH_GP5
79,81 CAPS_LED_N DT19 DU25
RC66 1 2 0_0201_5% PCH_Fnlk_LED_N GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_D17/ISH_GP4
81 Fnlk_LED_N DR18 DV31
GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_D3/ISH_GP3/BK3/SBK3
@ DU19 DU31
GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_D2/ISH_GP2/BK2/SBK2
DT27
UART_TX GPP_D1/ISH_GP1/BK1/SBK1
67 UART_TX DJ21 DV27
UART_RX GPP_C21/UART2_TXD GPP_D0/ISH_GP0/BK0/SBK0
67 UART_RX DG23
PCH_PCIE_WAKE_N_WLAN GPP_C20/UART2_RXD GPP_RCOMP
71 PCH_PCIE_WAKE_N_WLAN DJ19 DR51
-TPM_IRQ GPP_C23/UART2_CTS# GPP_RCOMP
82 -TPM_IRQ DF21
GPP_C22/UART2_RTS#
TPM@ DN33

1
R1201 1 2 10K_0201_5% GPP_T3
+3VSUS DV18 DT35
GPP_C17/I2C0_SCL GPP_T2 RC97
DW18
GPP_C16/I2C0_SDA 1/20W_200_1%_0201
DG17
PCH_I2C1_SCL GPP_U5
TP 83 PCH_I2C1_SCL DJ23 DG19
PCH_I2C1_SDA GPP_C19/I2C1_SCL GPP_U4
83 PCH_I2C1_SDA DT18

2
GPP_C18/I2C1_SDA
DJ29
GPP_H5/I2C2_SCL
DJ31
GPP_H4/I2C2_SDA
DF29
GPP_H7/I2C3_SCL
DG29
GPP_H6/I2C3_SDA
DF25
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
DF27
GPP_H8/I2C4_SDA/CNV_MFUART2_RXD

C @ TGLLAKE-U_BGA1449 C

+3VALW_PCH

RC98 1 2 100K_0201_5% PCH_ECLPM_BREAK

RC99 1 @ 2 100K_0201_5% PCH_WLAN_PERST_N

+3VALW_PCH

RPC4
PCH_I2C1_SCL 1 4
PCH_I2C1_SDA 2 3

+3VS 2.2K_0404_4P2R_5%

PCH_TP_INT_N RC82 1 2 10K_0201_5%

RC101 1 @ 2 1/20W_4.7K_5%_0201 PCH_BEEP

TPM ID
GPP_B14(PCH_BEEP):
Rising edge of PCH_PWROK +3VS Status GPP_D18
The strap has a 20 kohm ± 30% internal pull-down.
0 = Disable Top Swap mode. (Default) FPR_DELINK 1 2 2.2K_0402_5%
RC83 @ TPM 0 (RC9120)
1 = Enable Top Swap mode. This inverts an address on access to SPI +3VS
and firmware hub, so the processor believes it fetches the alternate FP_RESETN RC864 1 @ 2 10K_0201_5%
boot block instead of the original boot-block. PCH will invert A16
(default) for cycles going to the upper two 64-KB blocks in the FWH NTPM 1 (RC9119)
or the appropriate address lines (A16, A17, or A18) as selected

2
in Top Swap Block size soft strap.
Notes: NTPM@
1. The internal pull-down is disabled after PCH_PWROK is high. RC9119
2. Software will not be able to clear the Top Swap bit until the system 10K_0201_5%
is rebooted.

1
B B
3. The status of this strap is readable using the Top Swap bit
(Bus0, Device31, Function0, offset DCh, bit4).
PLANARID4
4. This signal is in the primary well.

2
TPM@
RC9120
10K_0201_5%

1
+3VS
+3VS

RC102 1 @ 2 1/20W_4.7K_5%_0201 GPP_B18 PCH_CAPS_LED_N RC862 1 2 10K_0201_5%

PCH_Fnlk_LED_N RC811 1 2 10K_0201_5%
RC103 1 @ 2 1/20W_20K_5%_0201

+3V_WLAN

GPP_B18:Rising edge of PCH_PWROK

The signal has a weak internal pull-down. PCH_WLAN_OFF_N RC9123 1 @ 2 10K_0201_5%
0 = Disable No Reboot mode. (Default)
1 = Enable No Reboot mode (PCH will disable the
TCO Timer system reboot feature). This function is
useful when running ITP/XDP.
Notes:
1. The internal pull-down is disabled after
PCH_PWROK is high.
2. This signal is in the primary well.

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. I2C/ISH/UART/GPIO
Date: Friday, September 03, 2021 Sheet 12 of 110
5 4 3 2 1
 5 4 3 2 1

UC1G
7 OF 21

RC111 1 2 1/20W_33_5%_0201 PCH_HDA_BCLK DR38 DW15

D 66 HDA_BITCLK_AUDIO GPP_R0/HDA_BCLK/I2S0_SCLK GPP_F8/I2S_MCLK2_INOUT D
RC109 1 2 1/20W_33_5%_0201 PCH_HDA_SYNC DU37 DW24
66 HDA_SYNC_AUDIO 1 2 1/20W_33_5%_0201 PCH_HDA_SDO GPP_R1/HDA_SYNC/I2S0_SFRM GPP_D19/I2S_MCLK1
RC110 DT37
66 HDA_SDOUT_AUDIO HDA_SDIN0 GPP_R2/HDA_SDO/I2S0_TXD
66 HDA_SDIN0 DV37 DG41
GPP_R3/HDA_SDI0/I2S0_RXD GPP_A23/I2S1_SCLK
DT38
@ TP109 1 HDA_RST_N GPP_R7/I2S1_SFRM
DV41 DV38
GPP_R4/HDA_RST# GPP_R6/I2S1_TXD
DL53 DW38
GPP_A7/I2S2_SCLK/DMIC_CLK_A0 GPP_R5/HDA_SDI1/I2S1_RXD
DG51
GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0
DG50 DN31 PCH_DMIC_CLK0 47
GPP_A10/I2S2_RXD/DMIC_DATA1 GPP_S6/SNDW3_CLK/DMIC_CLK_A0
2021/07/28 GPP_S7/SNDW3_DATA/DMIC_DATA0
DM31 PCH_DMIC_DAT0 47
DL49
GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1
DL52 DK33
GPP_A11/PMC_I2C_SDA/I2S3_SCLK GPP_S4/SNDW2_CLK/DMIC_CLK_A1
DK31
RC861 1 @ 2 0_0201_5% PCH_A13_BT_OFF_N GPP_S5/SNDW2_DATA/DMIC_DATA1
71 PCH_BT_OFF_N DH49
GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0
DW35
RC117 1 2 1/20W_200_1%_0201 SNDW_RCOMP GPP_S2/SNDW1_CLK/DMIC_CLK_B0
DF33 DV35
SNDW_RCOMP GPP_S3/SNDW1_DATA/DMIC_CLK_B1
DT32
GPP_S0/SNDW0_CLK
DR35
GPP_S1/SNDW0_DATA

@ TGLLAKE-U_BGA1449

C C
+1.8VALW_PCH
1

RC107
1/20W_4.7K_5%_0201
2

PCH_HDA_SDO RC108 1 @ 2 0_0402_5%

ME_FLASH 79
GPP_R2(HDA_SDO_R):
This signal has a 20K ±30% internal pull-down.
0 = Enable security measures defined in the Flash Descriptor. (Default) PCH_HDA_BCLK PCH_HDA_SDO PCH_DMIC_CLK0
1 = Disable Flash Descriptor Security (override). This strap should only
be asserted high using external Pull-up in manufacturing/debug
environments ONLY.
Notes: 1 1 1
1. The internal pull-down is disabled after PCH_PWROK is high. CC2 CC15 CC13
2. This signal is in the primary well. 0.1U_6.3V_K_X5R_0201 2P_25V_C_NPO_0201 100P 25V J NPO 0201
EMC_NS@ EMC_NS@ EMC@
2 2 2

B B
RC104 2 @ 1 100K_0201_5% PCH_HDA_BCLK
RC105 2 @ 1 100K_0201_5% HDA_SDIN0

PCH_HDA_SYNC PCH_DMIC_DAT0 HDA_SDIN0

Glitch Free Requirements:
Pull-down resistor to ensure the stability of the signal
during platform bootup
1 1 1
CC3 CC14 CC8
Option 1:Cap Implementation 0.1U_6.3V_K_X5R_0201 33P_50V_J_NPO_0201 27P_0402_50V8J
NA for 3.3v Ramp Rate from 5-50ms EMC_NS@ EMC_NS@ EMC_NS@
NA for 3.3V Ramp Rate Less than 5ms 2 2 2

Option 2:Pull-down Resistor Implementation

NA for 3.3V Signaling Mode
75K for 1.8V Signaling Mode

+3VSUS

A A
PCH_BT_OFF_N RC9122 2 1 10K_0201_5%

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AUDIO
Date: Friday, September 03, 2021 Sheet 13 of 110
5 4 3 2 1
 5 4 3 2 1

UC1I
9 OF 21

BT7 CV4 USB20_10_P

BT8
PCIE12_TXP/SATA1_TXP
PCIE12_TXN/SATA1_TXN
USB2P_10
USB2N_10
CY3 USB20_10_N USB20_10_P
USB20_10_N
71
71
BT
CE2
PCIE12_RXP/SATA1_RXP
CE1 DD5
D
HDD PCIE12_RXN/SATA1_RXN USB2P_9
USB2N_9
DD4
D
SATA_PTX_DRX0_P BT9
61 SATA_PTX_DRX0_P SATA_PTX_DRX0_N PCIE11_TXP/SATA0_TXP
BV9 CW9
61 SATA_PTX_DRX0_N SATA_PRX_DTX0_P PCIE11_TXN/SATA0_TXN USB2P_8
CF4 DA9
61 SATA_PRX_DTX0_P SATA_PRX_DTX0_N PCIE11_RXP/SATA0_RXP USB2N_8
CF3
LAN 61 SATA_PRX_DTX0_N PCIE11_RXN/SATA0_RXN
DD1 USBC_USB2P
78 PCIE_PTX_C_DRX10_P
CC911 1 2 0.1u_0201_10V6K PCIE_PTX_DRX10_P BV7
PCIE10_TXP
USB2P_7
USB2N_7
DD2 USBC_USB2N USBC_USB2P
USBC_USB2N
56
56
TYPE-C FULL PORT
CC912 1 2 0.1u_0201_10V6K PCIE_PTX_DRX10_N BV8
78 PCIE_PTX_C_DRX10_N PCIE_PRX_DTX10_P PCIE10_TXN USB20_6_P
78 PCIE_PRX_DTX10_P PCIE_PRX_DTX10_N
CG2
CG1
PCIE10_RXP USB2P_6
DA1
DA2 USB20_6_N USB20_6_P 78 Finger Print
WLAN 78 PCIE_PRX_DTX10_N PCIE10_RXN USB2N_6 USB20_6_N 78
PCIE_PTX_DRX9_P BY7 DA12 USB20_5_P
71
71
PCIE_PTX_DRX9_P
PCIE_PTX_DRX9_N
PCIE_PTX_DRX9_N BY8
PCIE9_TXP
PCIE9_TXN
USB2P_5
USB2N_5
DA11 USB20_5_N USB20_5_P
USB20_5_N
47
47
Camera
PCIE_PRX_DTX9_P CG5
71 PCIE_PRX_DTX9_P PCIE_PRX_DTX9_N PCIE9_RXP USB20_4_P
CG4 DC8
71 PCIE_PRX_DTX9_N PCIE9_RXN USB2P_4
USB2N_4
DC7 USB20_4_N USB20_4_P
USB20_4_N
57
57
USB3.0 Normal
CB8 +1.8VALW_PCH
PCIE8_TXP
CB7 DB4
PCIE8_TXN USB2P_3
CK5 DB3
PCIE8_RXP USB2N_3
CK4
PCIE8_RXN USB20_2_P
DA5
USB2P_2 USB20_2_P 53 TYPE-C USB2.0

2
CD9 DA4 USB20_2_N
PCIE7_TXP USB2N_2 USB20_2_N 53
CD8
PCIE7_TXN USB20_1_P RC9110
CK1
CK2
PCIE7_RXP
PCIE7_RXN
USB2P_1
USB2N_1
DC11
DC9 USB20_1_N USB20_1_P
USB20_1_N
78
78
I/0 USB2.0 10K_0201_5%

1
CG8 DP4
PCIE6_TXP GPP_E0/SATAXPCIE0/SATAGP0
CG7 DF41 -SSD_DTCT 63
PCIE6_TXN GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM
CL4
PCIE6_RXP USB_OC0_N RC60 1 @ 2 0_0201_5%
CL3 DD8 TYPEC_OCP_N 53
PCIE6_RXN GPP_E9/USB_OC0# USB_OC3_N
DJ45
GPP_A16/USB_OC3#/I2S4_SFRM
CJ8

2
PCIE5_TXP PCH_SATA_DEVSLP1 @
CJ7 DN6 PCH_SATA_DEVSLP1 63
PCIE5_TXN GPP_E5/DEVSLP1 RC9111
CN2 DG8
PCIE5_RXP GPP_E4/DEVSLP0 10K_0201_5%
CN1
PCIE5_RXN
DN29
GPP_H15/M2_SKT2_CFG3
CR8 DK29

1
PCIE4_TXP/USB31_4_TXP GPP_H14/M2_SKT2_CFG2
CR7 DT31
PCIE4_TXN/USB31_4_TXN GPP_H13/M2_SKT2_CFG1
C
TYPE-C USB3.0 CN5
CN4
PCIE4_RXP/USB31_4_RXP
PCIE4_RXN/USB31_4_RXN
GPP_H12/M2_SKT2_CFG0
DR32 C

DV9 PCIE_RCOMPP RC118 1 2 1/20W_100_1%_0201

USB30_TX3_P PCIE_RCOMP_P PCIE_RCOMPN
53 USB30_TX3_P CU8 DT9
USB30_TX3_N PCIE3_TXP/USB31_3_TXP PCIE_RCOMP
53 USB30_TX3_N CU7
USB30_RX3_P PCIE3_TXN/USB31_3_TXN USB2_VBUSSENSE RC119 2 1 10K_0201_5%
53 USB30_RX3_P CT2 DC12
USB30_RX3_N PCIE3_RXP/USB31_3_RXP USB_VBUSSENSE USB2_ID RC120 2 1 10K_0201_5%
53 USB30_RX3_N CT1 DF1
PCIE3_RXN/USB31_3_RXN USB_ID USB2_COMP RC121 1 2 1/20W_113_1%_0201
DE1
USB30_TX2_P USB2_COMP
53 USB30_TX2_P CW8
USB30_TX2_N PCIE2_TXP/USB31_2_TXP
53 USB30_TX2_N CW7 E3
USB30_RX2_P PCIE2_TXN/USB31_2_TXN RSVD_BSCAN
53 USB30_RX2_P CU3
USB30_RX2_N PCIE2_RXP/USB31_2_RXP
53 USB30_RX2_N CT4
PCIE2_RXN/USB31_2_RXN
USB30_TX1_P
USB3.0 MB PORTB 57 USB30_TX1_P USB30_TX1_N
DA8
DA7
PCIE1_TXP/USB31_1_TXP
57 USB30_TX1_N USB30_RX1_P PCIE1_TXN/USB31_1_TXN
57 USB30_RX1_P CV2
USB30_RX1_N PCIE1_RXP/USB31_1_RXP
57 USB30_RX1_N CV1
PCIE1_RXN/USB31_1_RXN

@ TGLLAKE-U_BGA1449

UC1H
8 OF 21

+3VALW_PCH
B B
PCIE Gen4 for NVMe SSD 63 PCIE4_L3_TXP P5
P7
PCIE4_TX_P_3 PCIE4_TX_P_1
V5
V7
PCIE4_L1_TXP 63 USB_OC0_N RC122 1 @ 2 10K_0201_5%
63 PCIE4_L3_TXN PCIE4_TX_N_3 PCIE4_TX_N_1 PCIE4_L1_TXN 63
63 PCIE4_L3_RXP N1 T1 PCIE4_L1_RXP 63
PCIE4_RX_P_3 PCIE4_RX_P_1
63 PCIE4_L3_RXN N2 T2 PCIE4_L1_RXN 63
PCIE4_RX_N_3 PCIE4_RX_N_1
T5 Y5 VCC_3P3_1P8_USB_OC
63 PCIE4_L2_TXP PCIE4_TX_P_2 PCIE4_TX_P_0 PCIE4_L0_TXP 63
63 PCIE4_L2_TXN T7 Y7 PCIE4_L0_TXN 63
PCIE4_TX_N_2 PCIE4_TX_N_0
63 PCIE4_L2_RXP R1 V1 PCIE4_L0_RXP 63
PCIE4_RX_P_2 PCIE4_RX_P_0 USB_OC3_N RC125 1 @ 2 10K_0201_5%
63 PCIE4_L2_RXN R2 V2 PCIE4_L0_RXN 63
PCIE4_RX_N_2 PCIE4_RX_N_0
Y12 PCIE4_RCOMP_P
PCIE4_RCOMP_P
V12 PCIE4_RCOMP_N RC126 2 1
PCIE4_RCOMP V12 +3VALW_PCH
1/20W_2.2K_5%_0201
@ TGLLAKE-U_BGA1449 PCH_SATA_DEVSLP1
This RCOMP should be connected even if the CPU PCIe interface is not used RC127 1 @ 2 10K_0201_5%

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PCIE/USB/SATA
Date: Friday, September 03, 2021 Sheet 14 of 110
5 4 3 2 1
 5 4 3 2 1

UC1J
10 OF 21

D22 DK47
D CSI_F_DP_1 CNVI_WT_D1P +1.8VALW_PCH D
B22 DM47
CSI_F_DN_1 CNVI_WT_D1N
E22 DN49
CSI_F_DP_0 CNVI_WT_D0P
D20 DR49
CSI_F_DN_0 CNVI_WT_D0N
A20 DN45
CSI_F_CLK_P CNVI_WT_CLKP BRI_DT_R RC9108 1 @ 2 4.7K_0402_5%
B20 DN47
CSI_F_CLK CNVI_WT_CLKN RGI_DT_R RC9105 2 1 100K_0402_5%
B18 DU43
CSI_E_DP_1/CSI_F_DP_2 CNVI_WR_D1P
A18 DV43
CSI_E_DN_1/CSI_F_DN_2 CNVI_WR_D1N
D18 DR44
CSI_E_DP_0/CSI_F_DP_3 CNVI_WR_D0P
E18 DT43
CSI_E_DN_0/CSI_F_DN_3 CNVI_WR_D0N
C16 DV44
CSI_E_CLK_P CNVI_WR_CLKP
D16 DW44
CSI_E_CLK CNVI_WR_CLKN
D15 DN51 BRI_DT_R RC9106 2 1 100K_0402_5%
CSI_C_DP_2 CNVI_WT_RCOMP RGI_DT_R RC9107 2 @ 1 100K_0402_5%
E15
CSI_C_DN_2
A15 DJ13
CSI_C_DP_3 GPP_F3/CNV_RGI_RSP/UART0_CTS#
B15 DG13 RGI_DT_R
CSI_C_DN_3 GPP_F2/CNV_RGI_DT/UART0_TXD

2
DF15
GPP_F1/CNV_BRI_RSP/UART0_RXD
L18 DF17 BRI_DT_R RC9109
CSI_C_DP_1 GPP_F0/CNV_BRI_DT/UART0_RTS#
N18 1/20W_150_1%_0201
CSI_C_DN_1
L20 DJ10
CSI_C_DP_0 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ
N20 DV15

1
CSI_C_DN_0 GPP_F6/CNV_PA_BLANKING
G20
CSI_C_CLK_P GPP_F4/CNV_RF_RESET#
DK10 TABLE : Functional Strap
C H20 C
CSI_C_CLK
H16 GPP_F2/CNV_RGI_DT(M.2 CNVI Mode Select)
CSI_B_DP_1
G16
G18
CSI_B_DN_1 HIGH Integrated CNVI Disabled
CSI_B_DP_0
H18
L16
CSI_B_DN_0 LOW Integrated CNVI Enabled
CSI_B_CLK_P
N16
CSI_B_CLK
G14
CSI_B_DP_2 TABLE : Functional Strap
H14
CSI_B_DN_2
L14
N14
CSI_B_DP_3 GPP_F0/CNV_BRI_DT (XTAL Frequency Selection)
CSI_B_DN_3
RC139 1 2 CSI_COMP K14 HIGH 24MHz XTAL Selected
CSI_RCOMP
1/20W_150_1%_0201
DK25 LOW 38.4MHz XTAL Frequency Selected (Default) LOGIC
GPP_H23/IMGCLKOUT4
DM25
GPP_H22/IMGCLKOUT3
DN25
GPP_H21/IMGCLKOUT2
DJ25
GPP_H20/IMGCLKOUT1
DR30
GPP_D4/IMGCLKOUT_0/BK4/SBK4

@ TGLLAKE-U_BGA1449
B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CSI
Date: Friday, September 03, 2021 Sheet 15 of 110
5 4 3 2 1
 5 4 3 2 1

CLKOUT_PCIE_P /N [6,5,4, 2,1] = Support up to PCIe Gen3

CLKOUT_PCIE_P /N [3, 0] = Support up to PCIe Gen4
UC1K
11 OF 21
2021/08/30
BW1 DU14
CLKOUT_PCIE_P6 GPP_F19/SRCCLKREQ6#
BW2 DF23
CLKOUT_PCIE_N6 GPP_H11/SRCCLKREQ5#
DG25
D GPP_H10/SRCCLKREQ4# LAN_CLKREQ_N D
CB2 DT24 LAN_CLKREQ_N 78
CLKOUT_PCIE_P5 GPP_D8/SRCCLKREQ3# WLAN_CLKREQ_N XTAL_PCH_38P4M_IN RC144 1 @ 2 0_0402_5% XTAL_PCH_38P4M_IN_R
CB1 DT30 WLAN_CLKREQ_N 71
CLKOUT_PCIE_N5 GPP_D7/SRCCLKREQ2#
DV30
GPP_D6/SRCCLKREQ1# SSD_CLKREQ0_N
DW30 SSD_CLKREQ0_N 63
GPP_D5/SRCCLKREQ0#
BW4
CLKOUT_PCIE_P4 XTAL_PCH_38P4M_OUT
BW5 DM1
CLKOUT_PCIE_N4 XTAL_OUT XTAL_PCH_38P4M_IN XTAL_PCH_38P4M_OUT RC146 1 @ 2 0_0402_5% XTAL_PCH_38P4M_OUT_R
DL1
CLK_PCIE_LAN_P XTAL_IN
78 CLK_PCIE_LAN_P CL7
CLK_PCIE_LAN_N CLKOUT_PCIE_P3 SUSCLK
78 CLK_PCIE_LAN_N CL8 DW41 SUSCLK 71
CLKOUT_PCIE_N3 GPD8/SUSCLK
CLK_PCIE_WLAN_P CB4 DT47 RTC_X2
71 CLK_PCIE_WLAN_P CLK_PCIE_WLAN_N CLKOUT_PCIE_P2 RTCX2 RTC_X1
71 CLK_PCIE_WLAN_N CB5 DR47
CLKOUT_PCIE_N2 RTCX1
BY4 DN37 RTC_RST_N
CLKOUT_PCIE_P1 RTCRST# SRTC_RST_N
BY3 DK37
CLKOUT_PCIE_N1 SRTCRST#
CLK_PCIE_SSD_P CN7
63 CLK_PCIE_SSD_P CLK_PCIE_SSD_N CLKOUT_PCIE_P0
63 CLK_PCIE_SSD_N CN8
CLKOUT_PCIE_N0
1/20W_60.4_1%_0201 2 1 RC143 XCLK_BIASREF DJ5
XCLK_BIASREF

@ TGLLAKE-U_BGA1449

C C

XTAL_PCH_38P4M_IN_R RC147 1 2 200K_0402_1% XTAL_PCH_38P4M_OUT_R

RTC_X1 YC2

RTC_X2 4 3
+3VALW_PCH NC1 OSC2
RC145 1 2 10M_0402_5% 1 2
OSC1 NC2
WLAN_CLKREQ_N RC140 1 @ 2 10K_0201_5% YC1 1 1
SSD_CLKREQ0_N RC141 1 @ 2 10K_0201_5% 1 2 CC22
38.4MHZ_10PF_7R38400001
10P_0402_50V8J CC23
32.768KHZ 9PF 202934-PG14 10P_0402_50V8J
2 2
1 1
+3VS CC19 CC20
9P_50V_B_NPO_0402 9P_50V_B_NPO_0402
2 2
LAN_CLKREQ_N RC865 1 2 10K_0201_5%

B B

SUSCLK RC142 1 @ 2 1K_0201_5%

VCCRTC
1
CC21
1U_6.3V_K_X5R_0201

RC148 1 2 1/20W_20K_1%_0201 2 RTC_RST_N RC149 1 @ 2 0_0201_5%

RTC_RST_N 1 2 0.01U_6.3V_K_X7R_0201 EC_RTC_RST_N 79
CC4
RC150 1 2 1/20W_20K_1%_0201 SRTC_RST_N
EMC_NS@ 1
CMOS RESET CC24
SAVE CMOS = PU (Default) 1U_6.3V_K_X5R_0201
CLEAR CMOS = PD 2

ME RESET
SAVE ME = PU (Default)
CLEAR ME = PD
A A

Security Classification LCFC Highly Confidential Information Title

K14-TGL
Issued Date 2021/04/29 Deciphered Date 2021/08/19
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CLOCK SIGNALS
Date: Friday, September 03, 2021 Sheet 16 of 110
5 4 3 2 1
 5 4 3 2 1

UC1L
12 OF 21

PCH_PM_SLP_SUS_N DV49 BM9 CPU_PROCPWRGD 1 TP16 @

79 PCH_PM_SLP_SUS_N SLP_SUS# PROCPWRGD PBTN_OUT_N
DK41 PBTN_OUT_N 79
1 PCH_PM_SLP_S5_N GPD3/PWRBTN# BATLOW_N
@ TP17 DM43 DN41 BATLOW_N 79
D PCH_PM_SLP_S4_N GPD10/SLP_S5# GPD0/BATLOW# AC_PRESENT D
79,84 PCH_PM_SLP_S4_N DJ41 DK43 AC_PRESENT 79
PCH_PM_SLP_S3_N GPD5/SLP_S4# GPD1/ACPRESENT
79 PCH_PM_SLP_S3_N DJ43
1 PCH_PM_SLP_A_N GPD4/SLP_S3# PCH_PMC_ALERT_N
@ TP18 DR41 CW40 PCH_PMC_ALERT_N 59
1 PCH_PM_SLP_WLAN_N GPD6/SLP_A# GPP_B11/PMCALERT# CPU_C10_GATE_N
@ TP108 DT44 DN27 CPU_C10_GATE_N 84
GPD9/SPL_WLAN# GPP_H18/CPU_C10_GATE# SX_EXIT_HOLDOFF_N
DG31 SX_EXIT_HOLDOFF_N 79
RC152 1 2 0_0201_5% PCH_PM_SLP_S0_N GPP_H3/SX_EXIT_HOLDOFF#
79,84 PM_SLP_S0_N DD42
PCH_PM_SLP_LAN_N GPP_B12/SLP_S0# PCIE_WAKE_N_R RC2819 1 @ 2 0_0201_5%
DN39 DK39 PCIE_WAKE_N 71,78,79
SLP_LAN# WAKE#
PCH_RSMRST_N DM35 DM41 PCH_LAN_WAKE_N
PCH_SYS_RESET_N RSMRST# GPD2/LAN_WAKE#
DD10 DT41
RC154 1 @ 2 0_0201_5% PCH_PLT_RST_N SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON
63,71,78,79,82 PLT_RST_N DD41
GPP_B13/PLTRST# BB_TBT_PERST_N
DN43
PCH_DPWROK GPD7
DK35
RC155 1 @ 2 0_0201_5% SYS_PWROK DSW_PWROK VCCSTPWRGOOD_TCSS RC156 1 @ 2 0_0201_5%
79 EC_SYS_PWROK DF10 CE5 VCCST_OVERRIDE 17,84
RC157 1 2 0_0201_5% PCH_PWROK SYS_PWROK VCCSTPWRGOOD_TCSS VCCST_PWRGD RC158 1 2 1/20W_60.4_1%_0201
79 EC_PCH_PWROK DN35 BP8 EC_VCCST_PWRGD 79
@ PCH_PWROK VCCST_PWRGD VCCST_OVERRIDE_R RC159 1 @ 2 0_0201_5%
BP9 VCCST_OVERRIDE 84
INTRUDER_N VCCST_OVERRIDE
DM37
SPI VCCIOSEL INTRUDER#
DT49 DR12
SPIVCCIOSEL GPP_F20/EXT_PWR_GATE#
DW12
GPP_F21/EXT_PWR_GATE2#

@ TGLLAKE-U_BGA1449

DSW_PWROK and RSMRST# are always separate power good signals +VCCST_CPU

EC_PCH_DPWROK_R RC161 1 @ 2 0_0201_5% PCH_DPWROK EC_VCCST_PWRGD RC164 1 2 1K_0201_5%

79 EC_PCH_DPWROK_R PCH_PM_SLP_S5_N RC188 1 @ 2 100K_0201_5%
RC160 1 2 10K_0201_5% PCH_PM_SLP_S3_N RC181 1 2 100K_0201_5%
PCH_PM_SLP_S4_N RC182 1 2 100K_0201_5%
PCH_PM_SLP_A_N RC185 1 @ 2 100K_0201_5%

EC_RSMRST_N_R RC162 1 @ 2 0_0201_5% PCH_RSMRST_N

C C
79 EC_RSMRST_N_R PCH_PM_SLP_WLAN_N 1 2
RC186 @ 100K_0201_5%
RC163 1 2 10K_0201_5% +3VS

PCH_PM_SLP_LAN_N RC187 1 @ 2 100K_0201_5%

PCH_SYS_RESET_N RC167 1 2 10K_0201_5% PCH_PM_SLP_SUS_N RC178 1 2 100K_0201_5%
PLT_RST_N RC189 1 2 100K_0201_5%
PCH_PWROK RC177 1 2 10K_0201_5%
SYS_PWROK RC179 1 2 10K_0201_5%
VCCST_OVERRIDE RC180 1 2 100K_0201_5%

Glitch Free Requirements:

Cap or pull-down resistor is required
+VCCPDSW_3P3
Option 1:Cap Implementation
330 nF for 3.3v Ramp Rate from 5-50ms
RC165 2 @ 1 1/20W_4.7K_5%_0201 SPI VCCIOSEL 33 nF for 3.3V Ramp Rate Less than 5ms
+3VALW_PCH
RC166 2 1 1/20W_4.7K_5%_0201 Option 2:Pull-down Resistor Implementation
100K for 3.3V Signaling Mode
PCH_PMC_ALERT_N RC169 1 2 1K_0201_5% 75K for 1.8V Signaling Mode
PCH_PM_SLP_S0_N RC168 1 2 100K_0201_5%
The VCCSPI voltage (3.3V or 1.8V) is selected via a strap on SPIVCCIOSEL； CPU_C10_GATE_N RC3 1 @ 2 100K_0201_5%
This strap sets the SPI interface signaling voltage at the rising edge of DSW_PWROK.
Designers should strap this pin to match the expected interface operational voltage for Glitch Free Requirements:
their target SPI device as follows. Pull-up resistor is required if a device is monitoring SLP_S0#
0 = SPI voltage is 3.3V (4.7K ohm pull-down to GND)； before RSMRST# de-assertion
1 = SPI voltage is 1.8V (4.7K ohm pull-up to VCCDSW_3P3) 100K for 3.3V Signaling Mode
75K for 1.8V Signaling Mode
CAD NOTE:
INPUT3VSEL: 3V SELECT STRAP
LOW-> 3.3V +/-5%
HIGH->3.0V +/-5%

B B

+VCCPDSW_3P3 FOR EMC

VCCRTC 0.1U_6.3V_K_X5R_0201 1 2 CC5 EMC_NS@ PCH_PLT_RST_N
0.1U_6.3V_K_X5R_0201 1 2 CC6 EMC_NS@ PCH_PWROK
PCIE_WAKE_N_R RC170 1 2 1K_0201_5% 0.1U_6.3V_K_X5R_0201 1 2 CC7 EMC_NS@ SYS_PWROK
RC172 1 2 1/20W_1M_5%_0201 INTRUDER_N PCH_LAN_WAKE_N RC171 1 2 10K_0201_5% 1000P 25V K X7R 0201 1 2 CC33 EMC_NS@ PCH_RSMRST_N
PBTN_OUT_N RC173 1 @ 2 100K_0201_5% 1000P 25V K X7R 0201 1 2 CC34 EMC_NS@ PCH_DPWROK
BATLOW_N RC175 1 2 100K_0201_5% 0.01U_25V_K_X5R_0201 1 2 CC55 EMC_NS@ VCCST_PWRGD
RC174 1 @ 2 1/20W_1M_5%_0201 AC_PRESENT RC176 1 2 100K_0201_5%

CC25 2 1 0.1U_6.3V_K_X5R_0201

INTRUDER#
RTC-Well Input Strap Requirements
should have a weak external pull-up to VccRTC

BB_TBT_PERST_N RC184 1 @ 2 1/20W_20K_5%_0201

GPD7(BB_TBT_PERST#): Rising edge of DSW_PWROK

This signal has a 20K+-30% internal pull-down.
This strap should sample LOW. There should NOT be
any on-board device driving it to opposite direction
during strap sampling
A
Notes: A
1. The internal pull-down is disabled after DSW_PWROK is high.
2. This signal is in the DSW well

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. SYSTEM PM
Date: Friday, September 03, 2021 Sheet 17 of 110
5 4 3 2 1
 5 4 3 2 1

UC1M
13 OF 21
+VCCIN +VCCIN

A24 G32 +VCCSTG_OUT_LGC +VCCSTG_TERM

VCCIN_1 VCCIN_66
A26 H24
VCCIN_2 VCCIN_67
A29 H26
VCCIN_3 VCCIN_68 RC193 1 @ 2 0_0402_5%
A30 H30
VCCIN_4 VCCIN_69
A33 H32
VCCIN_5 VCCIN_70 +1.2V +1.2V
A35 J1
VCCIN_6 VCCIN_71
AY39 J2
VCCIN_7 VCCIN_72
B24 K1
D VCCIN_8 VCCIN_73 D
B26 K2
VCCIN_9 VCCIN_74
B29 K24
VCCIN_10 VCCIN_75 +VCCSTG_OUT +VCCSTG_FUSE
B30 K26
VCCIN_11 VCCIN_76
B33 K30
VCCIN_12 VCCIN_77
B35 K32
VCCIN_13 VCCIN_78 RC197 1 @ 2 0_0402_5%
BA10 L24
VCCIN_14 VCCIN_79
BA40 L26
VCCIN_15 VCCIN_80 +VCCSTG_OUT +VCCFPGM
BB39 L30
VCCIN_16 VCCIN_81
BB9 L32
VCCIN_17 VCCIN_82
BC10 N24
VCCIN_18 VCCIN_83 RC198 1 @ 2 0_0402_5%
BC40 N26
VCCIN_19 VCCIN_84
BD39 N30
VCCIN_20 VCCIN_85
BD9 N32
VCCIN_21 VCCIN_86
BE10 P24
VCCIN_22 VCCIN_87
BE40 P26
VCCIN_23 VCCIN_88
BF9 P28
VCCIN_24 VCCIN_89
BG10 P30
VCCIN_25 VCCIN_90
BG40 P32
VCCIN_26 VCCIN_91
BH12 T21
VCCIN_27 VCCIN_92 +VCCST_CPU
BH39 T23
VCCIN_28 VCCIN_93
BH9 T25
VCCIN_29 VCCIN_94
BJ10 T27
VCCIN_30 VCCIN_95 RC190 2 1 100_0402_1% VR_SVID_DATA
BJ40 T31
VCCIN_31 VCCIN_96
BK39 U23
VCCIN_32 VCCIN_97 RC191 2 1 56_0402_5% VR_SVID_ALERT_N
BL10 U27
VCCIN_33 VCCIN_98
BL40 U29
VCCIN_34 VCCIN_99 RC192 2 @ 1 1/16W_45.3_1%_0402 VR_SVID_CLK
BM39 U31
VCCIN_35 VCCIN_100
BN40 U33
VCCIN_36 VCCIN_101
BP12
VCCIN_37 VCCIN_102
V23 CAD NOTE:
BP39
VCCIN_38 VCCIN_103
V25 Alert signal must be routed between Clk and Data signals
BR10 V27 +VCCIN to minimize Cross-Talk.
VCCIN_39 VCCIN_104
BR40 V29
VCCIN_40 VCCIN_105
BT12 V31
VCCIN_41 VCCIN_106
BT39 V33
VCCIN_42 VCCIN_107

1
BU10 W22
VCCIN_43 VCCIN_108 RC194
BU40 W24
VCCIN_44 VCCIN_109 100_0402_1%
BV12 W28
VCCIN_45 VCCIN_110
C BY12 W32 C
VCCIN_46 VCCIN_111
CA10

2
VCCIN_47
CB12 R38 VCCIN_SENSE VCCIN_SENSE 95
VCCIN_48 VCCIN_SENSE
D24 R37 VSSIN_SENSE VSSIN_SENSE 95
VCCIN_49 VSSIN_SENSE
D26
VCCIN_50
D29 M12 VR_SVID_DATA VR_SVID_DATA 95
VCCIN_51 VIDSOUT
D30 M11 VR_SVID_CLK VR_SVID_CLK 95
VCCIN_52 VIDSCK

1
D33 P12 VR_SVID_ALERT_N VR_SVID_ALERT_N 95
VCCIN_53 VIDALERT#
D35
VCCIN_54 RC196
E24
VCCIN_55 100_0402_1%
E26
VCCIN_56 UC1O
E27

2
VCCIN_57
E29
VCCIN_58 +1.2V 15 OF 21
E30
VCCIN_59
E32
VCCIN_60
E33 AA39 AF9 +VCCSTG_OUT
VCCIN_61 VDD2_1 VCCSTG_OUT_1
G2 AB40 AF12
VCCIN_62 VDD2_2 VCCSTG_1
G24 AC39 AD12 +VCCSTG_FUSE
VCCIN_63 VDD2_3 VCCSTG_2
G26 AD40
VCCIN_64 VDD2_4
G30 AD51 AN10 +VCCFPGM
VCCIN_65 VDD2_5 VCCSTG_OUT_2
AD52 AM9
VDD2_6 VCCSTG_OUT_3
AE39 AG10
VDD2_7 VCCSTG_OUT_4
@ TGLLAKE-U_BGA1449 AF40
VDD2_8
AG39 V15 +VCCIO_OUT
VDD2_9 VCCIO_OUT
AH40
VDD2_10
AJ39 M9 +VCCSTG_OUT_LGC
VDD2_11 VCCSTG_OUT_LGC
AK40
VDD2_12
AK51 BT2 +VCCST_CPU
VDD2_13 VCCST_1
AK52 BT1
VDD2_14 VCCST_2
AL39 BT4
VDD2_15 VCCST_3
AM40
VDD2_16
AN39 BP2 +VCCSTG_CPU
VDD2_17 VCCSTG_3
AP40 BP1
VDD2_18 VCCSTG_4
AR39 BP4
VDD2_19 VCCSTG_5
AT52
VDD2_20
+VCCIN PDG: VCCST PDG: VCCSTG AU40
VDD2_21
1u_0402 * 2 1u_0402 * 2 AW40
VDD2_22
AW51
B
+VCCST_CPU +VCCSTG_CPU VDD2_23 B
AW52
VDD2_24
BD51
VDD2_25
BD52
VDD2_26
100P_0402_50V8J

0.1U_6.3V_K_X5R_0201

EMC@ 1 EMC@ 1 EMC@ 1 BK51

VDD2_27
12P_50V_F_COG_0402

CC89 CC90 CC91 BK52

VDD2_28
BV51
VDD2_29
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1 @ 1 1 @ 1 BV52
2 2 2 CC35 CC36 CC37 CC38 VDD2_30
CA40
VDD2_31
CC40
VDD2_32
CC49
2 2 2 2 VDD2_33
CC50
VDD2_34
CE40
VDD2_35
CG40
VDD2_36
CH39
VDD2_37
CJ40
VDD2_38
CL40
VDD2_39
Place as close as possible to the CN40
VDD2_40
package (less than 5mm). CP47
VDD2_41
CR40
VDD2_42
D50
VDD2_43
E51
VDD2_44
F49
VDD2_45
T51
VDD2_46
T52
VDD2_47

@ TGLLAKE-U_BGA1449

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU Power(1/2)
Date: Friday, September 03, 2021 Sheet 18 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU Power(2/2)
Date: Friday, September 03, 2021 Sheet 19 of 110
5 4 3 2 1
 5 4 3 2 1

+VCCIN_AUX UC1N
+1.8VALW +1.8VALW_PCH
14 OF 21
+VCCPRIM_1P8

RC857 1 @ 2 0_5%_0603 AB12 CY18

VCCIN_AUX_1 VCCPRIM_1P8_1
AC10 CY20
VCCIN_AUX_2 VCCPRIM_1P8_2
AE10 CY24
VCCIN_AUX_3 VCCPRIM_1P8_3
AK2 CY26
VCCIN_AUX_4 VCCPRIM_1P8_4
AR10 DA18
VCCIN_AUX_5 VCCPRIM_1P8_5
AT12 DA20
D VCCIN_AUX_6 VCCPRIM_1P8_6 D
AU10 DA22
VCCIN_AUX_7 VCCPRIM_1P8_7
AW10 DA24
VCCIN_AUX_8 VCCPRIM_1P8_8
BV1 DA26
+VCCPDSW_3P3 VCCIN_AUX_9 VCCPRIM_1P8_9
BV39 DC18
+3VALW VCCIN_AUX_10 VCCPRIM_1P8_10
BW40 DC20
VCCIN_AUX_11 VCCPRIM_1P8_11
BY39 DC22
RC232 1 @ 2 0_0402_5% VCCIN_AUX_12 VCCPRIM_1P8_12
CC1 DC24
VCCIN_AUX_13 VCCPRIM_1P8_13
CD12 DC26
+3VALW_PCH VCCIN_AUX_14 VCCPRIM_1P8_14
CF10 DD20
VCCIN_AUX_15 VCCPRIM_1P8_15
CG12 DD22
RC199 1 @ 2 0_0402_5% VCCIN_AUX_16 VCCPRIM_1P8_16
CH10 DV22
1U_6.3V_M_X5R_0201 VCCIN_AUX_17 VCCPRIM_1P8_17
1 CJ1
CC39 VCCIN_AUX_18
CJ12 DA35 +VCCPRIM_3P3
VCCIN_AUX_19 VCCPRIM_3P3_1
CK10 DC28
VCCIN_AUX_20 VCCPRIM_3P3_2
PDG: VCCDSW_3P3 2
CL12
VCCIN_AUX_21 VCCPRIM_3P3_3
DC30
Placeholder 1* 0402 capacitor on primary side CM10
VCCIN_AUX_22 VCCPRIM_3P3_4
DD30
as close as possible to the vias. CP1
VCCIN_AUX_23
CP10 DV34 +VCCRTCEXT
VCCIN_AUX_24 DCPRTC
CR12
VCCIN_AUX_25
CT10 DV46 +VCCLDOSTD_OUT_0P85
VCCIN_AUX_26 VCCLDOSTD_0P85
CU12
VCCIN_AUX_27
CY1 DV16
VCCIN_AUX_28 VCCA_CLKLDO_1P8_1
AK1 DC15 +VCCA_CLKLDO_1P8
VCCIN_AUX_29 VCCA_CLKLDO_1P8_2
VCCIN_AUX_VSSSENSE AV9 DV28
VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE VCCDPHY_1P24 +VCCDPHY_1P24
AT9
VCCIN_AUX_VCCSENSE
DD38 +VCCDSW_1P05
VCCDSW_1P05
+VNN_BYPASS DD17
VCC_VNNEXT_1P05_1
DD18 BR3
VCC_VNNEXT_1P05_2 VCC1P05_OUT_FET_1
BR4
+3VALW_PCH +VCCPRIM_3P3 VCC1P05_OUT_FET_2
+V1.05A_BYPASS DA15 BT5 +VCC1.05_OUT_FET
VCC_V1P05EXT_1P05_1 VCC1P05_OUT_FET_3
DA17
RC858 1 @ 2 0_0402_5% VCC_V1P05EXT_1P05_2
DA31
GPPC_B2_VRALERT_N VCCPRIM1P05_OUT_PCH_1
DB39 DC33
GPP_B2/VRALERT# VCCPRIM1P05_OUT_PCH_2
1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201

1 1 @ TP20 1 GPPC_F22_VNN_CTRL DV12 DC31

GPPC_F23_V1P05_CTRL GPP_F22/VNN_CTRL VCCPRIM1P05_OUT_PCH_3 +VCC1.05_OUT_PCH
PDG: VCCPRIM_3P3 CC40 CC41 @ TP21 1 DT12
GPP_F23/V1P05_CTRL
Placeholder up to 2 capacitor VCCRTC
DC35 VCCRTC
C VCCIN_AUX_VID0 DB37 DD37
If capacitor is on primary side place it near to 2 2 84,93 VCCIN_AUX_VID0 VCCIN_AUX_VID1 GPP_B0/CORE_VID0 VCCDSW_3P3 +VCCPDSW_3P3 C
package pins right after signal breakout. 84,93 VCCIN_AUX_VID1 DB38 DA28 +VCCPGPPR_3P3_1P8
GPP_B1/CORE_VID1 VCCPGPPR
If capacitor is on secondary side, make sure
CY31
the capacitor pads have power(VCC) and VCCPRIM_3P3_5
CY33
+VCCPRIM_3P3
ground (GND) vias next to each other, VCCPRIM_3P3_6
CV39
connected to main plane VCCPRIM_1P8_18 +VCCPRIM_1P8
AP12
RSVD_1

@ TGLLAKE-U_BGA1449
+VCCPGPPR_3P3_1P8
+1.8VALW_PCH

RC859 1 @ 2 0_0402_5%
1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201

1 1
CC42 CC43 +VCCIN_AUX +3VALW_PCH

1
2 2

1
RC205 RC203
100_0402_1% 1/20W_20K_5%_0201

2
DC4 2 1 GPPC_B2_VRALERT_N
10,59,79,93 H_PROCHOT_N

2
VCCIN_AUX_VCCSENSE
93 VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE
93 VCCIN_AUX_VSSSENSE
RB521CM-30T2R_VMN2M-2 Follow CRB Page35

1
RC204 1 @ 2 0_0402_5%
RC206
+1.8VALW_PCH +VCCPRIM_1P8 100_0402_1%

2
RC815 1 @ 2 0_5%_0603
B B
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1 1 1
PDG: VCCPRIM_1P8 CC46 CC47 CC48
Placeholder ?u_0402 * 1
Place the 0402 capacitor on the primary side, 2 2 2
as close as possible to the vias.

VCCRTC
+VCCLDOSTD_OUT_0P85 +VCCRTCEXT

+1.8VALW_PCH +VCCA_CLKLDO_1P8 PDG: VCCRTC

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
1 PDG: VCCLDOSTD_0P85 1 PDG: VCCRTCEXT 1 1 1u_0402 *1 + 0.1u_0402 *1
2.2u_0402 *1 0.1u_0402 *1 CC44 CC45 If capacitor is on primary side place it near to
RC860 1 @ 2 0_0402_5% +VCCIN_AUX CC49 CC51
Place on Primary/Secondary Side Place on Primary/Secondary Side package pins right after signal breakout.
2.2U_0402_6.3V6M as close as possible to the package 0.1u_0201_10V6K as close as possible to the package
2 2 2 2 If capacitor is on secondary side, make sure
edge (less than 3mm). Do not use edge (less than 3mm). the capacitor pads have power(VCC) and
2

RC208 bigger capacitance value than 2.2uF. ground (GND) vias next to each other,
0_0402_5% Use 10% tolerance capacitance. connected to main plane
100P_0402_50V8J

0.1U_6.3V_K_X5R_0201

EMC@ 1 EMC@ 1 EMC@ 1

12P_50V_F_COG_0402

CC92 CC93 CC94

1

VCCA_CLKLDO_R
1U_6.3V_M_X5R_0201

1 1 2 2 2
CC53 CC54 +VCCDSW_1P05 +VCCDPHY_1P24 +V1.05A_BYPASS +VNN_BYPASS
47U_6.3V_M_X5R_0805_H1.25
2 2
1U_6.3V_M_X5R_0201

1 1

1
CC50 PDG: VCCDPHY_1P24
PDG: VCCDSW_1P05 CC52 4.7u_0402 *1 @ @
PDG: VCCA_CLKLDO_1P8 1u_0402/0201 *1 4.7U_0402_6.3V6M Place on Primary/Secondary Side RC209 RC210
2 2 100K_0201_5% 1K_0402_5%
Place on Primary/Secondary Side as close as possible to the package
Place as close as possible to the as close as possible to the package edge (less than 3mm).

2
Inductor by default is a placeholder. If stuffed, the
680nF 1 inductor needs to meet following requirement: package (less than 5mm). edge (less than 3mm).
A (Placeholder) Rated at least 150mA; DCR = 0.036Ohm +/- 20% A

Option 1: stuff with 0 ohm if the inductor is not stuffed.

0 ohm_0603 1 Option 2: stuff 100 mohm if the inductor stuffed
100 mohm_0603

Place the cap near to package pin DR15 and DR12

47u_0603 1 right after signal breakout

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PCH Power
Date: Friday, September 03, 2021 Sheet 20 of 110
5 4 3 2 1
 5 4 3 2 1

UC1P UC1Q UC1R

16 OF 21 17 OF 21 18 OF 21

A27 B19 BY44 CY44 DP53 K34

VSS_223 VSS_289 VSS_109 VSS_169 VSS_2 VSS_46
A32 B2 BY45 CY45 DR11 K48
VSS_224 VSS_290 VSS_110 VSS_170 VSS_3 VSS_47
A45 B23 BY47 CY47 DR16 K5
VSS_225 VSS_291 VSS_111 VSS_171 VSS_4 VSS_48
A49 B27 BY49 CY5 DR22 L22
D VSS_226 VSS_292 VSS_112 VSS_172 VSS_5 VSS_49 D
AA41 B32 BY9 D27 DR28 L28
VSS_227 VSS_293 VSS_113 VSS_173 VSS_6 VSS_50
AA48 B36 C13 D32 DR34 L34
VSS_228 VSS_294 VSS_114 VSS_174 VSS_7 VSS_51
AB5 B39 C19 D36 DR40 L39
VSS_229 VSS_295 VSS_115 VSS_175 VSS_8 VSS_52
AB7 B42 C23 D42 DR46 L41
VSS_230 VSS_296 VSS_116 VSS_176 VSS_9 VSS_53
AB8 B48 CA48 D49 DT4 L42
VSS_231 VSS_297 VSS_117 VSS_177 VSS_10 VSS_54
AC44 B52 CB41 D5 DT50 L44
VSS_232 VSS_298 VSS_118 VSS_178 VSS_11 VSS_55
AC49 B8 CC10 DA30 DU11 L45
VSS_233 VSS_299 VSS_119 VSS_179 VSS_12 VSS_56
AD4 BA48 CC3 DA33 DU16 L47
VSS_234 VSS_300 VSS_120 VSS_180 VSS_13 VSS_57
AD48 BA53 CC5 DA53 DU22 L49
VSS_235 VSS_301 VSS_121 VSS_181 VSS_14 VSS_58
AD8 BB4 CD44 DC17 DU28 M1
VSS_236 VSS_302 VSS_122 VSS_182 VSS_15 VSS_59
AF4 BB8 CD48 DD15 DU34 M2
VSS_237 VSS_303 VSS_123 VSS_183 VSS_16 VSS_60
AF8 BC1 CD7 DD24 DU40 M50
VSS_238 VSS_304 VSS_124 VSS_184 VSS_17 VSS_61
AG41 BC2 CE49 DD26 DU46 N22
VSS_239 VSS_305 VSS_125 VSS_185 VSS_18 VSS_62
AG42 BD12 CG48 DD28 DV1 N28
VSS_240 VSS_306 VSS_126 VSS_186 VSS_19 VSS_63
AG44 BD4 CG51 DD31 DV40 N34
VSS_241 VSS_307 VSS_127 VSS_187 VSS_20 VSS_64
AG45 BD48 CG52 DD33 DV52 N39
VSS_242 VSS_308 VSS_128 VSS_188 VSS_21 VSS_65
AG47 BD8 CG9 DD35 DW51 N41
VSS_243 VSS_309 VSS_129 VSS_189 VSS_22 VSS_66
AG48 BF39 CH41 DD39 E13 N48
VSS_244 VSS_310 VSS_130 VSS_190 VSS_23 VSS_67
AG53 BF4 CH42 DD45 E19 P11
VSS_245 VSS_311 VSS_131 VSS_191 VSS_24 VSS_68
AH4 BF41 CH44 DD51 E35 P14
VSS_246 VSS_312 VSS_132 VSS_192 VSS_25 VSS_69
AH8 BF42 CH45 DD52 E48 P16
VSS_247 VSS_313 VSS_133 VSS_193 VSS_26 VSS_70
AK12 BF44 CH47 DE3 G22 P18
VSS_248 VSS_314 VSS_134 VSS_194 VSS_27 VSS_71
AK4 BF45 CJ3 DE5 G28 P20
VSS_249 VSS_315 VSS_135 VSS_195 VSS_28 VSS_72
C AK48 BF47 CJ5 DF19 G34 P22 C
VSS_250 VSS_316 VSS_136 VSS_196 VSS_29 VSS_73
AK5 BF5 CJ9 DF37 G39 P33
VSS_251 VSS_317 VSS_137 VSS_197 VSS_30 VSS_74
AK7 BF7 CK39 DG15 G48 P35
VSS_252 VSS_318 VSS_138 VSS_198 VSS_31 VSS_75
AK8 BF8 CK48 DG21 G51 P4
VSS_253 VSS_319 VSS_139 VSS_199 VSS_32 VSS_76
AM1 BG48 CK53 DG27 G52 P49
VSS_254 VSS_320 VSS_140 VSS_200 VSS_33 VSS_77
AM2 BG53 CL9 DG33 H12 P8
VSS_255 VSS_321 VSS_141 VSS_201 VSS_34 VSS_78
AM4 BH1 CN12 DG39 H22 R39
VSS_256 VSS_322 VSS_142 VSS_202 VSS_35 VSS_79
AM8 BH2 CN48 DG45 H28 R44
VSS_257 VSS_323 VSS_143 VSS_203 VSS_36 VSS_80
AN41 BH4 CN51 DG5 H34 T19
VSS_258 VSS_324 VSS_144 VSS_204 VSS_37 VSS_81
AN42 BH8 CN52 DG53 H8 T29
VSS_259 VSS_325 VSS_145 VSS_205 VSS_38 VSS_82
AN44 BK12 CN9 DG6 J39 T33
VSS_260 VSS_326 VSS_146 VSS_206 VSS_39 VSS_83
AN45 BK4 CP3 DJ1 J49 T4
VSS_261 VSS_327 VSS_147 VSS_207 VSS_40 VSS_84
AN47 BK48 CP41 DJ2 K16 T48
VSS_262 VSS_328 VSS_148 VSS_208 VSS_41 VSS_85
AN48 BK8 CP42 DJ4 K18 T8
VSS_263 VSS_329 VSS_149 VSS_209 VSS_42 VSS_86
AN53 BL49 CP44 DK51 K20 U19
VSS_264 VSS_330 VSS_150 VSS_210 VSS_43 VSS_87
AP4 BM1 CP45 DL3 K22 U25
VSS_265 VSS_331 VSS_151 VSS_211 VSS_44 VSS_88
AP8 BM4 CP5 DL5 K28 U39
VSS_266 VSS_332 VSS_152 VSS_212 VSS_45 VSS_89
AT4 BM41 CR48 DM10 U49
VSS_267 VSS_333 VSS_153 VSS_213 VSS_90
AT48 BM42 CR53 DM15 V19
VSS_268 VSS_334 VSS_154 VSS_214 VSS_91
AT51 BM44 CR9 DM21 V4
VSS_269 VSS_335 VSS_155 VSS_215 VSS_92
AT8 BM45 CT5 DM27 V8
VSS_270 VSS_336 VSS_156 VSS_216 VSS_93
AV12 BM47 CU4 DM33 W1
VSS_271 VSS_337 VSS_157 VSS_217 VSS_94
AV39 BM8 CU9 DM39 W16
VSS_272 VSS_338 VSS_158 VSS_218 VSS_95
AV4 BN48 CV10 DM4 W26
VSS_273 VSS_339 VSS_159 VSS_219 VSS_96
B AV5 BP41 CV48 DM45 W30 B
VSS_274 VSS_340 VSS_160 VSS_220 VSS_97
AV7 BP49 CV5 DN1 W39
VSS_275 VSS_341 VSS_161 VSS_221 VSS_98
AV8 BP5 CV51 DN2 W41
VSS_276 VSS_342 VSS_162 VSS_222 VSS_99
AW1 BP50 CV52 W42
VSS_277 VSS_343 VSS_163 VSS_100
AW2 BP7 CY17 W44
VSS_278 VSS_344 VSS_164 VSS_101
AW48 BT44 CY22 W45
VSS_279 VSS_345 VSS_165 VSS_102
AY4 BT48 CY35 W47
VSS_280 VSS_346 VSS_166 VSS_103
AY41 BU49 CY41 W48
VSS_281 VSS_347 VSS_167 VSS_104
AY42 BV3 CY42 Y4
VSS_282 VSS_348 VSS_168 VSS_105
AY44 BV48 Y49
VSS_283 VSS_349 VSS_106
AY45 BV5 Y50
VSS_284 VSS_350 VSS_107
AY47 BW10 @ TGLLAKE-U_BGA1449 Y8
VSS_285 VSS_351 VSS_108
AY8 BY41
VSS_286 VSS_352
AY9 BY42
VSS_287 VSS_353
B13 @ TGLLAKE-U_BGA1449
VSS_288

@ TGLLAKE-U_BGA1449

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B PCH Power 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 21 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B PCH PWR_Reserved 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 22 of 110
5 4 3 2 1
 5 4 3 2 1

UC1T +VCCIO_OUT
20 OF 21

@ TP22 1 CPU_CFG15 T15 A51 RSVD_TP_7 1 TP23 @

CPU_CFG14 CFG_15 RSVD_TP_7 RSVD_TP_8 1 TP32 @
V17 B51
@ TP25 1 CPU_CFG13 CFG_14 RSVD_TP_8
U15
@ TP26 1 CPU_CFG12 CFG_13 RSVD_TP_9 1 TP33 @
K11 C1
CPU_CFG11 CFG_12 RSVD_TP_9 RSVD_TP_10 1 TP34 @
K12 D2
CPU_CFG10 CFG_11 RSVD_TP_10
K9

RC220

RC217

RC216

RC215

RC218

RC219

RC214

RC213

RC212
CPU_CFG9 CFG_10
T17 CP39
@ TP29 1 CPU_CFG8 CFG_9 RSVD_TP_11 RSVD_TP_12 1 TP36 @
K7 CU40
CFG_8 RSVD_TP_12

2
CPU_CFG7 H7 AK9
D
@ TP31 1 CPU_CFG6 CFG_7 RSVD_12 D
K8
@ TP37 1 CPU_CFG5 CFG_6 @
H9 AH9
CPU_CFG4 CFG_5 RSVD_13
E6
CPU_CFG3 CFG_4
H5 DW6

1
CPU_CFG2 CFG_3 RSVD_14
E9 DV6

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%
CPU_CFG1 CFG_2 RSVD_15 CPU_CFG14
D9
@ TP41 1 CPU_CFG0 CFG_1 RSVD_TP_13 1 TP42 @ CPU_CFG11
E7 DV4
CFG_0 RSVD_TP_13 RSVD_TP_14 1 TP43 @ CPU_CFG10
DW3
RC221 2 1 49.9_0402_1% CFG_RCOMP RSVD_TP_14 CPU_CFG9
B5
CFG_RCOMP RSVD_TP_15 1 TP44 @ CPU_CFG7
DU1
@ TP47 1 CPU_CFG17 RSVD_TP_15 RSVD_TP_16 1 TP48 @ CPU_CFG4
U17 DT2
@ TP51 1 CPU_CFG16 CFG_17 RSVD_TP_16 CPU_CFG3
H11
CFG_16 RSVD_TP_17 1 TP53 @ CPU_CFG2
DW2
@ TP56 1 BPM3_N RSVD_TP_17 RSVD_TP_18 1 TP57 @ CPU_CFG1
Y1 DV2
@ TP59 1 BPM2_N BPM#_3 RSVD_TP_18
M4
@ TP62 1 BPM1_N BPM#_2 RSVD_TP_19 1 TP63 @
AB4 E1
@ TP65 1 BPM0_N BPM#_1 RSVD_TP_19 RSVD_TP_20 1 TP66 @
Y2 F1

RC230

RC227

RC226

RC225

RC228

RC229

RC224

RC223

RC222
BPM#_0 RSVD_TP_20
A3 AB2
RSVD_6 RSVD_16

2
B3
RSVD_7 RSVD_TP_21 1 TP71 @
DR1
RC231 1 2 2.2K_0402_1% TCP0_MBIAS RSVD_TP_21 RSVD_TP_22 1 TP73 @ @ @ @ @ @ @ @ @
AR2 DR2
@ TP75 1 RSVD_TP_2 TCP0_MBIAS_RCOMP RSVD_TP_22
AL10
@ TP76 1 RSVD_TP_3 RSVD_TP_2 RSVD_TP_23 1 TP77 @
AM12 DR53

1
@ TP78 1 RSVD_TP_4 RSVD_TP_3 RSVD_TP_23 RSVD_TP_24 1 TP79 @
AH12 DW5

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%
@ TP80 1 RSVD_TP_5 RSVD_TP_4 RSVD_TP_24
AJ10
@ TP81 1 RSVD_TP_6 RSVD_TP_5
AR1 DV51
RSVD_TP_6 VSS_1
DW52 TP_3 1 TP82 @
TP_3
BN10 DV53 TP_4 1 TP83 @
RSVD_8 TP_4
BM12 W34
RSVD_9 RSVD_17
DD13 V35
RSVD_10 RSVD_18
DF13
RSVD_11 SKTOCC_N 1 TP84 @
D52
SKTOCC#

@ TGLLAKE-U_BGA1449
C C

Pin Name Strap Description Configuration Default Value

CFG[0] RSVD None

UC1S
19 OF 21 CFG[3:1] RSVD Pull-up to VCCIO 1Kohm

DF53
RSVD_19 RSVD_23
C53 eDP enable strap Pull-up to VCCIO / Pull-down
RSVD_24
T35 CFG[4] 1 = Disabled Platform design dependent 1Kohm
DF52 E53 0 = Enabled
RSVD_20 RSVD_25
CF39
@ TP38 1 PCH_IST_TP_1 RSVD_26
DT52 U35
1 PCH_IST_TP_0 PCH_IST_TP_1 RSVD_27
@ TP40 DU53
PCH_IST_TP_0 RSVD_28
F53 CFG[6:5] RSVD None
B53
RSVD_29
DF50 AP9
RSVD_21 RSVD_30
DF49
RSVD_22 RSVD_31
A52 PEG deferred link training Pull-up to VCCIO / Pull-down
CFG[7] 1 = (default) PEG Trainimmediately Platform design dependent 1Kohm
@ TP45 1 CPU_CFG25 CY30 BF12 CPU_CFG28 1 TP46 @
CPU_CFG26 RSVD_TP_25 RSVD_TP_28 CPU_CFG29
following RESET# de-assertion.
@ TP49 1 CY15 V21 1 TP50 @
RSVD_TP_26 RSVD_TP_29 CPU_CFG30 1
0 = PEG Wait for BIOS for training.
W20 TP52 @
@ TP54 1 CPU_CFG27 RSVD_TP_30 CPU_CFG31 1 TP55 @
D4 U37
RSVD_TP_27 RSVD_TP_31
RSVD_TP_32
CD39 CFG[8] RSVD None
A6 U21 CPU_CFG33 1 TP61 @
IST_TP_1 RSVD_TP_33
A4 CB39
IST_TP_0 RSVD_32
RSVD_TP_34
BB12 CFG[11:9] RSVD Pull-up to VCCIO 1Kohm
W37 CPU_CFG35 1 TP68 @
RSVD_TP_35 CPU_CFG36 1 TP69 @
AY12
B RSVD_TP_36 CPU_CFG37 1 B
RSVD_TP_37
W38 TP70 @ CFG[13:12] RSVD None
U38 CPU_CFG38 1 TP72 @
RSVD_TP_38 CPU_CFG39 1 TP74 @
CY28
RSVD_TP_39
PEG60 Lane Reversal Pull-up to VCCIO / Pull-down
CFG[14] 1 = Normal(Default) Platform design dependent 1Kohm
@ TGLLAKE-U_BGA1449 0 = Reversed

CFG[17:15] RSVD None

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C PCH PWR_Reserved 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 23 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B XDP 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 24 of 110
5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[0..63]
DDRA_DQ[0..63] 8

+1.2V

1
+1.2V +1.2V @
JDDR1B RD133 +1.2V JDDR1A +1.2V
240_0402_1%

DDRA_MA3 131 132 DDRA_MA2 1 2

8 DDRA_MA3 DDRA_MA2 8

2
DDRA_MA1 133 A3 A2 134 DDRA_EVENT_N DDRA_DQ59 3 VSS_1 VSS_2 4 DDRA_DQ58
D 8 DDRA_MA1 A1 EVENT_n DQ5 DQ4 D
135 136 5 6
DDRA_CLK0_P 137 VDD_9 VDD_10 138 DDRA_CLK1_P DDRA_DQ60 7 VSS_3 VSS_4 8 DDRA_DQ62
8 DDRA_CLK0_P DDRA_CLK0_N CK0_t CK1_t DDRA_CLK1_N DDRA_CLK1_P 8 DQ1 DQ0
139 140 9 10
8 DDRA_CLK0_N 141 CK0_c CK1_c 142 DDRA_CLK1_N 8 DDRA_DQS7_N 11 VSS_5 VSS_6 12
DDRA_PAR VDD_11 VDD_12 DDRA_MA0 8 DDRA_DQS7_N DDRA_DQS7_P DQS0_C DM0_n/DBIO_n/NC
143 144 13 14
8 DDRA_PAR Parity A0 DDRA_MA0 8 8 DDRA_DQS7_P DQS0_t VSS_7 DDRA_DQ57
15 16
DDRA_DQ61 17 VSS_8 DQ6 18
DDRA_BA1 145 146 DDRA_MA10 19 DQ7 VSS_9 20 DDRA_DQ56
8 DDRA_BA1 147 BA1 A10/AP 148 DDRA_MA10 8 DDRA_DQ63 21 VSS_10 DQ2 22
DDRA_CS0_N 149 VDD_13 VDD_14 150 DDRA_BA0 23 DQ3 VSS_11 24 DDRA_DQ45
8 DDRA_CS0_N DDRA_MA14_WE_N CS0_n BA0 DDRA_MA16_RAS_N DDRA_BA0 8 DDRA_DQ47 VSS_12 DQ12
151 152 25 26
8 DDRA_MA14_WE_N 153 WE_n/A14 RAS_n/A16 154 DDRA_MA16_RAS_N 8 27 DQ13 VSS_13 28 DDRA_DQ44
DDRA_ODT0 155 VDD_15 VDD_16 156 DDRA_MA15_CAS_N DDRA_DQ46 29 VSS_14 DQ8 30
8 DDRA_ODT0 DDRA_CS1_N 157 ODT0 CAS_n/A15 158 DDRA_MA13 DDRA_MA15_CAS_N 8 31 DQ9 VSS_15 32 DDRA_DQS5_N
8 DDRA_CS1_N CS1_n A13 DDRA_MA13 8 VSS_16 DQS1_c DDRA_DQS5_P DDRA_DQS5_N 8
159 160 33 34
DDRA_ODT1 VDD_17 VDD_18 DM1_n/DBl1_n/NC DQS1_t DDRA_DQS5_P 8
161 162 35 36
8 DDRA_ODT1 163 ODT1 C0/CS2_n/NC 164 +VREF_CA_DIMM DDRA_DQ40 37 VSS_17 VSS_18 38 DDRA_DQ42
165 VDD_19 VREFCA 166 DDRA_SA2 39 DQ15 DQ14 40
167 C1/CS3_n/NC SA2 168 DDRA_DQ43 41 VSS_19 VSS_20 42 DDRA_DQ41
DDRA_DQ19 169 VSS_53 VSS_54 170 DDRA_DQ21 43 DQ10 DQ11 44
DQ37 DQ36 1 1 VSS_21 VSS_22
171 172 @ DDRA_DQ38 45 46 DDRA_DQ36
DDRA_DQ17 173 VSS_55 VSS_56 174 DDRA_DQ23 CD74 CD75 47 DQ21 DQ20 48
175 DQ33 DQ32 176 0.1u_0201_10V6K 2.2U_0402_6.3V6M DDRA_DQ37 49 VSS_23 VSS_24 50 DDRA_DQ39
DDRA_DQS2_N 177 VSS_57 VSS_58 178 2 2 51 DQ17 DQ16 52
8 DDRA_DQS2_N DDRA_DQS2_P DQS4_c DM4_n/DBl4_n/NC DDRA_DQS4_N VSS_25 VSS_26
179 180 53 54
8 DDRA_DQS2_P DQS4_t VSS_59 DDRA_DQ20 8 DDRA_DQS4_N DDRA_DQS4_P DQS2_c DM2_n/DBl2_n/NC
181 182 55 56
DDRA_DQ22 183 VSS_60 DQ39 184 8 DDRA_DQS4_P 57 DQS2_t VSS_27 58 DDRA_DQ34
185 DQ38 VSS_61 186 DDRA_DQ16 DDRA_DQ35 59 VSS_28 DQ22 60
DDRA_DQ18 187 VSS_62 DQ35 188 61 DQ23 VSS_29 62 DDRA_DQ33
189 DQ34 VSS_63 190 DDRA_DQ12 DDRA_DQ32 63 VSS_30 DQ18 64
DDRA_DQ14 191 VSS_64 DQ45 192 65 DQ19 VSS_31 66 DDRA_DQ52
193 DQ44 VSS_65 194 DDRA_DQ13 DDRA_DQ51 67 VSS_32 DQ28 68
DDRA_DQ15 195 VSS_66 DQ41 196 69 DQ29 VSS_33 70 DDRA_DQ53
197 DQ40 VSS_67 198 DDRA_DQS1_N DDRA_DQ48 71 VSS_34 DQ24 72
VSS_68 DQS5_c DDRA_DQS1_P DDRA_DQS1_N 8 DQ25 VSS_35 DDRA_DQS6_N
199 200 73 74
DM5_n/DBl5_n/NC DQS5_t DDRA_DQS1_P 8 VSS_36 DQS3_c DDRA_DQS6_P DDRA_DQS6_N 8
201 202 +1.2V 75 76
DDRA_DQ8 203 VSS_69 VSS_70 204 DDRA_DQ10 77 DM3_n/DBl3_n/NC DQS3_t 78 DDRA_DQS6_P 8
205 DQ46 DQ47 206 DDRA_DQ54 79 VSS_37 VSS_38 80 DDRA_DQ50
C C
DDRA_DQ9 207 VSS_71 VSS_72 208 DDRA_DQ11 81 DQ30 DQ31 82
209 DQ42 DQ43 210 DDRA_DQ55 83 VSS_39 VSS_40 84 DDRA_DQ49

1
DDRA_DQ5 211 VSS_73 VSS_74 212 DDRA_DQ7 85 DQ26 DQ27 86
213 DQ52 DQ53 214 RD129 RD128 87 VSS_41 VSS_42 88
DDRA_DQ4 215 VSS_75 VSS_76 216 DDRA_DQ6 240_0402_1% 240_0402_1% 89 CB5/NC CB4/NC 90
217 DQ49 DQ48 218 91 VSS_43 VSS_44 92
DDRA_DQS0_N 219 VSS_77 VSS_78 220 93 CB1/NC CB0/NC 94
8 DDRA_DQS0_N

2
DDRA_DQS0_P 221 DQS6_c DM6_n/DBl6_n/NC 222 DDRA_DQS8_N 95 VSS_45 VSS_46 96
8 DDRA_DQS0_P 223 DQS6_t VSS_79 224 DDRA_DQ1 DDRA_DQS8_P 97 DQS8_c DM8_n/DBI8_n/NC 98
DDRA_DQ3 225 VSS_80 DQ54 226 99 DQS8_t VSS_47 100
227 DQ55 VSS_81 228 DDRA_DQ2 101 VSS_48 CB6/NC 102
DDRA_DQ0 229 VSS_82 DQ50 230 103 CB2/NC VSS_49 104
231 DQ51 VSS_83 232 DDRA_DQ29 105 VSS_50 CB7/NC 106
DDRA_DQ27 233 VSS_84 DQ60 234 107 CB3/NC VSS_51 108
DQ61 VSS_85 DDRA_DQ31 DDRA_CKE0 VSS_52 RESET_n DDRA_CKE1 CPU_DRAMRST_N_R 8,26
235 236 109 110
DDRA_DQ24 237 VSS_86 DQ57 238 8 DDRA_CKE0 111 CKE0 CKE1 112 DDRA_CKE1 8
DQ56 VSS_87 VDD_1 VDD_2 1
239 240 DDRA_DQS3_N DDRA_BG1 113 114 DDRA_ACT_N @
VSS_88 DQS7_c DDRA_DQS3_P DDRA_DQS3_N 8 8 DDRA_BG1 DDRA_BG0 BG1 ACT_n DDRA_ALERT_N DDRA_ACT_N 8
241 242 115 116 CD1806
243 DM7_n/DBl7_n/NC DQS7_t 244 DDRA_DQS3_P 8 8 DDRA_BG0 117 BG0 ALERT_n 118 DDRA_ALERT_N 8
VSS_89 VSS_90 VDD_3 VDD_4 0.1u_0201_10V6K
DDRA_DQ28 245 246 DDRA_DQ26 DDRA_MA12 119 120 DDRA_MA11 2
247 DQ62 DQ63 248 8 DDRA_MA12 DDRA_MA9 121 A12 A11 122 DDRA_MA7 DDRA_MA11 8
DDRA_DQ30 VSS_91 VSS_92 DDRA_DQ25 8 DDRA_MA9 A9 A7 DDRA_MA7 8
249 250 123 124
251 DQ58 DQ59 252 DDRA_MA8 125 VDD_5 VDD_6 126 DDRA_MA5
SMB_CLK_S1 253 VSS_93 VSS_94 254 SMB_DATA_S1 8 DDRA_MA8 DDRA_MA6 127 A8 A5 128 DDRA_MA4 DDRA_MA5 8
11,26 SMB_CLK_S1 @ +VDD_SPD SCL SDA DDRA_SA0 SMB_DATA_S1 11,26 8 DDRA_MA6 A6 A4 DDRA_MA4 8
+3VS 1 2 255 256 129 130
257 VDDSPD SA0 258 VDD_7 VDD_8
VPP_1 VTT DDRA_SA1 +0.6VS
RD77 259 260
0_5%_0603 VPP_2 SA1
1 1 261 262 ARGOS_D4AR0-26001-1P40
GND_1 GND_2
ME@
CD72 CD73 ARGOS_D4AR0-26001-1P40
2.2U_0402_6.3V6M 0.1u_0201_10V6K ME@
2 2

+1.2V
B B
1 @ 2 +VPP
+2.5V_DDR
1

1
RD127 CD151
0_5%_0603 0.1u_0201_10V6K
RD73
2 1K_0402_1% SPD Address = 50H

2
RD70 1 2 2_0402_5% +VREF_CA_DIMM +3VS +3VS
8 DDR_SA_VREFCA +3VS
1
+1.2V

1
CD68 @ @ @

1
0.022U_16V_K_X7R_0402 RD67 RD71 RD131
2 0_0402_5% 0_0402_5% 0_0402_5%
1
1

RD74 CD70

2
2 1K_0402_1% 0.1u_0201_10V6K DDRA_SA0 DDRA_SA1 DDRA_SA2
RD134 2

2
1 EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 24.9_0402_1%
10P_50V_J_COG_0201
C8124

10P_50V_J_COG_0201
C8214

10P_50V_J_COG_0201
C8215

10P_50V_J_COG_0201
C8216

10P_50V_J_COG_0201
C8217

10P_50V_J_COG_0201
C8218

10P_50V_J_COG_0201
C8219

RD68 RD130 RD132

0_0402_5% 0_0402_5% 0_0402_5%
2 2 2 2 2 2 2

1
@
+2.5V_DDR

1 EMC@ 1 EMC@ 1 EMC@

10P_50V_J_COG_0201
C8220

10P_50V_J_COG_0201
C8221

10P_50V_J_COG_0201
C8222

A A
2 2 2

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C Memory_CHA 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 25 of 110
5 4 3 2 1
 5 4 3 2 1

9 DDRB_MA[16:0]

9 DDRB_DQ0_[7:0]

9 DDRB_DQ1_[7:0]

9 DDRB_DQ2_[7:0]

9 DDRB_DQ3_[7:0]

9 DDRB_DQ4_[7:0]
+1.2V +1.2V +1.2V
D 9 DDRB_DQ5_[7:0] D
+1.2V +1.2V
9 DDRB_DQ6_[7:0]

1
JDDR2A @
JDDR2B RD150
9 DDRB_DQ7_[7:0]
240_0402_1%
1 2
DDRB_DQ7_2 3 VSS_1 VSS_2 4 DDRB_DQ7_3 DDRB_MA3 131 132 DDRB_MA2

2
5 DQ5 DQ4 6 DDRB_MA1 133 A3 A2 134 JDDRB_EVENT_N
DDRB_DQ7_6 7 VSS_3 VSS_4 8 DDRB_DQ7_5 135 A1 EVENT_n 136
9 DQ1 DQ0 10 DDRB_CLK0_DP 137 VDD_9 VDD_10 138 DDRB_CLK1_DP
DDRB_DQS7_DN VSS_5 VSS_6 9 DDRB_CLK0_DP DDRB_CLK0_DN CK0_t CK1_t DDRB_CLK1_DN DDRB_CLK1_DP 9
11 12 139 140
9 DDRB_DQS7_DN DDRB_DQS7_DP 13 DQS0_CDM0_n/DBIO_n/NC 14 9 DDRB_CLK0_DN 141 CK0_c CK1_c 142 DDRB_CLK1_DN 9
9 DDRB_DQS7_DP DQS0_t VSS_7 DDRB_DQ7_7 DDRB_PARITY VDD_11 VDD_12 DDRB_MA0
15 16 143 144
DDRB_DQ7_4 17 VSS_8 DQ6 18 9 DDRB_PARITY Parity A0
19 DQ7 VSS_9 20 DDRB_DQ7_1
DDRB_DQ7_0 21 VSS_10 DQ2 22 DDRB_BA1 145 146 DDRB_MA10
23 DQ3 VSS_11 24 DDRB_DQ5_1 9 DDRB_BA1 147 BA1 A10/AP 148
DDRB_DQ5_2 25 VSS_12 DQ12 26 DDRB_CS0 149 VDD_13 VDD_14 150 DDRB_BA0
27 DQ13 VSS_13 28 DDRB_DQ5_0 9 DDRB_CS0 DDRB_MA14 151 CS0_n BA0 152 DDRB_MA16 DDRB_BA0 9
DDRB_DQ5_7 29 VSS_14 DQ8 30 153 WE_n/A14 RAS_n/A16 154
31 DQ9 VSS_15 32 DDRB_DQS5_DN DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15
33 VSS_16 DQS1_c 34 DDRB_DQS5_DP DDRB_DQS5_DN 9 9 DDRB_ODT0 DDRB_CS1 157 ODT0 CAS_n/A15 158 DDRB_MA13 M_B_VREF_CA
DM1_n/DBl1_n/NC DQS1_t DDRB_DQS5_DP 9 9 DDRB_CS1 CS1_n A13
35 36 159 160
DDRB_DQ5_4 37 VSS_17 VSS_18 38 DDRB_DQ5_6 DDRB_ODT1 161 VDD_17 VDD_18 162
39 DQ15 DQ14 40 9 DDRB_ODT1 163 ODT1 C0/CS2_n/NC 164
DDRB_DQ5_3 41 VSS_19 VSS_20 42 DDRB_DQ5_5 165 VDD_19 VREFCA 166 DDRB_SA2
43 DQ10 DQ11 44 167 C1/CS3_n/NC SA2 168
DDRB_DQ4_2 VSS_21 VSS_22 DDRB_DQ4_3 DDRB_DQ1_0 VSS_53 VSS_54 DDRB_DQ1_7 @

0.1u_0201_10V6K

2.2U_0402_6.3V6M
45 46 169 170 1 1
47 DQ21 DQ20 48 171 DQ37 DQ36 172 CD1816 CD1815
DDRB_DQ4_1 49 VSS_23 VSS_24 50 DDRB_DQ4_4 DDRB_DQ1_6 173 VSS_55 VSS_56 174 DDRB_DQ1_5
51 DQ17 DQ16 52 175 DQ33 DQ32 176
DDRB_DQS4_DN 53 VSS_25 VSS_26 54 DDRB_DQS1_DN 177 VSS_57 VSS_58 178 2 2
9 DDRB_DQS4_DN DDRB_DQS4_DP DQS2_c DM2_n/DBl2_n/NC 9 DDRB_DQS1_DN DDRB_DQS1_DP DQS4_c DM4_n/DBl4_n/NC
55 56 179 180
9 DDRB_DQS4_DP 57 DQS2_t VSS_27 58 DDRB_DQ4_5 9 DDRB_DQS1_DP 181 DQS4_t VSS_59 182 DDRB_DQ1_3
DDRB_DQ4_7 59 VSS_28 DQ22 60 DDRB_DQ1_4 183 VSS_60 DQ39 184
61 DQ23 VSS_29 62 DDRB_DQ4_6 185 DQ38 VSS_61 186 DDRB_DQ1_1
DDRB_DQ4_0 63 VSS_30 DQ18 64 DDRB_DQ1_2 187 VSS_62 DQ35 188
65 DQ19 VSS_31 66 DDRB_DQ6_6 189 DQ34 VSS_63 190 DDRB_DQ0_7
DDRB_DQ6_3 67 VSS_32 DQ28 68 DDRB_DQ0_0 191 VSS_64 DQ45 192
69 DQ29 VSS_33 70 DDRB_DQ6_7 193 DQ44 VSS_65 194 DDRB_DQ0_5
DDRB_DQ6_1 71 VSS_34 DQ24 72 DDRB_DQ0_6 195 VSS_66 DQ41 196
73 DQ25 VSS_35 74 DDRB_DQS6_DN 197 DQ40 VSS_67 198 DDRB_DQS0_DN
VSS_36 DQS3_c DDRB_DQS6_DP DDRB_DQS6_DN 9 VSS_68 DQS5_c DDRB_DQS0_DP DDRB_DQS0_DN 9
+1.2V 75 76 199 200
77 DM3_n/DBl3_n/NC DQS3_t 78 DDRB_DQS6_DP 9 201 DM5_n/DBl5_n/NC DQS5_t 202 DDRB_DQS0_DP 9
DDRB_DQ6_2 79 VSS_37 VSS_38 80 DDRB_DQ6_0 DDRB_DQ0_3 203 VSS_69 VSS_70 204 DDRB_DQ0_4
81 DQ30 DQ31 82 205 DQ46 DQ47 206
DDRB_DQ6_5 83 VSS_39 VSS_40 84 DDRB_DQ6_4 DDRB_DQ0_1 207 VSS_71 VSS_72 208 DDRB_DQ0_2
DQ26 DQ27 DQ42 DQ43

1
85 86 209 210
RD148 RD149 87 VSS_41 VSS_42 88 DDRB_DQ3_3 211 VSS_73 VSS_74 212 DDRB_DQ3_7
240_0402_1% 240_0402_1% 89 CB5/NC CB4/NC 90 213 DQ52 DQ53 214
C 91 VSS_43 VSS_44 92 DDRB_DQ3_2 215 VSS_75 VSS_76 216 DDRB_DQ3_6 C
2 93 CB1/NC CB0/NC 94 217 DQ49 DQ48 218

2
-M_B_DQS8 95 VSS_45 VSS_46 96 DDRB_DQS3_DN 219 VSS_77 VSS_78 220
M_B_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 9 DDRB_DQS3_DN DDRB_DQS3_DP 221 DQS6_c DM6_n/DBl6_n/NC 222
99 DQS8_t VSS_47 100 9 DDRB_DQS3_DP 223 DQS6_t VSS_79 224 DDRB_DQ3_0
101 VSS_48 CB6/NC 102 DDRB_DQ3_4 225 VSS_80 DQ54 226
103 CB2/NC VSS_49 104 227 DQ55 VSS_81 228 DDRB_DQ3_1
105 VSS_50 CB7/NC 106 DDRB_DQ3_5 229 VSS_82 DQ50 230
107 CB3/NC VSS_51 108 CPU_DRAMRST_N_R 231 DQ51 VSS_83 232 DDRB_DQ2_0
DDRB_CKE0 109 VSS_52 RESET_n 110 DDRB_CKE1 CPU_DRAMRST_N_R 8,25 DDRB_DQ2_7 233 VSS_84 DQ60 234
9 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 9 DQ61 VSS_85 DDRB_DQ2_2
111 112 235 236
DDRB_BG1 113 VDD_1 VDD_2 114 DDRB_ACT_N DDRB_DQ2_5 237 VSS_86 DQ57 238
9 DDRB_BG1 DDRB_BG0 BG1 ACT_n DDRB_ALERT_N DDRB_ACT_N 9 DQ56 VSS_87 DDRB_DQS2_DN
115 116 239 240
9 DDRB_BG0 117 BG0 ALERT_n 118 DDRB_ALERT_N 9 241 VSS_88 DQS7_c 242 DDRB_DQS2_DP DDRB_DQS2_DN 9
DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 243 DM7_n/DBl7_n/NC DQS7_t 244 DDRB_DQS2_DP 9
DDRB_MA9 121 A12 A11 122 DDRB_MA7 DDRB_DQ2_3 245 VSS_89 VSS_90 246 DDRB_DQ2_6
123 A9 A7 124 +2.5V_DDR +3VS 247 DQ62 DQ63 248 +0.6VS
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 DDRB_DQ2_1 249 VSS_91 VSS_92 250 DDRB_DQ2_4
DDRB_MA6 127 A8 A5 128 DDRB_MA4 251 DQ58 DQ59 252
129 A6 A4 130 SMB_CLK_S1 253 VSS_93 VSS_94 254 SMB_DATA_S1
VDD_7 VDD_8 11,25 SMB_CLK_S1 SCL SDA DDRB_SA0 SMB_DATA_S1 11,25
1 255 256
EMC_NS@ 257 VDDSPD SA0 258
C3301 259 VPP_1 VTT 260 DDRB_SA1
ARGOS_D4AR0-26001-1P40 0.1U_25V_K_X5R_0402 VPP_2 SA1
ME@ 2 261 262
GND_1 GND_2

2.2U_0402_6.3V6M

0.1u_0201_10V6K
1 1
CD1817 CD1818 ARGOS_D4AR0-26001-1P40
ME@
2 2

+1.2V

1 EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 1 EMC@

10P_50V_J_COG_0201
C8223

10P_50V_J_COG_0201
C8224

10P_50V_J_COG_0201
C8225

10P_50V_J_COG_0201
C8226

10P_50V_J_COG_0201
C8227

10P_50V_J_COG_0201
C8228

10P_50V_J_COG_0201
C8229

2 2 2 2 2 2 2

B B
SPD Address = 52H

+2.5V_DDR
+3VS +3VS +3VS

1
1 EMC@ 1 EMC@ 1 EMC@ @ @
10P_50V_J_COG_0201
C8230

10P_50V_J_COG_0201
C8231

10P_50V_J_COG_0201
C8232
+1.2V RD145 RD139 RD147
10K_0402_5% 10K_0402_5% 10K_0402_5%

2
2 2 2 DDRB_SA0 DDRB_SA1 DDRB_SA2
1

2
CD1807
0.1u_0201_10V6K @
RD143 RD137 RD138 RD140
2 1K_0402_1% 0_0402_5% 0_0402_5%
0_0402_5%

1
@ @

RD142 1 2 2_0402_5% M_B_VREF_CA

9 DDRB_VREF_CA

1
CD1813

1
0.022U_16V_K_X7R_0402
2
1
DDR_SA_VREFCA_C RD144

1
1K_0402_1% CD1814
0.1u_0201_10V6K

2
RD146 2
24.9_0402_1%

A 2 A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D Memory_CHB 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 26 of 110
5 4 3 2 1
 5 4 3 2 1

PCH_SPI0_CS0_N RB1 1 2 0_0201_5% SPI_CS0_N

11 PCH_SPI0_CS0_N PCH_SPI0_CLK 1 2 SPI_CLK
RB8 1/20W_15_5%_0201
11,82 PCH_SPI0_CLK PCH_SPI0_SI SPI_SI
RB3 1 2 1/20W_15_5%_0201
11,82 PCH_SPI0_SI PCH_SPI0_SO 1 2 SPI_SO +3VSUS +3V_SPI
RB6 1/20W_15_5%_0201
D 11,82 PCH_SPI0_SO PCH_SPI0_IO2 SPI_IO2 D
RB4 1 2 1/20W_49.9_1%_0201
11 PCH_SPI0_IO2 PCH_SPI0_IO3 1 2 SPI_IO3
RB5 1/20W_49.9_1%_0201
11 PCH_SPI0_IO3 1 2 0_0201_5%
RB2 @

NEED EC VENDER CHECK DB1 2 1

EC_SPI_CS0_N RB26 1 2 1/20W_49.9_1%_0201 PCH_SPI0_CS0_N RB521CM-30T2R_VMN2M-2

79 EC_SPI_CS0_N EC_SPI_CLK 1 2 PCH_SPI0_CLK
RB10 1/20W_49.9_1%_0201
79 EC_SPI_CLK EC_SPI_SI RB11 1 2 1/20W_49.9_1%_0201 PCH_SPI0_SI
79 EC_SPI_SI EC_SPI_SO RB12 1 2 1/20W_49.9_1%_0201 PCH_SPI0_SO
79 EC_SPI_SO

SPI_SO RB7 1 @ 2 100K_0201_5%

2021/07/08
C Change BIOS ROM PN C

+3V_SPI

+3V_SPI
1
@
C8210
0.22U_6.3V_K_X5R_0201 JBIOS
2 SPI_CS0_N 1 2
UB1 SPI_SO 3 1 2 4 SPI_IO3
SPI_CS0_N 1 8 SPI_IO2 5 3 4 6 SPI_CLK
/CS VCC 7 5 6 8 SPI_SI
SPI_SO 2 7 SPI_IO3 7 8
IO1 IO3 CVILUX_CH51082M103-0P-NH
SPI_IO2 3 6 SPI_CLK
IO2 CLK
4 5 SPI_SI
GND IO0
9
PTH
B B

W25R256JVEIN_WSON8_8X6

TABLE of BIOS ROM (UB1)

Vendor LCFC P/N Description

WINBOND SA0000BND00 S IC FL 256M W25R256JVEIN WSON 8P SPI

MXIC SA0000A1R00 S IC FL 256M MX77L25650FZ4I42 WSON 8P

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B SPI ROM/TPM 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 27 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C GPU_PCIE Interface 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 28 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C GPU_Display Interface1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 29 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C GPU_MEM Interface(A/B)
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 30 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B GPU_MEM Interface(C/D) 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 31 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C GPU_GPIO/JTAG 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 32 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C GPU_Strap 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 33 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C GPU_PWR1 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 34 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C GPU_PWR2 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 35 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B GPU_GND 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 36 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C VRAM_A_[31:0] 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 37 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C VRAM_A_[64:32] 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 38 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B VRAM_B_[31:0] 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 39 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B VRAM_B_[64:32] 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 40 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B VRAM_C_[31:0] 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 41 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B VRAM_C_[64:32] 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 42 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B VRAM_D_[31:0] 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 43 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B VRAM_D_[64:32] 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 44 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B eDP MUX 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 45 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B NV DDS LOGIC 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 46 of 110
5 4 3 2 1
 5 4 3 2 1

2021/07/06
Connector PN from SP01001XA00 to SP01002LY00
LCD EDP Display
JEDP1

+LEDVDD 1
+3VS 2 1
3 2
+LCDVDD +LCDVDD_CON 4 3
B+ +LEDVDD 5 4
1 5

0.1U_6.3V_K_X5R_0201
@ DISPOFF_N 6
UV1 @ INVT_PWM 6
CV1 FV1 7
RV1 W=60mils CPU_EDP_HPD 7
5 1 1 2 1 2 8
2 IN OUT 7 CPU_EDP_HPD 8
0_5%_0603 9
2 3A_32V_ERBRD3R00X CPU_EDP_AUX_P CV8 1 2 0.1u_0201_10V6K EDP_AUX_CON_P 10 9
GND 7 CPU_EDP_AUX_P 10

0.1U_6.3V_K_X5R_0201

33P_50V_J_NPO_0201

0.1U_25V_K_X5R_0201

10U_25V_M_X5R_0603

0.1U_25V_K_X5R_0201
1 @ 1 @ 1 @ 1 1 EMC@ 1 CPU_EDP_AUX_N CV9 1 2 0.1u_0201_10V6K EDP_AUX_CON_N 11
D 7 CPU_EDP_AUX_N 11 D

10U 6.3V M X5R 0402

4 3 CV2 CV3 CV4 CV5 CV6 CV7 12
7 PCH_ENVDD EN OCB CPU_EDP_TX0_P EDP_TX0_CON_P 12
CV10 1 2 0.1u_0201_10V6K 13
7 CPU_EDP_TX0_P CPU_EDP_TX0_N EDP_TX0_CON_N 13
SY6288C20AAC_SOT23-5 CV11 1 2 0.1u_0201_10V6K 14
2 2 2 2 2 2 7 CPU_EDP_TX0_N 15 14
CPU_EDP_TX1_P CV12 1 2 0.1u_0201_10V6K EDP_TX1_CON_P 16 15
7 CPU_EDP_TX1_P CPU_EDP_TX1_N EDP_TX1_CON_N 16
CV13 1 2 0.1u_0201_10V6K 17
7 CPU_EDP_TX1_N 18 17
USB20_5_CON_N 19 18
USB20_5_CON_P 20 19
21 20
DMIC_CLK_CON 22 21
DMIC_DAT_CON 23 22
24 23
25 24
+3VS_MIC 25
26
27 26
+3VS_CAMERA 27
28
TABLE of POWER SWITCH (UV1) 29 28 32
+LCDVDD_CON 29 GND1
30 31
30 GND2
Vendor LCFC P/N Description
HIGHS_FC5AF301-3182-1H
ME@
SILERGY SA000074P00 S IC SY6288C20AAC SOT23 5P POWER SWITCH
+3VS
GMT SA000093600 S IC G517F1T13U SOT-23 5P POWER SWITCH

1
@
RV3
PCH_ENBKL RV10 1 @ 2 0_0201_5% 1/20W_4.7K_5%_0201
7,79 PCH_ENBKL

2
EC_BKOFF_N RV2 1 @ 2 0_0201_5% DISPOFF_N +3VS
79 EC_BKOFF_N

+3VS RV8 1 @ 2 100K_0201_5% EDP_AUX_CON_N

C DMIC 3.3V Level RV9 1 @ 2 100K_0201_5% EDP_AUX_CON_P C

2
@
DMIC_DATA RA78 1 @ 2 0_0201_5% DMIC_DAT_CON RV5
1K_0201_5%
DMIC_CLK RA79 1 @ 2 0_0201_5% DMIC_CLK_CON RV7 2 1 100K_0201_5% CPU_EDP_HPD

1
PCH_EDP_PWM RV4 1 @ 2 0_0201_5% INVT_PWM
RA81 1 @ 7 PCH_EDP_PWM
2 0_0201_5%
13 PCH_DMIC_DAT0
RA80 2 @ 1 0_0201_5% DMIC_DATA
66 CODEC_DMIC_DAT

RA82 2 @ 1 0_0201_5% DMIC_CLK

66 CODEC_DMIC_CLK
RA17 1 @ 2 0_0201_5%
13 PCH_DMIC_CLK0

+1.8VS +3VS
DMIC
DMIC 1.8V Level +1.8VS
@
FA2
1 2
4
3
100P 25V J NPO 0201

100P 25V J NPO 0201

1 1
4
3

2.2K_0404_4P2R_5%
RPA3

RPA2 CA85 CA86 1A_32V_ERBRD1R00X

+3VS
2.2K_0404_4P2R_5%

+3VS_MIC
2 2 FA1
Camera
1
2

+1.8VS 1 2 W=40mils
1
2

UA5 +3VS

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201
@ 1 1A_32V_ERBRD1R00X 1 EMC@ 1 +3VS_CAMERA
2

0.1U_6.3V_K_X5R_0201

1 8 CA90 CA89 CA88

VCCA VCCB FI101
DMIC_DATA 2 7 DMIC_DAT_CON RA77 1 2 W=40mils
A0 B0 0_0201_5% 2 2 2
B DMIC_CLK DMIC_CLK_CON B
3 6 1A_32V_ERBRD1R00X
1

A1 B1

0.1U_6.3V_K_X5R_0201

10U 6.3V M X5R 0402

.047U_0201_6.3V6K
@ 1 1 @ 1
DMIC_OUTPUT_EN @
4 5 CI101 CI102 CI103
GND OE
1

FXMA2102UMX_U-MLP8_1P2X1P4 2 2 2
RA76
100K_0201_5%
2

2021/08/30

LI101 EMC@
USB20_5_P 1 2 USB20_5_CON_P
EMC Close to Connector 14 USB20_5_P 1 2

DMIC_DAT_CON DMIC_CLK_CON DISPOFF_N INVT_PWM USB20_5_N 4 3 USB20_5_CON_N

14 USB20_5_N 4 3
EXC24CH900U_4P
100P_0402_50V8J

100P_0402_50V8J

470P_0402_50V_X7R_0402

470P_50V_K_X7R_0201

CA84 1 CA87 1 CV14 1 CV15 1

EMC@ EMC@ EMC@ EMC@

2 2 2 2
A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C eDP_DDI/CAM/DMIC/ISH 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 47 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B DP 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 48 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B HDMI_RETIMER 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 49 of 110
5 4 3 2 1
 5 4 3 2 1

2021/08/30
HDMI Power Request DFC

EMC
+5VS +5VS_HDMI_F +5VS_HDMI

HDMI_CLK_DP_C RV513 1 2 2_0402_5% HDMI_CLK_CON_P HDMI_TX1_DP_C RV519 1 2 2_0402_5% HDMI_TX1_CON_P

FV501

1
1 3 1 2

S
1 RV515 RV521
QV501 1.1A_8V_1206L110THYR 220_0402_1% 220_0402_1%
LP2301ALT1G_SOT-23-3 CV501 EMC_NS@ EMC_NS@

G
2
D D
0.1u_0201_10V6K

2
2 HDMI_CLK_DN_C RV514 1 2 2_0402_5% HDMI_CLK_CON_N HDMI_TX1_DN_C RV520 1 2 2_0402_5% HDMI_TX1_CON_N
84 SUSP

HDMI_TX0_DP_C RV516 1 2 2_0402_5% HDMI_TX0_CON_P

HDMI_TX2_DP_C RV522 1 2 2_0402_5% HDMI_TX2_CON_P

1
RV518
220_0402_1% RV524
EMC_NS@ 220_0402_1%
EMC_NS@

2
CPU_HDMI_TX0_P CV502 1 2 0.1u_0201_10V6K HDMI_TX0_DP_C HDMI_TX0_DN_C RV517 1 2 2_0402_5% HDMI_TX0_CON_N
7 CPU_HDMI_TX0_P

2
CPU_HDMI_TX0_N CV503 1 2 0.1u_0201_10V6K HDMI_TX0_DN_C HDMI_TX2_DN_C RV523 1 2 2_0402_5% HDMI_TX2_CON_N
7 CPU_HDMI_TX0_N CPU_HDMI_TX1_P 1 2 HDMI_TX1_DP_C
CV504 0.1u_0201_10V6K
7 CPU_HDMI_TX1_P CPU_HDMI_TX1_N HDMI_TX1_DN_C
CV505 1 2 0.1u_0201_10V6K
7 CPU_HDMI_TX1_N CPU_HDMI_TX2_P 1 2 HDMI_TX2_DP_C
CV506 0.1u_0201_10V6K
7 CPU_HDMI_TX2_P CPU_HDMI_TX2_N HDMI_TX2_DN_C
CV507 1 2 0.1u_0201_10V6K
7 CPU_HDMI_TX2_N CPU_HDMI_CLK_P HDMI_CLK_DP_C
CV508 1 2 0.1u_0201_10V6K DV501 EMC@ DV502 EMC@
7 CPU_HDMI_CLK_P CPU_HDMI_CLK_N 1 2 HDMI_CLK_DN_C HDMI_TX1_CON_N 1 1 HDMI_TX1_CON_N HDMI_DET HDMI_DET
7 CPU_HDMI_CLK_N
CV509 0.1u_0201_10V6K 10 9 1 1 10 9
HDMI_TX1_CON_P 2 2 9 8 HDMI_TX1_CON_P DDPB_CLK_U 2 2 9 8 DDPB_CLK_U

HDMI_TX2_CON_N 4 4 7 7 HDMI_TX2_CON_N DDPB_DATA_U 4 4 7 7 DDPB_DATA_U

HDMI_TX2_CON_P 5 5 6 6 HDMI_TX2_CON_P 5 5 6 6

3 3 3 3
HDMI_TX0_DP_C RV504 1 2 470_0402_5%
HDMI_TX0_DN_C RV505 1 2 470_0402_5% 8 8
HDMI_TX1_DP_C RV506 1 2 470_0402_5%
HDMI_TX1_DN_C RV507 1 2 470_0402_5% AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
HDMI_TX2_DP_C RV508 1 2 470_0402_5%
HDMI_TX2_DN_C RV509 1 2 470_0402_5%
HDMI_CLK_DP_C RV510 1 2 470_0402_5%
C HDMI_CLK_DN_C RV511 1 2 470_0402_5% DV503 EMC@ C
HDMI_CLK_CON_P 1 1 10 9 HDMI_CLK_CON_P
HDMI_CRLS_Q
HDMI_CLK_CON_N 2 2 9 8 HDMI_CLK_CON_N
1

D HDMI_TX0_CON_P 4 4 7 7 HDMI_TX0_CON_P
2
+3VS HDMI_TX0_CON_N HDMI_TX0_CON_N
G QV504 5 5 6 6
L2N7002KWT1G_SOT323-3
S 3 3
3

1 2
8
@ RV512
100K_0402_5% AZ1045-04F_DFN2510P10E-10-9

+3VS

+5VS_HDMI
2
G

QV503A
L2N7002KDW1T1G_SOT363-6

2
1
1 6 DDPB_CLK_U RPV501
S

7 CPU_HDMI_DDC_CLK
D

2.2K_0404_4P2R_5%
+5VS_HDMI
B JHDMI1 B

3
4
18 15 DDPB_CLK_U
5

+5V_Power SCL 16 DDPB_DATA_U

G

SDA
HDMI_TX0_CON_P 7
HDMI_TX0_CON_N 9 TMDS_Data0+ 13
4 3 DDPB_DATA_U HDMI_TX1_CON_P 4 TMDS_Data0- CEC 17
S

7 CPU_HDMI_DDC_DATA HDMI_TX1_CON_N TMDS_Data1+ DDC/CEC_Ground HDMI_DET

D

6 19
HDMI_TX2_CON_P 1 TMDS_Data1- Hot_Plug_Detect
QV503B HDMI_TX2_CON_N 3 TMDS_Data2+
TMDS_Data2-
L2N7002KDW1T1G_SOT363-6
8 14
5 TMDS_Data0_Shield Utility
2 TMDS_Data1_Shield
TMDS_Data2_Shield
20
11 GND1 21
HDMI_CLK_CON_P 10 TMDS_Clock_Shield GND2 22
HDMI_CLK_CON_N 12 TMDS_Clock+ GND3 23
TMDS_Clock- GND4

ALLTO_C128AF-K1935-L
+1.8VS ME@

RV501 1 @ 2 0_0402_5%
HDMI_HPD_PWR
2

RV502 1 2
1M_0402_5%

CPU_HDMI_HPD 3 1 HDMI_DET
7 CPU_HDMI_HPD
2

QV502
A LSI1012XT1G_SC-89-3 RV503 A
20K_0402_5%
Recommend 50 ohm nominal trace impedance
with reasonable noise isolation;
1

power supply must be turned off when the CPU power is off

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C HDMI_CONN 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, September 03, 2021 Sheet 50 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_Controller_PortA
Date: Friday, September 03, 2021 Sheet 51 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_MUX_PortA
Date: Friday, September 03, 2021 Sheet 52 of 110
5 4 3 2 1
 5 4 3 2 1

VBUS_P0
+5VALW
+5VALW +5V_TYPEC
+3VALW +3V_TYPEC

RU3 1 @ 2 0_0402_5%

150U_B2_6.3VM_R35M

47U_6.3V_M_X5R_0805_H1.25

0.1u_0201_10V6K
RU1 1 @ 2 0_0402_5% 1
+5VS

10U_0805_25V6K

4.7U_0805_25V6-K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K
@ 1 1 @ 1 1 1 1 1

1
+3VS CU1 + CU2 CU27 CU3 CU4 CU5 CU6 CU7 CU8

RU2 1 @ 2 0_0402_5% RU4 1 @ 2 0_0402_5%

2
2 2 2 2 2 2 2 2

4.7U_0402_6.3V6M

0.1u_0201_10V6K
D D
+5V_TYPEC
1

1
CU9 CU10

2
2 UU2

10U_0603_10V6K

0.1u_0201_10V6K

10U_0603_10V6K
1 @ 1 RTS5467A-GRT_QFN24_4X4

1
0.1u_0201_10V6K
CU22 CU21 CU28 CU29 @ 1 @ 1

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201
1 3 CU19 CU20
VBUS_IN1 VBUS_OUT1

2
2 2 2 4
VBUS_IN2 VBUS_OUT2 2 2
16 17 TYPEC_CC2
VCONN_IN CC2
+3V_TYPEC +3V_TYPEC 5 15 TYPEC_CC1
5V_IN CC1
Type-C current mode selection RU5 1 @ 2 0_0402_5% TYPEC_VBUS_EN 11 23 TYPEC_OCP_N
79 EC_VBUS_EN EN #FLT TYPEC_OCP_N 14
1

@ @
{RP_SEL1,RP_SEL0} 6 22 1
RU13 RU15 2'b00: Standard USB mode. 7 NC1 #ATTD TP5904 @
NC2
47K_0402_5% 47K_0402_5% 2'b01: Standard USB mode. 12
19 NC3 #PLG_ORI
21 1
TP5905 @
2'b10: 1.5A current mode.
2

TYPEC_RP_SEL0 TYPEC_RP_SEL1 24 NC4 20 TYPEC_DBG_N

2'b11: 3A current mode
NC5 #DBG VBUS_P0
EC_RP_SEL0 RU6 1 @ 2 0_0402_5% TYPEC_RP_SEL0 9 10 TYPEC_AUDIO_N
PCB pull selection if not connected to SOC
1

79 EC_RP_SEL0 RP_SEL0 #AUDIO 18 VMON RU9 1 2 69.8K_0402_1%

E-PAD
@ @ EC_RP_SEL1 RU7 1 @ 2 0_0402_5% TYPEC_RP_SEL1 8 VMON 13 TYPEC_REXT 1 2

GND
79 EC_RP_SEL1 RP_SEL1 REXT

1
RU14 RU16 38W DC change 1.5A
47K_0402_5% 47K_0402_5% RU8 RU10
100K_0402_1% 10K_0402_1%

14

25
2

GND1
GND2
GND3
GND4
+3VALW
+3V_TYPEC UU3
C VBUS_P0 JUC1 C
CU25 1 2 0.1U_6.3V_K_X5R_0201 8 7
Chip enable control.High acitve.PCB pulled up if not

GND5
GND6
GND7
GND8
VCC NC
1

@ A1 B12 VBUS_P0
RU17 connected to SOC CU26 1 2 1U_6.3V_M_X5R_0201 GND1 GND4
47K_0402_5% USB20_2_R_P 2 3 USB20_2_P USB30_TX3_CON_P A2 B11 USB30_RX3_CON_P
HSD+ D+ SSTXp1 SSRXp1
Power switch enable pin Note USB20_2_R_N USB20_2_N USB30_TX3_CON_N
+3VALW 6 5 A3 B10 USB30_RX3_CON_N
2

TYPEC_VBUS_EN HSD- D- SSTXn1 SSRXn1

Low Active RU18 mount
A4 B9
1

RU33 1 2 USBSWITCH_EN_N 1 4 Vbus1 Vbus4

High Active RU17 mount OE# GND
RU18 100K_0402_5% TYPEC_CC1 A5 B8
47K_0402_5% CC1 SBU2

1
TS3USB31ERSER_UQFN8_1P5X1P5 USB20_2_CON_P A6 B7 USB20_2_CON_N
Dp1 Dn2
2

USB20_2_CON_N A7 B6 USB20_2_CON_P
1 @ 2 USBSWITCH_EN 2 QU1 1/16W_220K_5%_0402 2 1 RU39 USB30_RX3_CON_N Dn1 Dp2
79,84,93 EC_ON_PCH 2 1 USB30_RX3_CON_P A8 B5 TYPEC_CC2
SSM3K15AMFV_2-1L1B 1/16W_220K_5%_0402 RU40
RU34 0_0402_5% 1/16W_220K_5%_0402 2 1 RU41 USB30_RX2_CON_N SBU1 CC2

3
1/16W_220K_5%_0402 2 1 RU42 USB30_RX2_CON_P A9 B4
Vbus2 Vbus3
+3V_TYPEC USB30_RX2_CON_N A10 B3 USB30_TX2_CON_N
SSRXn2 SSTXn2
+3V_TYPEC USB30_RX2_CON_P A11 B2 USB30_TX2_CON_P
1

USB30_RX3_CMC_N CU11 1 2 0.33U_25V_K_X5R_0402 USB30_RX3_CON_N SSRXp2 SSTXp2

USB30_RX3_CMC_P CU12 1 2 0.33U_25V_K_X5R_0402 USB30_RX3_CON_P A12 B1

GND10
GND2 GND3

GND9
RU19 USB30_TX3_CMC_N CU13 1 2 0.1U_25V_K_X5R_0402 USB30_TX3_CON_N
47K_0402_5% RU11 1 @ 2 47K_0402_5% TYPEC_DBG_N USB30_TX3_CMC_P CU14 1 2 0.1U_25V_K_X5R_0402 USB30_TX3_CON_P
2

TYPEC_OCP_N RU12 1 @ 2 47K_0402_5% TYPEC_AUDIO_N USB30_RX2_CMC_N CU15 1 2 0.33U_25V_K_X5R_0402 USB30_RX2_CON_N ATOB_066-12A1-3211

GND6
GND5
USB30_RX2_CMC_P CU16 1 2 0.33U_25V_K_X5R_0402 USB30_RX2_CON_P ME@
1

USB30_TX2_CMC_N CU17 1 2 0.1U_25V_K_X5R_0402 USB30_TX2_CON_N

@ USB30_TX2_CMC_P CU18 1 2 0.1U_25V_K_X5R_0402 USB30_TX2_CON_P
RU20
47K_0402_5%
2

USB20_2_P RU21 1 @ 2 0_0201_5% USB20_2_R_P

B 14 USB20_2_P USB20_2_N USB20_2_R_N B
USB20_2_N RU22 1 @ 2 0_0201_5%
14
LU5 EMC@
USB20_2_R_P 1 2 USB20_2_CON_P
1 2

USB20_2_R_N 4 3 USB20_2_CON_N
4 3
EXC24CH900U_4P

2021/08/30
DU1 EMC@ DFC Request
USB30_TX3_CMC_P 10 1 USB30_TX3_CMC_P
NC1 Line-1 VBUS_P0 USB20_2_CON_P
USB30_TX3_CMC_N 9 2 USB30_TX3_CMC_N USB20_2_CON_N
NC2 Line-2
1

USB30_RX2_CMC_N 7 4 USB30_RX2_CMC_N
NC3 Line-3
AZ5725-01F.R7GR_DFN1006P2X2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
1

USB30_RX2_CMC_P 6 5 USB30_RX2_CMC_P USB30_TX3_N RU25 1 @ 2 0_0402_5% USB30_TX3_CMC_N USB30_TX2_N RU29 1 @ 2 0_0402_5% USB30_TX2_CMC_N
NC4 Line-4 DU3 DU4 DU5 14 USB30_TX3_N 14 USB30_TX2_N
3 EMC@ EMC@ EMC@
GND1 USB30_TX3_P RU26 1 @ 2 0_0402_5% USB30_TX3_CMC_P USB30_TX2_P RU30 1 @ 2 0_0402_5% USB30_TX2_CMC_P
14 USB30_TX3_P 14 USB30_TX2_P
2

8
GND2
2

AZ1143-04F-R7G_DFN2510P10E10
USB30_RX2_P RU31 1 @ 2 0_0402_5% USB30_RX2_CMC_P
USB30_RX3_P 1 @ 2 0_0402_5% USB30_RX3_CMC_P 14 USB30_RX2_P
RU27
14 USB30_RX3_P
DU2 EMC@ USB30_RX2_N RU32 1 @ 2 0_0402_5% USB30_RX2_CMC_N
USB30_TX2_CMC_P 10 1 USB30_TX2_CMC_P USB30_RX3_N 1 @ 2 0_0402_5% USB30_RX3_CMC_N 14 USB30_RX2_N
RU28
NC1 Line-1 14 USB30_RX3_N
USB30_TX2_CMC_N 9 2 USB30_TX2_CMC_N
NC2 Line-2
USB30_RX3_CMC_N 7 4 USB30_RX3_CMC_N TYPEC_CC2 TYPEC_CC1
NC3 Line-3
1

A USB30_RX3_CMC_P 6 5 USB30_RX3_CMC_P A
NC4 Line-4
AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
1

220P_25V_K_X7R_0201

3 1 1
GND1
220P_25V_K_X7R_0201

DU6 CU23 DU7 CU24

8 EMC@ EMC_NS@ EMC@ EMC_NS@
GND2
2 2
2

AZ1143-04F-R7G_DFN2510P10E10
2

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_CONN_PortA
Date: Friday, September 03, 2021 Sheet 53 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_Controller_PortB
Date: Friday, September 03, 2021 Sheet 54 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_MUX_PortB
Date: Friday, September 03, 2021 Sheet 55 of 110
5 4 3 2 1
 5 4 3 2 1

USBC_VBUS20 USBC_VBUS20 59,60

2021/08/19
SM01000L000 to SM01003110J

EMC@
USBC_VBUS20 L5607 1 2 2021/07/07
MPZ1608S300AT_2P~D EMC Request to Add
D D
EMC@
L5606 1 2 USBC_VBUS20_CONN
MPZ1608S300AT_2P~D

1
18P_0402_50V8J

10P_50V_F_NPO_0402

1000P_50V_J_COG_0402

100P_50V_J_X7R_0402

100P_50V_J_X7R_0402

UCLAMP2271P.TNT SGP1610N2
RF@ 1 RF@ 1 EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 1 EMC_NS@

1
1000P_50V_J_COG_0402
C5614 C5613 C5601 C5603 C5604 C5602 D5615

4
3
2
1
EMC@

NC3
NC2
NC1
D5616

Vbus
2 2 2 2 2 2 SP1224-01UTG_UDFN-6

2
2

GND1
GND2
GND3
GND4
5
6
7
8

GND1
GND2
GND3
GND4
JUSBC1

GND5
GND6
GND7
GND8
A1 B12
GND1 GND4
USBC_TX1P_CONN A2 B11 USBC_RX1P_CONN
SSTXp1 SSRXp1
USBC_TX1N_CONN A3 B10 USBC_RX1N_CONN
SSTXn1 SSRXn1
A4 B9
Vbus1 Vbus4
A5 B8 USBC_SBU2
59 USBC_CC1 CC1 SBU2 USBC_SBU2 59
USBC_USB2P_CONN A6 B7 USBC_USB2N_CONN
Dp1 Dn2
USBC_USB2N_CONN A7 B6 USBC_USB2P_CONN
Dn1 Dp2
C USBC_SBU1 A8 B5 USBC_CC2 C
59 USBC_SBU1 SBU1 CC2 USBC_CC2 59
A9 B4
Vbus2 Vbus3
USBC_RX2N_CONN A10 B3 USBC_TX2N_CONN
SSRXn2 SSTXn2
USBC_RX2P_CONN A11 B2 USBC_TX2P_CONN
SSRXp2 SSTXp2
A12 B1

GND10
GND2 GND3

GND9
2021/08/30
ATOB_066-12A1-3211

GND6
GND5
ME@
R8415 1 @ 2 0_0402_5% USBC_TX1N_C
7 TCP1_TX0_DN

R8416 1 @ 2 0_0402_5% USBC_TX1P_C

7 TCP1_TX0_DP
AC Cap Close to Connector
USBC_TX1N_C C5606 1 2 0.1U_35V_K_X5R_0201 USBC_TX1N_CONN R8417 1 @ 2 0_0402_5% USBC_TX2P_C
USBC_TX1P_C USBC_TX1P_CONN 7 TCP1_TX1_DP
C5607 1 2 0.1U_35V_K_X5R_0201
USBC_TX2P_C C5608 1 2 0.1U_35V_K_X5R_0201 USBC_TX2P_CONN
USBC_TX2N_C C5609 1 2 0.1U_35V_K_X5R_0201 USBC_TX2N_CONN R8418 1 @ 2 0_0402_5% USBC_TX2N_C
7 TCP1_TX1_DN

USBC_RX1N_C C5610 1 2 0.33U_25V_K_X5R_0201 USBC_RX1N_CONN R8419 1 @ 2 0_0402_5% USBC_RX1N_C

USBC_RX1P_C 1 2 USBC_RX1P_CONN 7 TCP1_RX0_DN
C5611 0.33U_25V_K_X5R_0201
USBC_RX2P_C C5612 1 2 0.33U_25V_K_X5R_0201 USBC_RX2P_CONN D5601 EMC@ D5609 EMC@
USBC_RX2N_C C5605 1 2 0.33U_25V_K_X5R_0201 USBC_RX2N_CONN R8420 1 @ 2 0_0402_5% USBC_RX1P_C
USBC_TX1P_C USBC_RX1P_C 7 TCP1_RX0_DP
1 2 2 1
1 2 2 1

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 R8421 1 @ 2 0_0402_5% USBC_RX2P_C

7 TCP1_RX1_DP
R5601 R5602 R5603 R5604 D5602 EMC@ D5610 EMC@
1

B USBC_TX1N_C USBC_RX1N_C @ USBC_RX2N_C B

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%

1 2 2 1 R8422 1 2 0_0402_5%
1 2 2 1 7 TCP1_RX1_DN

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
D5603 EMC@ D5611 EMC@
2

USBC_CC2 1 2 2 1 USBC_SBU1
1 2 2 1
L5605 EMC@
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 1 2 USBC_USB2P_CONN
14 USBC_USB2P 1 2
D5604 EMC@ D5605 EMC@

USBC_USB2P_CONN 1 2 2 1 USBC_USB2N_CONN 4 3 USBC_USB2N_CONN

1 2 2 1 14 USBC_USB2N 4 3

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 EXC24CH900U_4P

D5606 EMC@ D5612 EMC@

USBC_SBU2 1 2 2 1 USBC_CC1
1 2 2 1

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
D5607 EMC@ D5613 EMC@

USBC_SBU2 R5613 1 @ 2 1/20W_2M_5%_0201 USBC_RX2N_C 1 2 2 1 USBC_TX2N_C

USBC_SBU1 R5614 1 @ 2 1/20W_2M_5%_0201 1 2 2 1

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
D5608 EMC@ D5614 EMC@

USBC_RX2P_C 1 2 2 1 USBC_TX2P_C
1 2 2 1

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

TABLE of EMC TVS (D6301~D6314)

A
Vendor LCFC P/N Description A

NXP SC400008300 S DIO_ESD PESD5V0H1BSF SOD962

AMAZING SC400009F00 S DIO_ESD AZ5B6S-01B.R7G CSP0603P2Y

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_CONN_PortB FULL
Date: Friday, September 03, 2021 Sheet 56 of 110
5 4 3 2 1
 A B C D E

Close to USB Conn

+USB_VCCA
+5VALW +USB_VCCA
Current Limit Target:
1 1
2.3A(2.1-2.45A)
1 1
@
U5701 CU602 CU603
1 12 100U_1206_6.3V6M 1U_0402_16V6K
IN OUT 10 USB20_4_P_AOU 2 2
USB20_4_P 3 DP_IN 11 USB20_4_N_AOU
14 USB20_4_P USB20_4_N DP_OUT DM_IN
2 14
14 USB20_4_N DM_OUT GND

9 -AOU_IFLG -AOU_IFLG 79
STATUS#
4
USB_OC2_N 13 ILIM_SEL
7 USB_OC2_N USB_ON2 FAULT# +USB_VCCA
79 USB_ON2 5
EN 15 U6901_ILIM_LO R5701 1 2 1/16W_2.7M_5%_0402
AOU_SEL1 6 ILIM_LO 16 U6901_ILIM_HI R5702 1 2 22.1K_0402_1%
79 AOU_SEL1 CLT1 ILIM_HI JUA1
7
AOU_SEL2 8 CLT2 17
79 AOU_SEL2 CLT3 GND_Pad USB30_TX1_CON_P 9
SN1702001RTER_WQFN16_3X3 1 StdA_SSTX+
1 VBUS
@ USB30_TX1_CON_N 8
C5701 USB20_4_CON_P 3 StdA_SSTX-
0.1u_0201_10V6K 7 D+
2 USB20_4_CON_N 2 GND_DRAIN 10
USB30_RX1_CON_P 6 D- GND_2 11
4 StdA_SSRX+ GND_3 12
USB30_RX1_CON_N 5 GND_1 GND_4 13
StdA_SSRX- GND_5

ALLTO_C19043-10905-L
ME@

TABLE of POWER SWITCH (U5701)

2
Vendor LCFC P/N Description 2

TI SA00008HF00 S IC SN1702001RTER WQFN 16P USB CHARGING

DIODES SA00009D800 S IC PI5USB2546HZHEX TQFN 16P CONTROLLER

2021/08/30
DU601 EMC@
USB30_RX1_CON_N 10 1 USB30_RX1_CON_N
NC1 Line-1
USB30_RX1_CON_P 9 2 USB30_RX1_CON_P
NC2 Line-2
LU601 EMC@ USB30_TX1_CON_N 7 4 USB30_TX1_CON_N
USB30_RX1_N RU603 1 @ 2 0_0402_5% USB30_RX1_CON_N USB20_4_N_AOU 1 2 USB20_4_CON_N NC3 Line-3
14 USB30_RX1_N 1 2 USB30_TX1_CON_P USB30_TX1_CON_P
6 5
NC4 Line-4
USB30_RX1_P RU604 1 @ 2 0_0402_5% USB30_RX1_CON_P USB20_4_P_AOU 4 3 USB20_4_CON_P 3
14 USB30_RX1_P 4 3 GND1
EXC24CH900U_4P 8
GND2
AZ1143-04F-R7G_DFN2510P10E10

CU605 0.1U_6.3V_K_X5R_0201
3 USB30_TX1_N 1 2 USB30_TX1_C_N RU605 1 @ 2 0_0402_5% USB30_TX1_CON_N 3
14 USB30_TX1_N USB20_4_CON_P
+USB_VCCA
USB30_TX1_P 1 2 USB30_TX1_C_P RU606 1 @ 2 0_0402_5% USB30_TX1_CON_P USB20_4_CON_N
14 USB30_TX1_P
CU604 0.1U_6.3V_K_X5R_0201

2
AZ5725-01F.R7GR_DFN1006P2X2

AZ5515-02FPR7GR_DFN1006P3X
DU602 DU603

1
EMC@ EMC@

2
2

3
4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. USBA_PortA
Date: Friday, September 03, 2021 Sheet 57 of 110
A B C D E
 5 4 3 2 1

D D

USB2.0 PORT
+5VALW

C C
1
CU401 +USB_VCCB
1U_6.3V_M_X5R_0201
2 UU401
5 1
IN OUT
2
GND
EC_USB_ON_N 4 3 USB_OC1_N
79 EC_USB_ON_N ENB OCB USB_OC1_N 7
SY6288D20AAC_SOT23-5

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. USBA_PortB
Date: Friday, September 03, 2021 Sheet 58 of 110
5 4 3 2 1
 5 4 3 2 1

+3VSUS

USBC_VBUS20 USBC_VBUS20 56,60

VCC3_LDO_PD VCC3_LDO_PD 60

5V_IN 5V_IN 60

2
USBC_VBUS20 USBC_VBUS20_RC 5V_IN 5V_IN

G
R5920 1 2 4.7_1206_5%
D PD_SUPER_CLK D
1 6

S
11 PCH_SML1_CLK

D
2021/07/06
@ Q5901A

0.1U_35V_K_X5R_0201
1 1 1 1 L2N7002KDW1T1G_SOT363-6

4.7U_25V_K_X5R_0805_H0.85

10U 6.3V M X5R 0402

0.1u_0201_10V6K
C5909 C5910 C5901 C5902
R5926 1 @ 2 0_0402_5%
2 2 2 2

5
G
11 4 3 PD_SUPER_DATA

S
PCH_SML1_DATA

D
Slave Addr R5917 5% R5916 5% @ Q5901B
L2N7002KDW1T1G_SOT363-6
Addr0:0xCC NC 10K <0.2V
1 @ 2 0_0402_5%
addr1:0xCE 75K 10K >=0.2V&&<0.6V 2021/07/06 R5927

addr2:0xD0 33K 10K >=0.6V&&<1.0V +3VL VCC3_LDO_PD VCC3_LDO_PD VCC3_LDO_PD

10U 6.3V M X5R 0402

2021/07/01 1

C5908
addr3:0xD2 10K 10K >=1.0V

2
2

4.7U_10V_K_X5R_0603
C5903

0.1U_6.3V_K_X5R_0201
C5913
@ @ 1 1

1
R5922 R5923
VCC3_LDO_PD 0_0201_5% 0_0201_5% R8434
47K_0402_5%

1
2 2

1/20W_4.7K_5%_0201
R5924

1/20W_4.7K_5%_0201
R5925
@ @

1
1

1
100K_0201_5%
R5912

100K_0201_5%
R5921

1/20W_4.7K_5%_0201
R5909

1/20W_4.7K_5%_0201
R5908

1/20W_4.7K_5%_0201
R5907

33

31

32

11
C @ @ @ @ U5901 C

2
VBUS_IN

VCONN_IN
5V_IN
3V3_OUT
2

2
ADDR_CFG 26 9 U5901_DB_CFG
LOC_PWR_MON 28 ADDR_CFG/MGPIO17 DB_CFG 17 VBCAP R5918 1 2 1/8W_2.2_5%_0805 VBCAP_C
VMON_PD 29 LOC_PWR_MON/MGPIO16 VBCAP 10 USBC_CC1
-SRC_PS_FLT VMON/MGPIO14 CC1 USBC_CC2 USBC_CC1 56
27 12
60 -SRC_PS_FLT DDIP1_AUXP_C IMON/MGPIO15 CC2 USBC_SBU1 USBC_CC2 56

0.1U_35V_K_X5R_0201
C5911

1/20W_100_5%_0201
R5902
C5905 1 2 0.1u_0201_10V6K 14 16 1 @
7 TCP1_AUX_DP AUX_P/MGPIO8 SBU1/MGPIO10 USBC_SBU1 56

1
C5904 1 2 0.1u_0201_10V6K DDIP1_AUXN_C 13 15 USBC_SBU2
7 TCP1_AUX_DN DDIP1_HPD_R AUX_N/MGPIO9 SBU2/MGPIO11 USBC_SBU2 56
R5928 1 @ 2 0_0201_5% 2 23
7 DDIP1_HPD SNK_PS_ACK 18 HPD/GPIO3 C_DP_A/MGPIO0 22
60 SNK_PS_ACK 19 H_DP/MGPIO4 C_DM_A/MGPIO1 21 2
25 H_DM/MGPIO5 C_DP_B/MGPIO2 20

2
24 BB_DP C_DM_B/MGPIO3 34 PD_GPIO21
R8209 1 2 0_0402_5% EC_SMB_CK0_C 3 BB_DM GPIO21 35 SRC_PS_EN
79 EC_SMB_CK0 EC_SMB_DA0_C SCL1/GPIO4 GPIO20 SRC_PS_EN 60
R8210 1 2 0_0402_5% 4 38
79 EC_SMB_DA0 -PD_I2C_INT_C SDA1/GPIO5 SCL4/GPIO13
79 -PD_I2C_INT R8211 1 2 0_0402_5% 5 37
-SNK_PS_EN 6 INT1/GPIO6 SDA4/GPIO14 36 PD_GPIO15 1
60 -SNK_PS_EN SCL2/GPIO7 INT4/GPIO15 @ TP5901
7 1 PD_SUPER_CLK_C R8212 1 2 0_0402_5% PD_SUPER_CLK
VBUS_DSCHG 8 SDA2/GPIO8 SCL3/GPIO10 40 PD_SUPER_DATA_C R8213 1 2 0_0402_5% PD_SUPER_DATA
U5901_REXT 30 INT2/GPIO9 SDA3/GPIO11 39 PCH_PMC_ALERT R8214 1 2 0_0402_5%
@ PCH_PMC_ALERT_N 17
REXT INT3/GPIO12
1

220P_0402_50V_X7R_0402
C5906

220P_0402_50V_X7R_0402
C5907
@ 1
TP5902
1

EPAD
R5929 1 1
100K_0402_5% R5905
100K_0201_5% R5913
2

1/16W_6.2K_1%_0402 RTS5457V-GR_QFN40_5X5

41
2

2 2
SA0000ACME0
2

B B

USBC_VBUS20

VCC3_LDO_PD +5VALW USBC_VBUS20

1
R5915
1

150_0603_1%
@ 2
R5917 R5903 R5904 H_PROCHOT_N
10K_0201_5% 1/20W_200K_1%_0201 1/20W_200K_1%_0201 10,20,79,93 H_PROCHOT_N
1

1
D D
2

ADDR_CFG LOC_PWR_MON VMON_PD VBUS_DSCHG 2 Q5902 PD_GPIO21 2 @

G L2N7002KWT1G_SOT323-3 G Q5903 1
1

1
L2N7002KWT1G_SOT323-3 @
S @ S C8207
3

3
1

R5916 R5910 R5911 R5919 47P_0402_50V8J

10K_0201_5% 10K_0201_1% 10K_0201_1% 100K_0201_5% 2
R5914
2

2
100K_0402_5%
2

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PD CONTROLLER(RTS5457U)
Date: Friday, September 03, 2021 Sheet 59 of 110
5 4 3 2 1
 5 4 3 2 1

USBC_VBUS20 USBC_VBUS20 56,59

VCC3_LDO_PD VCC3_LDO_PD 59 +5VALW 5V_IN

5V_IN 5V_IN 59

R6001 1 2 0_0402_5%

D 2021/07/07 D

D
3 1
@

1
Q6002
@ AO3413_SOT23-3

G
2
R6011
100K_0201_5%

2
JIWAWA

1
D
R6002 1 @ 2 0_0201_5% MA2JISI 2 @
79 PD_VBUS_C_CTRL1
G Q6001
1 L2N7002KWT1G_SOT323-3 1
@ S @

3
C6001 C6002
0.1U_25V_K_X7R_0402 0.1U_25V_K_X7R_0402
2 2

C C
2021/07/07
For GCM Request

VCC3_LDO_PD

USBC_VBUS20

VCC3_LDO_PD

1
R6005 J6001

1
10K_0402_1% JUMP_43X118
3A

2
2

1
2
U6001 R6008 R6009
59 SRC_PS_EN 4 3 -SRC_PS_FLT 10K_0201_5% 10K_0201_5%
SRC_PS_EN EN OCB -SRC_PS_FLT 59

2
+5VALW R6003 1 2 2K_0402_1% 5 2
ISET GND
6 1 USBC_VBUS20_J R6007 1 @ 2 1M_0402_5%
IN OUT

SY6863B3ABC_SOT23-6 U6002
VINT20_IN

1
@ B2 B3
J6002 C2 VBUS1 OVLO A2 SNK_PS_ACK

1
VBUS2 ACK SNK_PS_ACK 59
1

22U_10V_M_X5R_0603

22U_10V_M_X5R_0603

22U_10V_M_X5R_0603

22U_10V_M_X5R_0603

1U_25V_K_X5R_0402

C8213 1 C6003 1 C8211 1 C8212 1 C6004 1 1 JUMP_43X118 D2

C6006 E1 VBUS3 C3
VBUS4 GND1

2
R6004 4.7U_25V_M_X5R_0402 E2 D3
100K_0201_5% VBUS5 GND2 E3

2
2 2 2 2 2 2 A1 GND3
2

B1 VINT1 A3 -SNK_PS_EN 59
B VINT2 EN# -SNK_PS_EN B
C1
D1 VINT3
VINT4

1
@
NX20P5090UK_WLCSP15 R6012 R6010
100K_0201_5% 0_0402_5%

2
1 1
C6007 C6008
1U_25V_K_X5R_0402 4.7U_25V_M_X5R_0402
2 2

TABLE of Type-C Load Switch (U6001)

Vendor LCFC P/N P/N TABLE of TypeC Load Switch (U6002)
SILERGY SA0000A7100 S IC SY6863B3ABC SOT23 6P POWER SWITCH Vendor LCFC P/N P/N
DIODES SA0000BE100 S IC AP22615AWU-7 TSOT26 6P POWER SWITCH NXP SA00007JY00 NX20P5090UKAZ
FORTUNE SA0000BU600 S IC FA7626AA6R SOT-23 6P LOAD SWITCH KINETIC SA00009G700 KTS1677EVH-TR

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PD_DCIN
Date: Friday, September 03, 2021 Sheet 60 of 110
5 4 3 2 1
 5 4 3 2 1

HDD Power
D D
2021/07/13
+5VS +5VS_HDD RF Request to Add

JK1
1 2
1 2

22U_10V_M_X5R_0603

22U_10V_M_X5R_0603

10U_0603_10V6K

0.1u_0201_10V6K

33P_0402_50V8J

33P_0402_50V8J
JUMP_43X39 @ 1 @ 1 SATA@1 SATA@1 RF@ 1 RF@ 1
CK1 CK2 CK4 CK5 CK6 CK7

2 2 2 2 2 2

C C

SATA_PTX_DRX0_P RK1 1 @ 2 0_0201_5% SATA_PTX_DRX0_R_P SATA@ CK8 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX0_CON_P

14 SATA_PTX_DRX0_P @
SATA_PTX_DRX0_N RK2 1 2 0_0201_5% SATA_PTX_DRX0_R_N SATA@ CK9 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX0_CON_N
14 SATA_PTX_DRX0_N @
SATA_PRX_DTX0_N RK3 1 2 0_0201_5% SATA_PRX_DTX0_R_N SATA@ CK10 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX0_CON_N
14 SATA_PRX_DTX0_N SATA_PRX_DTX0_P RK4 1 @ 2 0_0201_5% SATA_PRX_DTX0_R_P SATA@ CK11 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX0_CON_P
14 SATA_PRX_DTX0_P

2021/07/06
Connector PN from SP01001WV00 to SP01002MB00

+5VS_HDD JHDD1
1
2 1
3 2
4 3
SATA_PRX_DTX0_CON_P 5 4
SATA_PRX_DTX0_CON_N 6 5
B B
7 6
SATA_PTX_DRX0_CON_N 8 7
SATA_PTX_DRX0_CON_P 9 8 11
10 9 GND1 12
10 GND2
HIGHS_FC5AF101-2933-1H
ME@

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HDD
Date: Friday, September 03, 2021 Sheet 61 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ODD
Date: Friday, September 03, 2021 Sheet 62 of 110
5 4 3 2 1
 5 4 3 2 1

+3VS
+3VS_SSD

RK201 1 @ 2 0_5%_0603

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

0.1U_10V_K_X7R_0402
1 @ 1 1 @ 1
D CK209 CK210 CK211 CK212 D

2 2 2 2

+3VS_SSD

JSSD1

1 2
3 GND_1 3.3V_1 4
PCIE4_L3_RXN 5 GND_2 3.3V_2 6
14 PCIE4_L3_RXN PCIE4_L3_RXP PERN3 N/C_2 +3VS_SSD
7 8
14 PCIE4_L3_RXP 9 PERP3 N/C_3 10
CK201 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L3_TXN_C 11 GND_3 DAS/DSS# 12
14 PCIE4_L3_TXN 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L3_TXP_C 13 PETN3 3.3V_3 14 SSD_CLKREQ0_N 1 2 10K_0201_5%
CK202 RC207
14 PCIE4_L3_TXP 15 PETP3 3.3V_4 16
PCIE4_L2_RXN 17 GND_4 3.3V_5 18
14 PCIE4_L2_RXN PCIE4_L2_RXP 19 PERN2 3.3V_6 20
14 PCIE4_L2_RXP PERP2 N/C_4
21 22
CK203 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L2_TXN_C 23 GND_5 N/C_5 24
14 PCIE4_L2_TXN PETN2 N/C_6

2
CK204 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L2_TXP_C 25 26 @
14 PCIE4_L2_TXP PETP2 N/C_7
27 28 RK203
C GND_6 N/C_8 C
PCIE4_L1_RXN_C 29 30 10K_0201_5%
14 PCIE4_L1_RXN PCIE4_L1_RXP_C PERN1 N/C_9
31 32
14 PCIE4_L1_RXP 33 PERP1 N/C_10 34

1
CK205 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L1_TXN_C 35 GND_7 N/C_11 36
14 PCIE4_L1_TXN PETN1 N/C_12
CK206 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L1_TXP_C 37 38 PCH_SATA_DEVSLP1_R RK204 2 @ 1 0_0402_5%
14 PCIE4_L1_TXP 39 PETP1 DEVSLP 40 PCH_SATA_DEVSLP1 14
PCIE4_L0_RXN 41 GND_8 N/C_13 42
14 PCIE4_L0_RXN PCIE4_L0_RXP 43 PERN0/SATA-B+ N/C_14 44
14 PCIE4_L0_RXP 45 PERP0/SATA-B- N/C_15 46
CK207 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L0_TXN_C 47 GND_9 N/C_16 48
14 PCIE4_L0_TXN 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L0_TXP_C 49 PETN0/SATA-A- N/C_17 50 SSD_PLT_RST_N 1 @ 2 0_0402_5%
CK208 RK205
14 PCIE4_L0_TXP PETP0/SATA-A+ PERST# SSD_CLKREQ_Q_N PLT_RST_N 17,71,78,79,82
51 52 RK206 1 2 0_0402_5% SSD_CLKREQ0_N 16
CLK_PCIE_SSD_N 53 GND_10 CLKREQ# 54 PEWAKE# 1
16 CLK_PCIE_SSD_N REFCLKN PEWAKE# TK201 @ @
CLK_PCIE_SSD_P 55 56
16 CLK_PCIE_SSD_P REFCLKP N/C_18
57 58
GND_11 N/C_19
+3VS_SSD

67 68
69 N/C_1 SUSCLK 70
RK202 1 @ 2 0_0402_5% 71 PEDET 3.3V_7 72
14 -SSD_DTCT GND_12 3.3V_8

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201
73 74 1 1
75 GND_13 3.3V_9 CK214 CK213
GND_14
B B
77 76
PEG1 PEG2 2 2

ARGOSY_NASM0-S6710-TS20
ME@

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. SSD
Date: Friday, September 03, 2021 Sheet 63 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EMMC
Date: Friday, September 03, 2021 Sheet 64 of 110
5 4 3 2 1
 5 4 3 2 1

D
FP Power Control D

+3VL FP_PWR

R8427 1 @ 2 0_0402_5%

FPR_PWR_OUT RI5 1 @

D
3 1 2 0_0201_5%
FP@
QI3 FP@

1
+3VL LP2301ALT1G_SOT-23-3 CI2

G
2
1 1@ 0.1u_0201_10V6K

1
FP@ CI3

2
FP@ CI1 0.1U_6.3V_K_X5R_0201
RI2 0.047U_0402_16V_X7R_0402
1/20W_200K_5%_0201 2 2

2
RI4 1 @ 2 0_0201_5% FPR_PWR_EN_R 1 @ 2 FPR_PWR_EN

FPR_PWR_EN_N RI6

1
0_0201_5%
C
FP@ 1@ C
RI3 CI4
100K_0201_5% 0.1U_6.3V_K_X5R_0201

2
2

FP_PWR

1
FP@
79 FPR_PWR_EN 2 QI1 FP@
SSM3K15AMFV_2-1L1B RI7
330_0402_1%

3
1

1 2
FP@
RI1
100K_0201_5% FP@
QI2
2

FPR_PWR_EN_N_R 2 SSM3K15AMFV_2-1L1B

3
B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FPR
Date: Friday, September 03, 2021 Sheet 65 of 110
5 4 3 2 1
 5 4 3 2 1

Note: DVDD-IO must be equal to or smaller than DVDD

DVDD_IO
+3VALW +3VS DVDD

DVDD_IO
RA3 1 @ 2 0_0402_5% RA1 1 @ 2 0_0402_5% +1.8V_AUDIO
DVDD +5VD +5VA

10U 6.3V M X5R 0402

+1.8VALW

2.2U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
CA3 1 CA6 1 CA4 2 CA5 1

+5VD
D D

0.1U_6.3V_K_X5R_0201

2.2U_0402_6.3V6M
+5VA
2 2
CA1 CA2
RA6 1 @ 2 0_0402_5%
2 2 1 2
1 1

18

46

41

40

20
3
UA1

DVDD

PVDD2

PVDD1

AVDD1

CPVDD/AVDD2
DVDD-IO
2 SPKR_MUTE_N RA16 1 @ 2 0_0402_5% EC_MUTE_N
PDB EC_MUTE_N 79
14 HDA_BITCLK_AUDIO
67 HPOUT_L HPOUT_L 27 BCLK HDA_BITCLK_AUDIO 13
HPOUT-L 15 HDA_SYNC_AUDIO
HPOUT_R SYNC HDA_SYNC_AUDIO 13
26
67 HPOUT_R HPOUT-R 47 RA7 2 @ 1 100K_0402_1%
+5VS +5VA MIC2_VREFOL JD2 +3VS
28
+5VS +5VD 69 MIC2_VREFOL MIC2-VREFO-L 48 JSENSE RA8 1 @ 2 0_0402_5% PLUG_IN
MIC2_VREFOR 29 JD1 PLUG_IN 69
69 MIC2_VREFOR MIC2-VREFO-R
RA11 1 @
Note: need to configuration 1*JD mode by verb table
2 0_0402_5% LA1 1 2 1
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
EMC@ BLM15PD600SN1D_2P 4 DMIC_DATA_R RA9 1 2 0_0402_5% CODEC_DMIC_DAT
@ @
GPIO0/DMIC-DATA12 CODEC_DMIC_DAT 47
0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

CA8 1 CA9 2 CA10 1 CA11 CA12 1 CA13 1 RING2_CONN 30

1 69 RING2_CONN MIC2-L/RING2
RA13 1 @ 2 5 DMIC_CLK_R RA10 1 @ 2 0_0402_5% CODEC_DMIC_CLK
GPIO1/DMIC-CLK

0.1U_6.3V_K_X5R_0201
RING3_CONN CODEC_DMIC_CLK 47

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201
10U 6.3V M X5R 0402
31
1/10W_0_5%_0603 69 RING3_CONN MIC2-R/SLEEVE 6
2 1 2 2 2 2 PC_BEEP 34 I2C-DATA
PCBEEP 7
I2C-CLK
+5VA
8
RA12 1 2 10K_0402_5% VDD_STB 33 NC1
5VSTB 9
LINE2-R 35 NC2
69 LINE2-R LINE2-R 10
LINE2-L 36 NC3
C C
69 LINE2-L LINE2-L 11
NC4
12
NC5

CA14 1 2 1U_6.3V_M_X5R_0201 CBP 23 45 SPK_R+

CBP SPK-OUT-R+ SPK_R+ 69
CBN 24 44 SPK_R-
CBN SPK-OUT-R- SPK_R- 69
43 SPK_L-
+1.8VS +1.8V_AUDIO SPK-OUT-L- SPK_L- 69
42 SPK_L+
2.2U_0402_6.3V6M 2 1 CA15 MIC2-CAP 32 SPK-OUT-L+ SPK_L+ 69
RA2 1 @ 2 0_0402_5% MIC2-CAP 13
2.2U_0402_6.3V6M 2 1 CA16 VREF 38 DC DET/EAPD
VREF
2.2U_0402_6.3V6M 1 2 CA17 LDO3-CAP 19 16 SDATA_IN RA14 2 1 33_0402_5% HDA_SDIN0
LDO3-CAP SDATA-IN HDA_SDIN0 13
2.2U_0402_6.3V6M 1 2 CA18 LDO2-CAP 21 17 HDA_SDOUT_AUDIO
LDO2-CAP SDATA-OUT HDA_SDOUT_AUDIO 13
2.2U_0402_6.3V6M 1 2 CA19 LDO1-CAP 39
LDO1-CAP 25 CPVEE
CPVEE

Thermal Pad
2
CA20

AVSS1

AVSS2
1U_6.3V_M_X5R_0201
1

ALC3287-CG_MQFN48_6X6

37

22

49
RA88 CA93
EC_SPKR 1 2 4.7K_0402_5% 1 2 0.1U_6.3V_K_X5R_0201
79 EC_SPKR

RA18 CA94 CA22

PCH_BEEP 1 2 4.7K_0402_5% 1 2 0.1U_6.3V_K_X5R_0201 PC_BEEP1_R 1 2 0.1U_6.3V_K_X5R_0201 PC_BEEP
12 PCH_BEEP
1

B B

@
RA19
10K_0402_5%
2

RA21 1 @ 2 0_0402_5%

RA26 1 @ 2 0_0402_5%

HPOUT_L RA27 1 @ 2 0_0402_5%

CODEC_DMIC_CLK
HPOUT_R RA29 1 @ 2 0_0402_5%
HDA_SYNC_AUDIO CODEC_DMIC_DAT
EMC_NS@ EMC_NS@
1000P 25V K X7R 0201

1000P 25V K X7R 0201

HDA_SDOUT_AUDIO EMC_NS@ EMC_NS@ CA91 1 CA92 1

100P 25V J NPO 0201

100P 25V J NPO 0201

RA28 EMC_NS@ CA31 1 CA32 1 EMC_NS@ RA83 1 2 0_0402_5%

HDA_BITCLK_AUDIO_R 1 2 HDA_BITCLK_AUDIO EMC_NS@ RA84 1 2 0_0402_5%

1/16W_27_5%_0402 HDA_SDIN0 2 2
EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@ 2 2
22P_0201_258J

22P_0201_258J

33P_50V_J_NPO_0201

33P_50V_J_NPO_0201

CA33 1 CA34 1 CA35 1 CA36 1

2 2 2 2
GND GNDA

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Audio_Codec
Date: Friday, September 03, 2021 Sheet 66 of 110
5 4 3 2 1
 5 4 3 2 1

Audio Debug Function P.79

EC IT8227VG
D D
UART_EN

P.12
PCH UART
UART2_TX SW@
UART2_RX P.67
U8401 P.69
SW@ TS5USBA224RSWR
R8401
R8402 Audio Jack
P.66 P.69
Codec Head Phone/ R8403
USB/AUDIO SWITCH
HPOUT_R Line Out R8404
HPOUT_L

AUDIO@
R8407
R8408

C 2021/07/16 C

Fix Audio Test Issue

+3VALW +3VALW +5VALW

+3VALW
AUDIO DEBUG PORT

1
@ @
R8405 R8406

1
TABLE: @ 10K_0201_5% 10K_0201_5%
R8413
10K_0201_5%
Mode Audio UART

2
2
VBUS L H U8401
9 1 UART_RX
HP_R_JACK_C R8403 1 2 0_0201_5% HP_R_JACK_SW 7 VBUS D- 10 UART_TX UART_RX 12
69 HP_R_JACK_C @ UART_TX 12
HP_L_JACK_C R8404 1 @ 2 0_0201_5% HP_L_JACK_SW 6 D+/R D+ 5 +5VALW
69 HP_L_JACK_C D-/L VAUDIO
8 2 HPOUT_R_SW R8407 1 @ 2 0_0201_5% HPOUT_R
4 ASEL R 3 HPOUT_L_SW HPOUT_L HPOUT_R 66
B R8408 1 @ 2 0_0201_5% B
GND L HPOUT_L 66
TABLE: 2021/07/08

1
@ TS5USBA224_UQFN10_1P8X1P4
Audio Issue Change R8414 SA00007RR00
10K_0201_5% @
Part Name For NPI For MP

2
U8401 SW@ ASM NA
R8403 SW@ ASM NA Co-Lay
R8404 SW@ ASM NA HP_R_JACK_C R8409 1 @ 2 0_0201_5% HPOUT_R_RR R8401 1 @ 2 0_0201_5% HPOUT_R
R8405 SW@ ASM NA HP_L_JACK_C R8410 1 @ 2 0_0201_5% HPOUT_L_RR R8402 1 @ 2 0_0201_5% HPOUT_L
R8406 SW@ ASM NA
R8407 SW@ ASM NA
R8408 SW@ ASM NA
R8401 AUDIO@ NA ASM
A R8402 AUDIO@ NA ASM
A

R8409 AUDIO@ NA ASM

Security Classification LCFC Highly Confidential Information Title
R8410 AUDIO@ NA ASM
Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Audio_Amplifier
Date: Friday, September 03, 2021 Sheet 67 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Audio_DSP
Date: Friday, September 03, 2021 Sheet 68 of 110
5 4 3 2 1
 5 4 3 2 1

Speaker
JSPK1

SPK_R+ EMC@ RA23 1 2 HCB1608KF-121T30_0603 SPK_R+_CONN 1

66 SPK_R+ 1
SPK_R- EMC@ RA22 1 2 HCB1608KF-121T30_0603 SPK_R-_CONN 2
66 SPK_R- 2
SPK_L+ EMC@ RA24 1 2 HCB1608KF-121T30_0603 SPK_L+_CONN 3 5
66 SPK_L+ 3 GND1
SPK_L- EMC@ RA25 1 2 HCB1608KF-121T30_0603 SPK_L-_CONN 4 6
66 SPK_L- 4 GND2
D D
HIGHS_WS33041-S0191-HF
@ 2 @ 2 @ 2 @ 2 ME@
EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 1 CA27 CA28 CA29 CA30

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201
CA23 CA24 CA25 CA26

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201
1 1 1 1
2 2 2 2

For EMC Near CODEC

For EMC Near Conn.

C 6pin&7pin audio jack comon design,stuff 6pin default; C

need vitrual symbol control Audio Jack

JHP1

MIC2_VREFOL RA31 2 1 2.2K_0402_5% RING2_CONN 3 G/M

@ 66 MIC2_VREFOL HP_L_JACK_C RA86 2 1 56_0402_5% HPOUT_L_R 1
1 2 HPOUT_L_R_C CA37 1 2 HPOUT_L_R 67 HP_L_JACK_C L
RA30 @
0_0402_5% 470P_50V_K_X7R_0201 LINE2-L @ CA38 1 2 1U_6.3V_M_X5R_0201 PLUG_IN 5
66 LINE2-L 5
RA15 1 @ 2 100K_0402_1% LINE2-R @ CA40 1 2 1U_6.3V_M_X5R_0201 6
66 LINE2-R 6
HP_R_JACK_C RA87 2 1 56_0402_5% HPOUT_R_R 2
67 HP_R_JACK_C R
@ MIC2_VREFOR RA36 2 1 2.2K_0402_5% RING3_CONN 4
RA35 1 @ 2 HPOUT_R_R_C CA41 1 2 HPOUT_R_R 66 MIC2_VREFOR M/G
0_0402_5% 470P_50V_K_X7R_0201 7
EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 1 MS
RA85 1 @ 2 10K_0402_5% CA42 CA43 CA44 CA45 ATOB_063-RT04-0601

100P 25V J NPO 0201

100P 25V J NPO 0201

100P 25V J NPO 0201

100P 25V J NPO 0201

ME@

2
2 2 2 2
R8428
B B
RING3_CONN 0_0402_5%
66 RING3_CONN RING2_CONN
66 RING2_CONN

1
HPOUT_L_R
HPOUT_R_R @
PLUG_IN
66 PLUG_IN

7/15, Fix Audio noise issue

EMC_NS@ 1 EMC@ EMC@ EMC@ EMC@ EMC@
PN from SM01000HK0J to SD028560A8J
1

CA39 DA7 DA3 DA4 DA5 DA2

47P_25V_J_NPO_0201

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
1

2
2

2
2

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Audio_SPK/Jack
Date: Friday, September 03, 2021 Sheet 69 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Card Reader
Date: Friday, September 03, 2021 Sheet 70 of 110
5 4 3 2 1
 A B C D E

+3VS +3V_WLAN

WLAN

2
+3V_WLAN

2
@ RN6
QN2 10K_0402_5%

1
+3VSUS +3V_WLAN SSM3K15AMFV_2-1L1B

1
3 1 RN8
1 1/20W_200K_5%_0201 1
RN1 1 @ 2

2
0_5%_0603 RN9 1 @ 2 PCIE_WAKE_N_WLAN
RN7 1 @ 2 WLAN_CLKREQ_Q_N +3V_WLAN 17,78,79 PCIE_WAKE_N
16 WLAN_CLKREQ_N 0_0201_5%
0_0402_5% RN10 1 @ 2
12 PCH_PCIE_WAKE_N_WLAN
0_0201_5%
1 1 1
CN1 CN2 CN3

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

0.01U_6.3V_K_X7R_0201
2 2 2

JWLAN1
1 2
USB20_10_P 3 GND1 3.3VAUX1 4
14 USB20_10_P USB20_10_N 5 USB_D+ 3.3VAUX2 6 WLAN_PERST_N
14 USB20_10_N RN12 1 @ 2
PCH_WLAN_PERST_N 12
7 USB_D- LED1# 8
9 GND2 PCM_CLK/I2S_SCK 10 0_0201_5%
11 SDIO_CLK PCM_SYNC/I2S_WS 12
13 SDIO_CMD PCM_IN/I2S_SD_IN 14
2 SDIO_DATA0 PCM_OUT/I2S_SD_OUT RN11 1 2
PLT_RST_N 17,63,78,79,82 2
15 16
17 SDIO_DATA1 LED#2 18 0_0201_5%
19 SDIO_DATA2 GND11 20
21 SDIO_DATA3 UART_WAKE# 22
23 SDIO_WAKE# UART_RXD
SDIO_RESET#

WLAN_SMB_CLK RN23 2 @ 1 100K_0201_5%

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32
0.1U_6.3V_K_X5R_0201 CN8 1 2 PCIE_PTX_C_DRX9_P 35 GND3 UART_TXD 34
14 PCIE_PTX_DRX9_P PCIE_PTX_C_DRX9_N PETP0 UART_CTS
0.1U_6.3V_K_X5R_0201 CN9 1 2 37 36
14 PCIE_PTX_DRX9_N 39 PETN0 UART_RTS 38 CL_RST_N_WLAN1
GND4 VENDOR_DEFINED1 TP5909 @
PCIE_PRX_DTX9_P 41 40 CL_DAT_WLAN 1
14 PCIE_PRX_DTX9_P PCIE_PRX_DTX9_N PERP0 VENDOR_DEFINED2 TP5910 @
43 42
14 PCIE_PRX_DTX9_N 45 PERN0 VENDOR_DEFINED3 44
CLK_PCIE_WLAN_P 47 GND5 COEX3 46
16 CLK_PCIE_WLAN_P CLK_PCIE_WLAN_N 49 REFCLKP0 COEX2 48
16 CLK_PCIE_WLAN_N 51 REFCLKN0 COEX1 50 SUSCLK_R RN17 1 @ 2 0_0201_5%
3 SUSCLK 16 3
WLAN_CLKREQ_Q_N 53 GND6 SUSCLK 52 WLAN_PERST_N
PCIE_WAKE_N_WLAN 55 CLKREQ0# PERST0# 54 BT_OFF_N_R RN18 1 @ 2 0_0201_5%
PEWAKE0# W_DISABLE2# WLAN_OFF_N RN19 1 @ PCH_BT_OFF_N 13
57 56 2 0_0201_5%
GND7 W_DISABLE1# RN20 1 2 0_0201_5% PCH_WLAN_OFF_N 12
EC_RX 79
@
59 58 WLAN_SMB_DATA RN15 1 @ 2 0_0201_5% EC_RX
61 RSRVD/PETP1 I2C_DATA 60 WLAN_SMB_CLK RN16 1 @ 2 0_0201_5% EC_TX
63 RSRVD/PETN1 I2C_CLK 62
65 GND8 ALERT# 64 EC_TX_WLAN RN21 1 @ 2 0_0201_5%
RSRVD/PERP1 RSRVD EC_TX 79
67 66
69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3V_WLAN
71 GND9 UIM_POWER_SNK/CLKREQ1# 70
73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72
75 RSRVD/REFCLKN1 3.3VAUX3 74
GND10 3.3VAUX4 1 1 1 1

2
100K_0201_5%

RN22

10U 6.3V M X5R 0402

CN4

0.1U_6.3V_K_X5R_0201
CN5

0.01U_6.3V_K_X7R_0201
CN6

100U_1206_6.3V6M
CN7
77 76 @
GND15 GND14
2 2 2 2
ARGOSY_NASE0-S6701-TSH4

1
ME@

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. WLAN
Date: Friday, September 03, 2021 Sheet 71 of 110
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. WWAN
Date: Friday, September 03, 2021 Sheet 72 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. LAN_Chipset
Date: Friday, September 03, 2021 Sheet 73 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. LAN_Transformer
Date: Friday, September 03, 2021 Sheet 74 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. LAN_CONN
Date: Friday, September 03, 2021 Sheet 75 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Sensor
Date: Friday, September 03, 2021 Sheet 76 of 110
5 4 3 2 1
 5 4 3 2 1

+3VS
+3VS
AMBIENT Near CPU
REMOTE1+_R REMOTE2+_R
1
Charger

1
@
D RS309 D
CS301 1 1
RS301

C
0.1U_6.3V_K_X5R_0201 4.7K_0402_5%
2

100P 25V J NPO 0201

100P 25V J NPO 0201

10K_0402_5% CS305 2 B QS302 CS304 2 B QS301
US301 LMBT3904WT1G_SOT323-3 LMBT3904WT1G_SOT323-3

2
2 2

E
1 1 10 EC_SMB_CK3 REMOTE1-_R REMOTE2-_R
VCC SCL EC_SMB_CK3 79,93

3
CS302 REMOTE1+ 2 9 EC_SMB_DA3
DP1 SDA EC_SMB_DA3 79,93
2200P_25V_K_X7R_0201
2 REMOTE1- 3 8 SEN_ALERT_N
DN1 ALERT#
REMOTE2+ 4 7 SEN_THERM_N
DP2 THERM#
1
REMOTE2- 5 6
CS303 DN2 GND
2200P_25V_K_X7R_0201
2 F75303M_MSOP10
REMOTE1+ RS304 1 @ 2 0_0402_5% REMOTE1+_R REMOTE+

1
REMOTE1- RS305 1 @ 2 0_0402_5% REMOTE1-_R 1

C
@ @
@

100P 25V J NPO 0201

REMOTE2+ RS302 1 2 0_0402_5% REMOTE2+_R CS307 2 B QS303
C
LMBT3904WT1G_SOT323-3 C
REMOTE2- RS303 1 @ 2 0_0402_5% REMOTE2-_R 2

E
REMOTE+_R RS307 1 @ 2 0_0402_5% REMOTE+ REMOTE-

3
REMOTE-_R RS308 1 @ 2 0_0402_5% REMOTE-

+3VS

1
@
CS306 FAN
1

0.1U_6.3V_K_X5R_0201
@ 2 +5VS +5VS_FAN1
RS306 Heat Pipe
100K_0201_5%
RF1 1 @ 2 0_5%_0603
2

REMOTE+_R US302
@ 1 1 8
VDD SCL EC_SMB_CK3 79,93
CS308 @
2200P_25V_K_X7R_0201 2 7 1 CF2 1 1 @
D+ SDA EC_SMB_DA3 79,93
B CF1 CF3 B
2 REMOTE-_R 3 6 10U 6.3V M X5R 0402 10U 6.3V M X5R 0402 0.1u_0201_10V6K
D- ALERT#
TCRIT_N 4 5 2 2 2
T_CRIT# GND
@ NCT7718W_MSOP8

+5VS_FAN1

JFAN1
79 EC_FAN1_PWM 1
2 1
79 EC_FAN1_SPEED 2
3
4 3
4
5
6 GND1
GND2

HIGHS_WS33040-S0351-HF
ME@

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thermal
Date: Friday, September 03, 2021 Sheet 77 of 110
5 4 3 2 1
 5 4 3 2 1

D D

FP_PWR +USB_VCCB
JIO1
1
2 1
3 2
4 3
5 4
6 5
+3VALW 6
7
8 7
+3VS 8
9
10 9
LID_0D_SW_N +3VL 10
11
79 LID_0D_SW_N ON/OFFBTN_N 11
12
80 ON/OFFBTN_N 13 12
FPR_LED_AMBER_N 14 13
79 FPR_LED_AMBER_N PWR_LED_WIT_N 14
15
79 PWR_LED_WIT_N 15
16
USB20_1_N 17 16
14 USB20_1_N USB20_1_P 18 17
14 USB20_1_P 18
19
USB20_6_P 20 19
14 USB20_6_P USB20_6_N 20
21
14 USB20_6_N 21
22
PCIE_WAKE_N 23 22
17,71,79 PCIE_WAKE_N 23
24
PCIE_PRX_DTX10_N 25 24
14 PCIE_PRX_DTX10_N PCIE_PRX_DTX10_P 25
14 PCIE_PRX_DTX10_P 26
27 26
PCIE_PTX_C_DRX10_N 28 27
14 PCIE_PTX_C_DRX10_N PCIE_PTX_C_DRX10_P 28
C 29 C
14 PCIE_PTX_C_DRX10_P 30 29
CLK_PCIE_LAN_N 31 30
16 CLK_PCIE_LAN_N CLK_PCIE_LAN_P 31
32
16 CLK_PCIE_LAN_P 33 32
LAN_CLKREQ_N 34 33
16 LAN_CLKREQ_N EC_LAN_WAKE_N 35 34
79 EC_LAN_WAKE_N PLT_RST_N 35
36
17,63,71,79,82 PLT_RST_N GPIO_SCL_R 36
37
79 GPIO_SCL_R FP_RESETN_R 38 37
12 FP_RESETN_R GPIO_AL0_R 38
39 41
79 GPIO_AL0_R FPR_LED_WHITE_N 40 39 GND1 42
79 FPR_LED_WHITE_N 40 GND2
HIGHS_FC5AF401-3181H
ME@
1

@ @
RL25 RL24
0_0402_5% 0_0402_5%
2

@
RL23
0_0402_5%
1
2

@
RL21
0_0402_5%
2

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Sub Board CONN
Date: Friday, September 03, 2021 Sheet 78 of 110
5 4 3 2 1
 5 4 3 2 1

+3VL
+3VL_EC VCC_LPC_ESPI
+3VL_EC +3VL_EC_R +1.8VALW +3VL +3VSUS VCC_FSPI

RE5 1 @ 2 0_5%_0603
RE2 1 @ 2 0_5%_0603 RE3 1 @ 2 0_0402_5% RE4 1 @ 2 0_0402_5%
1 1 1 1 1 1
CE1 CE2 CE3 CE4 CE7 CE8 RE6 1 @ 2 0_0402_5% +3VL_EC
1 1 1

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
CE5 CE6
0.1U_6.3V_K_X5R_0201 1000P_50V_K_X7R_0201 CE10 1
2 2 2 2 2 2 0.1U_6.3V_K_X5R_0201 CE9 EC_SMB_DA0 RE133 1 2 1/20W_2.2K_5%_0201
2 2 2 0.1U_6.3V_K_X5R_0201 EC_SMB_CK0 RE134 1 2 1/20W_2.2K_5%_0201
RE8 1 @ 2 EC_AGND -PD_I2C_INT RE135 1 2 1/20W_2.2K_5%_0201
2
0_5%_0603 +3VS

EC_AGND EC_FAN1_PWM RE9 1 @ 2 10K_0201_5%

EC_FAN1_SPEED RE11 1 2 100K_0402_5%
EC_TP_ON RE112 1 @ 2 100K_0201_5%
D CPU_VR_READY RE13 1 2 100K_0402_5% D

+3VL_EC
+3VL_EC
RPE3
EC_SMB_CK1 1 4
EC_SMB_DA1 2 3

2.2K_0404_4P2R_5%

1
@ +3VL_EC
RE94 DE3
100K_0402_5% RB521CS-30GT2RA_VMN2-2

2
EC_SMB_DA3 RE59 1 2 1/20W_2.2K_5%_0201

1
VCC_LPC_ESPI EC_SMB_CK3 RE61 1 2 1/20W_2.2K_5%_0201

VCC_FSPI
+3VL_EC
2
+3VL_EC +3VL_EC_R
CE23 EC_USB_ON_N RE117 1 2 100K_0201_5%
LAN_WAKE_N_R RE126 1 2 10K_0201_5%
1U_6.3V_M_X5R_0201
1

+3VL_EC

UE1
SA0000ADV00 LID_0D_SW_N RE12 1 2 100K_0201_5%

D10

K10
EC_ON_3VALW_R

D4
D5

K4

E6
E9

E4
IT8227VG-256CX_VFBGA128 RE37 1 2 100K_0201_5%

J5
EC_ON_5VALW_R RE38 1 2 100K_0201_5%
RE19 1 @ 2 0_0201_5% EC_ESPI_IO0 K1 A10 EC_SMB_CK0_R RE116 1 @ 2 0_0201_5% EC_ON_1.8V RE39 1 @ 2 100K_0201_5%

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5

VSTBY6
VCC

VFSPI
AVCC
11 LPC_ESPI_IO0 @ EIO0/LAD0/GPM0 SMCLK0/GPF2 @ EC_SMB_CK0 59
11 LPC_ESPI_IO1
RE20 1 2 0_0201_5% EC_ESPI_IO1 J2 B10 EC_SMB_DA0_R RE113 1 2 0_0201_5% EC_SMB_DA0 59
EC_ON_PCH_R RE40 1 2 100K_0201_5%
@ EIO1/LAD1/GPM1 SMDAT0/GPF3
11 LPC_ESPI_IO2
RE24 1 2 0_0201_5% EC_ESPI_IO2 J1 B3 EC_SMB_CK1
EC_SMB_CK1 87,89
ECLPM_BREAK RE43 1 @ 2 100K_0201_5%
@ EIO2/LAD2/GPM2 SMCLK1/GPC1
11 LPC_ESPI_IO3
RE25 1 2 0_0201_5% EC_ESPI_IO3 H2 B2 EC_SMB_DA1
EC_SMB_DA1 87,89
EC_ESPI_RST_N M4 EIO3/LAD3/GPM3 SMDAT1/GPC2 B1 PCH_PECI_EC RE26 1 2 1/20W_43_5%_0201
@ ERST#/LPCRST#/GPD2 SMCLK2/PECI/GPF6 @ PCH_PECI 10
11 LPC_ESPI_CLK
RE27 1 2 0_0201_5% EC_ESPI_CLK K2 C1 EC_ME_FLASH RE72 1 2 0_0201_5%
ME_FLASH 13
@ ESCK/LPCCLK/GPM4 SMDAT2/PECIRQT#/GPF7
11 LPC_ESPI_CS_N
RE22 1 2 0_0201_5% EC_ESPI_CS_N H1
When mirror, GPG2 Pull High +3VL_EC
ECS#/LFRAME#/GPM5
When no mirror, GPG2 Pull Low GPG2 RE45 1 2 100K_0201_5%

RE46 1 @ 2 0_0201_5% PCH_EC_ENBKL F1 RE47 1 @ 2 10K_0201_5%

7,47 PCH_ENBKL G2 GA20/GPB5 A11 EC_ON_PCH_R @
RE34 1 2 0_0201_5%
@ ALERT#/SERIRQ/GPM6 PS2CLK0/TMB0/CEC/GPF0 @ EC_ON_PCH 53,84,93
17,63,71,78,82 PLT_RST_N
RE79 1 2 0_0201_5% EC_PLT_RST_N L2 B11 EC_PBTN_OUT_N RE35 1 2 0_0201_5% PBTN_OUT_N 17
@ PLTRST#/ECSMI#/GPD4 PS2DAT0/TMB1/GPF1
10 EC_PCH_SCI_N
RE36 1 2 0_0201_5% EC_SCI_N N4 D9 CAPS_LED_N_R RE111 1 @ 2 0_0201_5% CAPS_LED_N 12,81
L1 ECSCI#/GPD3 PS2CLK2/GPF4 B9 RE66 1 @ 2 0_0201_5% PCH_PM_SLP_S4_N 17,84
@ WRST# PS2DAT2/GPF5
59 -PD_I2C_INT
RE98 1 2 0_0201_5% -PD_I2C_INT_EC H4
KBRST#/GPB6 EC_USM_3V_5VALW RE128 1 @ 2 EC_VCCST_EN RE57 1 @ 2 100K_0201_5%
0_0201_5% EC_USM 91,92 SUSP_N RE60 1 2 100K_0201_5%
C M5 EC_PWR_LED_WIT_N RE41 1 @ 2 0_0201_5% EC_BKOFF_N RE64 1 2 10K_0201_5% C
PWM0/GPA0 N5 EC_FPR_LED_AMBER_N 1 @ 2 PWR_LED_WIT_N 78 EC_ON_1.8V 1 2
RE81 0_0201_5% FPR_LED_AMBER_N 78 RE14 100K_0201_5%
PWM1/GPA1 M6 BATT_LOW_LED_N EC_ON_5VALW_R RE17 1 @ 2 100K_0201_5%
EC_RTCRST E5 PWM2/GPA2 N6 EC_KB_BKL_EN BATT_LOW_LED_N 80
@ CRX0/GPC0 PWM3/GPA3 @ EC_KB_BKL_EN 81
12 PCH_ECLPM_BREAK
RE44 1 2 0_0201_5% ECLPM_BREAK D2 K6 EC_FAN1_PWM_R RE10 1 2 0_0201_5% EC_FAN1_PWM 77
CTX0/TMA0/GPB2 SMCLK5/PWM4/GPA4 J6 FPR_LED_WHITE_R RE124 1 @ 2 0_0201_5% FPR_LED_WHITE_N 78
SMDAT5/PWM5/GPA5

EC_PROCHOT B13
EC_VBUS_EN D1 DAC4/DCD0#/GPJ4 M11 EC_FAN1_SPEED EC_USM_3V_5VALW RE125 1 @ 2 100K_0201_5%
53 EC_VBUS_EN @ FDIO3/DSR0#/GPG6 Don't pull up TACH0A/GPD6 EC_FAN1_SPEED 77
65 FPR_PWR_EN
RE114 1 2 0_0201_5% EC_FPR_PWR_EN N7 M12 AOU_SEL2
AOU_SEL2 57
GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7
RE130 1 @ 2 0_0201_5% EC_VR_ON_R C12 C2 AOU_SEL1_R RE15 1 @ 2 0_0201_5%
95 EC_VR_ON DAC5/RIG0#/GPJ5 GPC4 SUSP_N AOU_SEL1 57
E1
EC_TX M1 GPC6 SUSP_N 84
71 EC_TX EC_RX TXD/SOUT0/LPCPD#/GPE6
M2
71 EC_RX RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7
89 ADP_I RE131 1 @ 2 0_0201_5%
USB_ON2 F10 A5 PD_VBUS_C_CTRL1_EC RE132 1 @ 2 0_0201_5%
57 USB_ON2 @ ADC5/DCD1#/GPI5 GPE4 PD_VBUS_C_CTRL1 60
RE99 1 2 0_0201_5% -AOU_IFLG_R F12 N1 EC_VPP_PWREN
57 -AOU_IFLG @ ADC6/DSR1#/GPI6 RI1#/GPD0 EC_VPP_PWREN 93
RE49 1 2 0_0201_5% PSYS_R E13 N3 EC_USB_ON_N CPU_VR_READY CE12 1 2 0.1U_6.3V_K_X5R_0201 EMC@
89,95 PSYS ADC7/CTS1#/GPI7 RI2#/GPD1 EC_USB_ON_N 58
RE51 1 2 1K_0201_5%EC_PCH_DPWROK N8 VDDQ_PGOOD CE13 1 2 0.01U_6.3V_K_X7R_0201 EMC@
17 EC_PCH_DPWROK_R 1 @ 2 0_0201_5% EC_BATT_CHG_LED_N K7 RTS1#/GPE5 PCH_PM_SLP_S4_N CE14 1 2
RE42 1000P_50V_K_X7R_0201 EMC_NS@
80 BATT_CHG_LED_N EC_SYS_PWROK PWM7/RIG1#/GPA7 EC_ON_5VALW @ PCH_PECI
F4 A1 RE53 1 2 0_0201_5% CE18 1 2 47P_25V_J_NPO_0201 EMC_NS@
17 EC_SYS_PWROK EC_SMB_DA3 D7 FDIO2/DTR1#/SBUSY/GPG1/ID7 RING#//CK32KOUT/LPCRST#/GPB7 B4 ON/OFF_N EC_ON_5VALW_R 92 BATT_TEMP 1 2
ON/OFF_N 80 CE19 100P 25V J NPO 0201 EMC_NS@
77,93 EC_SMB_DA3 EC_SMB_CK3 E8 CTX1/SOUT1/SMDAT3/GPH2/ID2 PWRSW/GPB3 A2 EC_ON_3VALW 1 @ 2 ACIN_N 1 2
RE75 0_0201_5% CE20 100P 25V J NPO 0201 EMC_NS@
77,93 EC_SMB_CK3 CRX1/SIN1/SMCLK3/GPH1/ID1 GPB4 EC_LID_SW_N @ EC_ON_3VALW_R 91 ON/OFF_N
A3 RE54 1 2 0_0201_5% CE21 1 2 1U_6.3V_M_X5R_0201 EMC_NS@
EC_SPI_CLK GPB1 ACIN_N LID_0D_SW_N 78 PLT_RST_N
B5 A4 CE22 1 2 220P_25V_K_X7R_0201 EMC_NS@
27 EC_SPI_CLK EC_SPI_CS0_N FSCK GPB0 EC_RSMRST_N
A7 CE24 1 2 1000P_50V_K_X7R_0201 EMC_NS@
27 EC_SPI_CS0_N EC_SPI_SI FSCE#
B6
27 EC_SPI_SI EC_SPI_SO A6 FMOSI G10 EC_VCCST_EN
27 EC_SPI_SO FMISO ADC0/GPI0 PM_SLP_S0_N_EC @ EC_VCCST_EN 84
G13 RE63 1 2 0_0201_5%
K13 ADC1/GPI1 G12 BATT_TEMP_EC RE52 1 @ 2 PM_SLP_S0_N 17,84
KSO16 0_0201_5% 87,89
KSO16/SMOSI/GPC3 ADC2/GPI2 PM_SLP_SUS_N_EC @ BATT_TEMP
17 PCH_PM_SLP_S3_N RE136 1 @ 2 0_0201_5% KSO17 J10 F9 RE69 1 2 0_0201_5% PCH_PM_SLP_SUS_N
@ 2 0_0201_5% EC_SPKR_R KSO17/SMISO/GPC5 ADC3/GPI3 CPU_VR_READY_EC @ 17
RE68 1 M7 F13 RE77 1 2 0_0201_5%
66 EC_SPKR PWM6/SSCK/GPA6 ADC4/GPI4 CPU_VR_READY 95
GPG2 E7 Pull up for Mirror code
0_0201_5% 2 @ 1 EC_GPIO_SCL E2 SSCE0#/GPG2 Pull down for load code via Download board or Offline baord
78 GPIO_SCL_R SSCE1#/GPG0 Don't pull up E12 EC_VCCST_PWRGD
RE118 M8 TACH2A/GPJ0 D13 EC_MUTE_N_R 1 @ 2 EC_VCCST_PWRGD 17
KSO0 RE70 0_0201_5% EC_MUTE_N 66
KSO1 J7 KSO0/PD0 TACH2B/GPJ1 D12 EC_TP_ON RE71 1 @ 2 0_0201_5%
KSO2 N9 KSO1/PD1 DAC2/TACH0B/GPJ2 C13 EC_BKOFF_N EC_TP_ON_R 83
M9 KSO2/PD2 DAC3/TACH1B/GPJ3 EC_BKOFF_N 47
KSO3
KSI[0..7] KSO4 K8 KSO3/PD3
81 KSI[0..7] J8 KSO4/PD4
KSO5
KSO[0..17] KSO6 N10 KSO5/PD5
81 KSO[0..17] KSO6/PD6
KSO7 M10
KSO8 N11 KSO7/PD7
KSO9 K9 KSO8/ACK#
KSO10 N12 KSO9/BUSY
KSO11 N13 KSO10/PE G1 LAN_WAKE_N_R RE28 1 @ 2 0_0201_5% EC_LAN_WAKE_N 78
B KSO12 M13 KSO11/ERR# GPJ7 F2 EC_AC_PRESENT RE74 1 @ 2 B
0_0201_5% AC_PRESENT 17
KSO13 L12 KSO12/SLCT GPJ6
KSO14 L13 KSO13
KSO15 K12 KSO14 B12 TOP_SWAP_EN_N RE121 1 @ 2 0_0201_5%
KSO15 EGCLK/GPE3 VDDQ_PGOOD_EC TOP_SWAP_EN 12
A12 RE76 1 @ 2 0_0201_5%
EGCS#/GPE2 @ VDDQ_PGOOD 93
A13 RE109 1 2 0_0201_5%
EGAD/GPE1 EC_GPIO_AL0 @ PCH_TP_INT_N 12,83
KSI0 J12 RE104 1 2 0_0201_5%
KSI0/STB# GPIO_AL0_R 78
KSI1 J13
KSI2 J9 KSI1/AFD# Don't pull up N2 EC_RP_SEL0
H12 KSI2/INIT# Don't pull up SMCLK4/L80HLAT/BAO/GPE0 M3 EC_RP_SEL1 EC_RP_SEL0 53
KSI3
KSI3/SLIN# SMDAT4/L80LLAT/GPE7 EC_RP_SEL1 53
KSI4 H9
KSI5 H10 KSI4 Don't pull up J4 EC_PCIE_WAKE_N
@ TE1 1 KSI6 H13 KSI5 Don't pull up GPH7 B7 EC_PCH_PWROK RE127 1 @ 2 0_0201_5%
KSI6 GPH6/ID6 EC_BATLOW_N_YMC1 PCIE_WAKE_N 17,71,78
@ TE2 1 KSI7 G9 A8
KSI7 GPH5/ID5 EC_PCH_PWROK 17
B8 RE65 1 @ 2 0_0201_5%
GPH4/ID4 @ BATLOW_N 17
VCORE

A9 RE122 1 2 0_0201_5%
GPH3/ID3 ACOFF
AVSS

89
VSS1
VSS2
VSS3
VSS4
VSS5

D8 RE73 1 @ 2 0_0201_5%
CLKRUN#/GPH0/ID0 EC_GPD7_ANS RE16 1 @ 2 0_0201_5% SX_EXIT_HOLDOFF_N 17
EC_ON_1.8V EC_ANS 95
EC_RSMRST_N RE80 1 2 1K_0201_5% EC_ON_1.8V 93
F5
G4
G5

E10
D6

H5

K5

EC_RSMRST_N_R 17

VCOREVCC CE11 1 2 0.1U_6.3V_K_X5R_0201

EC_AGND

RE88 1 @ 2 0_0201_5%
89,95 VR_HOT_N H_PROCHOT_N 10,20,59,93
Emergency Power Loss Early De-assertion of DSW_PWROK control circuit
1

+3VALW_PWRGD RE82 1 @ 2 0_0201_5% ALW_PWRGD_R DE1 1 2 EC_RSMRST_N

1 91 +3VALW_PWRGD
RE90 @
1/20W_100_5%_0201 CE16 RB521CM-30T2R_VMN2M-2
47P_25V_J_NPO_0201
2

EC_PROCHOT_N 2 +5VALW_PWRGD RE123 1 @ 2 0_0201_5% DE2 1 2 EC_PCH_DPWROK_R

92,93 +5VALW_PWRGD
1

RB521CM-30T2R_VMN2M-2

EC_PROCHOT 2
QE4
A SSM3K15AMFV_2-1L1B A
3

VCC3_LDO_PD
1

EC_RTC_RST_N 16
RE89
100K_0201_5%
1

ACIN_N RE91 1 @ 2 0_0201_5%

EC_RTCRST 2
1

PLT_RST_N RE95 1 @ 2 0_0201_5% QE2

1

SSM3K15AMFV_2-1L1B
3

RE96 1 @ 2 0_0201_5% EC_ESPI_RST_N @

11 LPC_ESPI_RST_N 2
RE92 QE3
SSM3K15AMFV_2-1L1B ACIN 89
10K_0201_5%
Security Classification LCFC Highly Confidential Information Title
2

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EC
Date: Friday, September 03, 2021 Sheet 79 of 110
5 4 3 2 1
 5 4 3 2 1

LED State LED Behavior ON/OFF Switch +3VL

2
System on White_ON(Battery：21%~100%)
RI501
Standby Amber_ON(Battery：0%~20%) 100K_0402_5%
Power Button LID closed
D White_ON(Battery：21%~100%) D

1
System off OFF ON/OFFBTN_N 1 2 ON/OFF_N
78 ON/OFFBTN_N ON/OFF_N 79
Battery only OFF RI502
2.2K_0402_5%
Charging Amber_ON(Battery：1%~90%) JBT501 1 2
Charging
White_ON(Battery：91%~100%) SHORT PADS

2021/07/08 JBT502 1 2
EMC Request SHORT PADS

RI403 1 @ 2
BATT_LOW_LED +5VALW
1/16W_1.4K_5%_0402

BATT_LOW_LED_N 1 2 BATT_LOW_LED_N_R RI401 1 2

79 BATT_LOW_LED_N +3VALW
C 300_0402_5% C
LEDI1
1

L-C192JFCT-LCFC_SUPER_AMBER
1

EMC_NS@
DI401
AZ5123-01F.R7GR_DFN1006P2X2
2
2

BATT_CHG_LED RI404 1 @ 2 +3VALW

470_0402_5%

BATT_CHG_LED_N 1 2 BATT_CHG_LED_N_R RI402 1 2

79 BATT_CHG_LED_N +5VALW
LEDI2 430_0402_1%
L-C192WDT-LCFC_WHITE
1
1

EMC_NS@
DI402
B AZ5725-01F.R7GR_DFN1006P2X2 B
2
2

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. LED/Button
Date: Wednesday, September 08, 2021Sheet 80 of 110
5 4 3 2 1
 5 4 3 2 1

K/B Connector

+3VS RI206 1 2 1/20W_200_1%_0201

JKB1
RI207 1 @ 2 1/20W_200_1%_0201 PWR_CAPS_LED 1
D +3VALW @ 1 D
RI208 1 2 0_0402_5% CAPS_LED_N_CON 2
KSO15 3 2

12,79 CAPS_LED_N
CAPS_LED_N KSO10
KSO11
4
5
3
4 KB Backlight Connector +5VS +5VALW +5VS
+VCC_KB_LED
KSO14 6 5 @
KSO13 7 6 QI202
7

1
KSI[0..7] KSO12 8 @ @ LP2301ALT1G_SOT-23-3
KSI[0..7] 79 9 8
KSO3 RI203 RI204
KSO[0..17] 9

D
KSO6 10 10K_0201_5% 10K_0201_5% 3 1
KSO[0..17] 79 11 10
KSO8
KSO7 12 11

2
KSO4 13 12 @

G
2
KSO2 14 13 RI201 1 @ 2 KBBL_EN_N RI205 1 2KBBL_EN_N_R
KSI0 15 14 0_0201_5% 1/20W_30K_1%_0201
15

0.01U_0201_10V6K

10U 6.3V M X5R 0402

0.1u_0201_10V6K
KSO1 16 1 @ 1 @
16

1
KSO5 17 @ CI203 CI204
17

1
KSI3 18 CI202
KSI2 19 18

2
KSO0 20 19 @ 2 2
KSI5 21 20 RI202 1 @ 2EC_KB_BKL_EN_R 2 QI201
21 79 EC_KB_BKL_EN
KSI4 22 0_0201_5% 1 SSM3K15AMFV_2-1L1B
KSO9 23 22 @

3
KSI6 24 23 CI201
KSI7 25 24 0.1U_6.3V_K_X5R_0201
C 25 2 C
KSI1 26
KSO16 RI209 1 @ 2 0_0402_5% KSO16_R 27 26
KSO17 RI210 1 @ 2 0_0402_5% KSO17_R 28 27
29 28
30 29
RI213 1 2 1/20W_200_1%_0201 PWR_Fnlk_LED 31 30
+3VS 31
+3VALW RI214 1 @ 2 1/20W_200_1%_0201 32
RI215 1 @ 2 0_0402_5% Fnlk_LED_N_CON 33 32 36
12 Fnlk_LED_N 34 33 GND2 35
34 GND1
HIGHSTAR_FC8AF341-3201H
ME@

EMC
Close to Conn
B B

CAPS_LED_N_CON Fnlk_LED_N_CON PWR_CAPS_LED CAPS_LED_N_CON Fnlk_LED_N_CON

+VCC_KB_LED JKBL1
6
5 GND2
GND1
1

1
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

1 1 1 4
1

DI201 DI203 CI208 CI206 CI310 3 4

3
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
EMC@ EMC@ EMC@ EMC_NS@ EMC_NS@ @ 1 2
CI205 1 2
2 2 2 0.1u_0201_10V6K 1
2

HIGHS_FC1AF040-1201H
2 ME@
2

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KB/KBBL CONN
Date: Friday, September 03, 2021 Sheet 81 of 110
5 4 3 2 1
 5 4 3 2 1

+3VS VCC3_SUS_TPM

D D
R8201 1 @ 2 0_0402_5%

+3VSUS

TPM@
R8202 1 2 1/5W_0.01_1%_0402_100PPM/C

VCC3_SUS_TPM

VCC3_SUS_TPM

1 1 1 1
TPM@ TPM@ @ TPM@
C8201 C8208 C8209 C8204
0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 10U 6.3V M X5R 0402
2 2 2 2

1
TPM@
R8208
10K_0201_5%

2
C C

TABLE

TPM@ Pin TCG Nuvoton ST Micro

22

1
U8201
No
PTP Spec (v38) NPCT750LABYX ST33HTPH2E32AHC0

VHIO2

VHIO1

VSB
-TPM_IRQ R8203 1 @ 2 0_0201_5% -TPM_IRQ_R 18 2
12 -TPM_IRQ PIRQ#/GPIO2 NC1 3 1 VDD VSB NC
NC2 4
PCH_SPI0_SI TPM@ R8204 1 2 1/20W_15_5%_0201 SPI_MOSI_IO0_2_R 21 PP/GPIO6 5 2 GND NC GND
11,27 PCH_SPI0_SI MOSI/GPIO7 NC3
11,27 PCH_SPI0_SO
PCH_SPI0_SO TPM@ R8205 1 2 1/20W_15_5%_0201 SPI_MISO_IO1_2_R 24
MISO NC5
9 3 NC NC NC
10 4 GPIO GPIO/PP PP
NC6 11
NC7 12 5 NC NC NC
-SPI_CS2 R8206 1 @ 2 0_0201_5% -SPI_CS2_R 20 NC8 13 6 GPIO GPIO3 NC
11 -SPI_CS2 SCS#/GPIO5 GPIO4 14 7 GPIO NC GPIO
PCH_SPI0_CLK TPM@ R8207 1 2 1/20W_15_5%_0201 PCH_SPI0_CLK_R 19 NC9 15
11,27 PCH_SPI0_CLK SCLK NPCT750LADYX_QFN32_5X5 NC10 16 8 VDD VHIO NC
PLT_RST_N 17 GND1 25
17,63,71,78,79 PLT_RST_N PLTRST# NC11 26
6 NC12 27
GPIO3 NC13 28
7 NC14 31
9 NC NC NC
NC4 NC15 32 10 NC NC NC
NC16 11 NC NC NC
29 12 NC NC NC
SDA/GPIo0 30
SCL/GPIO1 13 GPIO GPIO4 NC

GND2

GND3
14 NC NC NC
15 NC NC NC
SA00008KS30
16 GND GND NC
23

33
B B
17 SPI_RST# RST# SPI_RST#
18 SPI_PIRQ# PIRQ#/GPIO2 SPI_PIRQ#
19 SPI_CLK SCLK SPI_CLK
20 SPI_CS# SCS#/GPIO5 SPI_CS#
21 MOSI MOSI/GPIO7 MOSI
22 VDD VHIO VPS
23 GND GND NC
24 MISO MISO MISO

TABLE of TPM (U8201)

25 NC NC NC
Vendor P/N LCFC P/N 26 NC NC NC
Nuvoton NPCT750LADYX SA00008KS30 27 NC NC NC
28 NC NC NC
ST Micro ST33HTPH2X32AHD8 SA0000AB720 29 SDA/GPIO1 SDA/GPIO1 NC
30 SDA/GPIO0 SDA/GPIO0 NC
31 NC NC NC
32 NC NC NC

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DISCRETE TPM 2.0
Date: Friday, September 03, 2021 Sheet 82 of 110
5 4 3 2 1
 5 4 3 2 1

D D

2021/07/06
Connector PN from SP01001YV00 to SP01002M200

TP_PWR

JTP1
1
+3VSUS TP_PWR RI305 1 @ 2 0_0201_5% PCH_I2C1_SCL_TP 2 1
12 PCH_I2C1_SCL @ 2
RI304 1 2 0_0201_5% PCH_I2C1_SDA_TP 3
12 PCH_I2C1_SDA 4 3
+3VS RI301 1 @ 2 0_5%_0603 5 4
6 5
RI303 1 @ 2 0_0201_5% TP_INT_N 7 6 9
12,79 PCH_TP_INT_N @ 7 GND1
RI306 1 @ 2 1/10W_0_5%_0603 RI302 1 2 0_0201_5% TP_ON 8 10
79 EC_TP_ON_R 8 GND2
HIGHSTAR_FC5AF081-2933-1H
1 ME@
CI309
C
0.1U_6.3V_K_X5R_0201 C
2

2021/07/07
EMC Request to Add

PCH_I2C1_SCL_TP TP_INT_N

PCH_I2C1_SDA_TP TP_ON
2

2
EMC_NS@ 1 EMC@ EMC_NS@ 1 EMC@

2
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
CI301 DI301 CI302 DI302
2

2
100P 25V J NPO 0201

100P 25V J NPO 0201

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@ EMC_NS@

2
D5617 D5618
2 2
1

1
1

1
B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TouchPad CONN
Date: Friday, September 03, 2021 Sheet 83 of 110
5 4 3 2 1
 A B C D E

+3VALW Load Switch +3VS, C173 --> 2.74ms

+5VALW To +5VS +5VS, C176 --> 2.03ms
+3VALW To +3VS VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm
Need Short +3VS
1
@ +3VALW
CR7901 +3VALW_PCH +3VSUS UR2 J3
1
0.01U_0402_25V_X7R_0402 CR7902 1 14 +3VS_LS 1 2
2 1U_6.3V_M_X5R_0201 2 IN1_1 OUT1_2 13 1 2
UR1 J4 @ IN1_2 OUT1_1 JUMP_43X79
2 1 1
1 14 3VALW_PCH_R RR7908 1 @ 2 0_5%_0603 1 2 3VSON 3 12 3VS_CT1 CR3 1 2 CR4
2 IN1_1 OUT1_2 13 1 2 CR1 EN1 CT1 1000P_50V_K_X7R_0201 0.1U_6.3V_K_X5R_0201
IN1_2 OUT1_1 1
JUMP_43X79 1U_6.3V_M_X5R_0201 4 11
@ 3VSUS_EN 3VALW_PCH_CT1 2 +5VALW VBIAS GND 2
RR7901 1 2 0_0402_5% 3 12 1 2 CR7905 CR7907
1 53,79,93 EC_ON_PCH EN1 CT1 +5VALW 5VS_CT2 1
1000P_50V_K_X7R_0201 0.1U_6.3V_K_X5R_0201 5VSON 5 10 CR7 1 2
RR7902 1 @ 2 0_0201_5% VBIAS 4 11 +1.8VS 2 EN2 CT2 1000P_50V_K_X7R_0201 +5VS
+5VALW VBIAS GND
1 6 9 J5
SUSP_N RR7903 1 @ 2 0_0402_5% 1.8VS_EN 5 10 1.8VS_CT2 1 2 CR7906 7 IN2_1 OUT2_2 8 +5VS_LS 1 2
79,84 SUSP_N EN2 CT2 IN2_2 OUT2_1 1 2
1000P_50V_K_X7R_0201 CR15 1
1 6 9 1U_10V_M_X5R_0201 15 JUMP_43X79 CR14
@ 7 IN2_1 OUT2_2 8 2 Thermal Pad 0.1u_0201_10V6K
IN2_2 OUT2_1 1.8VS_VOUT_R @
Need Short
CR7903 RR7909 1 2 0_5%_0603 G2898KD1U_TDFN14P_2X3
0.01U_0402_25V_X7R_0402 15 2
2 Thermal Pad
1
+5VL G2898KD1U_TDFN14P_2X3
CR7908
1.8VS_VIN_R
0.1U_6.3V_K_X5R_0201
2

RR7910
100K_0402_5% 1
CR7904
1

1U_6.3V_M_X5R_0201
RR7906 1 @ 2 0_0402_5%
+1.8VALW 2 SUSP_N @
SUSP RR1 1 2 0_0402_5% 3VSON
50 SUSP 79,84 SUSP_N
1

2 SSM3K15AMFV_2-1L1B
79,84 SUSP_N QR7901 1 @ 2 0_0402_5%
RR2 5VSON
1 1
3

@ @
CR12 CR13
0.01U_6.3V_K_X7R_0201 0.01U_6.3V_K_X7R_0201
2 2

2 2

+3VALW +VCC1.05_OUT_FET

VCCSTG
1 1
+3VALW CR17 CR18
+3VS 1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402
+3VALW +VCCSTG_CPU
2 2
1

+VCCSTG_CPU_LS
1
@ @
RR6 CR19 1 UR3
100K_0201_5% @ 2 4 RR31 1 @ 2 0_0402_5%
0.1U_6.3V_K_X5R_0201 VIN VOUT
2 CR20
2

0.1U_6.3V_K_X5R_0201 5 3
@ 2 VBIAS NC
@ @ 1
RR8 1 @ 2 0_0201_5% RR28 1 2 0_0201_5% UR5 VCCSTG_EN_R RR11 1 2 0_0201_5% VCCSTG_ENABLE 6 1 EMC@
17,79 PM_SLP_S0_N VCCSTG_EN_R VCCSTG_ENABLE_R ON GND
UR4 @ 1 4 CR7909
RR9 1 @ 2 0_0201_5% PM_SLP_VCCSTG_N 1 4 PM_SLP_VCCSTG_R_N
1 2 0_0201_5% VCCSTG_EN_R VCCIN_AUX_VALID 2 IN B OUT Y VCCSTG_ENABLE_R RR15 1 @ 2 0_0201_5% EM5201BJ-45_SOT23-6
17 CPU_C10_GATE_N 0.1U_6.3V_K_X5R_0201
2 IN B OUT Y IN A 2
EC_VCCST_EN 3V3_VCCST_OVERRIDE_R IN A @ RR29
RR10 1 @ 2 0_0201_5% 3 5
79 EC_VCCST_EN 3 5 GND Vcc
GND Vcc

1
3V3_VCCST_OVERRIDE RR12 1 @ 2 0_0201_5%
MC74VHC1G32DFT2G_SC70-5
MC74VHC1G32DFT2G_SC70-5 RR14
200K_0402_5%

2
3 3

VCCST
+3VALW
+3VALW
+3VALW
1

1
@ @ 1
RR16 CR23 @
100K_0201_5% 0.1U_6.3V_K_X5R_0201 CR24 +3VALW +VCC1.05_OUT_FET
@ 2 @ 0.1U_6.3V_K_X5R_0201
2

+3VALW UR6 @ @ UR8 2

3V3_VCCST_OVERRIDE 1 4 SLP_VCCST_OVRD_R RR32 1 2 PM_SLP_VCCST_OVRD PM_SLP_VCCST_OVRD RR20 1 2 PM_SLP_VCCST_OVRD_R 1 4 VCCST_EN_R
IN B OUT Y IN B OUT Y 1
2 0_0201_5% 0_0201_5% 2 1 CR22
1

1
EC_VCCST_EN RR18 1 @ 2 0_0201_5% +VCCST_EN IN A IN A CR21 10U 6.3V M X5R 0402
@ 3 5 @ 3 5 1U_6.3V_M_X5R_0201
RR19 GND Vcc RR22 GND Vcc 2 +VCCST_CPU_LS
1

100K_0201_5% 200K_0402_5% 2 +VCCST_CPU

MC74VHC1G32DFT2G_SC70-5 MC74VHC1G32DFT2G_SC70-5 UR7
2

2
2 4 RR30 1 @ 2 0_0402_5%
VCCST_OVERRIDE_N 2 @ VIN VOUT
QR2 5 3
SSM3K15AMFV_2-1L1B RR27 1 @ 2 0_0201_5% +3VALW VBIAS NC
1
3

PM_SLP_VCCST_OVRD RR5 1 @ 2 0_0201_5% VCCST_EN 6 1 EMC@

ON GND CR7910
1

1 EM5201BJ-45_SOT23-6 0.1U_6.3V_K_X5R_0201
@ VCCIN_AUX_VCCST_PRESENT VCCST_EN_R RR21 1 @ 2 0_0201_5% 2
2

CR25
2 @ 0.1U_6.3V_K_X5R_0201 @
17 VCCST_OVERRIDE 2
QR1 RR25 RR23 1 @ 2 0_0201_5%
17,79 PCH_PM_SLP_S4_N
1

SSM3K15AMFV_2-1L1B @ 0_0201_5%
3

UR9 @
1

1
1 4 VCCIN_AUX_VALID RR26
20,93 VCCIN_AUX_VID0 IN B OUT Y
2 200K_0402_5%
20,93 VCCIN_AUX_VID1 IN A RR24
2

3 5 200K_0402_5%
GND Vcc

2
4 MC74VHC1G32DFT2G_SC70-5 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DCDC_SYSTEM PWR
Date: Friday, September 03, 2021 Sheet 84 of 110
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DCDC_MS PWR
Date: Friday, September 03, 2021 Sheet 85 of 110
5 4 3 2 1
 5 4 3 2 1

PCB Fedical Mark PAD SO-DIMM 0 Shielding

SH12 SH13 SH14 SH15

FD1 FD2 FD3 FD4 FD5 FD6 SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
D D
1

1
@ @ @ @ @ @

1
1

1
Hole
@ @ @ @

H2 H3 H4 H5
HOLEA HOLEA HOLEA HOLEA
1

1
PAD_C7P0D3P4 PAD_C7P0D3P4 PAD_C7P0D3P4 PAD_C7P0D3P4
C
@ @ @ @ C

SO-DIMM 1 Shielding
H6 H9 H10 H11
HOLEA HOLEA HOLEA HOLEA SH8 SH9 SH10 SH11
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
1

PAD_C7P0D2P3 PAD_C7P0D3P3 PAD_C8P0D2P8 1

PAD_CT8P0B6P0D2P3
@ @ @ @

1
1

1
H14 H15 H18
H12 HOLEA HOLEA HOLEA
HOLEA @ @ @ @
1

B B
1

PAD_D2P3X3P8 PAD_D4P0X3P0 PAD_C7P0D3P3

PAD_C7P0D2P8 @ @ @
@

NH1 NH2 NH3 NH4

HOLEA HOLEA HOLEA HOLEA
1

PAD_O8P0X7P0D8P0X7P0N PAD_C2P5D2P5N PAD_O3P0X2P5D3P0X2P5N PAD_C4P0D4P0N

@ @ @ @

NH8
HOLEA
1

A A
PAD_C6P5D6P5N
@
Security Classification LCFC Highly Confidential Information Title
Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Hole/Shielding
Date: Friday, September 03, 2021 Sheet 86 of 110
5 4 3 2 1
 5 4 3 2 1

JBATT1
VBAT 10A BATT+
HIGHS_WS33081-S120C-1H 2020/4/21
1 PF100
1 2 1 2
2 3 EC_SMCA PR100 1 2 100_0402_1%
3 4 EC_SMDA EC_SMB_CK1 79,89
PR101 1 2 100_0402_1% 15A_32V_0501015.WR
4 5 EC_SMB_DA1 79,89
9 5 6 RTC_VCC_BAT 1 @ 2 0_0402_5%
10 GND1 6 7
GND2 7 8

3
11 PR102
D
12 GND3 8 RTC_VCC PD100
D
GND4 AZC199-02S.R7G_SOT23-3

1
ME@ EMC@ PC100 PC101
1000P_50V_K_X7R_0201 0.01U_25V_K_X5R_0201
EMC@ EMC@

2
Just reserved for RTC integrated into Battery
2021/5/14

1
PR108
1 2 100K_0402_1% +3VALW
2021/07/01
PR103
BATT_TEMP_IN 1 @ 2 100K_0402_1%
+3VL

PR104 1 2 10K_0402_5%
BATT_TEMP 79,89

1
PD101

1
SP1007-01ETG-1_SOD882
EMC@
2021/5/26
2

C C
2

+3VL
2

PR105
0_0402_SP
1
1

@ PR106
45.3K_0402_1%
VCCRTC
2

2 VCCRTC_D2
RTC_VCC
1
JRTC1
3 VCCRTC_D3 2 PR107 1 1
2 1
PD102 1K_0603_5% 3 2
GND1
2

@ PC102 BAT54CW_SOT323-3 4
1U_0402_6.3V6K GND2
Just reserved for RTC integrated into Battery,Remove RTC Connector
1

HIGHS_WS33020-S0351-HF
ME@

RTC_VCC 20MIL
B +3VL 20MIL B
VCCRTC 20MIL

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_DCIN/RTC
Date: Friday, September 03, 2021 Sheet 87 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_ACIN
Date: Friday, September 03, 2021 Sheet 88 of 110
5 4 3 2 1
 5 4 3 2 1

2021/4/20
@ PJ5401
JUMP_43X79
2 1
D 2 1 D

FAIRCHILD : FDMC007N30D
耾猧 AOS : AONH36334
by EMC 2021/4/20
VINT20_IN PQ5405
2021/4/20
PL5402 PL5401
2021/5/14 2021/4/29 1.0UH_HMLQ25201B-1R0MSR_4.0A_20% PR5401
2.2UH_PCMB104T-2R2MS_12A_20%
FDMC007N30D_POWER33-10
0.01_1206_1% EMC@EMC@
1 2 1 2 VBUS 1 2 9 10
B+

7
22U_25V_M_B2_ESR90M_TQC
D2/S1 D1-4
PQ5404 AONY36324_DFN5X6D-8-7EMC@ EMC@

1
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
1000P_50V_K_X7R_0201

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
Q2
5 4

0.01U_0402_25V_X7R_0402
PC5420 1

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
S2-1 D1-3
PR5402 2021/4/21 PR5405 5 PR5404 PC5413 0.047U_0402_25V_X7R_0402 PR5403
EMC@ PC5432

EMC@ PC5410

PC5454

PC5453

EMC@ PC5406

EMC@ PC5402
1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1
1/20W_4.99_1%_0201 1/20W_4.99_1%_0201 2 4 56_0402_5% 56_0402_5% 6 3 PC5451 +

PC5431

PC5401

PC5412

PC5429

PC5446

PC5447

PC5448

PC5428

PC5449

PC5433

PC5427

PC5416
1 1 1 1 0.047U_0402_25V_X7R_0402

2 1

2 1
+ @ PC5424
S2-2 D1-2
3

PC5452

PC5411

PC5435

PC5439

PC5444
0.01U_0402_25V_X7R_0402 7 2 33U_B2

1 2

1 2
2 2 2@ 2@ 2 2 1 2 2 1 PR5407 PR5406
S2-3 D1-1 2 2 2 2 2 2 2 2 @ 2 2 2
@ 2 2 2 2 2 EMC@ 2.2_0603_5%
EMC@ 8 1
2.2_0603_5%

0.033U_25V_K_X7R_0402

0.033U_25V_K_X7R_0402
G2 Q1 G1
2 2 PC5405 PC5440
330P_0402_50V_X7R_0402 30 25 330P_0402_50V_X7R_0402

PC5408

PC5441

2
BTST1 BTST2

1
PR5410

0_0201_SP

0_0201_SP
LX1_CHG 32 23 LX2_CHG PQ5401 AONR21357_DFN8 0.01_1206_1%

PR5408

PR5409
1 1 SW1 SW2 1 8 1 2
1
DL1_CHG 29 26 DL2_CHG 2 7 BATT+
LODRV1 LODRV2

1U_25V_K_X5R_0402

1U_25V_K_X5R_0402

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402

0.1U_25V_K_X7R_0402
PC5425 3 6 1 2

2
0.47U_0402_25V6K DH1_CHG 31 24 DH2_CHG 5
HIDRV1 HIDRV2 1 1 1 1 1 1
PC5419

PC5442

PC5414

PC5415

PC5430

PC5418

PC5455
2 1 22 0.1U_25V_K_X7R_0402

4
VBUS VSYS
C 2 21 BATDRV# 2 2 2 2 2 2 C
VDDA ACN BATDRV#
PR5411 3 20 PR5412 1 2 10_0603_5%
1/16W_10_1%_0402 ACP SRP
1 2 7 19 PR5413 1 2 10_0603_5%
BQ25710_VDD VDDA SRN
BQ25710_VDD

1
CHARGER_ILIM 6 28 1 2
ILIM_HIZ REGN 2021/4/29
PR5414 PU5401 PC5434 2.2U_10V_K_X5R_0402
255K_0402_1% 1 2 1 2 BQ25710RSNR QFN 32P_4X4
1 PC5423 1800P_25V_K_X7R_0201 PR5415 40.2K_0402_1% 16 17 1 2 1 2
PC5407 2 1 COMP1 COMP2 PR5416 10K_0201_1% PC5409 680P_25V_K_X7R_0201

2
1U_25V_K_X5R_0402 PC5417 33P_50V_J_NPO_0201 1 2
-PROCHOT_P 1 2 11 18 PC5437 15P_25V_J_NPO_0201

1
2 PR5417 0_0201_SP PROCHOT# CELL_BATPRES @ PR5421
PR5419 1 2 13 0_0402_5%
PD5403 79,87 EC_SMB_CK1 SCL 8 1 2
220K_0201_5% PR5418 0_0402_SP ADP_I 79
2 1 -PROCHOT_P 1 2 12 IADPT
79,95 VR_HOT_N 79,87 EC_SMB_DA1 SDA
PR5420 0_0402_SP 9 1 2

2
1 2 4 IBAT PR5422 0_0201_SP
1SS355VMTE-17 79 ACIN
PR5423 0_0402_SP CHRG_OK 10 1 2
PSYS 79,95
+3VALW VDDA
PSYS

1
100P_50V_K_X7R_0402
CHARGER_ENZ_OTG 5 PR5424 0_0201_SP PR5428 2021/4/20
ENZ_OTG 27 137K_0402_1%
PGND 2 2

1
15

PC5403
2

1
PR5426 CMPOUT 33 PC5422

PC5421
PAD

100P_50V_K_X7R_0402
1/20W_100K_1%_0201 14 100P_50V_K_X7R_0402 PR5432 PR5429

2
CMPIN 1 1 2021/4/20 1/20W_301K_1%_0201 1/20W_71.5K_1%_0201
PR5437 1

2
1
0_0402_SP PQ5704 D

2
1 2 2
B 79 ACOFF G B

S 2N7002KW_SOT323-3 PQ5402

3
PD5401 2N7002KW_SOT323-3

1
1SS355VMTE-17 D

1
PR5438 1 2 2
10K_0201_1% 79,87 BATT_TEMP G PR5434
2021/5/11 1/20W_100K_1%_0201

1
S
2

3
PR5435

2
1/20W_1M_5%_0201

2
A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_CHARGER
Date: Friday, September 03, 2021 Sheet 89 of 110
5 4 3 2 1

ACDECT setting 17.2V

Charge current limit HW=7A
DC discharge limit =26A
Discharge current limit HW=9A during Turbo boost

IDPM V(ILIM) PR5320

500mA 1.2V 402K IND IN USE PR5333 # of CELL VCELL_PRES PR5322
1.0A 1.4V 332K
1uH 93K 1-CELL 1.5V 301K
1.5A 1.6V 280K
2.0A 2.2uH 137K LOGIC 2-CELL 2.4V 150K
1.8V 237K
3.0A 2.2V 174K LOGIC 3.3uH 169K 3-CELL 3.3V 82K LOGIC
3.25A 2.3V 162K 4-CELL 4.5V 33.2K
4.0A 2.6V 162K
VILIM=1V+40x(VACP-VACN)=1+40xIDPMxRAC
 A B C D

1 1

2 2

3 3

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_DCC
Date: Friday, September 03, 2021 Sheet 90 of 110
A B C D
 A B C D

1
+3VALW 1

1
@
PR5601
100K_0402_1%
PU5601
@ SY8386BRHC_QFN16_2P5X2P5

2
PJ5601 2021/5/12 2021/5/3 2021/07/05
2 1 P_+3VALW_VIN_S 2 7 +3VALW_PWRGD PC5602
B+ 2 1 3 IN1 PG 1 P_+3VALW_BST1 2 +3VALW_PWRGD 79

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402
0.01U_0402_25V_X7R_0402
4 IN2 BS
1 1 1 1 1 1 IN3

PC5603
JUMP_43X79 PL5601

EMC@ PC5615

PC5601

PC5604

PC5613

PC5614
5 0.1U_25V_K_X7R_0402
6 LX1 15
@
2.2UH_PCMB063T-2R2MS_8A_20% PJ5602
2 2 2 2 2 2 14 GND1 LX2 16 P_+3VALW_LX_S 1 2 P_+3VALW_O 2 1
@ @ 17 GND2 LX3 2 1 +3VALW
GND3

1
PR5602 JUMP_43X79

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
P_+3VALW_EN 9 11 P_+3VALW_O 1/8W_2.2_5%_0805
EN1 OUT

1
8 EMC_NS@
P_+3VALW_VIN_S 2 1 EN2 10 P_+3VALW_FF

PC5605

PC5606

PC5607

PC5608
1 2
FF P_+3VALW_SN

PC5609

2
PR5607

1
12

0.1U_10V_K_X7R_0402
10K_0402_1% TEST 100mA

1
13 PC5610

1M_0402_5%
+3VLP Vout=3.338V+-1.5%

1
LDO

PR5604
1M_0402_5%
1000P_0402_50V_X7R_0402

PR5603
2021/5/5

2
@ 1 EMC_NS@ TDC=6A
PC5611 PC5612 PR5605 OCP=8A

2
4.7U_6.3V_K_X5R_0402 1000P_25V_K_X7R_0402 1K_0402_1%

2
2
2 1 2 P_+3VALW_FF_RC 1 2 OVP=(1.15~1.25)*Vout 2

Fsw=600KHz typ
@
PJ5603
2 1
USM mode: 1V <EN1<1.7V +3VLP 2 1 +3VL
PFM mode: 2V <EN1 JUMP_43X79
PR5609
0_0402_SP
1 2 P_+3VALW_EN

79 EC_ON_3VALW_R
1

PR5600
68K_0402_1%
2

P_+3VALW_USM_REF
1

PQ5600

2
79,92 EC_USM SSM3K15AMFV_2-1L1B
3
1

3
USM@ 3

PR5606
100K_0402_5%
2

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_3VALW
Date: Friday, September 03, 2021 Sheet 91 of 110
A B C D
 A B C D

+5VALW

1
PR5702
100K_0402_1%

2
1 1
79,93 +5VALW_PWRGD
10A
B+ +5VALW

@ PJ5701 PU5701
JUMP_43X79 EMC@ EMC@ SY8370C1TMC_QFN13_3X4
1 2
RF@ +5VALW_VIN 1 4 +5VALW_PGD
1 2 IN PG
1 13 +5VALW_BST 1 2 PC5705 PL5701 2021/5/14 2021/5/14 @ PJ5702

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
22U_B2_25VM_R100M

10P_0201_25V8G
2200P_25V_K_X7R_0402

0.1U_0402_25V4Z
BS 1.5UH_PCMB063T-1R5MS_10A_20% JUMP_43X79
1 1 2 2 EMC@ EMC@

2
+ 0.1U_25V_J_X7R_0402 1 2 +5VALW_P 1 2

PC5701

PC5706

PC5707

PC5702

PC5703

PC5708

PC5704

PC5725
1 2

2200P_25V_K_X7R_0402
1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
EMC_NS@ 1

0.1U_0402_25V4Z

150U_B2_6.3VM_R35M
2

1
2 2 2 1 1 2 +5VALW_LX
@ LX1 2 1 1 1 1 1 1 1 1

2
@ 3 PR5703 +

PC5709

PC5710

PC5711

PC5712

PC5713

PC5714

PC5715

PC5716

PC5717

PC5718

PC5719
GND1 12 1/4W_2.2_5%_0603
11 LX2

1
GND2 1 2 2 2 2 2 2 2 2 2
1 EMC_NS@ @ @ @ @ @ @
2021/5/5 +5VALW_EN1 6 PC5720
EN1 1200P_50V_K_X7R_0402
PR5708 8 +5VALW_P 2

1M_0402_5%
0.1U_0402_10V7K

1
0_0201_SP OUT
PC5724

1
1 2 +5VALW_EN2 5 PR5705

PC5721

PR5704
EN2 +5VALW_FF
2021/5/5
7 1 2 1 2
FF

2
@ 470P_0402_50V_X7R_0402 1K_0402_1%

2
USM mode: 1V <EN1<1.6V +5VALW_VCC 10
VCC LDO
9 +5VLP 2021/5/10
2
PFM mode: 2V <EN1 1 100mA
2

1M_0402_5%
1

1
PC5722
@ PR5709 4.7U_6.3V_K_X5R_0402 PC5723

PR5706
+5VALW_VIN 1 2 2 4.7U_6.3V_K_X5R_0402
2
0_0201_5%
Vout=5.15V+-1.5%

2
@
TDC=10A
OCP=14A
OVP=(1.15~1.25)*Vout
Fsw=600Khz

EC_ON pull high reserve at EC， PJ5703

@
2 1
no need USM enable=1.57V USM +5VLP 2 1 +5VL
PR5701
0_0402_SP JUMP_43X79
1 2 +5VALW_EN1

79 EC_ON_5VALW_R
1

3 PR5707 3

68K_0402_1%
2

P_+5VALW_USM_REF
1

PQ5703

2
79,91 EC_USM SSM3K15AMFV_2-1L1B
3

USM@

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_5VALW
Date: Friday, September 03, 2021 Sheet 92 of 110
A B C D
 5 4 3 2 1

B+

2
+5VL
PR3001
2.2_0603_5%

1
2 1 P_LV5116A_VCC_30 P_LV5116A_VSYS_10
2
PR3002 1
D
+5VALW 2.2_0603_5% PC3211 D
1U_0402_10V6K PC3212
1 0.1U_25V_K_X7R_0402 +5VALW
2 PJ6505
2 1 1 2
1 2 1A
2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR3003 JUMP_43X39
2.2_0603_5% PC3213
79,92 +5VALW_PWRGD
1 2 P_LV5116A_EN 1U_0402_10V6K PU3000 @
PR1511 0_0402_SP 1 LV5116AGQW_WQFN40_5X5
1 1
1 2 VTT_EN 6

PC6516

PC6517
8 CPU_DRAMPG_CNTL VSYS
PR3014 0_0402_SP 36 @
VCC
1 2 +1.8VALW_EN P_LV5116A_PVCC_30 4 27 P_+1.8VALW_VIN_S 2 2 +1.8VALW
79 EC_ON_1.8V PR3006 0_0402_SP PVCC V1P8A_IN
1 2 PR3004 P_VDDQ_UG_30 1 PJ6506
53,79,84 EC_ON_PCH @ PR3017 0_0402_5% 0_0603_SP VDDQ_HG
V1P8A_PH1
25 P_+1.8VALW_LX_S 1 2 +1.8VALW_P 1
1 2
2 4A
1 2P_VDDQ_BST_R_30 1 2 P_VDDQ_BST_30 40
VDDQ_BOOT

1
VDDQ_VPP_EN

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 2 26 PL6502 JUMP_43X79
79 EC_VPP_PWREN PR3008 0_0402_SP PC3215 V1P8A_PH2 2 1 PR6501 1UH_PCMB053T-1R0MS_7A_20%
0.1U_25V_K_X5R_0402 P_VDDQ_LX_30 2
VDDQ_PH V1P8A_SNS
29 +1.8VALW_P +3VALW 4.7_0603_5% @
PC3216 PJ3000 EMC_NS@
P_VDDQ_LX_SENS_10 39 9 P_VDDQ_VPP_IN 10U 6.3V M X5R 0402 1 2
1A 1 1 1 1

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

1 2
VDDQ_SWSNS VPP_IN 1 2 P_+1.8VALW_SN_30

2
P_VDDQ_LG_30 3 8 P_VDDQ_VPP JUMP_43X39 @ +VDDQ_OUT

PC3214

PC3223

PC3217

PC3210

PC6520

PC6521

PC6522

PC6523
VDDQ_LG VPP PJ3006 PC6524 2 2 2 2
13 P_VTT_IN_30 1A 1 2 1200P_50V_K_X7R_0402

2
P_VDDQ_SENS_10 12 VTT_IN 1 2
2 1 VDDQ_SNS 14 P_VDDQ_VTT EMC_NS@
@ @ @ @ @ JUMP_43X39
VTT
PC3218 @ 2 1 @ +0.6VS
0.1U_25V_K_X7R_0402 15
P_VCCIN_AUX_EN_10 23 VTT_SNS PC3219 PJ3004
AUX_DRVEN 10U 6.3V M X5R 0402 P_VDDQ_VTT 1
1 2
2 1A
28 P_LV5116A_DDR_ID_10
DDR_ID

10U 6.3V M X5R 0402

P_VCCIN_AUX_PWM_10 21 JUMP_43X79
AUX_PWM 1
20 P_LV5116A_AUX_CS_10 PR1501 1 2 300K_0402_1%

PC3220
AUX_CS @
PR1502 5 P_LV5116A_VDDQ_CS_10 PR3005 1 2 1/16W_240K_1%_0402 +3VALW +3VALW
0_0402_SP P_VCCIN_AUX_LXSENS_10 22 VDDQ_CS 2
1 2 P_VCCIN_AUX_VCCSENSE_10 AUX_SWSNS
20 VCCIN_AUX_VCCSENSE +VCCIN_AUX OCP=41A

2
P_VCCIN_AUX_VCCSENSE_1019 24 P_LV5116A_V1P8A_CTRL_10
AUX_SNS V1P8A_CTRL

2
PC1508 +VDDQ OCP=13A +2.5V_DDR
PR1505 1000P_0402_50V_X7R_0402 30 P_LV5116A_AUX_SET_10 PR1503 PR1504 PJ3005
0_0402_SP AUX_SET 100K_0402_5% 100K_0402_5% P_VDDQ_VPP 1 2
1A

1
1 2 P_VCCIN_AUX_VSSSENSE_10 1 2 P_LV5116A_PROCHOT_N 7 1 2
10,20,59,79 H_PROCHOT_N

1
20 VCCIN_AUX_VSSSENSE PROCHOT# VCCIN_AUX_VID0

22UC_6.3VC_MC_X5RC_0603
PR3007 0_0402_SP 16 JUMP_43X79
P_VCCIN_AUX_PG_1011 AUX_VID0 VCCIN_AUX_VID0 20,84
2021/4/22 +3VALW
1 2
PG_ARAIL
PR3009 100K_0402_5%
AUX_VID1
17 VCCIN_AUX_VID1 @
1 2 VDDQ_PGOOD 10 VCCIN_AUX_VID1 20,84
+3VALW PG_DDR

10U 6.3V M X5R 0402

C @ PR3010 100K_0402_5% 33 P_LV5116A_CLK_5 1 2 C

PC3221
SCL EC_SMB_CK3 76,79 1 1
PR3011 0_0402_SP

PC3222
79 VDDQ_PGOOD P_LV5116A_DAT_5
34 1 2 PR1506 PR1507
P_LV5116A_EN 38 SDA EC_SMB_DA3 76,79
PR3012 0_0402_SP 10K_0402_5% 10K_0402_5%
PMIC_EN @ @ 2 2

1
1 2 P_LV5116A_DIGITAL_CTL_10 37 @
@ PR3013 0_0402_5% DIGITAL_CTRL 18 P_VCCIN_AUX_VSSSENSE_10
1 2 +1.8VALW_EN 35 AUX_RGND +5VALW +5VALW +5VALW
+5VL SLP_SUS#
PR3015 0_0402_SP
VDDQ_VPP_EN 32 41

100K_0402_5%

100K_0402_5%
SLP_S4# GND

2
AUX_VID1 AUX_VID0 Vout_AUX

10K_0402_5%
VTT_EN 31
DIGITAL_CTRL Control Mode

PR3016

PR3018

PR3021
DDR_VTT_CTRL
@ 0 0 0V
High

1
P_LV5116A_DDR_ID_10 @
P_LV5116A_V1P8A_CTRL_10
HW Control P_LV5116A_AUX_SET_10 0 1 1.1V
Low SW Control

2
P_VCCIN_AUX_VIN_S 1 0 1.65V

0_0402_SP

10K_0402_5%

10K_0402_5%
B+ AUX_SET VCCIN_AUX Internal RAMP

PR3019

PR3020

PR1500
@ PJ1501
1 2 5.5A High RAMP1
1 1 1.8V

1
1 2 @ @

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
22U_B2_25VM_R100M
0.1U_25V_K_X5R_0201

P_VCCIN_AUX_BST_R_30 JUMP_43X118
PR1508 PQ1500
1 Low RAMP2 DDR_ID Type VPP VDDQ VTT/VDDQTX
EMC@ PC1501

PC1509

PC1502

PC1503

PC1514

PC1515
+5VALW 1 1 1 1
P_VCCIN_AUX_BST_30

0_0603_SP AON6380_DFN8-5 +
5

1 2 1 2
Floating RAMP3 Low DDR4 2.5V 1.2V VDDQ/2(VTT)
2

PC1500 2 2 2 2@ 2@
--
2

0.22U_25V_K_X5R_0402 Floating LPDDR4 1.8V 1.1V

PR1509
P_VCCIN_AUX_UG_30
4
2.2_0603_5% DIGITAL_CTRL V1P8A_CTRL V1P8A Sequence
PU1500
4
1 2021/4/26 2021/07/05 High LPDDR4X 1.8V 1.1V 0.6V(VDDQTX) B+
+VCCIN_AUX
1

P_VCCIN_AUX_VCC_30 8 BOOT PC1504

VCC 3 P_VCCIN_AUX_UG_30 High Low V1P8A follow PMIC_EN
2A
3
2
1

P_VCCIN_AUX_PWM_10 5 UGATE 2
2200P_0402_50V_X7R_0402 PJ3001
1U_0402_10V6K

PWM 2 P_VCCIN_AUX_LX_S 1 2 P_VDDQ_VIN_S 1 2

High High V1P8A follow SLP_SUS#

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
1

0.1U_25V_K_X7R_0402
P_VCCIN_AUX_EN_10 1 PHASE PL1502 1 2
PC1505

330U_B2_2.5VM_R9M
EN 7 P_VCCIN_AUX_LG_30 0.22UH_CMMS063T-R22MS2R107_26A_20%

5
LGATE 1 JUMP_43X39
6
Low Low V1P8A follow PMIC_EN

PC3201

PC3202
1 1 1
2

D
GND1
1

9 + @

PC1506

PC3200
EMC_NS@
GND2 PQ3000
2

PR1510 PJ1500 AONR32340C_DFN8-5

5

RT9610CGQW_WDFN8_2X2 1/8W_2.2_5%_0805 JUMPER Low High V1P8A follow I2C

PQ1501 2 P_VDDQ_UG_30 2 2 2
EMC_NS@ @ 4
1

AON6324_DFN8-5 G
2

S3
S2
S1
B P_VCCIN_AUX_SN_30 B
place close to VCCIN_ALX LMOS drain +VDDQ_OUT +1.2V
1

4
8A

3
2
1
PC1507
PL3000
1000P_50V_K_X7R_0201 PJ3002
2

Rdson=2.8mohm@Vth=4.5V P_VCCIN_AUX_LXSENS_10 P_VDDQ_LX_30 1 2 1 2

EMC_NS@ 1 2
PQ3001
3
2
1

0.47UH_PCMB053T-R47MS_13A_20% JUMP_43X118

5
AON7380_DFN8-5
@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
2
1 1 1 1 1 1
4.7_0603_5%

PC3203

PC3204

PC3205

PC3206

PC3207

PC3208
Vboot=1.8V Loadline=6mΩ

2
PR3000 PJ3007

2
P_VDDQ_LG_30 4 JUMPER @2 PJ3003
AC+DC Ripple=(-10%~+5%)*VOUT EMC_NS@ @ 2 2 2 2 2 JUMPER

1
P_VDDQ_SN_30
TDC=14A Iccmax=27A place close to VDDQ LMOS drain @

1
1
CURRENT LIMIT=45A

3
2
1
Rdson=10.5mohm@Vth=4.5V PC3209
1200P_50V_K_X7R_0402 add
Max Overshoot:2.13v/500us

2
EMC_NS@ JUMP？？？
OVP=(1.2~1.3)*Vref P_VDDQ_LX_SENS_10 P_VDDQ_SENS_10
UVP=(0.45~0.55)*Vref
Fsw=600Khz

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_Memory PMIC
Date: Friday, September 03, 2021 Sheet 93 of 110
5 4 3 2 1
 D

Rev
1.0

110
PWR_Memory PWR Decoupling
of
94
that connect to the outer row of SoC pins, use wide traces
Place on the primary side, as close as possible to the vias

Place on the primary side, as close as possible to the vias

to connect the capacitor pins to the vias. Make sure to

put atleast 1 via down near the outer Vdd2 BGA and

Sheet

PC3134
1U_6.3V_M_X5R_0201
CHANGE VDD2 MLCC 0625

Place them as close to the VR as possible.

2
that connect to the outer row of SoC pins

PC3135
Note

Friday, September 03, 2021

1 via down near the cap pad
2 caps should be stuffed.

1U_6.3V_M_X5R_0201
1

K14-TGL
Primary Side

@
Primary Side

PC3133
Document Number

1U_6.3V_M_X5R_0201
@

PC3123
1

10U 6.3V M X5R 0402

1

PC3132
Qty

1U_6.3V_M_X5R_0201
8

8
1

1
@

PC3121
Title

Date:
Size

10U 6.3V M X5R 0402

D

PC3131
1

1U_6.3V_M_X5R_0201
PDG: VDD2

2
10u_0402

47u_0603

1u_0402

@
Value

PC3122
10U 6.3V M X5R 0402 PC3139
MD_3T@ 4.3U_0402_4V6-M
1

3 4
PC3124 1 2
PDG: 2*47UF(0603)+ 8*10UF(0402)+8*1UF(0402)

2021/08/19

10U 6.3V M X5R 0402 PC3138

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

MD_3T@ 4.3U_0402_4V6-M
1

3 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LCFC Highly Confidential Information

PC3117
@

1U_6.3V_M_X5R_0201 1 2 PC7731
PC3137 1U_6.3V_M_X5R_0201
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1

MD_3T@ 4.3U_0402_4V6-M
1

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 4
PC3113
@

@
K14: 6*22UF(0603 P93)+ 1*10UF+8*1UF

1U_6.3V_M_X5R_0201 PC3119 1 2 PC7721

1U_6.3V_M_X5R_0201 PC3136 1U_6.3V_M_X5R_0201
@
1

PC3118 MD_3T@ 4.3U_0402_4V6-M

1

Deciphered Date

10U 6.3V M X5R 0402 3 4

PC3112
@
1

1U_6.3V_M_X5R_0201 1 2 PC7730
@

PC3102 PC3126 1U_6.3V_M_X5R_0201

1

1U_6.3V_M_X5R_0201 PC3116 1U_6.3V_M_X5R_0201

1

10U 6.3V M X5R 0402

1

PC7710
1

MD_3T@ 4.3U_0402_4V6-M
@

PC3110 PC3125 3 4
@

PC3107 1U_6.3V_M_X5R_0201 PC3114 1U_6.3V_M_X5R_0201

10U 6.3V M X5R 0402 10U 6.3V M X5R 0402 1 2
1

PC7739
1

MD_3T@ 4.3U_0402_4V6-M
PC3130 3 4
@

PC3106 PC3109 PC3120 1U_6.3V_M_X5R_0201

10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 1 2
1

2021/04/29
@
1

PC7720
@

PC3129 1U_6.3V_M_X5R_0201
@

PC3105 PC3111 PC3115 1U_6.3V_M_X5R_0201

1

10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402

1

@
1

PC7735
PC3128 1U_6.3V_M_X5R_0201
@

PC3104 PC3108 PC3103 1U_6.3V_M_X5R_0201

1

10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402

1

@
1

2
VDD2

PC7712
@

PC3127 1U_6.3V_M_X5R_0201
Security Classification
+1.2V

1U_6.3V_M_X5R_0201
1

2
1

PDG 2 Channel SODIMM: 1*330UF(7343)+16*10UF(0603)+16*1UF(0402)

Issued Date
@

PC7745
1U_6.3V_M_X5R_0201
1

2
@

PC7724
1U_6.3V_M_X5R_0201
Place Near CPU
2

2
1

2
@

PC7741
1U_6.3V_M_X5R_0201
1

2
@

PC7722
1U_6.3V_M_X5R_0201
1

PC7740
@

PC7746 10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201
1

2
1

2
K14: Channel A:8*10UF(0402)+ 16*1UF(0201)

PC7708
PDG 2 Channel SODIMM: 2*10UF(0603,1 placeholder)+4*1UF(0402)

PC7707 10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201
1

2
1

PC7717
PC7729 10U 6.3V M X5R 0402
1U_6.3V_M_X5R_0201
1

2
1

PC7732
PC7736 10U 6.3V M X5R 0402
@

PDG 2 Channel SODIMM: 2*10UF(0603)+2*1UF(0402)

PC7738 1U_6.3V_M_X5R_0201
1

1U_6.3V_M_X5R_0201
1

2
CHANNELB SLOT DIMM decoupling

PC7714
PC7719 10U 6.3V M X5R 0402
@

PC7727 1U_6.3V_M_X5R_0201
1

1U_6.3V_M_X5R_0201
1

2
1

K14: Channel A:1*10UF(0402)+ 1*1UF(0201)

PC7726
K14: Channel A:1*10UF(0402)+ 2*1UF(0201)

PC7737 10U 6.3V M X5R 0402

PC7716 1U_6.3V_M_X5R_0201
1

1U_6.3V_M_X5R_0201 PC7742
1

1U_6.3V_M_X5R_0201
1

PC7734
1

PC7706 10U 6.3V M X5R 0402

PC7715 1U_6.3V_M_X5R_0201
@

1U_6.3V_M_X5R_0201 PC7725
1

1U_6.3V_M_X5R_0201
1

PC7713
1

PC7744 10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201
1

2
1

2
VDDQ

PC7743 PC7723
1U_6.3V_M_X5R_0201 330U_B2_2.5VM_R9M
@

+1.2V

+1.2V

PC7711
1

10U 6.3V M X5R 0402

+
1

2
@

PC7733
10U 6.3V M X5R 0402
1

2
3

3
@

PC3069
1U_6.3V_M_X5R_0201
@

PC7705
@

10U 6.3V M X5R 0402 PC7709

10U 6.3V M X5R 0402
@
1

PC3065
1

1U_6.3V_M_X5R_0201
PC7718
1

2
VPP

10U 6.3V M X5R 0402 PC7728

+0.6VS
VTT

+2.5V_DDR

10U 6.3V M X5R 0402

1

2
+0.6VS

@
1

PC3061
1U_6.3V_M_X5R_0201
1

MD_3T@ PC3079
4.3U_0402_4V6-M
3 4
1 2
MD_3T@ PC3078
4.3U_0402_4V6-M
3 4
1 2

@
PC3074
1U_6.3V_M_X5R_0201

2
@
PC3073
1U_6.3V_M_X5R_0201

2
@
PC3072
1U_6.3V_M_X5R_0201

2
PDG 2 Channel SODIMM: 1*330UF(7343)+16*10UF(0603)+16*1UF(0402)

@
PC3071
1U_6.3V_M_X5R_0201

2
@
PC3070
PDG 2 Channel SODIMM: 2*10UF(0603,1 placeholder)+4*1UF(0402)

1U_6.3V_M_X5R_0201

2
@
PC3077
1U_6.3V_M_X5R_0201

2
@
PC3068
@ 1U_6.3V_M_X5R_0201
PDG 2 Channel SODIMM: 2*10UF(0603)+2*1UF(0402)

PC3035

2
1U_6.3V_M_X5R_0201
CHANNELA SLOT DIMM decoupling

@
1

2
4

4
PC3067 PC3086
@ 1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402
PC3081

2
K14: Channel A:8*10UF(0402)+ 16*1UF(0201)
1U_6.3V_M_X5R_0201
1

K14: Channel A:1*10UF(0402)+ 1*1UF(0201)

PC3066 PC3089
K14: Channel A:1*10UF(0402)+ 2*1UF(0201)

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402

PC3082

2
1U_6.3V_M_X5R_0201
1

PC3076 PC3092
PC3005 1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402
PC3036 1U_6.3V_M_X5R_0201

2
1U_6.3V_M_X5R_0201

2
1

PC3064 PC3091
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402

@
PC3004

2
1U_6.3V_M_X5R_0201

2
PC3063 PC3093
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402

2
@
PC3003
10U 6.3V M X5R 0402 PC3062 PC3090
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402

2
@
PC3002 PC3075 PC3088
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402

2
@

PC3097 PC3060 PC3087

@
10U 6.3V M X5R 0402 PC3057 1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402
10U 6.3V M X5R 0402
1

2
VDDQ
1

@
PC3059 PC3001

VPP
PC3094 PC3055 1U_6.3V_M_X5R_0201 330U_B2_2.5VM_R9M
VTT

+2.5V_DDR

+1.2V

+1.2V
10U 6.3V M X5R 0402 10U 6.3V M X5R 0402

2
+0.6VS

+0.6VS

+
5

5
D

A
 5 4 3 2 1

TGL
PU1000
RT3613EJGQW_WQFN32_4X4
TDC=36A
+5VALW P_VCCIN_VIN_S Iccmax=55A
PR1002
1/10W 6.2 1% 0603
PR1003
1/16W_2.2_1%_0402
OCP=91A
1 2 P_RT3613EE_VCC_20 24 8 P_RT3613EE_VIN_101 2
VCC VIN
2

1
PC1005 PC1006
4.7U_6.3V_K_X5R_0402 0.1U_25V_K_X7R_0402

2
1
D D

16 12 P_VCCIN_PWM1_10
79,89 VR_HOT_N VR_HOT# PWM1

RT3613EE_VREF
26 13 P_VCCIN_PWM2_10
VREF06 PWM2

1
PR1007
3.9_0402_1% 11
PWM3
1/16W_118K_1%_0402

P_VCCIN_VREF06_R_10
2 2
1

1
1
1.37K_0402_1%

42.2K_0402_1%

15K_0402_1%

P_VCCIN_Driver_EN_10
PR1011
PR1010

15
PR1008

PR1009

PC1009 DRVEN
2021/4/20

1
0.47U_0402_25V6K
1

PR1013 PR1052
PR1012
2

2
2

100K_0201_5% 2021/4/20 2.55K_0402_1% 2.55K_0402_1%

PR1014 4 P_VCCIN_ISEN1P_R_10 1 2 1 2 P_VCCIN_ISEN1P_10

1
110K_0402_1% ISEN1P
2021/4/22 2021/4/20

2
1 2 PR1015
1.4K_0402_1% PC1010
PR1016 0.1u_0201_10V6K

1
P_VCCIN_TSEN_R_10 1 2 P_VCCIN_TSEN_10 7 3 P_VCCIN_ISEN1N_R_10 1 2 P_VCCIN_ISEN1N_10

22
TSEN ISEN1N
PH1000 1/16W_680_1%_0402 2021/4/20
PC1016 PR1018 PR1053
100K_0402_1%_TSM0B104F4251RZ
P_VCCIN_SET1_10 22 0.1u_0201_10V6K 2.55K_0402_1% 2.55K_0402_1%

1
P_VCCIN_SET2_10 21 SET1 1 P_VCCIN_ISEN2P_R_10 1 2 1 2 P_VCCIN_ISEN2P_10

1
P_VCCIN_SET3_10 20 SET2 ISEN2P
SET3
2021/4/20

2
PR1019
PR1025 1.4K_0402_1% PC1017
18.2K_0402_1%
33K_0402_5%
1

1
1.15K_0402_1%

0_0402_SP PR1026 0.1u_0201_10V6K

18K_0402_1%

1
PR1023

PR1024

2 1 P_VCCIN_EN_10 9 2 P_VCCIN_ISEN2N_R_10 1 2 P_VCCIN_ISEN2N_10

PR1022
PR1021

2 2
79 EC_VR_ON VRON ISEN2N
1 1/16W_680_1%_0402

PC1018 PC1019
+5VALW
2

100P 25V J NPO 0201 14 0.1u_0201_10V6K

1
P_VCCIN_SET2_R_10 P_VCCIN_TSEN_REF_10 2 NC1 5 P_VCCIN_ISEN3NP_10
2021/4/22 @

1
ISEN3P
P_VCCIN_SETQ_R_10 P_VCCIN_SET3_R_10 PR1035
1

1 2 P_RT3613EE_VCC_20 100K_0201_5%
0_0402_SP

PR1033
PR1032

32
PR1031
PR1030

1/16W_113_1%_0402
1/16W_3K_1%_0402
1/16W_20_1%_0402

NC2 6 PR1034

2
ISEN3N 10K_0402_5%
ANS@
2

C C
P_RT3613EE_ANS_10

1
2021/4/20

1
PR1037
100K_0201_5%
PQ1004
P_SVID_VCLK_5 19 31 2

2
VCLK ANS_EN ANS@
@
SSM3K15AMFV_2-1L1B

3
P_SVID_DAT_5 18 28 EC_ANS 79
+VCCST_CPU VDIO VSEN PC1023
PC1022
100P_0402_50V8J 180P_25V_J_NPO_0402
1 2 1 2 EC_ANS=Low, Enable ANS
2

P_SVID_ALERT_N_5 17 29 P_VCCIN_COMP_10
@ PR1038 ALERT# COMP PR1039 PR1040
54.9_0402_1% 1 2 1 2 VCCIN_SENSE 18
1

54.9K_0402_1% 20K_0402_1%
10 30 P_VCCIN_FB_10
79 CPU_VR_READY B+

1
VR_READY FB
1 2 P_VCCIN_PSYS_10 2021/4/22 PC1024
79,89 PSYS
PR1041 0_0402_SP 1000P_0402_50V_X7R_0402 PJ1000
+5VALW

2
P_VCCIN_VIN_S 1 2
2021/4/21 1 2
1 2 23 27 VSSIN_SENSE 18
1

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
PSYS RGND

22U_B2_25VM_R100M
PR1042 1/16W_16K_1%_0402 1 2 P_VCCIN_BST1_RC_30
1 1 JUMP_43X118

1
P_VCCIN_IMON_NTC_10 1 2 PR1000 +

PC1001

PC1002

PC1003

PC1004
0.1U_25V_K_X5R_0201
1 @
2.2_0603_5% PQ1000
PH1001

2
PR1043 @ PC1061 0.1U_50V_K_X5R_0402 PC1000 AON6380_DFN8-5

2
1 2 2 1P_VCCIN_IMON_R_10 P_VCCIN_IMON_10 25 33 PR1001 2 2 2
IMON GND 0.22U_16V_K_X7R_0402
2K_0201_1% 2
2.2_0603_5%
100K_0402_1%_TSM0B104F4251RZ
PR1045
PU1001 4 +VCCIN
PR1044 4 P_VCCIN_BST1_30

1
RT3613EE_VREF 2 1 2 1 P_VCCIN_VCC1_30 8 BOOT Vcore_PH1
VCC 3 P_VCCIN_UG1_30
P_VCCIN_PWM1_10 1 2 P_VCCIN_PWM1_R_10 5 UGATE PL1006
18K_0402_1% 25.5K_0402_1%

1U_0402_10V6K

3
2
1
PWM 2 P_VCCIN_PH1_S 1 2
2021/4/22 PR1004 0_0402_SP
PHASE

1
P_VCCIN_Driver_EN_10 1 2 P_VCCIN_EN1_10 1 0.22UH_CMMS063T-R22MS2R107_26A_20%

PC1007
2021/4/22

1
EN

5
PR1005 0_0402_SP 7 P_VCCIN_LG1_30
6 LGATE PR1006 @ @

2
GND1 9 1/8W_2.2_5%_0805
GND2 EMC_NS@ PJ1001 PJ1002
JUMPER JUMPER
Virtual Symbol
RT9610CGQW_WDFN8_2X2

1
4 4 P_VCCIN_PH1_SN_S

P_VCCIN_ISEN1N_10
P_VCCIN_ISEN1P_10
1
PC1008
B 15W 25W 28W 1000P_50V_K_X7R_0201 B

3
2
1

2
3
2
1
PQ1001 PQ1005 EMC_NS@
PR1045 16.8K SD03416928J 12.1K SD03412128J AON6324_DFN8-5 AON6324_DFN8-5
28K SD000015J00 +VCCST_CPU
PR1044 24.3K SD000011300 21.5K SD03421528J 18.2K SD03418228J
1/16W_45.3_1%_0402

PR1043 11.8K SD000019S0T 14.3K SD00001DR00

1

2K SD00000TL0J
75_0402_1%

100_0402_1%

2021/7/14
1
PR1048

PR1047

PR1039 42.2K SD03442228J 20K SD03420028J

PR1046

54.9K SD00000H88J @ PC1025

1U_0402_6.3V6K
PR1008 200K SD03420038T 93.1K SD04110028J
2
2

PR1021 19.6K SD00000358J 22.6K SD000019W00 P_SVID_VCLK_5 1 2

VR_SVID_CLK 18 B+
2.37K SD03423718J 3.65K SD00000DN0J PR1049 0_0402_SP
PJ1003
P_VCCIN_VIN_S 1 2
1.8K SD00000R58J 1.33K SD00000RF0J P_SVID_ALERT_N_5 1 2 1 2
VR_SVID_ALERT_N 18 1

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

22U_B2_25VM_R100M
PR1011 178K SD03417838T 19.6K SD00000358J PR1050 0_0402_SP JUMP_43X118
+5VALW 1 1

0.1U_25V_K_X5R_0201
1
+

PC1012

PC1013

PC1014

PC1015
PR1024 8.45K SD000013J8T 14K SD00001VD00 @
P_SVID_DAT_5 1 2 P_VCCIN_BST2_RC_30
VR_SVID_DATA 18 1 2

2
5
PR1051 0_0402_SP PR1017 2 2 2
2.2_0603_5% 1 PQ1002

2
AON6380_DFN8-5
PR1020 PC1011
2.2_0603_5% 0.22U_16V_K_X7R_0402
PU1002 2 4 +VCCIN
4 P_VCCIN_BST2_30

1
P_VCCIN_VCC2_30 8 BOOT Vcore_PH2
VCC 3 P_VCCIN_UG2_30
P_VCCIN_PWM2_10 1 2 P_VCCIN_PWM2_R_10 5 UGATE PL1007
1U_0402_10V6K

3
2
1
PR1027 0_0402_SP PWM 2 P_VCCIN_PH2_S 1 2
1

P_VCCIN_Driver_EN_10 1 2 P_VCCIN_EN2_10 1 PHASE 0.22UH_CMMS063T-R22MS2R107_26A_20%

PC1020

EN

1
PR1028 0_0402_SP 7 P_VCCIN_LG2_30
LGATE

5
5
6 PR1029 @ @
2

2
GND1 9 1/8W_2.2_5%_0805
GND2 EMC_NS@ PJ1004 PJ1005
RT9610CGQW_WDFN8_2X2 JUMPER JUMPER

1
P_VCCIN_PH2_SN_S
4

P_VCCIN_ISEN2N_10
4

P_VCCIN_ISEN2P_10
1
PC1021
1000P_50V_K_X7R_0201

2
EMC_NS@

3
2
1
3
2
1
PQ1003 PQ1006
AON6324_DFN8-5 AON6324_DFN8-5

A A
2021/7/14

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_CPU PWR Controller
Date: Friday, September 03, 2021 Sheet 95 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_CPU PWR1
Date: Friday, September 03, 2021 Sheet 96 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_CPU PWR2
Date: Friday, September 03, 2021 Sheet 97 of 110
5 4 3 2 1
 D

Rev
1.0

110
of
98
PWR_CPU Decoupling
Sheet
Friday, September 03, 2021
1

1
K14-TGL
Document Number
Title

Date:
Size
C

22UC_6.3VC_MC_X5RC_0603
PC1089
@
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

22UC_6.3VC_MC_X5RC_0603
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

PC1088
@ 1

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2021/08/19

22UC_6.3VC_MC_X5RC_0603
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

PC1087
1

LCFC Highly Confidential Information

22UC_6.3VC_MC_X5RC_0603
PC1086
1

22UC_6.3VC_MC_X5RC_0603 1U_6.3V_M_X5R_0201
PC1085 PC1081
Deciphered Date
1

2
2

2
22UC_6.3VC_MC_X5RC_0603 1U_6.3V_M_X5R_0201
PC1084 PC1080
1

22UC_6.3VC_MC_X5RC_0603 1U_6.3V_M_X5R_0201
PC1083 PC1079
@ 1

2
2021/4/21

22UC_6.3VC_MC_X5RC_0603 1U_6.3V_M_X5R_0201
PC1082 PC1078
@ 1

2021/04/29
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201
PC1046 PC1077
1

@
Remove PC1076 PC1082 PC1061

22UC_6.3VC_MC_X5RC_0603 10U 6.3V M X5R 0402

PC1043 PC1045
2021/4/21

Security Classification
22UC_6.3VC_MC_X5RC_0603 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201
PC1050 PC1044 PC1075
1

Issued Date
@

10U 6.3V M X5R 0402 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201

PC1053 PC1058 PC1074
1

2
@

10U 6.3V M X5R 0402 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201

PC1051 PC1057 PC1073
1

2
@

@
3

3
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201
10U 6.3V M X5R 0402 PC1048 PC1072
PC1039
1

@
1

2
S360: 2*330UF(B2)+ 10*22UF(0603)+10*10UF(0402)+3*1UF(0201)

10U 6.3V M X5R 0402 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201

PC1038 PC1056 PC1071
1

2
@

10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201

PC1037 PC1070
INTEL Gen2 : 1*330UF(d2)+ 18*22UF(0603)+11*10UF(0402)

2
@

10U 6.3V M X5R 0402 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201

PDG: 2*220UF(7343)+ 10*22UF(0603)+12*10UF(0402)

PC1036 PC1042 PC1069

1

2
@

22UC_6.3VC_MC_X5RC_0603 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201

PC1035 PC1055 PC1068
1

@
22UC_6.3VC_MC_X5RC_0603 1U_6.3V_M_X5R_0201
PC1034 PC1067

frequency, assuming BW=1/4 of Fsw. Place board

with 150kHz VR bandwidth or 600kHz switching
MLCC cap recommendation based on VR solution

caps as close as possible to package in this order

Put them as directly below the BGAs as possible.
1

2
@

where 0402 to be closest to package pins:

22UC_6.3VC_MC_X5RC_0603 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201

VR->7343->0603->0402->Package
PC1033 PC1054 PC1066
1

Note
22UC_6.3VC_MC_X5RC_0603 1U_6.3V_M_X5R_0201
PC1032 PC1065

Secondary Side

Primary Side
1

@
4

4
22UC_6.3VC_MC_X5RC_0603 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201
PC1031 PC1052 PC1064
1

Qty

12
22UC_6.3VC_MC_X5RC_0603 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201

8
PC1030 PC1049 PC1063
1

(Place holder)
22UC_6.3VC_MC_X5RC_0603 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201

PDG: VCCIN

220u_7343

220u_7343
PC1029 PC1041 PC1062

10u_0402

22u_0603
1

@2

Value
22UC_6.3VC_MC_X5RC_0603
PC1028
1

2
VCCIN

2021/5/19

330U_B2_2.5VM_R9M
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201
PC1027
PC1040 PC1060
1

@2
+

330U_B2_2.5VM_R9M
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201
PC1026
PC1047 PC1059
1

@2
CHANGE VCCIN MLCC 0625

@
+
+VCCIN
5

5
D

A
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_PCH PWR1
Date: Friday, September 03, 2021 Sheet 99 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_PCH PWR2
Date: Friday, September 03, 2021 Sheet 100 of 110
5 4 3 2 1
 A
B
C
D

5
5

@
2
1
PC1571
1U_6.3V_M_X5R_0201

@
2 1 2 1

2
1
+VCCIN_AUX

PC1572 PC1566 PC1550

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603

@
2 1 2 1

2
1
PC1573 PC1567 PC1551
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603

@
2 1 2 1

2
1
PC1574 PC1568 PC1552
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603

@
2 1 2 1

2
1
PC1575 PC1569 PC1553
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603
VCCIN_AUX

@
2 1 2 1

2
1
PC1576 PC1570 PC1554
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603

@
2 1 2 1

2
1

4
4

PC1577 PC1522 PC1555

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603

@
2 1 2 1

2
1
PC1578 PC1542 PC1556
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603

@
2 1 2 1

2
1
PC1511 PC1547 PC1557
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603

@
2 2 1 2 1
1
2021/4/21

PC1521 PC1582 PC1584

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603
2 1 2 1

PC1523 PC1585

Issued Date
@
10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603
2
1

PC1512

Security Classification
1U_6.3V_M_X5R_0201
@

2 1 2 1
2
1
PDG: 1*220UF+ 3*47UF+12*22UF+25*10UF

PC1518 PC1558 PC1560

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603
@

2 1 2 1
S360: 1*330UF(P93)+ 8*22UF+10*10UF*0*1UF

2
1

PC1517 PC1524 PC1561

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603
@

2 1 2 1

3
3

2
1

PC1586 PC1583 PC1562

2021/04/29
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603
@

2 1 2 1
2
1

PC1580 PC1581 PC1563

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603
@

2 1 2 1
2021/4/21

2
1

PC1579 PC1513 PC1564

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603
@

2 1 2 1
2
1

PC1544 PC1549 PC1565

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603
@
@

2 1 2 1
2
1

PC1525 PC1536 PC1587

Deciphered Date

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603

@
@

2 1 2 1
2021/4/21

2
1

PC1559 PC1530 PC1588

1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 22UC_6.3VC_MC_X5RC_0603
@

2 1
2
1

PC1537 PC1546
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402
@

2 1
LCFC Highly Confidential Information

PC1540
2
2

2021/08/19

10U 6.3V M X5R 0402

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
CHANGE VCCIN_AUX 1UF(6---12) MLCC 0625

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size

Date:
Title

Document Number
K14-TGL

Friday, September 03, 2021

1
1

Sheet
PWR_PCH Decoupling
101
of
110
1.0
Rev
A
B
C
D
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_GPU PWR Controller
Date: Friday, September 03, 2021 Sheet 102 of 110
5 4 3 2 1
 A B C D

1 1

2 2

3 3

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_GPU PWR1
Date: Friday, September 03, 2021 Sheet 103 of 110
A B C D
 A B C D

1 1

2 2

3 3

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_GPU PWR2
Date: Friday, September 03, 2021 Sheet 104 of 110
A B C D
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_GPU PWR Monitor
Date: Friday, September 03, 2021 Sheet 105 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_GPU PWR Decoupling
Date: Friday, September 03, 2021 Sheet 106 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_VRAM PWR
Date: Friday, September 03, 2021 Sheet 107 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_VRAM PWR Decouping
Date: Friday, September 03, 2021 Sheet 108 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2021/04/29 Deciphered Date 2021/08/19 K14-TGL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Change List_PWR
Date: Friday, September 03, 2021 Sheet 110 of 110
5 4 3 2 1