CPS 310

Computer Organization II
Prof. Alex Ufkes

Topic 2: Instruction Set Architecture, ARC

 Notice!

Obligatory copyright notice in the age of digital

delivery and online classrooms:

The copyright to this original work is held by Alex Ufkes. Students

registered in course C/CPS 310 can use this material for the purposes
of this course, but no other use is permitted, and there can be no sale
or transfer or use of the work for any other purpose without explicit
permission of Alex Ufkes.

© Alex Ufkes, 2020, 2025 2

 Let’s Get Started!

© Alex Ufkes, 2020, 2025 3

 Last Week: History

© Alex Ufkes, 2020, 2025 4

 Last Week: Von Neumann Model

© Alex Ufkes, 2020, 2025 5

 Last Week: System Bus Model

© Alex Ufkes, 2020, 2025 6

 Last Week: Levels

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 Last Week: Binary Representation

0x A B C 1 2 3
3 x 160 = 3
1 x 20 = 1 2 x 161 = 32
0 x 21 = 0 1 x 162 = 256
1 x 22 = 4 12 x 163 = 49152
0 x 23 = 0
11 x 164 = 720896
0 x 24 = 0
10 x 165 = 10485760
1 x 25 = 32
37 11256099
© Alex Ufkes, 2020, 2025 8
 Last Week: Two’s Complement

1. Write the magnitude in binary. If the number is positive, stop here.

2. If the number is negative, Invert the bits (1s becomes 0s, 0s become 1s)
3. Add 1 (add 1 to the VALUE of the number, do NOT append 1)

© Alex Ufkes, 2020, 2025 9

 Last Week: IEEE-754

Convert -12.62510 to single precision IEEE-754 format

Convert to
-12.62510 -1100.1012 Use remainder method
target base:
Normalize: -1100.1012 -1.1001012 x 23 Leading 1 assumed, not
Fill in bit fields: • Number is negative, sign bit is 1 included in bit pattern
• Exponent is biased: 3+127 = 130
• Fill in fraction, dropping implied 1

1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0

© Alex Ufkes, 2020, 2025 10

 This Week

Instruction Set Architecture

• ISA view of the computer system
• Memory, CPU, instruction set
• SPARC, ARC ISA
• ARC Assembly language
• My first ARC assembly program
• ARCTools tutorial
• Lab 1

© Alex Ufkes, 2020, 2025 11

 Back to Levels

“The computer system can be considered at many levels”

Application programmers
operate here

Assembly language
programmer operates here

Computer system architect

operates everywhere

© Alex Ufkes, 2020, 2025 12

 Instruction Set Architecture (ISA)

“The computer system can be considered at many levels”

• The ISA view of a machine

corresponds to the machine code
and assembly language level
• We’ll look at the computer system
as viewed by the assembly
language programmer

© Alex Ufkes, 2020, 2025 13

 Instruction Set Architecture (ISA)

A compiler translates a High-Level Language (HLL), which

is architecture independent, into assembly language.

Language A -> Compile -> Language B

• Technically, A and B can be any two languages.

• Compile typically refers to translating an HLL into
assembly or machine code (or byte code).
• Assembly and machine code are architecture dependent

© Alex Ufkes, 2020, 2025 14

 Instruction Set Architecture (ISA)

An assembler translates assembly language programs into

executable binary programs (comprised of machine code)

In fully compiled languages (C, Fortran), binary code is

executed by target machine.

• Java compiler produces bytecode

• The JVM executes this bytecode, and the
target machine executes the JVM

© Alex Ufkes, 2020, 2025 15

 ISA Level: System Bus Model

ISA Level?

We’re going to consider computer architecture not from the perspective

of an HLL programmer, but rather an assembly programmer.

This is a lower-level view, considering properties that an HLL programmer

is rarely required to worry about.

© Alex Ufkes, 2020, 2025 16

 ISA Level: System Bus Model

Typical scenario:
• User writes program in HLL
• Compiler translates into assembly
• Assembler translates into
machine code, stored on disk.
• Prior to execution, program
loaded into memory.

(Of course, compiler and assembler are themselves compiled programs…)

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 ISA Level: System Bus Model

During execution:
• Instructions loaded into CPU from
memory one at a time
• CPU executes instruction, may
generate address
• Address placed on address bus,
received by memory.
• Buses not necessarily bi-directional • Memory writes data at that
• Memory does not generate addresses; address to the data bus
CPU does not receive addresses.

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 ISA: View of Memory

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 ISA Level: Memory

Computer memory:
• A collection of consecutively
numbered cells
• Each cell is typically one byte
• One byte == 8 bits
• We address at the byte level
• Can manipulate bits using bit
shifting, masking, etc.

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 ISA Level: Memory

Bit, byte, nibble typically mean the same

thing regardless of architecture

Word size:
• Depends on CPU
• 32 bits is common,
as is 64 bits
• Text lists 32 bits as
most common
• (it’s from 2007)

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 ISA Level: Memory

Memory is byte-addressable, but most data

types are larger than one byte

Consider an integer:
• 4 bytes, however…
• CPU writes the integer at a
single byte address in memory
• In what order do we write the
bytes to memory?

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 ISA Level: Big/Little Endian

In what order do we write the bytes to memory?

MSB LSB
00000000 01001001 11100111 01010101

Big-endian: Little-endian:
MSB stored at LSB stored at
00000000 01010101
lowest address lowest address
01001001 11100111
11100111 01001001
01010101 Multi-byte words are always 00000000
accessed by their lowest address
© Alex Ufkes, 2020, 2025 23
 ISA Level: Big/Little Endian

Big Endian Advantage?

• Matches how we’d read the number (in English, anyway) - Left to right

Little Endian Advantage?

• If we need to allocate an extra byte to a number as it grows.
• We don’t have to shift all the bytes over and add to the front.
• Simply add another byte to the MSB end, LSBs can stay put.

HOWEVER! The bits within a byte are always Big Endian

• Bits within a byte are always read left to right.

© Alex Ufkes, 2020, 2025 24

 ISA Level: Big/Little Endian

Little Endian: Big Endian:

• Intel x86 • Atmel AVR32
• AMD64 / x86-64 • IBM z/Architecture (mainframes)

Which to use? And why?

• Initially an arbitrary decision by hardware vendors.
• Choice sticks to this day to ensure backwards compatibility.

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 ISA Level: Memory Map

A memory map is a drawing

that shows how various regions
of memory are allocated

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 ISA Level: Memory Map

• ARC is the example architecture we

will use in the first part of the course.
• Lowest address is 0
• Highest is total_size - 1
• We can’t arbitrarily address into
memory, some portions are reserved
• I.e., OS location in memory

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 ISA Level: Memory Map

• Map includes both RAM and IO

• IO devices are treated like
memory locations
• Not actual locations in RAM!
• 0 to 231-1 = RAM location
• 231 to 232-1 = IO location
• Memory mapped IO

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 ISA Level: Memory Map

Flat Address Space:

• Address space refers to the numerical
range of memory addresses to which
the CPU can refer.
• A flat address space means a single
address space for everything.
• Main memory, IO, etc.
• Size of the address space is bounded
by the size of the address bus
• 32-bit address space? Max ~4GB
memory can be utilized.

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 Address VS Data

An address is a pointer to a location in memory

Data is the value at that memory location

8-bit data item at

32-bit address
address 00001003

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 Address VS Data

Word at address
32-bit address 00001003

ARC is big-endian:
• 32-bit word at address 0x00001000 is 0xAABBCCDD

© Alex Ufkes, 2020, 2025 31

 ISA Level: CPU

At minimum, a CPU has:

• Data section with registers and ALU
• Control unit for interpreting and
executing instructions
• Interface between control and data
units formed by two registers:
Program Counter (PC):
• Holds address of next instruction to
be fetched
Instruction Register (IR):
• Holds next instruction to be executed
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 Fetch-Execute Cycle

The control unit does the following, in sequence:

1. Fetch next instruction to be executed

o Indicated by the PC
2. Decode the opcode
o Depends on instruction set, coming up
3. Read operands from memory (if any)
4. Execute instruction and store results (if any)
5. Repeat from 1.

This is known as the fetch-execute cycle

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 Fetch-Execute Cycle

This is known as the fetch-execute cycle

Fetching simply refers to the retrieval of the next instruction,

as pointed to by the program counter.
Execution involves decoding the instruction and performing
whatever is required as indicated by the opcode.
Opcode? Operation code:
• Specifies what exactly the instruction is to do.
• Add two registers, load a register from memory, etc.

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 Opcodes: Simple Example

Consider the following hypothetical 16-bit processor:

Instruction format

Integer format

Internal CPU registers: Partial list of opcodes:

• Program Counter (PC) 0001 = Load AC from memory
• Instruction Register (IR) 0010 = Store AC to memory
• Accumulator (AC) 0101 = Add to AC from memory

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 Sample program fragment:
b=a+b

Partial list of opcodes:

0b0001 = 0x1 = Load AC from memory
0b0010 = 0x2 = Store AC to memory
0b0101 = 0x5 = Add to AC from memory

Values are in hexadecimal

How many fetch-execute cycles?

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 CPU: Control Unit

• The control unit coordinates all other units in

the process of executing an instruction
• Thought of as a “computer within a computer”
• It tells the ALU what to do with what registers,
loads registers, copies registers back to
memory, etc.

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 CPU: Datapath

Register File: Collection of registers

• Managed by control unit
• Register sizes correspond to word sizes
• Anywhere from a few to a few 1000

• Registers are addressable,

just like main memory.
• Orders of magnitude faster

© Alex Ufkes, 2020, 2025 38

 CPU: Datapath

• Control unit tells ALU what to

do, and with what registers.
• I.e., add registers 5 and 6,
store result in register 9.

• ALU updates status register.

• Indicate overflow, divide by
0, parity of result, etc.
• More on status register later
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 CPU: ALU

Control unit tells ALU what to do, and with what registers

What to do?
• ALU implements a variety of binary (2-operand)
and unary (1 operand) operations.
• Binary: Addition, bit-wise AND, bit-shift, etc.
• Unary: Arithmetic negation, bitwise NOT, etc.

• Control directs ALU based on instruction being executed

• Instruction indicates operation and source/destination registers
• Speaking of instructions….
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 Instruction Set

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 Instruction Set

• A collection of instructions that a processor can execute

• A processor is defined by its instruction set

Three main categories:

1. Data Movement
• Move data back and forth between CPU (registers) and memory or I/O
2. Arithmetic and Logic
• Perform operations on data that’s been moved into registers
3. Control
• Transfer control from one section of program to another.
• I.e., branching, calling subroutines, etc.

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 Instruction Set

Instruction sets can vary drastically between CPU families

• Instruction size (length)

• Operations supported/allowed
• Types of operands allowed
• Types of results provided

• Contrast this with HLL source code, typically need not change at all
between CPU architectures (just need to recompile).
• Given the right compiler, the same source code can be turned into
machine code compatible with any given CPU’s instruction set

© Alex Ufkes, 2020, 2025 43

 Instruction Set

Interesting exception?

• Java, once compiled into byte-code, can be used on

any platform that has a corresponding JVM.
• This is the whole point. Java code does not vary by
platform, the JVM does.
• JVM compiled for target architecture, Java code
compiled for JVM.

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 Instruction Set

• Because of the incompatibility between instruction sets,

computer systems are often identified by their CPU
• This provides an indication of program compatibility

Programs compiled for an IBM PC (or compatible) system use 80x86 instruction set

• These won’t run on a SPARC computer, or an IBM RS6000

• Both use different instruction sets.
Operating Systems complicate this further:
• Windows and Linux machines can have the same CPU
• A program compiled in Windows will not work out of the box in Linux.
• Different APIs, the way each OS interacts with hardware is different.
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 Putting it all Together

HLLs allow us to ignore architecture during coding.

System bus, memory, CPU, registers, instruction set?

• All things we must consider as assembly programmers.
• We’re not yet assembly programmers…?
• Time to change that

© Alex Ufkes, 2020, 2025 46

 Model Instruction Set: ARC

ARC (a RISC computer) is based on the Scalable Processor Architecture (SPARC)

SPARC is a RISC:
• Reduced Instruction Set Computer
• A small set of simple instructions
• Accesses memory through specific
load/store instructions, as opposed
to as a part of most instructions
• Contrast this with CISC…

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 RISC vs CISC

SPARC is a RISC: Reduced Instruction Set Computer

CISC: Complex Instruction Set Computer

• Instead of a small set of general instructions…
• Large set of highly specific instructions.
• A single CISC instruction might accomplish
several things at once:
o Load from memory
o Perform arithmetic
o Store result back to memory

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 RISC vs CISC

A single CISC instruction might accomplish several things at once:

o Load from memory

One instruction cycle o Perform arithmetic
o Store result back to memory

HOWEVER!
• Instruction cycle != CPU cycle
• One single instruction might take multiple
CPU cycles to complete.
• Especially true of CISC architectures.

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 RISC vs CISC

HOWEVER!
• Instruction cycle != CPU cycle
• One single instruction might take multiple
CPU cycles to complete.
• Especially true of CISC architectures.

Contrast with RISC:

• Smaller set of general instructions
• Separate instructions for loading, arithmetic, and storing.
• Fewer CPU cycles per instruction

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 RISC vs CISC

Architectures most commonly considered RISC vs CISC:

RISC: CISC:
• SPARC • IBM System/360
• Atmel AVR • IBM z/Architecture
• ARM • Motorola 6800, 6809
• Power ISA • Intel 8080, x86

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 RISC vs CISC

(One of) the world’s fastest supercomputer uses RISC (and runs Linux):

© Alex Ufkes, 2020, 2025 52

 Model Instruction Set: ARC

ARC (a RISC computer) is based on the Scalable Processor Architecture (SPARC)

Not to be confused with: ARC (Argonaut RISC Core)
Interestingly:
• Argonaut Games was a British videogame company.
• Their ARC concept was originally designed for the
SuperFX chip on the SNES

© Alex Ufkes, 2020, 2025 53

 Model Instruction Set: ARC

ARC (a RISC computer) is based on the Scalable Processor Architecture (SPARC)

ARC ISA is a subset of SPARC ISA

ARC has most of the important features of SPARC, without the

complex aspects required in a commercial processor

Easier to learn and understand! Yay!

© Alex Ufkes, 2020, 2025 54

 ARC ISA: Memory

ARC ISA:
• Memory
• CPU Registers
• Instruction set

© Alex Ufkes, 2020, 2025 55

 ARC ISA: Memory

ARC ISA: 32-bit system

• Memory • Can manipulate 32-bit data types
• CPU Registers • This includes addresses!
• Instruction set • Cannot address beyond 32-bits
• 64GB memory? Doesn’t matter!
• Can only reference first ~4GB

© Alex Ufkes, 2020, 2025 56

 32- vs 64-Bit: A Quick Aside

• Architecture may support 64-bit computing.

o 64-bit registers, 64-bit address bus, etc.
• It’s still up to program(s/mers) to take advantage

Famous gaming example:

• Home computers have been 64-bit since early 2000s
• Windows has been 64-bit since XP (2001)
• Skyrim was 32-bit on release (2011!)
• Could only utilize ~4GB of memory,
• Insufficient for HD textures, user modding scene.
• The outcry was swift and belligerent.

© Alex Ufkes, 2020, 2025 57

 ARC ISA: Memory

ARC ISA: 32-bit machine:

• Memory • Can manipulate 32-bit data types
• CPU Registers • This includes addresses!
• Instruction set
Memory is byte-addressable:
• All data is stored as bytes
• Multi-byte types are big-endian
• Address of 32-bit word is address
of the byte with lowest address
32-bit address space:
• Divided into distinct regions

© Alex Ufkes, 2020, 2025 58

 ARC ISA: Memory

ARC ISA: 32-bit address space:

• Memory • Divided into distinct regions
• CPU Registers Lowest 2048 (211)
• Instruction set addresses reserved for OS

User space:
• User’s assembled
program loaded here
• Can grow until it meets
system stack

© Alex Ufkes, 2020, 2025 59

 ARC ISA: Memory

ARC ISA: 32-bit address space:

• Memory • Divided into distinct regions
• CPU Registers
User space:
• Instruction set
• User’s assembled
program loaded here
• Can grow until it meets
system stack

System stack
• Starts at word 231-4
• Grows “downward” until
it meets user space
© Alex Ufkes, 2020, 2025 60
 ARC ISA: Memory

ARC ISA: 32-bit address space:

• Memory • Divided into distinct regions
• CPU Registers User space:
• Instruction set • From 2048 up

System stack
• From 231-4 “down”

Accommodates:
• Small program, large stack
• Large program, small stack

© Alex Ufkes, 2020, 2025 61

 ARC ISA: Memory

ARC ISA: 32-bit address space:

• Memory • Divided into distinct regions
• CPU Registers
• Instruction set IO Devices:
• 231 to 232-1
• Each IO device has some
address range assigned to it.
• Memory-mapped IO

© Alex Ufkes, 2020, 2025 62

 ARC ISA: User-Visible Registers

ARC ISA:
• Memory
• CPU Registers
• Instruction set

© Alex Ufkes, 2020, 2025 63

 ARC ISA: User-Visible Registers

ARC ISA:
• Memory User-visible?
• CPU Registers • Registers we can access as an
• Instruction set assembly programmer
• Note we can’t access the IR!
• IR is loaded based on PC,
which we do have access to.
• %r0, %r1, etc. are mnemonics
• Names we can use in assembly
programs to access registers

© Alex Ufkes, 2020, 2025 64

 ARC ISA: User-Visible Registers

ARC ISA: ARC Registers:

• Memory • 32, 32-bit registers
• CPU Registers • %r1-%r31 are general purpose
• Instruction set • %r0 always contains 0
• %r14 doubles as stack pointer
• %r15 doubles as link register
• More on these later
Program Counter: %pc
• Contains address of next
instruction to execute

© Alex Ufkes, 2020, 2025 65

 ARC ISA: User-Visible Registers

ARC ISA: Processor Status Register: %psr

• Memory • Contains info about CPU state
• CPU Registers • PSR format varies by CPU
• Instruction set • CPU state includes things like…
Arithmetic Results:
• 1-bit condition code in PSR can
indicate a result of zero, negative
result, overflow, etc.
• Also, the carry-out bit of the ALU

© Alex Ufkes, 2020, 2025 66

 ARC ISA: User-Visible Registers

ARC ISA: Processor Status Register: %psr

• Memory • Contains info about CPU state
• CPU Registers • PSR format varies by CPU
• Instruction set • CPU state includes things like…
Support for Traps
• Traps are a mechanism for
interrupting normal processing
• Result of exception or interrupt
• (these have no universal meaning)

© Alex Ufkes, 2020, 2025 67

 ARC ISA: User-Visible Registers

ARC ISA: Support for Traps

• Memory • Result of exception or interrupt
• CPU Registers • (these have no universal meaning)
• Instruction set • Adopt SPARC standard:

Exception: Condition making it impossible

for CPU to continue executing without
software intervention.
Interrupt: Request for CPU attention
by external device
More on traps later.
© Alex Ufkes, 2020, 2025 68
 ARC ISA: Instruction Set

ARC ISA: Some miscellanea before ARC assembly:

• Memory • SPARC has ~200 instructions, ARC a subset of that
• CPU Registers • All ARC instructions are 32 bits long (1 word)
• Instruction set
ARC is a Load-Store machine:
• Before an ARC instruction can access operands, they
must be loaded into registers
• This is accomplished by a Load instruction
• I.e., we can’t simply add 5 and 7. Values 5 and 7 must
first be loaded into registers.
• Ditto storing results. Result is placed in a register, a
separate Store instruction writes it to main memory.
© Alex Ufkes, 2020, 2025 69
 ARC ISA: Instruction Set

ARC ISA: Some miscellanea before ARC assembly:

• Memory • SPARC has ~200 instructions, ARC a subset of that
• CPU Registers • All ARC instructions are 32 bits long (1 word)
• Instruction set
ARC (and SPARC) are Two’s Complement machines
• (as are nearly all general-purpose machines)
• Arithmetic integer operations (add, subtract, etc.)
read their operands as 2’s comp.

© Alex Ufkes, 2020, 2025 70

 ARC Assembly Language

© Alex Ufkes, 2020, 2025 71

 My First Assembly Program

.begin
.org 2048 This program performs:
prog1: ld [x], %r1 z = x + y
ld [y], %r2
addcc %r1, %r2, %r3
Let’s see how to read it
st %r3, [z]
halt
x: 15
y: 9
z: 0
.end

© Alex Ufkes, 2020, 2025 72

 ARC Assembly Language

Format is the same as SPARC:

Quick reminder:
• HLLs (depends on the language) get compiled into assembly
o Assembly is architecture specific, high-level languages are not.
• Assembly gets assembled by the assembler into machine language
• Machine language = binary bit strings loaded and decoded by the CPU
• One to one mapping between assembly and machine instructions!
• Not the case with HLLs, compiler might optimize many different ways.
© Alex Ufkes, 2020, 2025 73
 ARC Assembly Language

• Mnemonics are names for specific instructions

• Instead of a series of machine language opcodes
we have a name.
• Descriptive, easier to read and intuit meaning.
© Alex Ufkes, 2020, 2025 74
 ARC Assembly Language

• Nature of operands depends on the instruction.

• Contents of register + contents of register
• Contents of register + constant

© Alex Ufkes, 2020, 2025 75

 ARC Assembly Language

• Destination = register in which to store the result.

• If we want to save the result to memory, we need
to execute a subsequent store instruction.

© Alex Ufkes, 2020, 2025 76

 ARC Assembly Language

• Denoted with a !
• Comments in assembly serve
the same purpose as HLLs

© Alex Ufkes, 2020, 2025 77

 ARC Assembly Language

• Labels must be followed by a colon

• Label is NOT the same as variable!
• We can use labels to loop and branch.
• Like GOTO in C (bad form in HLL)

© Alex Ufkes, 2020, 2025 78

 ARC Assembly Language

“We can use labels to branch and call subroutines”

Branching sneak peak. Much more on branching later.

© Alex Ufkes, 2020, 2025 79

 ARC Assembly Language

lab_3: addcc %r1, 12, %r3 ! Register + Constant

! Set condition codes

Is the result zero? Negative? Overflowed? Etc.

© Alex Ufkes, 2020, 2025 80

 ARC Assembly: Numbers

• Numbers in ARC assembly are treated as being in base-10

• If we want to use a hex number, include the 0x prefix.
• This constant is called an immediate constant.

© Alex Ufkes, 2020, 2025 81

 ARC Assembly: Numbers

Immediate constants:
• Can be used immediately, don’t need to load into register first
• Number is baked right into the instruction.
Implications?
• Immediate constants are limited to 13 bits.
• Why? The whole instruction is 32 bits. Can’t have a full 32-bit number
• Immediate constants have a range of -4096 to 4095
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 ARC Assembly: Numbers

• Immediate constants are sign-extended to 32-bits to be used by the ALU

• Meaning: left-most bit of 13-bit immediate constant is copied leftwards
until the number is 32 bits:
+12 = 0 0000 1100 = 0000 0000 0000 0000 0000 0000 0000 1100
-12 = 1 1111 0100 = 1111 1111 1111 1111 1111 1111 1111 0100
This does not affect the value. Same in base 10: 99 == 099 == 00000099
© Alex Ufkes, 2020, 2025 83
 ARC Assembly: Load & Store

• Note the [] around source operand

• Indicates loading from the address contained in register
• lab_4 and lab_5 – address/pointer arithmetic!
• Needed to support HLL concepts like arrays and structs
© Alex Ufkes, 2020, 2025 84
 ARC Assembly: Load & Store

• Note the [] around destination operand

• Indicates storing to the address contained in register

© Alex Ufkes, 2020, 2025 85

 ARC Assembly: Simple Example

.begin
.org 2048
prog1: ld [x], %r1
ld [y], %r2 • x, y, z are labels corresponding
addcc %r1, %r2, %r3 to some address value
st %r3, [z] • %r1, %r2, %r3 are registers
halt
x: 15
y: 9
z: 0
.end

© Alex Ufkes, 2020, 2025 86

 ARC Assembly: More of the ISA

• Here’s a portion of the ARC ISA

• We’ll see more as we go

© Alex Ufkes, 2020, 2025 87

 ARC Assembly: More of the ISA

Complete set of instructions recognized by ARCTools:

halt
© Alex Ufkes, 2020, 2025 88
 ARC Assembly: VS Machine Instructions

We’ve gotten a taste of how assembly language instructions are composed:

• The assembler translates these into machine language

• What does the actual machine language look like?

© Alex Ufkes, 2020, 2025 89

 add,
addcc

ld, st

© Alex Ufkes, 2020, 2025 90

 rs1: first source register

If instruction
begins with 10, it
is Arithmetic
i = 0: 2nd operand in register
rd: Destination register i = 1: 2nd operand is 13-bit
• 5 bits, we have 32 registers op3: Choose sign extended value
• Represent values 0-31 operation
© Alex Ufkes, 2020, 2025 91
 If instruction op3: Choose
begins with 11, it operation
is Memory

rd: Register
• Load into i = 0: Address = rs1 + rs2 (register + register)
• Store from i = 1: Address = rs1 + simm13 (register + immediate constant)
© Alex Ufkes, 2020, 2025
Address from single register? Use %r0 for either rs1 or rs2 92
 Assembly is daunting enough for most programmers, never mind
composing and decoding machine instructions.

Then again, going from Python to C is daunting for most programmers.

Don’t be deterred. The initial learning curve is steep, but it gets

easier once you understand the fundamentals.

© Alex Ufkes, 2020, 2025 93

 ARC Pseudo-Ops

We’re almost ready to write

our first assembly program
Pseudo-Ops:
• Instructions to assembler.
• Not part of the ISA.
• Tell the assembler to do
something at assembly time.
• We’ll see how to use these
as we go

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 ARC Pseudo-Ops

Pop Quiz:
What is significant
about 2048?

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 My First Assembly Program

.begin
.org 2048 • Set location counter to 2048
prog1: ld [x], %r1 • We can change this
ld [y], %r2 throughout our program
addcc %r1, %r2, %r3 • Dictate where things are
st %r3, [z] stored in memory.
x: 15 • I.e., place a large array higher
y: 9 up in the address space.
z: 0
.end

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 My First Assembly Program

.begin Start of program labelled prog1

.org 2048
prog1: ld [x], %r1
ld [y], %r2
addcc %r1, %r2, %r3
st %r3, [z] • Labels x, y, z correspond to
x: 15 locations in memory
y: 9 • Addresses!
z: 0 • Hence the [ ] when we use
.end them in our load and store
instructions

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 My First Assembly Program

.begin
.org 2048 • Load value at address x into register 1
prog1: ld [x], %r1 • Load value at address y into register 2
ld [y], %r2
addcc %r1, %r2, %r3
st %r3, [z]
x: 15 • Add contents of registers 1 and
y: 9 2, place result in register 3.
z: 0 • Store contents of register 3 at
.end memory location z

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 Register
Contents

Memory

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© Alex Ufkes, 2020, 2025 100
 Machine instructions corresponding
to assembly statements

• Addresses in Hex and Decimal

• Machine words at those addresses
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 Let’s decode this!

Address Contents

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 0x c2002810 ld [2064], %r1

0b 1100 0010 0000 0000 0010 1000 0001 0000

0b 11 00001 000000 00000 1 0100000010000

Here we have:
rd = 1
rs1 = 0
simm13 = 2064

i = 1: Address = rs1 + simm13 (register + immediate constant)

Address from single register? Use %r0 for either rs1 or rs2
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 Let’s decode this!

Address Contents

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 0x 86804002 addcc %r1, %r2, %r3

0b 1000 0110 1000 0000 0100 0000 0000 0010

0b 10 00011 010000 00001 0 00000000 00010
Here:
rd = 3
rs1 = 1
rs2 = 2

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 • Decode the other
instructions yourself
• It’s good practice

Address Contents

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 • Step through the program
one instruction at a time.
• Observe the changing
register values

View addresses (Loc)

as hex or decimal

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 • Step through the program
one instruction at a time.
• Observe the changing
register values

© Alex Ufkes, 2020, 2025 108

 • Step through the program
one instruction at a time.
• Observe the changing
register values

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 • Step through the program
one instruction at a time.
• Observe the changing
register values

• We stored %r3
back to memory.
• 0x18 == 24

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 Ok what about…
• sethi is an instruction for
setting the 22 MSBs
• At 2064, we set the top 22
bits of r0 to 15
• Except… r0 is always zero
and can’t be changed
• In effect, this will do
nothing if executed.
• 2064, 2068, 2072 are used for numeric data • It’s data, not meant to be
• Decoding them as instructions yields sethi executed anyway!
• Actually… it doesn’t quite. Not sure why
ARCTools interprets it this way.

© Alex Ufkes, 2020, 2025 111

 Week 2: Summary

Instruction Set Architecture

• ISA view of the computer system
• Memory, CPU, instruction set
• SPARC, ARC ISA
• ARC Assembly language
• My first ARC assembly program
• ARCTools tutorial
• Lab 1

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 Lab #1

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