0% found this document useful (0 votes)
119 views14 pages

Low-Frequency Model for N-Channel Transistor

This document is a class test for VLPE 104 on Analog Integrated Circuit Design, consisting of various questions related to MOSFET operation, circuit analysis, and amplifier design. It includes calculations for device parameters, voltage gain, and output resistance, as well as theoretical explanations of MOSFET behavior. The test covers practical applications and fundamental concepts in analogue circuit design.

Uploaded by

rajarajisr06
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
119 views14 pages

Low-Frequency Model for N-Channel Transistor

This document is a class test for VLPE 104 on Analog Integrated Circuit Design, consisting of various questions related to MOSFET operation, circuit analysis, and amplifier design. It includes calculations for device parameters, voltage gain, and output resistance, as well as theoretical explanations of MOSFET behavior. The test covers practical applications and fundamental concepts in analogue circuit design.

Uploaded by

rajarajisr06
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 14

CLASS TEST 2 – 2012

VLPE 104 ANALOGUE INTEGRATED CIRCUIT DESIGN


Time – 1 hour
Full Marks - 100
Answer Question No. 1 which is compulsory and any four from the rest.
The figures in the right hand margin indicate marks

Q.1. Answer the following questions: (2×10)


(a) An n-channel MOS device in a technology for which oxide thickness is 20 nm,
minimum gate length is 1 µm, kʹn =100 µA/V2, and VTn = 0.8 V operates in the triode
region, with small vDS and with gate-source voltage in the range of 0 V to +5 V. What
device width is needed to ensure that the minimum available resistance is 1 kΩ?
Answer: We know that the drain current in the triode region is given by:
 W  1 
I Dn k 'n    VGS  VTn VDS  VDS2 
 L  2 
V 1
rDS  DS 
W  iDn W 
iDn  k 'n   VGS  VTn VDS k 'n   VGS  VTn 
vDS  L  L
For small , and
rDS 1 k
For , with VGS = 5 V, VTn = 0.8 V, kʹn =100 µA/V2, and gate length L = 1 µm, we have
1 1
rDS   1103 
W  W 
k 'n   VGS  VTn  100 10  6   5  0.8
 L  1
Solving for W we get, W = 2.4 µm.
(b) For the circuit shown in Figure Q.1(b) below following parameters are given:
 nCox  nCox 40 A V 2 , VThn  VThp 1 V , n  p 0.01 , I Q 1 mA ,
V
Av  O
determine the voltage gain Vi .

Figure Q.1(b) Figure Q.1(c)


Answer: The small-signal equivalent circuit is as shown below:

g m1
The transconductance is given by
W 
g m1  2 p Cox   I Q  2 40 10  6 100 110  3 2.8 mA V
 L 1
r r
The output resistances of the two transistors O1 and O 2 are given by
1 1
rO1 rO 2   100 k
I Q 0.01110  3
VO
Av 
Therefore, the voltage gain Vi is given by
V
Av  O  g m1 rO1 || rO 2   2.8 10  3 50 103  140
Vi
(c) Consider the MOSFET voltage divider circuit shown in Figure Q.1(c) above. Assume
that both the MOSFETs operate in the saturation region. Determine the output voltage
VO V
as a function of the supply voltage S , the gate voltages VA and VB , and the
MOSFET geometries L1 , W1 and L2 , W2 . Assume that the MOSFET threshold
voltage is Th , and remember that K  nCox W L   K n W L  for n-type MOSFET.
V
V
Answer: Since the current through both the MOSFETs must be the same, O is forced to a value
such that this is the case.
K nW2
VB  VTh 2  K nW1 VA  VO  VTh 2
2 L2 2 L1
W2 L1
VO VA  VTh  VB  VTh 2
L2W1
 .
(d) Draw the cross-sectional view of an n-channel MOS transistor. Label the necessary
parts
L, W , tox, D, G, S, etc . Explain, in brief, how an n-channel enhancement
mode MOS transistor operates.
Answer: The cross-sectional view of an n-channel MOS transistor is as shown below:
With zero bias between the gate (G) and the source (S), the current is zero since the substrate
V
separates the drain (D) and the source (S) regions. As GS increases, an electron inversion layer is
V V
created at the gate oxide below the gate. After GS increases beyond a threshold voltage Th , the
V 0
electron inversion layer connects the D and S terminals so that current may flow if DS . Source
terminal supplies electrons which are drained by the drain terminal where the magnitude of current is
I 0
a function of applied gate voltage. Essentially, G and
 1 W 
  nCox   VGS  VTh 2 for VDS  VGS  VTh saturation 
2  L
I D 
 nCox  W   VGS  VTh VDS  1 VDS2  for VDS  VGS  VTh triode region 
  L   2 
.
(e) Explain with the help of a suitable example, why MOSFETs are usually operated in
saturation region when used for amplification.
Answer: We know that the intrinsic voltage gain of a MOSFET is directly proportional to its
transconductance gm. Now let us consider the arrangement shown in the Figure (a) below
and study the variation of the transconductance as a function of VDS.

Figure (a) Figure (b)


We note that so long as VDS ≥ Vb – VTH, transistor M1 is in saturation, ID is relatively constant, and, gm
is given by
W 2I D
g m  2  nCox I D 
L VGS  VTH .
For VDS ≤ Vb – VTH, transistor M1 is in the triode region and
gm 
 1
  nCox
VGS  2
W
L
  W
2VGS  VTH VDS  VDS2    nCox VDS
L
 .
Thus, as plotted in Figure (b) above, we observe that the transconductance drops if the device enters
the triode region. Therefore, MOSFETs are usually operated in saturation region when used for
amplification.
V Veff
(f) Verify that when DS is used in the triode equation for a MOS transistor, the
 C W 
I D  n ox   VGS  VTh 
2

current equals that of the active region equation given by 2  L .


Answer: The current equation in the triode region is given by
 W  V2 
I D   nCox    VGS  VTh VDS  DS 
 L  2 
VDS Veff VGS  VTh
But, if , then we have,
 W  V2 
I D   nCox    VGS  VTh VDS  DS 
 L  2 
 W  1 2
  nCox    VGS  VTh   VGS  VTh  
2

 L  2 
 nCox  W 
  VGS  VTh 
2

2  L
V Veff
which is equal to the current equation in the active region. Thus it is verified that when DS is
used in the triode equation for a MOS transistor, the current equals that of the active region equation
 C W 
I D  n ox   VGS  VTh 
2

given by 2  L .
(g) For the common-source amplifier shown in Figure Q.1(g) below following parameters
I 100 A RS 1 k RL 10 k VThn 1 V  nCox 50 A V 2
are given: SUP , , , , ,
1
n 0.1 V @ L = 1.5 µm, and r = ∞. Choose the length L for the NMOS such that
oc

the Common-Source Amplifier has an output resistance of 250 k.

Figure Q.1(g) Figure Q.1 (h)


1
Rout ro  100 k @ L 1.5 m
Answer: We know that Rout ro is given by I D . We are
given a value of λ at a length of 1.5 µm. Using a length of 1.5 µm, we find that the output
resistance is 100 kΩ. We need an output resistance of 250 kΩ, or 2.5 times what is
provided by a length of 1.5 µm. Since λ is inversely proportional to length, increasing the
length by a factor of 2.5 will result in the necessary output resistance. So the length L for
the NMOS will be L = 3.75 µm so that the Common-Source Amplifier has an output
resistance of 250 k.
(h) An amplifier according to Figure Q.1(h) above is realized in the 0.35 m process. In the
calculations, use long channel equations and neglect all capacitances except the load. Find
V
the input voltage in at which the both the transistors are in the active region. (Hint: Set
the drain currents equal). Assume: T 0 n
V 0.6 V , VT 0 p  0.6 V ,  nCox 115 A V 2 ,
 pCox 40 A V 2
and .
Answer: We can calculate the two drain currents and then set them as equals. Thus, we have
1 W  1
I Dp   p Cox   VGSp  VT 0 p   40 10  6 302.2  3.0  0.6 24
2 2

2  L p 2
A
1 W  1
I Dn   nCox   VG  VT 0 n   115 10  6 10Vin  VT 0 n 
2 2

2  L p 2
A
24 10  6
Vin  VT 0 n   1
0.204
115 10  6 10
I Dn  I Dp 2
 V
Vin 0.204  VT 0 n 0.204  0.6 0.804
 V.
(i) What is the function of silicon nitride in the CMOS fabrication process?
Answer: The primary purpose of silicon nitride is to provide a barrier to oxygen so that when
deposited and patterned on top of silicon, silicon dioxide does not form below where the
silicon nitride exists.
(j) If the mobility of an electron is 500 cm 2/(V⋅s) and the mobility of a hole is 200
cm2/(V⋅s), compare the performance of an n-channel with a p-channel transistor. In
particular, consider the value of the transconductance parameter and speed of the MOS
transistor.
K   Cox
Answer: Since , the transconductance of an n-channel transistor will be 2.5 time greater
than the transconductance of a p-channel transistor. Remember that mobility will degrade
as a function of terminal conditions so transconductance will degrade as well. The speed
of a circuit is determined in a large part by the capacitance at the terminals and the
transconductance. When terminal capacitances are equal for an n-channel and p-channel
transistor of the same dimensions, the higher transconductance of the n-channel results in
a faster circuit.
Q.2. (a) Derive the low-frequency model parameters
g m , g mb , and rds  for an n-channel
25 3 22 3
transistor that has doping concentrations of N D 10 cm , N A 10 cm ,
 nCox 92 A/V 2 , with W 10 m , L 1.2 m , VGS 1.1 V , and VDS Veff .
V 1.0 V . Also take VTh 0.8 V .
Assume SB (12)
Veff VGS  VTh 1.1  0.8 0.3
Answer: Note that V, so the value for  will become
k ds 362 10 9
V   0.159 V  1
DS Veff
2 L VDS   Veff  
  0 2  1.2 10 6
 0.9
,
2 Si 0 2 11.8 8.854 10  12
k ds    19 22
362 10  9 m/ V
qN A 1.6 10 10
where .
6
 nCox  W  92 10  10 
  VGS  VTh    1.1  0.8 34.5
2 2
ID  
Now, 2  L 2  1 .2  A.
1 1
rds   182
Therefore, I D 0.159 34.5 10  6 k.
gm
Transconductance can be calculated from the equation
W   10 
g m  2 nCox   I D  2 92 10 6   34.5 10  6 230
 L  1,2  A/V.
KT  N A 
F  ln   0.35
  0.5  q  n 
Assuming and calculating F from the equation i
V at room
g
temperature, we get mb from the equation
g m 0.5 230 10 6
g mb   44
2 VSB  2F 2 1  0.7
A/V.
(b) Explain in your own words why the magnitude of the threshold voltage in the equation

VTh VTh 0   VSB  2F  2F 
increases as the magnitude of the source-bulk
voltage increases (Hint: The source-bulk pn diode remains reversed biased.) (8)
Answer: Considering an n-channel device, as the gate voltage increases relative to the bulk, the
region under the gate will begin to invert. What happens near the source? If the source is
at the same potential as the bulk, then the region adjacent to the edge of the source inverts
as the rest of the bulk region under the gate inverts. However, if the source is at a higher
potential than the bulk, then a greater gate voltage is required to overcome the electric
field induced by the source. While a portion of the region under the gate still inverts,
there is no path of current flow to the source because the gate voltage is not large enough
to invert right at the source edge. Once the gate is greater than the source and increasing,
then the region adjacent to the source can begin to invert and thus provide a current path
into the channel.
Q.3. (a) Given a polysilicon resistor like the one shown in Figure Q.3(a) below with
W 0.8 m and L 20 m , calculate  s (in /□), the number of squares of
resistance and the resistance value. Assume that for silicon the resistivity is
 9 10  4  - cm and the polysilicon is 3000 Å thick. Ignore any contact resistance.
(8)

Figure Q.3(a) Figure Q.3(b)


Answer: First let us calculate s :

 9 10  4
s   30
T 3000 10  8 /□.
The number of squares of resistance, N is
L 20 10  6
N  25
W 0.8 10  6
The total resistance is given by
R   s N 30 25 750

(b) Using the small-signal equivalent circuit derive an expression for the output resistance
of the MOS Wilson current mirror shown in Figure Q.3(b) above. You must show your
work to receive credit. (12)
Answer: The small-signal equivalent circuit of the MOS Wilson current mirror is as shown in the
Figure below:

ix i
v gs 2 v g 2  vs 2  g m 3vgs1rO 3   g m 3rO 3  1 x
We have, g m1 g m1
vx ix  g m 2vgs 2  g mb 2vs 2 rO 2  vgs1
 g 1  g m 3rO 3  g mb 2  ix
v x   ix  ix m 2  rO 2 
 g m1  g m1
vx 1 g r 1  g m 3rO 3  g mb 2 rO 2
rO 2   m2 O2
Therefore, ix g m1 g m1
vx g g r g r
rO 2  g m 2 rO 2 rO 3 m 3  m 2 O 2  mb 2 O 2
or, ix g m1 g m1 g m1
Rout rO 2 2  g m 2 rO 3 
So,
Q.4. (a) Using the small-signal low-frequency equivalent circuit derive the output impedance
of the source follower shown in Figure Q.4(a) below. (8)

Figure Q.4(a) Figure Q.4(b)


Answer: The small-signal low-frequency equivalent circuit of the source follower is given in the
Figure below:

Summing currents at node :


i X  g m1v X  g mb1v X  v X GS 1 0
1 i
Gout   X  g m1  g mb1  GS 1
Therefore, Rout v X
1 1
GS 1  g ds1  g ds 2  
where, rds1 rds 2
1 1 1
Rout   
or, g m1  g mb 1  GS 1 g m1  g mb1  g ds1  g ds 2 g m1  g mb1
(b) Show that two MOS transistors connected in parallel as shown in Figure Q.4(b) above
with channel widths of W1 and W2 and identical channel lengths of L can be modelled as
an equivalent MOS transistor whose width is W1  W2  and whose length is L , as
shown in the Figure below. Assume the transistors are identical except for their channel
widths. (12)
Answer: Note that all the transistors have equal terminal voltages. So,
VGS 1 VGS 2 VGS 3 VGS
VDS 1 VDS 2 VDS 3 VDS
VSB1 VSB 2 VSB3 VSB
VSB 0
If , there is a body effect, but
VTh1 VTh 2 VTh 3 VTh
Case I: All active
k W 
I D1   1  VGS  VTh  1  VDs 
2

2 L 
k W 
I D 2   2  VGS  VTh  1  VDs 
2

2 L 
k W W 
I D1  I D 2   1  2  VGS  VTh  1  VDs 
2

2 L L 
k   W  W2 
 VGS  VTh  1  VDs   I D1  I D 2
2
I D3   1
2 L 
Therefore, the two MOS transistors connected in parallel with channel widths of W1 and W2 and
identical channel lengths of L can be modelled as an equivalent MOS transistor whose width is
W1  W2  and whose length is L , as shown in the Figure above, assuming that the transistors are
identical except for their channel widths.
Case II: All triode
k W 

I D1   1  2VGS  VTh VDS  VDS2
2 L 

k W 

I D 2   2  2VGS  VTh VDS  VDS2
2 L 

k W W 

I D1  I D 2   1  2  2VGS  VTh VDS  VDS2
2 L L 

k   W  W2 
I D3   1
2 L 
 2

 2VGS  VTh VDS  VDS  I D1  I D 2

Therefore, in this case also, the two MOS transistors connected in parallel with channel widths of W1
and W2 and identical channel lengths of L can be modelled as an equivalent MOS transistor whose
width is W1  W2  and whose length is L , as shown in the Figure above, assuming that the
transistors are identical except for their channel widths.
 W  V2 
I D  nCox    VGS  VTh VDS _ DS 
Q.5. Derive the current equation given by  L  2 
for the
MOSFET for which the threshold voltage Th is not constant but varies linearly with V y 
V
V y  VTh 0  V y 
according to the equation Th . (20)
Answer: We know that when the channel is formed between the drain and the source in a
V
MOSFET, a drain current I D can flow if a voltage DS exists across the channel. The
dependence of this current on the terminal voltages of the MOSFET can be developed by
considering the characteristics of the incremental length of the channel designated as dy .
VDS
It is assumed that the width of the MOSFET is W and that is small. The charge per
unit area in the channel, QI y  , can now be expressed as
QI y  Cox VGS  V ( y )  VTh y 
The resistance in the channel per unit length dy can be written as
dy
dR 
 nQI y W

where n is the average mobility of the electrons in the channel. The voltage drop, referenced to the
source, along the channel in the y direction is
I D dy
dV y   I D dR 
 nQI y W
I D dy W nQI t dV y 
or .
Now integrating the above equation along the channel from y 0 to y L gives
L VDS VDS

I D dy  W nQI t dV y   W nCox VGS  V ( y )  VTh y dV y 


0 0 0

VTh y  VTh 0  V y 
Substituting , we get
VDS

I D L  W nCox VGS  V ( y )  VTh 0  V y dV y 


0
VDS

I D L W nCox V GS  VTh 0  1   V y dV y 


or, 0
VDS
 V y  
2
I D L W nCox  VGS  VTh 0 V y  1    
 2 0
or,
W  V2 
I D  nCox    VGS  VTh 0 VDS  1    DS 
Therefore,  L  2 

Q.6. Calculate the small-signal voltage gain of the common-source amplifier with depletion load
as shown in Figure Q.6 below, including both body effect and channel-length modulation.
Assume VDD 3 V and that the dc input voltage is adjusted so that the dc output voltage is
1 V. Assume that transistor M 1 has drawn dimensions of W 100 m and L 1 m . Also
assume that transistor M 2 has drawn dimensions of W 10 m and L 1 m . For both
o
X d 0 tox 80 A
, N A  N D 510 , k n   nCox 194 A V ,
15
 2
transistors assume ,
dX d
0.02 m V
dVDS L 0.09 m
, d . (20)

Figure Q.6
VTh
Answer: We know that the threshold voltage is given by

VTh VTh 0   2F  VSB  2F 
1 
 2 q N A Cox  ox
and Cox , where tox
 ox 3.9 8.86 10  14
Cox   4.3 10  7 F cm 2
Therefore, we calculate tox 80 10  8
1 1
 2 q N A  7
21.6 10  19 11.6 8.86 10  14 5 1015  0.094 V1 2
and C ox 4 .3 10
 kT   N A   5 1015 
2F 2  ln   20.026 ln   663 mV
10 
We get  q   ni   1.45 10 

So, we have from,



VTh VTh 0   2F  VSB  2F 

VTh 2  1  0.094 0.663  1  0.663  0.955 V 
Leff  L  2 LD
We know that
Leff 1 m  20.09 m  0.82 m
Therefore,
Now, we can find the drain current of M 2 from
1 W 
I D 2   nCox   VGS 2  VTh 2 2
2 L 
 eff 2
1  10 
 0  0.955 1.08 mA
2
I D2  194 10  6 
as 2  0.82  2
The small-signal voltage gain of the common-source amplifier with depletion load is given by
VO  1  g m1
Av   g m1  rO1 || rO1 ||  
Vi  g mb 2  g O1  g O 2  g mb 2
g m1  2  nCox W Leff 1 I D1  2 194 10  6 100 0.82 1.08 10  3 7.2 mA V
where,
nCox W Leff 2 VGS 2  VTh 2 
g mb 2 
2 2F  VSB 2
0.094 194 10  6 10 0.820  0.955
 82.3 A V
and 2  0.663  1
1 1 I dX 1.08 10  3
g O1  g O 2    D  d 
rO1 rO 2 Leff dVDS 0.82 10 6

0.02 10 6 26.3 A V 
V g m1 7.2 10 3
Av  O    53
Therefore, Vi g O1  g O 2  g mb 2 2 26.3 10 6  82.3 10 6
Q.7. (a) Using the small-signal equivalent circuit calculate the transfer function of the source
C gs 7.33 pF
follower circuit shown in Figure Q.7(a) below with ,
K W L  100 mA V , I D 4 mA , RS 190 Ω , and RL 2 kΩ . Ignore body
2

C gd 0 C gb 0
effect and let , , and Csb 0 . (10)

Figure Q.7(a) Figure Q.7(b)


Answer: (a) The small-signal model of the source-follower is given as
g m  2 100 4 mA/V 28.2 mA/V
From the data given we get, .

RL RL || 1 g mb  RL


Ignoring body effect, we have .

Cgd 0 T
Since , of the device is given by

g m 28.2 mA/V
T   3.85 109 rad/sec
C gs 7.33 pF

and thus fT 612 MHz .

From the equivalent circuit of the source-follower the zero of the transfer function is given by

gm
z1   T  3.85 109 rad/sec
C gs

and equation for the pole


p1 given by

1  R  RL 
p1  R1  S 
C gs R1  1  g m RL 
, where

190  2000
R1  Ω 38.2 Ω
Therefore, 1  0.0282 2000

So, the pole of the transfer function is given by

1012
p1  rad/sec  3.57 109 rad/sec
7.33 38.2

The pole and zero are thus quite closely spaced in the s-plane.

The transfer function of the circuit is thus given by

 s 
1
vo g m RL  z1 
  
vi 1  g m RL  1  s 
 p1 

The low-frequency gain of the circuit is given by

vo g R 28.2 10 3 2000


 m L  0.983
vi 1  g m RL 1  28.2 10 3 2000
The transfer function of the emitter follower is therefore given as,

 s 
vo  1  3.85 109 
0.983 
vi s
1 
 3.57 109  .
(b) Calculate the small-signal voltage gain for the cascode amplifier shown in Figure
v
Q.7(b) above, assuming that the dc value of IN is selected to keep all transistors in
saturation. Use the following device parameters:
 nCox  K n 110 A V 2 ,
 p Cox  K p 50 A V 2 n 0.04 V  1  p 0.05 V  1
, , . (10)
Answer: The small-signal voltage gain can be approximated as,
g 2 K n W L 1
Av   m1 Av  
g ds 3 I D 332
or
I D is calculated from M3 as,
K  W 

I D  p   VGS 3  VThp
2  L 2

2

50 10  6
2
2 2.7  0.7  200 A
2

2 K n W L 1 2 110 10  6 2
Av    29.67
200 10  6 0.05
2
I D 332
Therefore,

End of Answers

You might also like