Department of Electronics & Computer Engineering

Exp No: 8
Date :
WAVEFORM GENERATION
AIM
To set up and study square waveform, triangular waveform and sawtooth waveform generator using
Op-Amp.
THEORY
Square wave oscillator
The basic square wave oscillator is based on the charging and discharging of a capacitor. Op-
amps inverting input is the capacitor voltage and the noninverting input is a portion of the output fed
back through resistors R1 and R2 (refer figure 1). When the circuit is first turned on, the capacitor is
uncharged, and thus the inverting input is at 0V. This makes the output a positive maximum, and the
capacitor begins to charge towards voltage at VO through resistor R. When the capacitor voltage reaches
a value equal to the feedback voltage (Vf) on the non-inverting input, the op-amp switches to the
maximum negative state. At this point, the capacitor begins to discharge from +Vf towards –Vf. When
the capacitor voltage reaches –Vf, the op-amp switches back to the maximum positive state. This action
repeats and a square wave output voltage is obtained.
Expression for period is

Triangular-wave oscillator
This circuit (figure 2) uses two operational amplifiers. Op-amp A1 functions as a comparator
and the op-amp A2 as an integrator. Comparator compares the voltage at point P continuously with
respect to the voltage at the inverting input; which as at ground potential. When the voltage at P goes
slightly below zero, the output of A1 will switch to negative saturation. Suppose the output of A1 is at
positive saturation +Vsat. Since this voltage is the input of the integrator, the output of A2 will be a
negative going ramp. Thus, one end of the voltage divider R1-R2 is at +Vsat and the other at the negative
going ramp. At time t = t1, when the negative going ramp attains value of –Vramp the effective voltage at
point P becomes slightly less than 0 V. This switches output of A1 from positive saturation to negative
saturation level –Vsat. During the time when the output of A1 is at –Vsat, the output of A2 increases in
positive direction. At the instant t = t2, the voltage at point P becomes just above 0 V, thereby switching
the output of A1 from –Vsat to +Vsat. The cycle repeats and generates a triangular waveform.

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Sawtooth-wave oscillator
The difference between the triangular and sawtooth waveform is that the rise time of the
triangular wave is always equal to its fall time while in sawtooth wave generator, rise time may be
much higher than its fall time or vice versa. The triangular wave generator can be converted to a
sawtooth wave generator by injecting a variable dc voltage into the noninverting terminal of the
integrator. This can be done by using a potentiometer as shown in figure 3. When the wiper of the
potentiometer is at the centre, the output will be a triangular wave since the duty cycle is 50%. If the
wiper moves towards –V, the rise time of the sawtooth becomes longer than the fall time. If the wiper
moves towards +V, the fall time becomes more than the rise time.
DESIGN AND CIRCUIT DIAGRAMS
Design of square wave generator

Design of triangular wave generator

Let the frequency of oscillation be 1 kHz

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Design of sawtooth wave generator

Design is similar to that of triangle wave generator.
Select R3 = 47 kΩ potentiometer to vary the reference voltage of second op-amp.
Circuit diagram

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PROCEDURE
1. Set up the circuit after testing the components.
2. Set up the square wave generator as shown in figure and observe the output waveform and note
down their amplitudes and frequencies.
3. Set up the triangular wave generator as shown in figure and observe the variation in frequencies
of output waveform by varying the values of resistances R1, R2 and R3
4. Set up the sawtooth wave generator as shown in figure and note down the rise time and fall
time.
5. Move the wiper of the potentiometer in both directions and observe the changes taking place in
the waveform.
RESULT
Circuits of square wave generator, triangular wave generator and sawtooth wave generator are
designed, setup and waveforms observed.

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Exp No: 9
Date :
ASTABLE AND MONOSTABLE MULTIVIBRATOR USING 555 IC
Aim
To design and setup an astable and monostable Multivibrator using 555 IC for a frequency of 1
KHz.
Components and Equipment required
Power supply, CRO, Function generator, IC 555, Resistors 6.8K, 10K, 5.6K capacitors 0.1F
0.01F, diode 1N4007 and bread board.
Theory
Astable Multivibrator:- Initially the capacitor C starts charging through Ra and Rb towards Vcc
with a time constant ( Ra+Rb) C. During this time R = 0 S = 1 Q = 0 and output (pin3) is high (equal to
Vcc). When capacitor voltage equals (2/3) Vcc the upper comparator triggers the control flip-flop so that
Q = 1. This makes transistor Q1 ON and capacitor C starts discharging towards ground through Rb and
transistor Q1 with a time constant RbC.
During the discharge of the timing capacitor C, as it reaches Vcc/3 the lower comparator is
triggered and at the stage S = 1, R = 0 which turns Q = 0. This makes Q1 OFF and again Capacitor C
starts to charge. Thus the capacitor periodically charges and discharges between (2/3)Vcc and (1/3)Vcc.
The charging period of capacitor C=0.69(Ra+Rb) C
The discharging period of capacitor C=0.69 Rb C
Monostable Multivibrator:- In the stable state Q is high and in turn, Q1 is turned ON and
output is low. When the –ve going trigger passes through Vcc/3, the FF is set. That is Q = 0. This
makes transistor Q1 is OFF, the capacitor C starts charging towards Vcc, which was earlier clamped to
zero. After a time period the capacitor voltage becomes greater than 2/3 Vcc and upper comparator
resets the FF ie, R = 1, S = 0. This makes Q = 1. In turn, Q1 turns ON and there by discharging the
capacitor C rapidly to ground potential. The output returns to stable state.
The time duration of quasi stable state is given by equation, T=1.1 RC seconds.
Though it is possible to apply the trigger pulse directly to Pin 2 trigger shown in figure is better because
it makes narrow trigger pulses applied to trigger terminal.
Design
Astable Multivibrator:
Vcc = 10V
Timing Capacitor charges from Vcc through Ra and Diode, and discharges through Rb.
0.5 duty cycle implies TON = TOFF it means that the charging and discharging periods are equal.
Then Ra = Rb = R.
0.5 mS = 0.69 RC
Let C=0.1 F, Then R= 7.2KΩ, use 6.8 KΩ std.
Choose C1 = 0.01 F
Monostable Multivibrator:
Vcc = 10V, T = 1mS
T = 1.1 RC
Take R = 10KΩ to limit current through internal transistor to 1 mA. Then
C = 0.1F

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We have Ri Ci ≤ 0.0016Tt, where Tt = time period of the trigger.

Take Tt = 3 mS Take Ri = 5.6KΩ to avoid loading then Ci = 0.01F.
Circuit diagram
Astable multivibrator

Monostable multivibrator

Procedure
1. Set up the circuits on bread board.
2. Set triggering frequency = 300Hz
1. Observe the Waveforms at output and VC on CRO and note down their amplitudes and
frequencies.
Result
Exercises

1. Draw the internal block diagram of 555 timer.

2. Draw the pin diagram of the 555 timer IC. Explain the function of each pin.
3. Give the applications of 555 timer.
4. Explain how a monostable Multivibrator works?
5. Explain how an astable Multivibrator works?
6. Give the expressions for the charging and discharging time periods of astable Multivibrator.
7. Explain what is duty cycle? Derive the expression for duty cycle for astable Multivibrator.
8. Derive the expression for the time period of quasi-stable state of monostable Multivibrator.
9. Derive the expression for the time period of the output waveform of astable Multivibrator?
10. Setup a circuit to glow an LED intermittently.

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11. What are the applications of monostable Multivibrator?

12. Design a frequency divider using 555 timer IC.
13. It is not possible to have a duty cycle more than 50% why?
14. Give the applications of astable Multivibrator.
15. Which are the two timer packages available?
16. Give the supply voltage range for 555.
17. Explain the function of reset.

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Exp No: 10
Date :
D/A CONVERTERS- LADDER CIRCUIT
Aim:
To design and set up a R-2R ladder type DAC.
Components required:
Op-amp, resistors, capacitors, breadboard, CRO, function generator and power supplies.
Theory:
An R-2R ladder DAC uses fewer unique resistor values. Only two resistance values are used
anywhere in the entire circuit. This means that only two values of resistance in the ratio 2:1. Current
flowing through any input resistor (2R) encounters two possible paths at the far end. The effective
resistances of both paths are the same, so the incoming current splits equally along both paths. The half
current that flows back towards lower orders of magnitude does not reach the op amp, and therefore has
no effect on the output voltage. The half that takes the path towards the op amp along the ladder can
affect the output.
Circuit diagram:

Design:
Let R=……KΩ & 2R=…..KΩ
Observations and typical response curve

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d1 d2 d3 d4 Vo (observed) Vo (Calculated)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Procedure:
1. Verify the conditions of op-amp.

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2. Set up the DAC circuit and manually enter binary inputs ….. to ….
3. Measure the output voltage using a multimeter and tabulate the readings.
4. Draw the response with analog output on Y-axis and binary input on X-axis.
Results:
Designed the ladder circuit DAC
Error in the output....................................%

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