Data Sheet

AD7768/AD7768-4
8-/4-Channel, 24-Bit, Simultaneous Sampling ADCs with Power Scaling, 110.8 kHz
Bandwidth
FEATURES ► Linear phase digital filter
► Low latency sinc5 filter
► Precision ac and dc performance
► Wideband brick wall filter: ±0.005 dB pass band ripple to
► 8-/4-channel simultaneous sampling 102.4 kHz
► 256 kSPS maximum ADC ODR per channel ► Analog input precharge and reference precharge buffers
► 108 dB dynamic range ► Power supply
► DC to 110.8 kHz maximum input bandwidth (−3 dB bandwidth) ► AVDD1 = 5.0 V, AVDD2 = 2.25 V to 5.0 V
► −120 dB THD, typical ► IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V
► ±2 ppm of full-scale range (FSR) integral nonlinearity (INL), ► 64-lead LQFP, no exposed pad
±50 µV offset error, ±30 ppm of FSR gain error
► Temperature range: −40°C to +105°C
► Optimized power dissipation vs. noise vs. input bandwidth
► Selectable power, speed, and input bandwidth APPLICATIONS
► Fast (highest speed): 110.8 kHz bandwidth, 51.5 mW per
channel ► Data acquisition systems: USB/PXI/Ethernet
► Median (half speed): 55.4 kHz bandwidth, 27.5 mW per ► Instrumentation and industrial control loops
channel ► Audio testing and measurement
► Low power (lowest power): 13.8 kHz bandwidth, 9.375 mW ► Vibration and asset condition monitoring
per channel ► 3-phase power quality analysis
► Per channel digital filter ► Sonar
► Programmable input bandwidth/sampling rates ► High precision medical electroencephalogram (EEG)/electro-
► CRC error checking on data interface myography (EMG)/electrocardiogram (ECG)
► Daisy-chaining
FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Rev. D
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Data Sheet AD7768/AD7768-4
TABLE OF CONTENTS

Features................................................................ 1 Interface Configuration Register.......................85

Applications........................................................... 1 Digital Filter RAM Built In Self Test (BIST)
Functional Block Diagram......................................1 Register.......................................................... 85
General Description...............................................4 Status Register.................................................86
Specifications........................................................ 5 Revision Identification Register........................ 86
1.8 V IOVDD Specifications............................. 13 GPIO Control Register..................................... 86
Timing Specifications....................................... 17 GPIO Write Data Register................................ 87
1.8 V IOVDD Timing Specifications..................19 GPIO Read Data Register................................87
Absolute Maximum Ratings.................................23 Analog Input Precharge Buffer Enable
Thermal Resistance......................................... 23 Register Channel 0 to Channel 3 .................. 88
ESD Caution.....................................................23 Analog Input Precharge Buffer Enable
Pin Configurations and Function Descriptions.....24 Register Channel 4 to Channel 7 .................. 88
Typical Performance Characteristics................... 32 Positive Reference Precharge Buffer Enable
Terminology......................................................... 42 Register.......................................................... 89
Theory of Operation.............................................43 Negative Reference Precharge Buffer
Clocking, Sampling Tree, and Power Scaling.. 43 Enable Register..............................................89
Noise Performance and Resolution..................45 Offset Registers................................................90
Applications Information...................................... 47 Gain Registers..................................................90
Power Supplies................................................ 48 Sync Phase Offset Registers........................... 91
Device Configuration........................................ 49 ADC Diagnostic Receive Select Register.........91
Pin Control .......................................................49 ADC Diagnostic Control Register..................... 92
SPI Control....................................................... 52 Modulator Delay Control Register.................... 92
SPI Control Functionality .................................53 Chopping Control Register............................... 93
SPI Control Mode Extra Diagnostic Features...56 AD7768-4 Register Map Details (SPI Control).... 94
Circuit Information............................................... 57 AD7768-4 Register Map...................................94
Core Signal Chain ........................................... 57 Channel Standby Register............................... 96
Analog Inputs................................................... 58 Channel Mode A Register................................ 97
VCM................................................................. 60 Channel Mode B Register................................ 97
Reference Input................................................60 Channel Mode Select Register.........................98
Clock Selection.................................................60 Power Mode Select Register............................98
Digital Filtering..................................................61 General Device Configuration Register............99
Decimation Rate Control.................................. 65 Data Control: Soft Reset, Sync, and Single-
Antialiasing ...................................................... 65 Shot Control Register................................... 100
Calibration........................................................ 67 Interface Configuration Register.....................100
Data Interface...................................................... 68 Digital Filter RAM Built In Self Test (BIST)
Setting the Format of Data Output................... 68 Register........................................................ 101
ADC Conversion Output: Header and Data..... 69 Status Register...............................................101
Functionality........................................................ 77 Revision Identification Register...................... 102
GPIO Functionality .......................................... 77 GPIO Control Register................................... 102
AD7768 Register Map Details (SPI Control)....... 78 GPIO Write Data Register.............................. 103
AD7768 Register Map...................................... 78 GPIO Read Data Register..............................103
Channel Standby Register............................... 80 Analog Input Precharge Buffer Enable
Channel Mode A Register................................ 81 Register Channel 0 and Channel 1 ............. 103
Channel Mode B Register................................ 82 Analog Input Precharge Buffer Enable
Channel Mode Select Register.........................82 Register Channel 2 and Channel 3.............. 104
Power Mode Select Register............................83 Positive Reference Precharge Buffer Enable
General Device Configuration Register............83 Register........................................................ 104
Data Control: Soft Reset, Sync, and Single- Negative Reference Precharge Buffer
Shot Control Register..................................... 84 Enable Register............................................104

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Data Sheet AD7768/AD7768-4
TABLE OF CONTENTS

Offset Registers..............................................105 Modulator Delay Control Register.................. 107

Gain Registers................................................105 Chopping Control Register............................. 107
Sync Phase Offset Registers......................... 105 Outline Dimensions........................................... 108
ADC Diagnostic Receive Select Register.......106 Ordering Guide...............................................108
ADC Diagnostic Control Register................... 106 Evaluation Boards.......................................... 108

REVISION HISTORY

4/2025—Rev. C to Rev. D
Changed Master to Main and Slave to Subordinate (Throughout).................................................................. 1
Changes to Table 1.......................................................................................................................................... 5
Changes to Table 2........................................................................................................................................ 13
Changes to Clock Selection Section..............................................................................................................60
Change to Table 63........................................................................................................................................94
Changes to Table 69...................................................................................................................................... 99

8/2022—Rev. B to Rev. C
Changes to Features Section.......................................................................................................................... 1
Changes to General Description Section.........................................................................................................4
Changes to Specifications Section.................................................................................................................. 5
Changes to Table 9........................................................................................................................................ 24
Changes to Table 10...................................................................................................................................... 28
Changes to Figure 28 Caption....................................................................................................................... 34
Change to AC Common-Mode Rejection Ratio (AC CMRR) Section............................................................ 42
Changes to Power Supplies Section..............................................................................................................48
Changes to Recommended Power Supply Configuration Section.................................................................48
Changes to Analog Supply Internal Connectivity Section..............................................................................49
Changes to Pin Control Section.....................................................................................................................49
Change to SPI Control Functionality Section.................................................................................................53
Changes to Reset over SPI Control Interface Section...................................................................................54
Changes to CRC Protection Section..............................................................................................................55
Changes to ADC Synchronization over SPI Section......................................................................................55
Changes to Clock Selection Section..............................................................................................................60
Change to Table 28 Title................................................................................................................................ 62
Change to Table 29 Title................................................................................................................................ 64
Changes to Modulator Saturation Point Section............................................................................................ 66
Changes to Gain Adjustment Section............................................................................................................ 67
Changes to Daisy-Chaining Section.............................................................................................................. 73
Changes to Table 43...................................................................................................................................... 83
Change to Interface Configuration Register Section......................................................................................85
Changes to Digital Filter RAM Built In Self Test (BIST) Register Section...................................................... 85
Changes to Status Register Section.............................................................................................................. 86
Changes to Offset Registers Section.............................................................................................................90
Changes to Table 63...................................................................................................................................... 94
Changes to Table 67...................................................................................................................................... 98
Changes to Interface Configuration Register Section..................................................................................100
Changes to Digital Filter RAM Built In Self Test (BIST) Register Section.................................................... 101
Changes to Status Register Section............................................................................................................ 101

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Data Sheet AD7768/AD7768-4
GENERAL DESCRIPTION

The AD7768/AD7768-4 are 8-channel and 4-channel 24-bit, simul- Within these filter options, the user can improve the dynamic range
taneous sampling, sigma-delta (Σ-Δ) analog-to-digital converters by selecting from decimation rates of ×32, ×64, ×128, ×256, ×512,
(ADCs) with power scaling and 110.8 kHz bandwidth. The devices and ×1024. The ability to vary the decimation filtering optimizes
have a Σ-Δ modulator and digital filter per channel, which enables noise performance to the required input bandwidth.
synchronized sampling of ac and dc signals.
Embedded analog functionality on each ADC channel makes de-
The AD7768/AD7768-4 achieve 108 dB dynamic range at a max- sign easier, such as a precharge buffer on each analog input that
imum input bandwidth of 110.8 kHz, combined with a typical per- reduces analog input current and a precharge reference buffer per
formance of ±2 ppm integral nonlinearity (INL), ±50 µV offset error, channel that reduces input current and glitches on the reference
and ±30 ppm gain error. input terminals.
The AD7768/AD7768-4 user can trade off input bandwidth, output The device operates with a 5 V AVDD1A and AVDD1B supply, a
data rate, and power dissipation, and select one of three power 2.25 V to 5.0 V AVDD2A and AVDD2B supply, and a 2.5 V to 3.3 V
modes to optimize for noise targets and power consumption. The or 1.8 V IOVDD supply (see the 1.8 V IOVDD Operation section for
flexibility of the AD7768/AD7768-4 allows them to become reusable specific requirements for operating at 1.8 V IOVDD).
platforms for low power dc and high performance ac measurement
modules. The device requires an external reference. The absolute input
reference voltage range is 1 V to AVDD1 − AVSS.
The AD7768/AD7768-4 have three modes: fast mode (256 kSPS
maximum, 110.8 kHz input bandwidth, 51.5 mW per channel), For the purposes of clarity in this data sheet, the AVDD1A and
median mode (128 kSPS maximum, 55.4 kHz input bandwidth, AVDD1B supplies are referred to as AVDD1, and the AVDD2A
27.5 mW per channel) and low power mode (32 kSPS maximum, and AVDD2B supplies are referred to as AVDD2. For the negative
13.8 kHz input bandwidth, 9.375 mW per channel). supplies, AVSS refers to the AVSS1A, AVSS1B, AVSS2A, AVSS2B,
and AVSS pins.
The AD7768/AD7768-4 offer extensive digital filtering capabilities,
such as a wideband, low ±0.005 dB pass-band ripple, antialiasing The specified operating temperature range is −40°C to +105°C. The
low-pass filter with sharp roll-off, and 105 dB attenuation at the device is housed in a 10 mm × 10 mm, 64-lead low profile quad flat
Nyquist frequency. package (LQFP) with a 12 mm × 12 mm printed circuit board (PCB)
footprint.
Frequency domain measurements can use the wideband linear
phase filter. This filter has a flat pass band (±0.005 dB ripple) from Throughout this data sheet, multifunction pins, such as XTAL2/
dc to 102.4 kHz at 256 kSPS, from dc to 51.2 kHz at 128 kSPS, or MCLK, are referred to either by the entire pin name or by a single
from dc to 12.8 kHz at 32 kSPS. function of the pin, for example MCLK, when only that function is
relevant.
The AD7768/AD7768-4 also offer sinc response via a sinc5 filter, a
low latency path for low bandwidth, and low noise measurements.
The wideband and sinc5 filters can be selected and run on a per
channel basis.

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Data Sheet AD7768/AD7768-4
SPECIFICATIONS

AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 2.25 V to 3.6 V, AVSS = DGND = 0 V, REFx+ = 4.096 V
and REFx− = 0 V, MCLK = 32.768 MHz, analog input precharge buffers on, reference precharge buffers off, wideband filter, chopping frequency
(fCHOP) = fMOD/32, TA = −40°C to +105°C, unless otherwise noted. See Table 2 for specifications at 1.8 V IOVDD.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR), per Fast mode 8 256 kSPS
Channel1
Median mode 4 128 kSPS
Low power mode 1 32 kSPS
−3 dB Bandwidth Fast mode, wideband filter 110.8 kHz
Median mode, wideband filter 55.4 kHz
Low power mode, wideband filter 13.8 kHz
Data Output Coding Twos complement, MSB first
No Missing Codes2 24 Bits
DYNAMIC PERFORMANCE
Fast Mode Decimation by 32, 256 kSPS ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
Signal-to-Noise Ratio (SNR) 1 kHz, −0.5 dBFS, sine wave input
Sinc5 filter 109 111 dB
Wideband filter 106 107.8 dB
Signal-to-Noise-and-Distortion 1 kHz, −0.5 dBFS, sine wave input 104.7 107.5 dB
Ratio (SINAD)
Total Harmonic Distortion 1 kHz, −0.5 dBFS, sine wave input −120 −107 dB
(THD)
Spurious-Free Dynamic Range 128 dBc
(SFDR)
Median Mode Decimation by 32, 128 kHz ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
SNR Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave input 109 111 dB
Wideband filter, 1 kHz, −0.5 dBFS, sine wave input 106 107.8 dB
SINAD 1 kHz, −0.5 dBFS, sine wave input 105.8 107.5 dB
THD 1 kHz, −0.5 dBFS, sine wave input −120 −113 dB
SFDR 128 dBc
Low Power Mode Decimation by 32, 32 kHz ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
SNR Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave input 109 111 dB
Wideband filter, 1 kHz, −0.5 dBFS, sine wave input 106 107.8 dB
SINAD 1 kHz, −0.5 dBFS, sine wave input 105.8 107.5 dB
THD 1 kHz, −0.5 dBFS, sine wave input −120 −113 dB
SFDR 128 dBc
INTERMODULATON DISTORTION fINA = 9.7 kHz, fINB = 10.3 kHz
(IMD)3
Second-order −125 dB
Third-order −125 dB

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Data Sheet AD7768/AD7768-4
SPECIFICATIONS

Table 1. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
ACCURACY
INL Endpoint method ±2 ±7 ppm of FSR
Offset Error4 DCLK frequency ≤ 24 MHz ±50 ±115 µV
24 MHz to 32.768 MHz DCLK frequency2 ±75 ±150 µV
Offset Error Drift DCLK frequency ≤ 24 MHz ±250 nV/°C
24 MHz to 32.768 MHz DCLK frequency ±750 nV/°C
Gain Error4 TA = 25°C ±30 ±70 ppm of FSR
Gain Drift vs. Temperature2 ±0.5 ±1 ppm/°C
VCM PIN
Output With respect to AVSS (AVDD1 − V
AVSS)/2
Load Regulation Change in output voltage to change in load current (∆VOUT/∆IL) 400 µV/mA
Voltage Regulation Applies to the following VCM output options only: common-mode 5 µV/V
voltage (VCM) = ∆VOUT/∆(AVDD1 − AVSS)/2, VCM = 1.65 V, and
VCM = 2.5 V
Short-Circuit Current 30 mA
ANALOG INPUTS See the Analog Inputs section
Differential Input Voltage Range VREF = (REFx+) − (REFx−) −VREF +VREF V
Input Common-Mode Range2 AVSS AVDD1 V
Absolute Analog Input Voltage AVSS AVDD1 V
Limits2
Analog Input Current
Unbuffered Differential component ±48 µA/V
Common-mode component +17 µA/V
Precharge Buffer On5 −20 µA
Input Current Drift
Unbuffered ±5 nA/V/°C
Precharge Buffer On ±31 nA/°C
EXTERNAL REFERENCE
Reference Voltage VREF = (REFx+) − (REFx−) 1 AVDD1 − V
AVSS
Absolute Reference Voltage Lim- Precharge reference buffers off AVSS − AVDD1 + V
its2 0.05 0.05
Precharge reference buffer on AVSS AVDD1 V
Average Reference Current Fast mode, see Figure 63
Precharge reference buffers off ±72 µA/V/channel
Precharge reference buffers on ±16 µA/V/channel
Average Reference Current Drift Fast mode, see Figure 63
Precharge reference buffers off ±1.7 nA/V/°C
Precharge reference buffers on ±49 nA/V/°C
Common-Mode Rejection 95 dB
DIGITAL FILTER RESPONSE
Low Ripple Wideband Filter FILTER pin = 0
Decimation Rate Up to six selectable decimation rates 32 1024
Group Delay Latency 34/ODR sec

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Data Sheet AD7768/AD7768-4
SPECIFICATIONS

Table 1. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
Settling Time Complete settling 68/ODR sec
Pass-Band Ripple2 From dc to 102.4 kHz at 256 kSPS ±0.005 dB
Pass Band ±0.005 dB bandwidth 0.4 × ODR Hz
−0.1 dB bandwidth 0.409 × ODR Hz
−3 dB bandwidth 0.433 × ODR Hz
Stop Band Frequency Attenuation > 105 dB 0.499 × ODR Hz
Stop Band Attenuation 105 dB
Sinc5 Filter FILTER pin = 1
Decimation Rate Up to six selectable decimation rates 32 1024
Group Delay Latency 3/ODR sec
Settling Time Complete settling 7/ODR sec
Pass Band −3 dB bandwidth 0.204 × ODR Hz
REJECTION
AC Power Supply Rejection Ratio Input voltage (VIN) = 0.1 V, AVDD1 = 5 V, AVDD2 = 5 V, IOVDD =
(PSRR) 2.5 V
AVDD1 90 dB
AVDD2 100 dB
IOVDD 75 dB
DC PSRR VIN = 1 V
AVDD1 100 dB
AVDD2 118 dB
IOVDD 90 dB
Analog Input Common-Mode Re-
jection Ratio (CMRR)
DC VIN = 0.1 V 95 dB
AC Up to 10 kHz 95 dB
Crosstalk −0.5 dBFS input on adjacent channels −120 dB
CLOCK See the Clocking Selections section for performance functionality
Crystal Frequency 8 32.768 34 MHz
External Clock (MCLK) 32.768 MHz
Duty Cycle 50:50 %
MCLK Pulse Width2
Logic Low 12.2 ns
Logic High 12.2 ns
CMOS Clock Input Voltage See the Logic Inputs parameter
High (VINH)
Low (VINL)
LVDS Clock2 Load resistance (RL) = 100 Ω provided externally
Differential Input Voltage 100 650 mV
Common-Mode Input Voltage 800 1575 mV
Absolute Input Voltage 1.88 V
ADC RESET2
ADC Start-Up Time After Reset6 Time to first DRDY, fast mode, decimation by 32 1.58 1.66 ms
Minimum RESET Low Pulse Width tMCLK = 1/MCLK 2 × tMCLK

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Data Sheet AD7768/AD7768-4
SPECIFICATIONS

Table 1. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS
Input Voltage2
High (VINH) 0.65 × V
IOVDD
Low (VINL) 0.7 V
Hysteresis2 0.04 0.09 V
Leakage Current −10 +0.03 +10 µA
RESET pin7 −10 +10 µA
LOGIC OUTPUTS See Table 2 for 1.8 V operation
Output Voltage2
High (VOH) Source current (ISOURCE) = 200 μA 0.8 × V
IOVDD
Low (VOL) Sink current (ISINK) = 400 µA 0.4 V
Leakage Current Floating state −10 +10 µA
Output Capacitance Floating state 10 pF
SYSTEM CALIBRATION2
Full-Scale Calibration Limit 1.05 × VREF V
Zero-Scale Calibration Limit −1.05 × V
VREF
Input Span 0.4 × VREF 2.1 × VREF V
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 − AVSS 4.5 5.0 5.5 V
AVDD2 − AVSS 2.0 2.25 to 5.0 5.5 V
AVSS − DGND −2.75 0 V
IOVDD − DGND See Table 2 for 1.8 V operation 2.25 2.5 to 3.3 3.6 V
POWER SUPPLY CURRENTS Maximum output data rate, CMOS MCLK, eight DOUTx signals,
all supplies at maximum voltages, all channels in Channel Mode
A
AD7768 Eight channels active
Fast Mode
AVDD1 Current Analog input precharge ON 36 40 mA
Analog input precharge ON and positive reference buffer ON 46.9 mA
Analog input precharge ON, and positive and negative reference 57.5 64 mA
buffers ON
AVDD2 Current 37.5 40 mA
IOVDD Current Wideband filter 63 67 mA
Sinc5 filter 27 29 mA
Median Mode
AVDD1 Current Analog input precharge ON 18.5 20.5 mA
Analog input precharge ON and positive reference buffer ON 24.2 mA
Analog input precharge ON, and positive and negative reference 29 32.5 mA
buffers ON
AVDD2 Current 21.3 23 mA
IOVDD Current Wideband filter 34 37 mA
Sinc5 filter 16 18 mA

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Data Sheet AD7768/AD7768-4
SPECIFICATIONS

Table 1. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
Low Power Mode
AVDD1 Current Analog input precharge ON 5.1 5.8 mA
Analog input precharge ON and positive reference buffer ON 6.6 mA
Analog input precharge ON, and positive and negative reference 8 9 mA
buffers ON
AVDD2 Current 9.3 10.1 mA
IOVDD Current Wideband filter 12.5 13.7 mA
Sinc5 filter 8 9 mA
AD7768-4 Four channels active
Fast Mode
AVDD1 Current Analog input precharge ON 18.2 20.3 mA
Analog input precharge ON and positive reference buffer ON 24.5 mA
Analog input precharge ON, and positive and negative reference 28.8 32.5 mA
buffers ON
AVDD2 Current 18.8 20.3 mA
IOVDD Current Wideband filter2 43.5 46.8 mA
Wideband filter, SPI mode only, Channel Mode A set to sinc5 37 40 mA
filter8
Sinc5 filter2 17 18.6 mA
Median Mode
AVDD1 Current Analog input precharge ON 9.3 10.5 mA
Analog input precharge ON and positive reference buffer ON 13 mA
Analog input precharge ON, and positive and negative reference 14.7 16.6 mA
buffers ON
AVDD2 Current 10.7 11.7 mA
IOVDD Current Wideband filter2 24.4 26.4 mA
Wideband filter, SPI mode only, Channel Mode A set to sinc5 21 23 mA
filter8
Sinc5 filter2 11 12.3 mA
Low Power Mode
AVDD1 Current Analog input precharge ON 2.7 3.1 mA
Analog input precharge ON and positive reference buffer ON 3.48 mA
Analog input precharge ON, and positive and negative reference 4.1 4.7 mA
buffers ON
AVDD2 Current 4.7 5.3 mA
IOVDD Current Wideband filter2 10 11.1 mA
Wideband filter, SPI mode only, Channel Mode A set to sinc5 9 10 mA
filter8
Sinc5 filter2 6.5 7.6 mA
AD7768 and AD7768-4—Two Serial peripheral interface (SPI) control mode only, see the Chan-
Channels Active4 nel Standby section for details on disabling channels
Fast Mode
AVDD1 Current Analog input precharge ON 9.3 10.5 mA
Analog input precharge ON and positive reference buffer ON 11.92 mA
Analog input precharge ON, and positive and negative reference 14.7 16.6 mA
buffers ON
AVDD2 Current 9.5 10.5 mA

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Data Sheet AD7768/AD7768-4
SPECIFICATIONS

Table 1. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
IOVDD Current Wideband filter 33.7 36.3 mA
Wideband filter, disabled channels in Channel Mode A, and set to 23.4 25.5 mA
sinc5 filter mode8
Sinc5 filter 11.9 13.3 mA
Median Mode
AVDD1 Current Analog input precharge ON 4.8 5.5 mA
Analog input precharge ON and positive reference buffer ON 6.2 mA
Analog input precharge ON, and positive and negative reference 7.5 8.6 mA
buffers ON
AVDD2 Current 5.5 6.2 mA
IOVDD Current Wideband filter 19.4 21.1 mA
Wideband filter, disabled channels in Channel Mode A, and set to 14.1 15.5 mA
sinc5 filter mode8
Sinc5 filter 8.5 9.6 mA
Low Power Mode
AVDD1 Current Analog input precharge ON 1.52 1.77 mA
Analog input precharge ON and positive reference buffer ON 1.84 mA
Analog input precharge ON, and positive and negative reference 2.2 2.6 mA
buffers ON
AVDD2 Current 2.4 3 mA
IOVDD Current Wideband filter 8.6 9.7 mA
Wideband filter, disabled channels in Channel Mode A, and set to 7.2 8 mA
sinc5 filter mode8
Sinc5 filter 5.8 6.7 mA
Standby Mode All channels disabled (sinc5 filter enabled) 6.5 8 mA
Sleep Mode2 Full power-down (SPI control mode only) 0.73 1.2 mA
Crystal Excitation Current Extra current in IOVDD when using an external crystal compared 540 µA
to using the CMOS MCLK
POWER DISSIPATION External CMOS MCLK, all channels active, MCLK = 32.768 MHz,
all channels in Channel Mode A except where otherwise speci-
fied
Full Operating Mode—AD7768 Analog precharge buffers on
Wideband Filter
Fast Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 412 446 mW
buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 600 645 mW
buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 631 681 mW
reference buffers off
Median Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 220 240 mW
buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 320 345 mW
buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 341 372 mW
reference buffers off
Low Power Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 75 85 mW
buffers off2

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Data Sheet AD7768/AD7768-4
SPECIFICATIONS

Table 1. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 107 118 mW
buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 124 137 mW
reference buffers off
Sinc5 Filter
Fast Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 325 355 mW
buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 475 525 mW
buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 501 545 mW
reference buffers off
Median Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 175 195 mW
buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 260 285 mW
buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 277 304 mW
reference buffers off
Low Power Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 65 72 mW
buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 95 105 mW
buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 108 120 mW
reference buffers off
Full Operating Mode—AD7768-4
Wideband Filter
Fast Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 235 mW
buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 336 mW
buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 360 392 mW
reference buffers off2
SPI mode only; AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 337 368 mW
V, precharge reference buffers off, Channel Mode A set to sinc5
filter8
Median Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 127 mW
buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 181 mW
buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 198 218 mW
reference buffers off2
SPI mode only; AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 186 205 mW
V, precharge reference buffers off, Channel Mode A set to sinc5
filter8
Low Power Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 49 mW
buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 66 mW
buffers on

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Table 1. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 77 87 mW
reference buffers off2
SPI mode only; AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 73 83 mW
V, precharge reference buffers off, Channel Mode A set to sinc5
filter8
Sinc5 Filter
Fast Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 168 mW
buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 248 mW
buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 265 291 mW
reference buffers off
Median Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 94 mW
buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 137 mW
buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 150 167 mW
reference buffers off
Low Power Mode AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference 40 mW
buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference 55 mW
buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge 64 74 mW
reference buffers off
Standby Mode All channels disabled (sinc5 filter enabled), AVDD1 = 5 V, 18 mW
AVDD2 = IOVDD = 2.5 V2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V2 26 mW
AVDD1 = AVDD2 = 5.5 V, IOVDD = 3.6 V 29 mW
Sleep Mode2 Full power-down (SPI control mode), AVDD1 = 5 V, AVDD2 = 1.8 4 mW
IOVDD = 2.5 V
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V 2.5 5 mW
AVDD1 = AVDD2 = 5.5 V, IOVDD = 3.6 V 2.7 6.5 mW

1 The output data rate ranges refer to the programmable decimation rates available on the AD7768/AD7768-4 for a fixed MCLK rate of 32.768 MHz. Varying MCLK rates
allow users a wider variation of ODR.
2 These specifications are not production tested but are supported by characterization data at initial product release.
3 See the Terminology section for more information about the fa and fb input frequencies.
4 Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces
the gain error to the order of the noise for the programmed output data rate.
5 −25 µA is measured when the analog input is close to either the AVDD1 or AVSS rail. The input current reduces as the common-mode voltage approaches (AVDD1 −
AVSS)/2. The analog input current scales with the MCLK frequency and device power mode. See Figure 85 and Figure 86 for more details on how the analog input current
scales with input voltage.
6 For lower MCLK rates or higher decimation rates, use Table 28 and Table 29 to calculate any additional delay before the first DRDY pulse.
7 The RESET pin has an internal pull-up device to IOVDD.
8 Configuring Channel Mode A to the sinc5 filter and/or assigning disabled channels to Channel Mode A allows a lower power consumption to be achieved. To do this, the
user must be operating in SPI control mode because it requires assigning channels to different channel modes (only possible in SPI control mode). If using pin control

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Data Sheet AD7768/AD7768-4
SPECIFICATIONS

mode, all channels, whether active or in standby, are assigned to the same channel group and use the same filter type. This means that, in pin control mode, a higher
current consumption is seen from disabled channels than can be achieved in SPI mode. See the Channel Modes section for more details.

1.8 V IOVDD SPECIFICATIONS

AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 1.72 V to 1.88 V, AVSS = DGND = 0 V, REFx+ = 4.096 V
and REFx− = 0 V, MCLK = 32.768 MHz, analog precharge buffers on, reference precharge buffers off, wideband filter, fCHOP = fMOD/32, TA =
−40°C to +105°C, unless otherwise noted.

Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE For dynamic range and SNR across all decimation rates, see
Table 12 and Table 13
Fast Mode Decimation by 32, 256 kSPS ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
SNR Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave input 109 111 dB
Wideband filter, 1 kHz, −0.5 dBFS, sine wave input 106 107.8 dB
SINAD1 1 kHz, −0.5 dBFS, sine wave input 103.8 107.5 dB
THD 1 kHz, −0.5 dBFS, sine wave input −120 −107 dB
SFDR 128 dBc
Median Mode Decimation by 32, 128 kHz ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
SNR 1 kHz, −0.5 dBFS, sine wave input
Sinc5 filter 109 111 dB
Wideband filter 106 107.8 dB
SINAD 1 kHz, −0.5 dBFS, sine wave input 105.8 107.5 dB
THD 1 kHz, −0.5 dBFS, sine wave input −120 −113 dB
SFDR 128 dBc
Low Power Mode Decimation by 32, 32 kHz ODR
Dynamic Range Shorted input, wideband filter 106.2 108 dB
SNR Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave input 109 111 dB
Wideband filter, 1 kHz, −0.5 dBFS, sine wave input 106 107.8 dB
SINAD 1 kHz, −0.5 dBFS, sine wave input 105.8 107.5 dB
THD 1 kHz, −0.5 dBFS, sine wave input −120 −113 dB
SFDR 128 dBc
ACCURACY1
INL Endpoint method ±2 ±7 ppm of FSR
Offset Error2 DCLK frequency ≤ 24 MHz ±50 ±115 µV
24 MHz to 32.768 MHz DCLK frequency ±75 ±170 µV
Offset Error Drift DCLK frequency ≤ 24 MHz ±250 nV/°C
24 MHz to 32.768 MHz DCLK frequency ±750 nV/°C
Gain Error2 TA = 25°C ±60 ±120 ppm/FSR
Gain Drift vs. Temperature ±0.5 ±2 ppm/°C
LOGIC INPUTS
Input Voltage1
VINH 0.65 × IOVDD V
VINL 0.4 V
Hysteresis1 0.04 0.2 V

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Data Sheet AD7768/AD7768-4
SPECIFICATIONS

Table 2. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
Leakage Current −10 +0.03 +10 µA
RESET pin −10 +10 µA
LOGIC OUTPUTS
Output Voltage1
VOH ISOURCE = 200 µA 0.8 × IOVDD V
VOL ISINK = 400 µA 0.4 V
Leakage Current Floating state −10 +10 µA
Output Capacitance Floating state 10 pF
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 − AVSS 4.5 5.0 5.5 V
AVDD2 − AVSS 2.0 2.25 to 5.0 5.5 V
AVSS − DGND −2.75 0 V
IOVDD − DGND DREGCAP shorted to IOVDD 1.72 1.8 1.88 V
POWER SUPPLY CURRENTS1 Maximum output data rate, CMOS MCLK, eight DOUTx signals,
all supplies at maximum voltages, all channels in Channel
Mode A except where otherwise specified
AD7768 Eight channels active
Fast Mode
AVDD1 Current Analog input precharge ON 36 40 mA
Analog input precharge ON and positive reference buffer ON 46.9 mA
Analog input precharge ON, and positive and negative 57.5 64 mA
reference buffers ON
AVDD2 Current 37.5 40 mA
IOVDD Current Wideband filter 63 69 mA
Sinc5 filter 26 28.4 mA
Median Mode
AVDD1 Current Analog input precharge ON 18.5 20.5 mA
Analog input precharge ON and positive reference buffer ON 24.2 mA
Analog input precharge ON, and positive and negative 29 32.5 mA
reference buffers ON
AVDD2 Current 21.3 23 mA
IOVDD Current Wideband filter 34 36.8 mA
Sinc5 filter 15 16.8 mA
Low Power Mode
AVDD1 Current Analog input precharge ON 5.1 5.8 mA
Analog input precharge ON and positive reference buffer ON 6.6 mA
Analog input precharge ON, and positive and negative 8 9 mA
reference buffers ON
AVDD2 Current 9.3 10.1 mA
IOVDD Current Wideband filter 11.6 12.9 mA
Sinc5 filter 7 8.1 mA
AD7768-4 Four channels active
Fast Mode
AVDD1 Current Analog input precharge ON 18.2 20.3 mA
Analog input precharge ON and positive reference buffer ON 24.5 mA

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SPECIFICATIONS

Table 2. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
Analog input precharge ON, and positive and negative 28.8 32.5 mA
reference buffers ON
AVDD2 Current 18.8 20.3 mA
IOVDD Current Wideband filter 43.9 47.7 mA
Wideband filter, SPI mode only, Channel Mode A set to sinc5 36.8 41 mA
filter3
Sinc5 filter 16 17.7 mA
Median Mode
AVDD1 Current Analog input precharge ON 9.3 10.5 mA
Analog input precharge ON and positive reference buffer ON 13 mA
Analog input precharge ON, and positive and negative 14.7 16.6 mA
reference buffers ON
AVDD2 Current 10.7 11.7 mA
IOVDD Current Wideband filter 24 26.1 mA
Wideband filter, SPI mode only, Channel Mode A set to sinc5 20.4 22.7 mA
filter3
Sinc5 filter 10 11.3 mA
Low Power Mode
AVDD1 Current Analog input precharge ON 2.7 3.1 mA
Analog input precharge ON and positive reference buffer ON 3.48 mA
Analog input precharge ON, and positive and negative 4.1 4.7 mA
reference buffers ON
AVDD2 Current 4.7 5.3 mA
IOVDD Current Wideband filter 9 10.2 mA
Wideband filter, SPI mode only, Channel Mode A set to sinc5 8.1 9.2 mA
filter3
Sinc5 filter 5.5 6.5 mA
AD7768 and AD7768-4—Two SPI control mode only, see the Channel Standby section for
Channels Active details on disabling channels
Fast Mode
AVDD1 Current Analog input precharge ON 9.3 10.5 mA
Analog input precharge ON and positive reference buffer ON 11.92 mA
Analog input precharge ON, and positive and negative 14.7 16.6 mA
reference buffers ON
AVDD2 Current 9.5 10.5 mA
IOVDD Current Wideband filter 33.8 36.7 mA
Wideband filter, SPI mode only, disabled channels in Channel 23.1 25.6 mA
Mode A, and set to sinc5 filter3
Sinc5 filter 11 12.3 mA
Median Mode
AVDD1 Current Analog input precharge ON 4.8 5.5 mA
Analog input precharge ON and positive reference buffer ON 6.2 mA
Analog input precharge ON, and positive and negative 7.5 8.6 mA
reference buffers ON
AVDD2 Current 5.5 6.2 mA
IOVDD Current Wideband filter 18.9 20.6 mA

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SPECIFICATIONS

Table 2. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
Wideband filter, SPI mode only; disabled channels in Channel 13.4 15.1 mA
Mode A, and set to sinc5 filter3
Sinc5 filter 7.4 8.6 mA
Low Power Mode
AVDD1 Current Analog input precharge ON 1.52 1.77 mA
Analog input precharge ON and positive reference buffer ON 1.84 mA
Analog input precharge ON, and positive and negative 2.2 2.6 mA
reference buffers ON
AVDD2 Current 2.4 3 mA
IOVDD Current Wideband filter 7.6 8.8 mA
Wideband filter, SPI mode only, disabled channels in Channel 6.3 7.2 mA
Mode A, and set to sinc5 filter3
Sinc5 filter 4.8 5.8 mA
Standby Mode All channels disabled (sinc5 filter enabled) 6.5 8 mA
Sleep Mode Full power-down (SPI control mode) 0.73 1.2 mA
Crystal Excitation Current Extra current in IOVDD when using an external crystal com- 540 µA
pared to using the CMOS MCLK
POWER DISSIPATION1 External CMOS MCLK, all channels active, AVDD1 = AVDD2 =
5.5 V, IOVDD = 1.88 V, MCLK = 32.768 MHz, all channels in
Channel Mode A except where otherwise noted
Full Operating Mode—AD7768 Analog precharge buffers on, eight channels active
Wideband Filter
Fast Mode Reference precharge buffers off 524 571 mW
Positive and negative reference precharge buffers ON 638 704 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 422.9
ON
Median Mode Reference precharge buffers off 284 309 mW
Positive and negative reference precharge buffers ON 342 375 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 224.8
ON
Low Power Mode Reference precharge buffers off 98.5 109 mW
Positive and negative reference precharge buffers ON 118 130 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 74.1
ON
Sinc5 Filter
Fast Mode Reference precharge buffers off 455 495 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 358.1
ON
Median Mode Reference precharge buffers off 248 271 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 192.4
ON
Low Power Mode Reference precharge buffers off 94 105 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 66
ON
Full Operating Mode—AD7768-4 Four channels active
Wideband Filter
Fast Mode Reference precharge buffers off 287 314 mW

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SPECIFICATIONS

Table 2. (Continued)
Parameter Test Conditions/Comments Min Typ Max Unit
Positive and negative reference precharge buffers ON 345 381 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 238
ON
Median Mode Reference precharge buffers off 156 172 mW
Positive and negative reference precharge buffers ON 185 206 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 129.6
ON
Low Power Mode Reference precharge buffers off 58 66 mW
Reference precharge buffers on 66 75 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 43
ON
Sinc5 Filter
Fast Mode Reference precharge buffers off 234 257 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 190.7
ON
Median Mode Reference precharge buffers off 129 144 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 104.4
ON
Low Power Mode Reference precharge buffers off 51 59 mW
AVDD1 = 5 V, AVDD2 = 2 V, positive reference precharge buffer 36.7
ON
Standby Mode All channels disabled (sinc5 filter enabled) 17 mW
Sleep Mode Full power-down (SPI control mode) 1.5 4.5 mW

1 These specifications are not production tested but are supported by characterization data at initial product release.
2 Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces
the gain error to the order of the noise for the programmed output data rate.
3 This configuration of setting Channel Mode A to the sinc5 filter and/or assigning disabled channels to Channel Mode A allows a lower power consumption to be achieved
due to the disabling of internal clocks on the disabled only and sinc5 only channel modes. This configuration requires assigning sinc5 and wideband filters to different
channels, or channel modes, and is only available in SPI control mode. In pin control mode, all channels, whether active or in standby, effectively use the same channel
mode. See the Channel Modes section for more details.

TIMING SPECIFICATIONS
AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 2.25 V to 3.6 V, Input Logic 0 = DGND, Input Logic 1 = IOVDD, CLOAD = 10
pF on the DCLK pin, CLOAD = 20 pF on the other digital outputs, REFx+ = 4.096 V, TA = −40°C to +105°C. See Table 5 and Table 6 for timing
specifications at 1.8 V IOVDD.

Table 3. Data Interface Timing1

Parameter Description Test Conditions/Comments Min Typ Max Unit
MCLK Main clock 1.15 34 MHz
fMOD Modulator frequency Fast mode MCLK/4 Hz
Median mode MCLK/8 Hz
Low power mode MCLK/32 Hz
t1 DRDY high time DCLK time period (tDCLK) = t8 + t9 tDCLK − 10% 28 ns
t2 DCLK rising edge to DRDY rising edge 2 ns
t3 DCLK rising to DRDY falling −3.5 0 ns
t4 DCLK rise to DOUTx valid 1.5 ns
t5 DCLK rise to DOUTx invalid −3 ns

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SPECIFICATIONS

Table 3. Data Interface Timing1 (Continued)

Parameter Description Test Conditions/Comments Min Typ Max Unit
t6 DOUTx valid to DCLK falling 9.5 tDCLK/2 ns
t7 DCLK falling edge to DOUTx invalid 9.5 tDCLK/2 ns
t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns
t8a = DCLK = MCLK/2 tMCLK = 1/MCLK tMCLK ns
t8b = DCLK = MCLK/4 2 × tMCLK ns
t8c = DCLK = MCLK/8 4 × tMCLK ns
t9 DCLK low time DCLK = MCLK/1 50:50 CMOS clock (tDCLK/2) − 5 tMCLK/2 tDCLK/2 ns
t9a = DCLK = MCLK/2 tMCLK ns
t9b = DCLK = MCLK/4 2 × tMCLK ns
t9c = DCLK = MCLK/8 4 × tMCLK ns
t10 MCLK rising to DCLK rising CMOS clock 30 ns
t11 Setup time (daisy-chain inputs) DOUT6 and DOUT7 on the AD7768, DIN on 14 ns
the AD7768-4
t12 Hold time (daisy-chain inputs) DOUT6 and DOUT7 on the AD7768, DIN on 0 ns
the AD7768-4
t13 START low time 1 × tMCLK ns
t14 MCLK to SYNC_OUT valid CMOS clock
SYNC_OUT RETIME_EN bit disabled, 4.5 22 ns
measured from falling edge of MCLK
SYNC_OUT RETIME_EN bit enabled, 9.5 27.5 ns
measured from rising edge of MCLK
t15 SYNC_IN setup time CMOS clock 0 ns
t16 SYNC_IN hold time CMOS clock 10 ns

1 These specifications are not production tested but are supported by characterization data at initial product release.

Table 4. SPI Control Interface Timing1

Parameter Description Test Conditions/Comments Min Typ Max Unit
t17 SCLK period 100 ns
t18 CS falling edge to SCLK rising edge 26.5 ns
t19 SCLK falling edge to CS rising edge 27 ns
t20 CS falling edge to data output enable 22.5 40.5 ns
t21 SCLK high time 20 50 ns
t22 SCLK low time 20 50 ns
t23 SCLK falling edge to SDO valid 15 ns
t24 SDO hold time after SCLK falling 7 ns
t25 SDI setup time 0 ns
t26 SDI hold time 6 ns
t27 SCLK enable time 0 ns
t28 SCLK disable time 0 ns
t29 CS high time 10 ns
t30 CS low time fMOD = MCLK/4 1.1 × tMCLK ns
fMOD = MCLK/8 2.2 × tMCLK ns
fMOD = MCLK/32 8.8 × tMCLK ns

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SPECIFICATIONS

1 These specifications are not production tested but are supported by characterization data at initial product release.

1.8 V IOVDD TIMING SPECIFICATIONS

AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 1.72 V to 1.88 V (DREGCAP tied to IOVDD), Input Logic 0 = DGND, Input
Logic 1 = IOVDD, CLOAD = 10 pF on DCLK pin, CLOAD = 20 pF on other digital outputs, TA = −40°C to +105°C.

Table 5. Data Interface Timing1

Parameter Description Test Conditions/Comments Min Typ Max Unit
MCLK Main clock 1.15 34 MHz
fMOD Modulator frequency Fast mode MCLK/4 Hz
Median mode MCLK/8 Hz
Low power mode MCLK/32 Hz
t1 DRDY high time tDCLK − 10% 28 ns
t2 DCLK rising edge to DRDY rising edge 2 ns
t3 DCLK rising to DRDY falling −4.5 0 ns
t4 DCLK rise to DOUTx valid 2.0 ns
t5 DCLK rise to DOUTx invalid −4 ns
t6 DOUTx valid to DCLK falling 8.5 tDCLK/2 ns
t7 DCLK falling edge to DOUTx invalid 8.5 tDCLK/2 ns
t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns
t8a = DCLK = MCLK/2 tMCLK ns
t8b = DCLK = MCLK/4 2 × tMCLK ns
t8c = DCLK = MCLK/8 4 × tMCLK ns
t9 DCLK low time DCLK = MCLK/1 50:50 CMOS clock (tDCLK/2) − 5 tMCLK/2 tDCLK/2 ns
t9a = DCLK = MCLK/2 tMCLK ns
t9b = DCLK = MCLK/4 2 × tMCLK ns
t9c = DCLK = MCLK/8 4 × tMCLK ns
t10 MCLK rising to DCLK rising CMOS clock 37 ns
t11 Setup time (daisy-chain inputs) DOUT6 and DOUT7 on the AD7768, 14 ns
DIN on the AD7768-4
t12 Hold time (daisy-chain inputs) DOUT6 and DOUT7 on the AD7768, 0 ns
DIN on the AD7768-4
t13 START low time 1 × tMCLK ns
t14 MCLK to SYNC_OUT valid CMOS clock
SYNC_OUT RETIME_EN bit disabled, 10 31 ns
measured from falling edge of MCLK
SYNC_OUT RETIME_EN bit enabled, 15 37 ns
measured from rising edge of MCLK
t15 SYNC_IN setup time CMOS clock 0 ns
t16 SYNC_IN hold time CMOS clock 11 ns

1 These specifications are not production tested but are supported by characterization data at initial product release.

Table 6. SPI Control Interface Timing1

Parameter Description Test Conditions/Comments Min Typ Max Unit
t17 SCLK period 100 ns
t18 CS falling edge to SCLK rising edge 31.5 ns

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SPECIFICATIONS

Table 6. SPI Control Interface Timing1 (Continued)

Parameter Description Test Conditions/Comments Min Typ Max Unit
t19 SCLK falling edge to CS rising edge 30 ns
t20 CS falling edge to data output enable 29 54 ns
t21 SCLK high time 20 50 ns
t22 SCLK low time 20 50 ns
t23 SCLK falling edge to SDO valid 16 ns
t24 SDO hold time after SCLK falling 7 ns
t25 SDI setup time 0 ns
t26 SDI hold time 10 ns
t27 SCLK enable time 0 ns
t28 SCLK disable time 0 ns
t29 CS high time 10 ns
t30 CS low time fMOD = MCLK/4 1.1 × tMCLK ns
fMOD = MCLK/8 2.2 × tMCLK ns
fMOD = MCLK/32 8.8 × tMCLK ns

1 These specifications are not production tested but are supported by characterization data at initial product release.

Timing Diagrams

Figure 2. Data Interface Timing Diagram

Figure 3. MCLK to DCLK Divider Timing Diagram

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SPECIFICATIONS

Figure 4. Daisy-Chain Setup and Hold Timing Diagram

Figure 5. Asynchronous START and SYNC_OUT Timing Diagram

Figure 6. Synchronous SYNC_IN Pulse Timing Diagram

Figure 7. SPI Serial Read Timing Diagram

Figure 8. SPI Serial Write Timing Diagram

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Data Sheet AD7768/AD7768-4
SPECIFICATIONS

Figure 9. SCLK Enable and Disable Timing Diagram

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Data Sheet AD7768/AD7768-4
ABSOLUTE MAXIMUM RATINGS

Table 7. THERMAL RESISTANCE

Parameter Rating
Thermal performance is directly linked to printed circuit board
AVDD1, AVDD2 to AVSS1 −0.3 V to +6.5 V (PCB) design and operating environment. Careful attention to PCB
AVDD1 to DGND −0.3 V to +6.5 V thermal design is required.
IOVDD to DGND −0.3 V to +6.5 V Table 8. Thermal Resistance
IOVDD, DREGCAP to DGND (IOVDD Tied to −0.3 V to +2.25 V Package Type θJA θJC Unit JEDEC Board Layers
DREGCAP for 1.8 V Operation)
ST-64-2 38 9.2 °C/W 2P2S1
IOVDD to AVSS −0.3 V to +7.5 V
1 2P2S is a JEDEC standard PCB configuration per JEDEC Standard
AVSS to DGND −3.25 V to +0.3 V
Analog Input Voltage to AVSS −0.3 V to AVDD1 + 0.3 V JESD51-7.
Reference Input Voltage to AVSS −0.3 V to AVDD1 + 0.3 V ESD CAUTION
Digital Input Voltage to DGND −0.3 V to IOVDD + 0.3 V
ESD (electrostatic discharge) sensitive device. Charged devi-
Digital Output Voltage to DGND −0.3 V to IOVDD + 0.3 V ces and circuit boards can discharge without detection. Although
Operating Temperature Range −40°C to +105°C this product features patented or proprietary protection circuitry,
Storage Temperature Range −65°C to +150°C damage may occur on devices subjected to high energy ESD.
Pb-Free Temperature, Soldering Reflow (10 sec 260°C Therefore, proper ESD precautions should be taken to avoid
to 30 sec) performance degradation or loss of functionality.
Maximum Junction Temperature 150°C
Maximum Package Classification Temperature 260°C
1 Transient currents of up to 100 mA do not cause silicon-controlled rectifier
(SCR) latch-up.

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.

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Data Sheet AD7768/AD7768-4
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 10. AD7768 Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Type1 Description
1 AIN1− AI Negative Analog Input to ADC Channel 1.
2 AIN1+ AI Positive Analog Input to ADC Channel 1.
3 AVSS1A P Negative Analog Supply. This pin is nominally 0 V.
4 AVDD1A P Analog Supply Voltage, 5 V ± 10% with Respect to AVSS.
5 REF1− AI Reference Input, Negative. REF1− is the negative reference terminal for Channel 0 to Channel 3. The REF1− voltage
range is from AVSS to (AVDD1 − 1 V). A high quality decoupling capacitor of 1 μF is required between REF1− and
AVSS.
6 REF1+ AI Reference Input, Positive. REF1+ is the positive reference terminal for Channel 0 to Channel 3. The REF1+ voltage
range is from (AVSS + 1 V) to AVDD1. Apply an external differential reference voltage between REF1+ and REF1− in
the range from 1 V to |AVDD1 − AVSS|. A high quality decoupling capacitor of 1 μF is required between REF1+ and
AVSS.
7 AIN2− AI Negative Analog Input to ADC Channel 2.
8 AIN2+ AI Positive Analog Input to ADC Channel 2.
9 AIN3− AI Negative Analog Input to ADC Channel 3.
10 AIN3+ AI Positive Analog Input to ADC Channel 3.
11 FILTER/GPIO4 DI/O Filter Select/General-Purpose Input/Output 4. In pin control mode, this pin selects the filter type.
Set this pin to Logic 1 for the sinc5 filter. This sinc5 filter is a low latency filter and is best for dc applications or when a
user has specialized postfiltering implemented off chip.
Set this pin to Logic 0 for the wideband low ripple filter response. This filter has a steep transition band and 105 dB stop
band attenuation. Full attenuation at Nyquist (ODR/2) means that no aliasing occurs at ODR/2 out to the first chopping
zone.
In SPI control mode, this pin can be used as a general-purpose input/output (GPIO4). For further information on GPIO
configuration, see the GPIO Functionality section. In SPI control mode, when not used as a GPIO pin and when a crystal
is used as the clock source, this pin must be set to 1.
12 to 15 MODE0/GPIO0, DI/DI/O Mode Selection/General-Purpose Input/Output GPIO0 to GPIO3.
MODE1/GPIO1, In pin control mode, the MODEx pins set the mode of operation for all ADC channels, controlling power consumption,
MODE2/GPIO2,
DCLK frequency, and the ADC conversion type, allowing one-shot conversion operation.
MODE3/GPIO3

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Data Sheet AD7768/AD7768-4
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Table 9. Pin Function Descriptions (Continued)

Pin No. Mnemonic Type1 Description
In SPI control mode, the GPIOx pins, in addition to the FILTER/GPIO4 pin, form five general-purpose input/output pins
(GPIO4 to GPIO0).
16 ST0/CS DI Standby 0/Chip Select Input.
In pin control mode, a Logic 1 places Channel 0 to Channel 3 into standby mode.
In SPI control mode, this pin is the active low chip select input to the SPI control interface. The VCM voltage output is
associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also disabled
for maximum power savings. Channel 0 must be enabled while VCM is being used externally to the AD7768.
17 ST1/SCLK DI Standby 1/Serial Clock Input.
In pin control mode, a Logic 1 on this pin places Channel 4 to Channel 7 into standby mode.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is placed into standby mode, the
crystal circuitry is also disabled for maximum power savings. Channel 4 must be enabled while the external crystal is
used on the AD7768.
In SPI control mode, this pin is the serial clock input pin for the SPI control interface.
18 DEC1/SDI DI Decimation Rate Control Input 1/Serial Data Input.
In pin control mode, the DEC0 pin and DEC1 pin configure the decimation rate for all ADC channels. See Table 17 in the
Setting the Decimation Rate section for more information.
In SPI control mode, this pin is the serial data input pin used to write data to the AD7768 register bank.
19 DEC0/SDO DI/O Decimation Rate Control Input 0/Serial Data Output.
In pin control mode, the DEC0 pin and DEC1 pin configure the decimation rate for all ADC channels. See Table 17 in the
Setting the Decimation Rate section for more information.
In SPI control mode, this pin is the serial data output pin, allowing readback from the AD7768 registers.
20 DOUT7 DI/O Conversion Data Output 7. This pin is synchronous to DCLK and framed by DRDY. This pin acts as a digital input
from a separate AD7768 device if configured in a synchronized multidevice daisy chain when the FORMATx pins are
configured as 01. To use the AD7768 in a daisy chain, hardwire the FORMATx pins as 01, 10, or 11, depending on
the best interfacing format for the application. When FORMATx is set to 01, 10, or 11, and daisy-chaining is not used,
connect this pin to ground through a pull-down resistor.
21 DOUT6 DI/O Conversion Data Output 6. This pin is synchronous to DCLK and framed by DRDY. This pin acts as a digital input
from a separate AD7768 device if configured in a synchronized multidevice daisy chain. To use this pin in a daisy
chain, hardwire the FORMATx pins as 01, 10, or 11, depending on the best interfacing format for the application. When
FORMATx is set to 01, 10, or 11, and daisy chaining is not used, connect this pin to ground through a pull-down resistor.
22 DOUT5 DO Conversion Data Output 5. This pin is synchronous to DCLK and framed by DRDY.
23 DOUT4 DO Conversion Data Output 4. This pin is synchronous to DCLK and framed by DRDY.
24 DOUT3 DO Conversion Data Output 3. This pin is synchronous to DCLK and framed by DRDY.
25 DOUT2 DO Conversion Data Output 2. This pin is synchronous to DCLK and framed by DRDY.
26 DOUT1 DO Conversion Data Output 1. This pin is synchronous to DCLK and framed by DRDY.
27 DOUT0 DO Conversion Data Output 0. This pin is synchronous to DCLK and framed by DRDY.
28 DCLK DO ADC Conversion Data Clock. This pin clocks conversion data out to the digital host (digital signal processor (DSP)/
field-programmable gate array (FPGA)). This pin is synchronous with DRDY and any conversion data output on DOUT0
to DOUT7, and is derived from the MCLK signal. This pin is unrelated to the control SPI interface.
29 DRDY DO Data Ready. DRDY is a periodic signal output framing the conversion results from the eight ADCs. This pin is
synchronous to DCLK and DOUT0 to DOUT7.
30 RESET DI Hardware Asynchronous Reset Input. After the device is fully powered up, it is recommended to perform a hard reset
using this pin or, alternatively, to perform a soft reset by issuing a reset over the SPI control interface.
31 XTAL1 DI Input 1 for Crystal or Connection to an LVDS Clock. When CLK_SEL is 0, connect XTAL1 to DGND. In SPI control
mode, when using a crystal source, the FILTER pin must be set to Logic 1 for correct operation. The crystal excitation
circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into standby mode, the crystal circuitry is also
disabled for maximum power savings. Channel 4 must be enabled while the external crystal is used on the AD7768.

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Data Sheet AD7768/AD7768-4
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Table 9. Pin Function Descriptions (Continued)

Pin No. Mnemonic Type1 Description
When used with an LVDS clock, connect this pin to one trace of the LVDS signal pair. When used as an LVDS input, a
rising edge on this pin is detected as a rising MCLK edge by the AD7768.
32 XTAL2/MCLK DI Input 2 for CMOS or Crystal/LVDS Sampling Clock. See the CLK_SEL pin for the details of this configuration.
External crystal: XTAL2 is connected to the external crystal. In SPI control mode, when using a crystal source, the
FILTER pin must be set to Logic 1 for correct operation.
LVDS clock: when used with an LVDS clock, connect this pin to the second trace of the LVDS signal pair.
CMOS clock: this pin operates as an MCLK input. This pin is a CMOS input with a logic level of IOVDD/DGND. When
used as a CMOS clock input, a rising edge on this pin is detected as a rising MCLK edge by the AD7768.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into standby mode, the
crystal circuitry is also disabled for maximum power savings. Channel 4 must be enabled while the external crystal is
used on the AD7768.
33 DGND P Digital Ground. This pin is nominally 0 V.
34 DREGCAP AO Digital Low Dropout (LDO) Regulator Output. Decouple this pin to DGND with a high quality, low equivalent series
resistance (ESR), 10 µF capacitor. For optimum performance, use a decoupling capacitor with an ESR specification of
less than 400 mΩ. This pin is not for use in circuits external to the AD7768. For 1.8 V IOVDD operation, connect this pin
to IOVDD via an external trace to provide power to the digital processing core.
35 IOVDD P Digital Supply. This pin sets the logic levels for all interface pins. IOVDD also powers the digital processing core via the
digital LDO when IOVDD is at least 2.25 V. For 1.8 V IOVDD operation, connect this pin to DREGCAP via an external
trace to provide power to the digital processing core.
36 SYNC_IN DI Synchronization Input. SYNC_IN receives the synchronous signal from SYNC_OUT. SYNC_IN is used in the synchroni-
zation of any AD7768 that requires simultaneous sampling or is in a daisy chain. Ignore the START and SYNC_OUT
functions if the SYNC_IN pin is connected to the system synchronization pulse. This signal pulse must be synchronous
to the MCLK clock domain. In a daisy-chained system of AD7768 devices, two successive synchronization pulses must
be applied to guarantee that all ADCs are synchronized. Two synchronization pulses are also required in a system of
more than one AD7768 device sharing a single MCLK signal, where the DRDY pin of only one device is used to detect
new data.
37 START DI Start Signal. The START pulse synchronizes the AD7768 to other devices. The signal can be asynchronous. The
AD7768 samples the input and then outputs a SYNC_OUT pulse. This SYNC_OUT pulse must be routed to the
SYNC_IN pin of this device, and any other AD7768 devices that must be synchronized together. This means that the
user does not need to run the ADCs and their digital host from the same clock domain, which is useful when there
are long traces or back planes between the ADC and the controller. If this pin is not used, it must be tied to a Logic 1
through a pull-up resistor. In a daisy-chained system of AD7768 devices, two successive synchronization pulses must
be applied to guarantee that all ADCs are synchronized. Two synchronization pulses are also required in a system of
more than one AD7768 device sharing a single MCLK signal, where the DRDY pin of only one device is used to detect
new data.
38 SYNC_OUT DO Synchronization Output. This pin operates only when the START input is used. When using the START input feature,
the SYNC_OUT pin must be connected to SYNC_IN via an external trace. SYNC_OUT is a digital output that is
synchronous to the MCLK signal. The synchronization signal driven in on START is internally synchronized to the
MCLK signal and is driven out on SYNC_OUT. SYNC_OUT can also be routed to other AD7768 devices requiring
simultaneous sampling and/or daisy-chaining, ensuring synchronization of devices related to the MCLK clock domain.
SYNC_OUT must then be wired to drive the SYNC_IN pin on the same AD7768 and on the other AD7768 devices.
39 AIN7+ AI Positive Analog Input to ADC Channel 7.
40 AIN7− AI Negative Analog Input to ADC Channel 7.
41 AIN6+ AI Positive Analog Input to ADC Channel 6.
42 AIN6− AI Negative Analog Input to ADC Channel 6.
43 REF2+ AI Reference Input, Positive. REF2+ is the positive reference terminal for Channel 4 to Channel 7. The REF2+ voltage
range is from (AVSS + 1 V) to AVDD1. Apply an external differential reference voltage between REF2+ and REF2− in
the range from 1 V to |AVDD1 − AVSS|. A high quality decoupling capacitor of 1 μF is required between REF2+ and
AVSS.

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Data Sheet AD7768/AD7768-4
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Table 9. Pin Function Descriptions (Continued)

Pin No. Mnemonic Type1 Description
44 REF2− AI Reference Input, Negative. REF2− is the negative reference terminal for Channel 4 to Channel 7. The REF2− voltage
range is from AVSS to (AVDD1 − 1 V). A high quality decoupling capacitor of 1 μF is required between REF2− and
AVSS.
45 AVDD1B P Analog Supply Voltage. This pin is 5 V ± 10% with respect to AVSS.
46 AVSS1B P Negative Analog Supply. This pin is nominally 0 V.
47 AIN5+ AI Positive Analog Input to ADC Channel 5.
48 AIN5− AI Negative Analog Input to ADC Channel 5.
49 AIN4+ AI Positive Analog Input to ADC Channel 4.
50 AIN4− AI Negative Analog Input to ADC Channel 4.
51 AVSS2B P Negative Analog Supply. This pin is nominally 0 V.
52 REGCAPB AO Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
53 AVDD2B P Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.
54 AVSS P Negative Analog Supply. This pin is nominally 0 V.
55, 56 FORMAT1, FORMAT0 DI Format Selection Pins. Hardwire the FORMATx pins to the required values in pin control and SPI control mode. These
pins set the number of DOUTx pins used to output ADC conversion data. The FORMATx pins are checked by the
AD7768 on power-up. The AD7768 then remains in this data output configuration (see Table 33).
57 PIN/SPI DI Pin Control/SPI Control. This pin sets the control method.
Logic 0 = pin control mode for the AD7768. Pin control mode allows a pin strapped configuration of the AD7768 by
tying logic input pins to required logic levels. Tie the logic pins (MODE0 to MODE4, DEC0 and DEC1, and FILTER) as
required for the configuration. See the Pin Control section for more details.
Logic 1 = SPI control mode for the AD7768. Use the SPI control interface signals (CS, SCLK, SDI, and SDO) for reading
and writing to the AD7768 memory map.
58 CLK_SEL DI Clock Select.
Logic 0 = pull this pin low for the CMOS clock option. The clock is applied to Pin 32 (Connect Pin 31 to DGND).
Logic 1 = pull this pin high for the crystal or LVDS clock option. The crystal or LVDS clock is applied to Pin 31 and Pin
32. The LVDS option is available only in SPI control mode. A write is required to enable the LVDS clock option.
59 VCM AO Common-Mode Voltage Output. This pin outputs (AVDD1 − AVSS)/2 V, which is 2.5 V by default in pin control mode.
Configure this pin to (AVDD1 − AVSS)/2 V, 2.5 V, 2.14 V, or 1.65 V in SPI control mode. When driving capacitive loads
larger than 0.1 µF, it is recommended to place a 50 Ω series resistor between this pin and the capacitive load for
stability. The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the
VCM voltage output is also disabled for maximum power savings. Channel 0 must be enabled while VCM is being used
externally to the AD7768.
60 AVDD2A P Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.
61 REGCAPA AO Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
62 AVSS2A P Negative Analog Supply. This pin is nominally 0 V.
63 AIN0− AI Negative Analog Input to ADC Channel 0.
64 AIN0+ AI Positive Analog Input to ADC Channel 0.

1 AI is analog input, P is power, DI/O is digital input/output, DI is digital input, DO is digital output, and AO is analog output.

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Data Sheet AD7768/AD7768-4
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 11. AD7768-4 Pin Configuration

Table 10. AD7768-4 Pin Function Descriptions

Pin No. Mnemonic Type1 Description
1 AIN1− AI Negative Analog Input to ADC Channel 1.
2 AIN1+ AI Positive Analog Input to ADC Channel 1.
3 AVSS1A P Negative Analog Supply. This pin is nominally 0 V.
4 AVDD1A P Analog Supply Voltage. 5 V ± 10% with respect to AVSS.
5 REF1− AI Reference Input Negative. REF1− is the negative reference terminal for Channel 0 and Channel 1. The REF1−
voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to AVSS with a high quality capacitor, and
maintain a low impedance between this capacitor and Pin 3.
6 REF1+ AI Reference Input Positive. REF1+ is the positive reference terminal for Channel 0 and Channel 1. The REF1+
voltage range is from (AVSS + 1 V) to AVDD1. Apply an external differential reference voltage between REF1+
and REF1− in the range from 1 V to |AVDD1 − AVSS|. A high quality decoupling capacitor of 1 μF is required
between REF1+ and AVSS.
7 to 10, 39 to AVSS AI Negative Analog Supply. This pin is nominally 0 V.
42, 54
11 FILTER/GPIO4 DI/O Filter Select/General-Purpose Input/Output 4. In pin control mode, this pin selects the filter type.
Set this pin to Logic 1 for the sinc5 filter. This sinc5 filter is a low latency filter, and is best for dc applications or
where a user has specialized postfiltering implemented off chip.
Set this pin to Logic 0 for the wideband low ripple filter response. This filter has a steep transition band and
105 dB stop band attenuation. Full attenuation at Nyquist (ODR/2) means that no aliasing occurs at ODR/2 out to
the first chopping zone.
In SPI control mode, this pin can be used as a general-purpose input/output (GPIO4). For further information on
GPIO configuration, see the GPIO Functionality section.
In SPI control mode, when not used as a GPIO pin, and when a crystal is used as the clock source, this pin must
be set to 1.
12 to 15 MODE0/GPIO0, MODE1/ DI/DI/O Mode Selection/General-Purpose Input/Output GPIO0 to GPIO3.
GPIO1, MODE2/GPIO2, In pin control mode, the MODEx pins set the mode of operation for all ADC channels, controlling power
MODE3/GPIO3 consumption, DCLK frequency, and the ADC conversion type, allowing one-shot conversion operation.

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Data Sheet AD7768/AD7768-4
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Table 10. AD7768-4 Pin Function Descriptions (Continued)

Pin No. Mnemonic Type1 Description
In SPI control mode, the GPIOx pins, in addition to the FILTER/GPIO4 pin, form five general-purpose input/output
pins (GPIO4 to GPIO0). See Table 75 for more details.
16 ST0/CS DI Standby 0/Chip Select Input.
In pin control mode, a Logic 1 on this pin places Channel 0 to Channel 3 into standby mode.
In SPI control mode, this pin is the active low chip select input to the SPI control interface.
The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the
VCM voltage output is also disabled for maximum power savings. Channel 0 must be enabled while VCM is
being used externally to the AD7768-4. The crystal excitation circuitry is associated with the Channel 2 circuitry. If
Channel 2 is put into standby mode, the crystal circuitry is also disabled for maximum power savings. Channel 2
must be enabled while the external crystal is used on the AD7768-4.
17 SCLK DI Serial Clock Input.
In SPI control mode, this pin is the serial clock input pin for the SPI control interface.
In pin control mode, tie this pin to a Logic 0 or DGND.
18 DEC1/SDI DI Decimation Rate Control Input 1/Serial Data Input.
In pin control mode, the DEC0 pin and DEC1 pin configure the decimation rate for all ADC channels. See Table
17 in the Setting the Decimation Rate section.
In SPI control mode, this pin is the serial data input pin used to write data to the AD7768-4 register bank.
19 DEC0/SDO DI/O Decimation Rate Control Input 0/Serial Data Output.
In pin control mode, the DEC0 pin and DEC1 pin configure the decimation rate for all ADC channels. See Table
17 in the Setting the Decimation Rate section.
In SPI control mode, this pin is the serial data output pin, allowing readback from the AD7768-4 registers.
20 DNC/DGND DO/DI Do Not Connect/Digital Ground. This is an unused pin. Leave this pin floating if FORMAT0 is tied to logic low. If
FORMAT0 is tied to logic high, connect this pin to DGND through a pull-down resistor.
21 DIN DI Data Input Daisy Chain. This pin acts as a digital input from a separate AD7768-4 device if configured in a
synchronized multidevice daisy chain. To use this pin in a daisy chain, hardwire the FORMAT0 pin to logic high.
If FORMAT0 is tied to logic low, or the daisy-chaining input pin is not used, then tie this pin to DGND through a
pull-down resistor.
22, 23 DNC DO Do Not Connect. Do not connect to this pin.
24 DOUT3 DO Conversion Data Output 3. This pin is synchronous to DCLK and framed by DRDY.
25 DOUT2 DO Conversion Data Output 2. This pin is synchronous to DCLK and framed by DRDY.
26 DOUT1 DO Conversion Data Output 1. This pin is synchronous to DCLK and framed by DRDY.
27 DOUT0 DO Conversion Data Output 0. This pin is synchronous to DCLK and framed by DRDY.
28 DCLK DO ADC Conversion Data Clock. This pin clocks conversion data out to the digital host (DSP/FPGA). This pin is
synchronous with DRDY and any conversion data output on DOUT0 to DOUT3 and is derived from the MCLK
signal. This pin is unrelated to the control SPI interface.
29 DRDY DO Data Ready. DRDY is a periodic signal output framing the conversion results from the four ADCs. This pin is
synchronous to DCLK and DOUT0 to DOUT3.
30 RESET DI Hardware Asynchronous Reset Input. After the device is fully powered up, it is recommended to perform a hard
reset using this pin or, alternatively, to perform a soft reset by issuing a reset over the SPI control interface.
31 XTAL1 DI Input 1 for Crystal or Connection to an LVDS Clock. When CLK_SEL is 0, connect XTAL1 to DGND. In SPI
control mode, when using a crystal source, the FILTER pin must be set to Logic 1 for correct operation. When
used with an LVDS clock, it is recommended that this pin be connected to one trace of the LVDS signal pair.
When used as an LVDS input, a rising edge on this pin is detected as a rising MCLK edge by the AD7768-4.
32 XTAL2/MCLK DI Input 2 for CMOS/Crystal/LVDS Sampling Clock. See the CLK_SEL pin for the details of this configuration.
External crystal: XTAL2 is connected to the external crystal. In SPI control mode, when using a crystal source,
the FILTER pin must be set to Logic 1 for correct operation.
LVDS: when used with an LVDS clock, connect this pin to the second trace of the LVDS signal pair.

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Data Sheet AD7768/AD7768-4
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Table 10. AD7768-4 Pin Function Descriptions (Continued)

Pin No. Mnemonic Type1 Description
CMOS clock: this pin operates as an MCLK input. This pin is a CMOS input with a logic level of IOVDD/DGND.
When used as a CMOS clock input, a rising edge on this pin is detected as a rising MCLK edge by the
AD7768-4.
33 DGND P Digital Ground. Nominally GND (0 V).
34 DREGCAP AO Digital LDO Regulator Output. Decouple this pin to DGND with a high quality, low ESR, 10 µF capacitor. For
optimum performance, use a decoupling capacitor with an ESR specification of less than 400 mΩ. This pin is
not for use in circuits external to the AD7768-4. For 1.8 V IOVDD operation, connect this pin to IOVDD via an
external trace to provide power to the digital processing core.
35 IOVDD P Digital Supply. This pin sets the logic levels for all interface pins. IOVDD also powers the digital processing core,
via the digital LDO, when IOVDD is at least 2.25 V. For 1.8 V IOVDD operation, connect this pin to DREGCAP via
an external trace to provide power to the digital processing core.
36 SYNC_IN DI Synchronization Input. SYNC_IN receives the synchronous signal from SYNC_OUT. SYNC_IN is used in the
synchronization of any AD7768-4 that requires simultaneous sampling or is in a daisy chain. The user can ignore
the START and SYNC_OUT function if the AD7768-4 SYNC_IN pin is connected to the system synchronization
pulse. This signal pulse must be synchronous to the MCLK clock domain.
37 START DI Start Signal. The START pulse acts to synchronize the AD7768-4 to other devices. The signal can be
asynchronous. The AD7768-4 samples the input and then outputs a SYNC_OUT pulse. This SYNC_OUT pulse
must be routed to the SYNC_IN pin of this device, and any other AD7768-4 devices that must be synchronized
together. This means that the user does not need to run the ADCs and their digital host from the same clock
domain, which is useful when there are long traces or back planes between the ADC and the controller. If this
pin is not used, it must be tied to a Logic 1 through a pull-up resistor. In a daisy-chained system of AD7768-4
devices, two successive synchronization pulses must be applied to guarantee that all ADCs are synchronized.
Two synchronization pulses are also required in a system of more than one AD7768-4 device sharing a single
MCLK signal, where the DRDY pin of only one device is used to detect new data.
38 SYNC_OUT DO Synchronization Output. This pin operates only when the START input is used. When using the START input
feature, SYNC_OUT must be connected to SYNC_IN via an external trace. SYNC_OUT is a digital output that
is synchronous to the MCLK signal. The synchronization signal driven in on START is internally synchronized to
the MCLK signal and is driven out on SYNC_OUT. SYNC_OUT can also be routed to other AD7768-4 devices
requiring simultaneous sampling and/or daisy-chaining, ensuring synchronization of devices related to the MCLK
clock domain. SYNC_OUT must then be wired to drive the SYNC_IN pin on the same AD7768-4 and on the
other AD7768-4 devices.
43 REF2+ AI Reference Input Positive. REF2+ is the positive reference terminal for Channel 2 and Channel 3. The REF2+
voltage range is from (AVSS + 1 V) to AVDD1. Apply an external differential reference voltage between REF2+
and REF2− in the range from 1 V to |AVDD1 − AVSS|. Decouple this pin to AVSS with a high quality capacitor,
and maintain a low impedance between this capacitor and Pin 3.
44 REF2− AI Reference Input Negative. REF2− is the negative reference terminal for Channel 2 and Channel 3. The REF2−
voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to AVSS with a high quality capacitor, and
maintain a low impedance between this capacitor and Pin 3.
45 AVDD1B P Analog Supply Voltage. This pin is 5 V ± 10% with respect to AVSS.
46 AVSS1B P Negative Analog Supply. This pin is nominally 0 V.
47 AIN3+ AI Positive Analog Input to ADC Channel 3.
48 AIN3− AI Negative Analog Input to ADC Channel 3.
49 AIN2+ AI Positive Analog Input to ADC Channel 2.
50 AIN2− AI Negative Analog Input to ADC Channel 2.
51 AVSS2B P Negative Analog Supply. This pin is nominally 0 V.
52 REGCAPB AO Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
53 AVDD2B P Analog Supply Voltage. 2 V to 5.5 V with respect to AVSS.
55 DGND P Digital Ground. This pin is nominally 0 V.

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Data Sheet AD7768/AD7768-4
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Table 10. AD7768-4 Pin Function Descriptions (Continued)

Pin No. Mnemonic Type1 Description
56 FORMAT0 DI Format Selection. Hardwire the FORMAT0 pin to the required value in pin and SPI control mode. This pin sets
the number of DOUTx pins used to output ADC conversion data. The FORMAT0 pin is checked by the AD7768-4
on power-up, the AD7768-4 then remains in this data output configuration. See Table 34.
57 PIN/SPI DI Pin Control/SPI Control. This pin sets the AD7768-4 control method.
Logic 0 = pin control mode for the AD7768-4. Pin control mode allows pin strapped configuration of the AD7768-4
by tying logic input pins to required logic levels. Tie logic pins (MODE0 to MODE4, DEC0 and DEC1, and
FILTER) as required for the configuration. See the Pin Control section for more details.
Logic 1 = SPI control mode for the AD7768-4. Use the SPI control interface signals (CS, SCLK, SDI, and SDO)
for reading and writing to the AD7768-4 memory map.
58 CLK_SEL DI Clock Select.
Logic 0 = pull this pin low for the CMOS clock option. The clock is applied to Pin 32 (Connect Pin 31 to DGND).
Logic 1 = pull this pin high for the crystal or LVDS clock option. The crystal or LVDS clock is applied to Pin 31
and Pin 32. The LVDS option is available only in SPI control mode. A write is required to enable the LVDS clock
option.
59 VCM AO Common-Mode Voltage Output. This pin outputs (AVDD1 − AVSS)/2 V, which is 2.5 V by default in pin control
mode. Configure this pin to (AVDD1 − AVSS)/2 V, 2.5 V, 2.14 V, or 1.65 V in SP control mode. When driving
capacitive loads larger than 0.1 µF, it is recommended to place a 50 Ω series resistor between the pin and the
capacitive load for stability. The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is
put into standby mode, the VCM voltage output is also disabled for maximum power savings. Channel 0 must be
enabled while VCM is being used externally to the AD7768-4.
60 AVDD2A P Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.
61 REGCAPA AO Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
62 AVSS2A P Negative Analog Supply. This pin is nominally 0 V.
63 AIN0− AI Negative Analog Input to ADC Channel 0.
64 AIN0+ AI Positive Analog Input to ADC Channel 0.
1 AI is analog input, P is power, DI/O is digital input/output, DI is digital input, DO is digital output, and AO is analog output.

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Data Sheet AD7768/AD7768-4
TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 5 V, AVDD2 = 2.5 V, AVSS = 0 V, IOVDD = 2.5 V, VREF = 4.096 V, TA = 25°C, wideband filter, decimation = ×32, MCLK = 32.768 MHz,
analog input precharge buffers on, precharge reference buffers off, unless otherwise noted.

Figure 12. Fast Fourier Transform (FFT), Fast Mode, Wideband Filter, Figure 15. FFT, Fast Mode, Wideband Filter, −6 dBFS
−0.5 dBFS

Figure 16. FFT, Median Mode, Wideband Filter, −6 dBFS

Figure 13. FFT, Median Mode, Wideband Filter, −0.5 dBFS

Figure 17. FFT, Low Power Mode, Wideband Filter, −6 dBFS

Figure 14. FFT, Low Power Mode, Wideband Filter, −0.5 dBFS

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 18. FFT, Fast Mode, Sinc5 Filter, −0.5 dBFS Figure 21. FFT, Fast Mode, Sinc5 Filter, −6 dBFS

Figure 19. FFT, Median Mode, Sinc5 Filter, −0.5 dBFS Figure 22. FFT, Median Mode, Sinc5 Filter, −6 dBFS

Figure 20. FFT, Low Power Mode, Sinc5 Filter, −0.5 dBFS Figure 23. FFT, Low Power Mode, Sinc5 Filter, −6 dBFS

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 24. FFT One Shot Mode, Sinc5 Filter, Median Mode, Decimation = ×64, Figure 27. Shorted Noise, Sinc5 Filter
−0.5 dBFS, SYNC_IN Frequency = MCLK/4000

Figure 28. Shorted Noise at Different Temperatures, Wideband Filter

Figure 25. Intermodulation Distortion (IMD) with Input Signals at 9.7 kHz and
10.3 kHz

Figure 29. RMS Noise vs. Temperature, Fast Mode

Figure 26. Shorted Noise, Wideband Filter

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Data Sheet AD7768/AD7768-4
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 30. RMS Noise vs. Temperature, Median Mode Figure 33. Crosstalk

Figure 34. SNR, Dynamic Range, THD, and THD + N vs. MCLK Frequency
Figure 31. RMS Noise vs. Temperature, Low Power Mode

Figure 35. THD vs. Input Frequency, Three Power Modes, Wideband Filter
Figure 32. RMS Noise per Channel for Various VREF Values

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 36. THD vs. Input Frequency, Three Power Modes, Sinc5 Filter Figure 39. SNR vs. Input Amplitude

Figure 37. THD and THD + N vs. Input Amplitude, Wideband Filter Figure 40. INL Error vs. Input Voltage for Various VREF Levels, Fast Mode

Figure 38. THD and THD + N vs. Input Amplitude, Sinc5 Filter Figure 41. INL Error vs. Input Voltage for Various VREF Levels, Median Mode

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Data Sheet AD7768/AD7768-4
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 42. INL Error vs. Input Voltage for Various VREF Levels, Low Power Figure 45. Offset Error Distribution, DCLK = 24 MHz
Mode

Figure 46. Offset Error Distribution, DCLK = 32 MHz

Figure 43. INL Error vs. Input Voltage, Full-Scale, Half-Scale, and Quarter-
Scale Inputs

Figure 47. Offset Error Drift, DCLK = 24 MHz

Figure 44. INL Error vs. Input Voltage for Various Temperatures, Fast Mode

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Data Sheet AD7768/AD7768-4
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 48. Offset Error Drift, DCLK = 32 MHz Figure 51. Gain Error Distribution

Figure 49. Offset Drift vs. DCLK Frequency Figure 52. Channel to Channel Gain Error Matching

Figure 50. Channel Offset Error Matching Figure 53. AC CMRR vs. Input Frequency

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 54. AC PSRR vs. Frequency, AVDD1 Figure 57. Amplitude vs. Normalized Input Frequency (fIN/fODR), Wideband
Filter Profile

Figure 55. AC PSRR vs. Frequency, AVDD2 Figure 58. Step Response, Wideband Filter

Figure 56. AC PSRR vs. Frequency, IOVDD Figure 59. Wideband Filter Ripple

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Data Sheet AD7768/AD7768-4
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 60. Amplitude vs. Normalized Input Frequency (fIN/fODR), Sinc5 Filter Figure 63. Reference Input Current vs. Temperature, Reference Precharge
Profile Buffers On/Off

Figure 61. Step Response, Sinc5 Filter

Figure 64. VCM Output Voltage Distribution

Figure 62. Analog Input Current vs. Temperature, Analog Input Precharge
Buffers On/Off Figure 65. Supply Current vs. Temperature, AVDD1

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Data Sheet AD7768/AD7768-4
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 66. Supply Current vs. Temperature, AVDD2

Figure 67. Supply Current vs. Temperature, IOVDD

Figure 68. Total Power vs. Temperature

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Data Sheet AD7768/AD7768-4
TERMINOLOGY

AC Common-Mode Rejection Ratio (AC CMRR) Least Significant Bit (LSB)

AC CMRR is defined as the ratio of the power in the ADC output The least significant bit, or LSB, is the smallest increment that can
at frequency, f, to the power of a sine wave applied to the common- be represented by a converter. For a fully differential input ADC with
mode voltage of AINx+ and AINx− at sampling frequency, fS. N bits of resolution, the LSB expressed in volts is as follows:
AC CMRR (dB) = 10log(Pf/PfS) LSB (V) = (2 × VREF)/2N
where: For the AD7768/AD7768-4, VREF is the difference voltage between
Pf is the power at frequency, f, in the ADC output. the REFx+ and REFx− pins, and N = 24.
PfS is the power at frequency, fS, in the ADC output.
Offset Error
Gain Error
Offset error is the difference between the ideal midscale input
The first transition (from 100 … 000 to 100 … 001) occurs at voltage (0 V) and the actual voltage producing the midscale output
a level ½ LSB above nominal negative full scale (−4.0959375 V code.
for the ±4.096 V range). The last transition (from 011 … 110 to
011 … 111) occurs for an analog voltage 1½ LSB below the nominal Power Supply Rejection Ratio (PSRR)
full scale (4.0959375 V for the ±4.096 V range). The gain error Variations in power supply affect the full-scale transition but not
is the deviation of the difference between the actual level of the the linearity of the converter. PSRR is the maximum change in
last transition and the actual level of the first transition from the the full-scale transition point due to a change in the power supply
difference between the ideal levels. voltage from the nominal value.
Gain Error Drift Signal-to-Noise Ratio (SNR)
Gain error drift is the gain error change due to a temperature SNR is the ratio of the rms value of the actual input signal to
change of 1°C. It is expressed in parts per million per degree the rms sum of all other spectral components below the Nyquist
Celsius. frequency, excluding harmonics and dc. The value for SNR is
Integral Nonlinearity (INL) Error expressed in decibels.

INL error refers to the deviation of each individual code from a Signal-to-Noise-and-Distortion Ratio (SINAD)
line drawn from negative full scale through positive full scale. The SINAD is the ratio of the rms value of the actual input signal to
point used as negative full scale occurs ½ LSB before the first code the rms sum of all other spectral components below the Nyquist
transition. Positive full scale is defined as a level 1½ LSB greater frequency, including harmonics but excluding dc. The value for
than the last code transition. The deviation is measured from the SINAD is expressed in decibels.
middle of each code to the true straight line.
Spurious-Free Dynamic Range (SFDR)
Intermodulation Distortion (IMD)
SFDR is the difference, in decibels, between the rms amplitude of
With inputs consisting of sine waves at two frequencies, fa and fb, the input signal and the peak spurious signal (excluding the first five
any active device with nonlinearities creates distortion products at harmonics).
the sum and difference frequencies of mfa and nfb, where m, n =
0, 1, 2, 3, and so on. Intermodulation distortion terms are those for Total Harmonic Distortion (THD)
which neither m or n are equal to 0. For example, the second-order THD is the ratio of the rms sum of the first five harmonic compo-
terms include (fa + fb) and (fa − fb), and the third-order terms nents to the rms value of a full-scale input signal and is expressed
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). in decibels.
The AD7768/AD7768-4 are tested using the CCIF standard, where
two input frequencies near to each other are used. In this case,
the second-order terms are usually distanced in frequency from the
original sine waves, and the third-order terms are usually at a fre-
quency close to the input frequencies. As a result, the second-order
and third-order terms are specified separately. The calculation of
the intermodulation distortion is as per the THD specification, where
it is the ratio of the rms sum of the individual distortion products
to the rms amplitude of the sum of the fundamentals, expressed in
decibels.

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Data Sheet AD7768/AD7768-4
THEORY OF OPERATION

The AD7768/AD7768-4 are 8-channel/4-channel, simultaneously

sampled, low noise, 24-bit ∑-∆ ADCs, respectively.
Each ADC within the AD7768/AD7768-4 employs a Σ-Δ modulator
whose clock runs at a frequency of fMOD. The modulator samples
the inputs at a rate of 2 × fMOD to convert the analog input
into an equivalent digital representation. These samples, therefore,
represent a quantized version of the analog input signal. Figure 71. Σ-Δ ADC Digital Filter Cutoff Frequency (Linear Scale X-Axis)

The Σ-Δ conversion technique is an oversampled architecture. This CLOCKING, SAMPLING TREE, AND POWER
oversampled approach spreads the quantization noise over a wide SCALING
frequency band (see Figure 69). To reduce the quantization noise
in the signal band, the high order modulator shapes the noise The AD7768/AD7768-4 include multiple ADC cores. Each of these
spectrum so that most of the noise energy is shifted out of the ADCs receives the same main clock signal, MCLK. The MCLK
band of interest (see Figure 70). The digital filter that follows the signal can be sourced from one of three options: a CMOS clock,
modulator removes the large out of band quantization noise (see a crystal connected between the XTAL1 pin and XTAL2 pin, or
Figure 71). in the form of an LVDS signal. The MCLK signal received by the
AD7768/AD7768-4 defines the modulator clock rate, fMOD, and, in
For further information on the basics as well as more advanced turn, the sampling frequency of the modulator of 2 × fMOD. The
concepts of Σ-Δ ADCs, see the MT-022 Tutorial and the MT-023 same MCLK signal is also used to define the digital output clock,
Tutorial. DCLK. The fMOD and DCLK internal signals are synchronous with
Digital filtering has certain advantages over analog filtering. First, MCLK.
it is insensitive to component tolerances and the variation of com- Figure 72 illustrates the clock tree from the MCLK input to the
ponent parameters over time and temperature. Because digital modulator, the digital filter, and the DCLK output. There are divider
filtering on the AD7768/AD7768-4 occurs after the analog to digital settings for MCLK and DCLK. These dividers in conjunction with
conversion, digital filtering can remove some of the noise injected the power mode and digital filter decimation settings are key to
during the conversion process. Analog filtering cannot remove AD7768/AD7768-4 operation.
noise injected during conversion. Second, the digital filter combines
low pass-band ripple with a steep roll-off, and high stop band The AD7768/AD7768-4 have the ability to scale power consump-
attenuation, while also maintaining a linear phase response, which tion vs. the input bandwidth or noise desired. The user controls
is difficult to achieve in an analog filter implementation. two parameters to achieve this: MCLK division and power mode.
Combined, these two settings determine the clock frequency of the
modulator (fMOD) and the bias current supplied to each modulator.
The power mode (fast, median, or low power) sets the noise, speed
capability, and current consumption of the modulator. The power
mode is the dominant control for scaling the power consumption of
the ADC. All settings of MCLK division and power mode apply to all
ADC channels.
Figure 69. Σ-Δ ADC Quantization Noise (Linear Scale X-Axis)

Figure 70. Σ-Δ ADC Noise Shaping (Linear Scale X-Axis)

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Data Sheet AD7768/AD7768-4
THEORY OF OPERATION

Figure 72. Sampling Structure, Defined by MCLK, DCLK_DIV, and MCLK_DIV Settings

The modulator clock frequency (fMOD) is determined by selecting highest resolution. This choice is due to an overlap in the coverage
one of three clock divider settings: MCLK/4, MCLK/8, or MCLK/32. of each power mode. The devices offer the ability to balance the
MCLK division ratio with the rate of decimation (averaging) set
Although the MCLK division and power modes are independent in the digital filter. Lower power can be achieved by using lower
settings, there are restrictions that must be adhered to. A valid modulator clock frequencies. Conversely, the highest resolution
range of modulator frequencies exists for each power mode. Table can be achieved by using higher modulator clock frequencies and
11 describes this recommended range, which allows the device to maximizing the amount of oversampling.
achieve the best performance while minimizing power consumption.
The AD7768/AD7768-4 specifications do not cover the performance As an example, consider a system constraint with a maximum
and function beyond the maximum fMOD for a given power mode. available MCLK of 16 MHz. The system is targeting a measurement
bandwidth of approximately 25 kHz with the wideband filter, setting
For example, in fast mode, to maximize the speed of conversion the output data rate of the AD7768/AD7768-4 to 62.5 kHz. Because
or input bandwidth, an MCLK of 32.768 MHz is required and of the low MCLK frequency available and system power budget,
MCLK_DIV = 4 must be selected for a modulator frequency of median power mode is used.
8.192 MHz.
Table 11. Recommended fMOD Range for Each Power Mode
In median power mode, this 25 kHz input bandwidth can be ach-
ieved by setting the MCLK division and decimation ratio to balance,
Power Mode Recommended fMOD (MHz) Range, MCLK = 32.768 MHz using two configurations. This flexibility is possible in SPI control
Low Power 0.036 to 1.024 mode only.
Median 1.024 to 4.096
Fast 4.096 to 8.192
Configuration A
To maximize the dynamic range, use the following settings:
Control of the settings for power mode, the modulator frequency
and the data clock frequency differs in pin control mode vs. SPI ► MCLK = 16 MHz
control mode. ► Median power
In SPI control mode, the user can program the power mode, MCLK ► fMOD = MCLK/4
divider (MCLK_DIV), and DCLK frequency using Register 0x04 and ► Decimation = ×64 (digital filter setting)
Register 0x07 (see Table 42 and Table 45 for register information ► ODR = 62.5 kHz
for the AD7768 or Table 68 and Table 71 for the AD7768-4). Inde-
pendent selection of the power mode and MCLK_DIV allows full This configuration maximizes the available decimation rate (or over-
freedom in the MCLK speed selection to achieve a target modulator sampling ratio) for the bandwidth required and MCLK rate available.
frequency. The decimation averages the noise from the modulator, maximizing
the dynamic range.
In pin control mode, the MODEx pins determine the power mode,
modulator frequency, and DCLK frequency. The modulator frequen- Configuration B
cy tracks the power mode. This means that fMOD is fixed at
MCLK/32 for low power mode, MCLK/8 for median mode, and To minimize power, use the following settings:
MCLK/4 for fast mode (see Table 20). ► MCLK = 16 MHz
► Median power
Example of Power vs. Noise Performance
► fMOD = MCLK/8
Optimization
► Decimation = ×32 (digital filter setting)
Depending on the bandwidth of interest for the measurement, the ► ODR = 62.5 kHz
user can choose a strategy of either lowest current consumption or

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Data Sheet AD7768/AD7768-4
THEORY OF OPERATION

This configuration reduces the clocking speed of the modulator and the AD7768-4. Therefore, the intended minimum decimation and
the digital filter. desired DCLK_DIV setting must be understood prior to choosing
the setting of the FORMATx pins.
Compared to Configuration A, Configuration B saves 48 mW of
power. The trade-off in the case of Configuration B is that the digital NOISE PERFORMANCE AND RESOLUTION
filter must run at a 2× lower decimation rate. This 2× reduction in
decimation rate (or oversampling ratio) results in a 3 dB reduction in Table 12 and Table 13 show the noise performance for the wide-
the dynamic range vs. Configuration A. band and sinc5 digital filters of the AD7768/AD7768-4 for various
output data rates and power modes. The noise values and dynamic
Clocking Out the ADC Conversion Results range specified are typical for the bipolar input range with an
external 4.096 V reference (VREF). The rms noise is measured with
(DCLK)
shorted analog inputs, which are driven to (AVDD1 − AVSS)/2 using
The AD7768/AD7768-4 DCLK is a divided version of the main clock the on-board VCM buffer output.
input. As shown in Figure 72, the DCLK_DIV setting determines the The dynamic range is calculated as the ratio of the rms shorted
speed of the DCLK. DCLK is a continuous clock. input noise to the rms full-scale input signal range.
The user can set the DCLK frequency rate to one of four divisions Dynamic Range (dB) = 20log10((2 × VREF/2√2)/(RMS Noise)
of MCLK: MCLK/1, MCLK/2, MCLK/4, and MCLK/8. Because there
are eight channels and 32 bits of data per conversion, the conver- The LSB size with 4.096 V reference is 488 nV, and is calculated as
sion time and the setting of DCLK directly determine the number follows:
of data output lines that are required via the FORMAT0 pin and
FORMAT1 pin settings on the AD7768, or the FORMAT0 pin on LSB (V) = (2 × VREF)/224
Table 12. Wideband Filter Noise: Performance vs. Output Data Rate (VREF = 4.096 V)
Output Data Rate (kSPS) −3 dB Bandwidth (kHz) Shorted Input Dynamic Range (dB) RMS Noise (µV)
Fast Mode
256 110.8 107.96 11.58
128 55.4 111.43 7.77
64 27.7 114.55 5.42
32 13.9 117.58 3.82
16 6.9 120.56 2.72
8 3.5 123.5 1.94
Median Mode
128 55.4 108.13 11.36
64 27.7 111.62 7.6
32 13.9 114.75 5.3
16 6.9 117.79 3.74
8 3.5 120.8 2.64
4 1.7 123.81 1.87
Low Power Mode
32 13.9 108.19 11.28
16 6.9 111.69 7.54
8 3.5 114.83 5.25
4 1.7 117.26 3.71
2 0.87 120.88 2.62
1 0.43 123.88 1.85

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THEORY OF OPERATION

Table 13. Sinc5 Filter Noise: Performance vs. Output Data Rate (VREF = 4.096 V)
Output Data Rate (kSPS) −3 dB Bandwidth (kHz) Shorted Input Dynamic Range (dB) RMS Noise (µV)
Fast Mode
256 52.224 111.36 7.83
128 26.112 114.55 5.43
64 13.056 117.61 3.82
32 6.528 120.61 2.71
16 3.264 123.52 1.93
8 1.632 126.39 1.39
Median Mode
128 26.112 111.53 7.68
64 13.056 114.75 5.3
32 6.528 117.81 3.72
16 3.264 120.82 2.64
8 1.632 123.82 1.87
4 0.816 126.79 1.33
Low Power Mode
32 6.528 111.57 7.65
16 3.264 114.82 5.26
8 1.632 117.88 3.7
4 0.816 120.9 2.61
2 0.408 123.91 1.85
1 0.204 126.89 1.31

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Data Sheet AD7768/AD7768-4
APPLICATIONS INFORMATION

The AD7768/AD7768-4 offer users a multichannel platform meas- ► Control of reference and analog input precharge buffers on a per
urement solution for ac and dc signal processing. channel basis.
Flexible filtering allows the AD7768/AD7768-4 to be configured to ► Wideband, low ripple, digital filter for ac measurement.
simultaneously sample ac and dc signals on a per channel basis. ► Fast sinc5 filter for precision low frequency measurement.
Power scaling allows users to trade off the input bandwidth of the ► Two channel modes, defined by the user selected filter choice,
measurement vs. the current consumption. This ability, coupled with and decimation ratios, can be defined for use on different ADC
the flexibility of the digital filtering, allows the user to optimize the channels. This enables optimization of the input bandwidth ver-
energy efficiency of the measurement, while still meeting power, sus the signal of interest.
bandwidth, and performance targets. ► Option of SPI or pin strapped control and configuration.
Key capabilities that allow users to choose the AD7768/ ► Offset, gain, and phase calibration registers per channel.
AD7768-4as their platform high resolution ADC are as follows: ► Common-mode voltage output buffer for use by driver amplifier.
► On-board AVDD2 and IOVDD LDOs for the low power, 1.8 V,
► Eight fully differential or pseudo differential analog inputs on the
internal circuitry.
AD7768 (four channels on the AD7768-4).
► Fast throughput simultaneous sampling ADCs catering for input Refer to Figure 73 and Table 14 for the typical connections
signals up to 110.8 kHz. and minimum requirements to get started using the AD7768/
► Three selectable power modes (fast, median, and low power) for AD7768-4.
scaling the current consumption and input bandwidth of the ADC Table 15 shows the typical power and performance of the AD7768/
for optimal measurement efficiency. AD7768-4 for the available power modes, for each filter type.
► Analog input precharge and reference precharge buffers reduce
the drive requirements of external amplifiers.

Figure 73. Typical Connection Diagram

Table 14. Requirements to Operate the AD7768/AD7768-4

Requirement Description
Power Supplies 5 V AVDD1 supply, 2.25 V to 5 V AVDD2 supply, 1.8 V or 2.5 V to 3.3 V IOVDD supply (ADP7104/ADP7118)
External Reference 2.5 V, 4.096 V, or 5 V (ADR4525, ADR4540, or ADR4550)
External Driver Amplifiers The ADA4896-2, the ADA4940-1/ADA4940-2, the ADA4805-2, and the ADA4807-2
External Clock Crystal or a CMOS/LVDS clock for the ADC modulator sampling
FPGA or DSP Input/output voltage of 2.5 V to 3.6 V, or 1.8 V (see the 1.8 V IOVDD Operation section)

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APPLICATIONS INFORMATION

Table 15. Speed, Dynamic Range, THD, and Power Overview, Eight Channels Active, Decimate by 321

Output Sinc5 Filter Wideband Filter

Data Rate THD Dynamic Bandwidth Power Dissipation (mW Dynamic Range Bandwidth Power Dissipation (mW
Power Mode (kSPS) (dB) Range (dB) (kHz) per channel) (dB) (kHz) per channel)
Fast 256 −115 111 52.224 41 108 110.8 52
Median 128 −120 111 26.112 22 108 55.4 28
Low Power 32 −120 111 6.528 8.5 108 13.9 9.5

1 Analog precharge buffers on, reference precharge buffers and VCM disabled, typical values, AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, VREF = 4.096 V, MCLK = 32.768 MHz,
DCLK = MCLK/4, TA = 25°C.

POWER SUPPLIES (minimum) to 1.88 V (maximum), with respect to DGND. See the
1.8 V IOVDD Operation section for more information on operating
The AD7768/AD7768-4 have three independent power supplies: the AD7768/AD7768-4 at 1.8 V IOVDD.
AVDD1 (AVDD1A and AVDD1B), AVDD2 (AVDD2A and AVDD2B),
and IOVDD. Recommended Power Supply Configuration
The reference potentials for these supplies are AVSS and DGND. Analog Devices, Inc., has a wide range of power management
Tie all the AVSS supply pins (AVSS1A, AVSS1B, AVSS2A, products to meet the requirements of most high performance signal
AVSS2B, and AVSS) to the same potential with respect to DGND. chains.
AVDD1A, AVDD1B, AVDD2A, and AVDD2B are referenced to this
AVSS rail. IOVDD is referenced to DGND. An example of a power solution that uses the ADP7118 is shown in
Figure 74. The ADP7118 provides positive supply rails for optimal
The supplies can be powered within the following ranges: converter performance, creating either a single 5 V, 3.3 V, or
► AVDD1 = 5 V ± 10%, relative to AVSS dual AVDD1x and AVDD2x/IOVDD supply rail, depending on the
► AVDD2 = 2 V to 5.5 V, relative to AVSS required supply configuration. The ADP7118 can operate from input
► IOVDD (with internal regulator) = 2.25 V to 3.6 V, relative to voltages of up to 20 V.
DGND
► IOVDD (bypassing regulator) = 1.72 V to 1.88 V, relative to
DGND
► AVSS = −2.75 V to 0 V, relative to DGND
The AVDD1A and AVDD1B (AVDD1) supplies power the analog
front end, reference input, and common-mode output circuitry. Figure 74. Power Supply Configuration
AVDD1 is referenced to AVSS, and all AVDD1 supplies must be tied
Alternatively, the ADP7112 or ADP7104 can be selected for power-
to the same potential with respect to AVSS. If AVDD1 supplies are
ing the AD7768/AD7768-4. Refer to the AN-1120 Application Note
used in a ±2.5 V split supply configuration, the ADC inputs are truly
for more information regarding low noise LDO performance and
bipolar. When using split supplies, reference the absolute maximum
power supply filtering.
ratings, which apply to the voltage allowed between AVSS and
IOVDD supplies.
1.8 V IOVDD Operation
The AVDD2A and AVDD2B (AVDD2) supplies connect to internal
1.8 V analog LDO regulators. The regulators power the ADC core. The AD7768/AD7768-4 contain an internal 1.8 V LDO on the
AVDD2 is referenced to AVSS, and all AVDD2 supplies must be tied IOVDD supply to regulate the IOVDD down to the operating voltage
to the same potential with respect to AVSS. The voltage on AVDD2 of the digital core. This internal LDO allows the internal logic to
can range from 2 V (minimum) to 5.5 V (maximum), with respect to operate efficiently at 1.8 V and the input/output logic to operate at
AVSS. the level set by IOVDD. The IOVDD supply is rated from 2.25 V to
3.6 V for normal operation, and 1.8 V for LDO bypass setup.
IOVDD powers the internal 1.8 V digital LDO regulator. This regula-
tor powers the digital logic of the ADC. IOVDD also sets the voltage
levels for the SPI interface of the ADC. IOVDD is referenced to
DGND, and the voltage on IOVDD can vary from 2.25 V (minimum)
to 3.6 V (maximum), with respect to DGND. IOVDD can also be
configured to run at 1.8 V. In this case, IOVDD and DREGCAP
must be tied together and must be within the range of 1.72 V
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Data Sheet AD7768/AD7768-4
APPLICATIONS INFORMATION

For control, the device can be configured in one of two modes. The
two modes of configuration are as follows:
► Pin control mode: pin strapped digital logic inputs (which allows a
subset of the configurability options)
► SPI control mode: over a 3-wire or 4-wire SPI interface (complete
configurability)
On power-up, the state of the PIN/SPI pin determines the mode
used. Immediately after power-up, the user must apply a soft or
hard reset to the device when using either control mode.

Interface Data Format

When operating the device, the data format of the serial interface
is determined by the FORMAT0 pin and FORMAT1 pin settings
Figure 75. DREGCAP and IOVDD Connection Diagram for 1.8 V IOVDD on the AD7768, or the FORMAT0 pin on the AD7768-4. Table
Operation
33 shows that each ADC can be assigned a DOUTx pin, or,
Users can bypass the LDO by shorting the DREGCAP pin to alternatively, the data can be arranged to share the DOUTx pins in
IOVDD (see Figure 75), which pulls the internal LDO out of reg- a time division multiplexed manner. For more details, see the Data
ulation and sets the internal core voltage and input/output logic Interface section.
levels to the IOVDD level. When bypassing the internal LDO, the PIN CONTROL
maximum operating voltage of the IOVDD supply is equal to the
maximum operating voltage of the internal digital core, which is Pin control mode eliminates the need for an SPI communication
1.72 V to 1.88 V. interface. When a single known configuration is required by the
user, or when only limited reconfiguration is required, the number
There are a number of performance differences to consider when of signals that require routing to the digital host can be reduced
operating at 1.8 V IOVDD. See the 1.8 V IOVDD Specifications using this mode. Pin control mode is useful in digitally isolated ap-
section for detailed specifications while operating at 1.8 V IOVDD. plications where minimal adjustment of the configuration is needed.
Pin control offers a subset of the core functionality and ensures
Analog Supply Internal Connectivity a known state of operation after power-up, reset, or a fault condi-
The AD7768/AD7768-4 have two analog supply rails, AVDD1 and tion on the power supply. In pin control mode, the analog input
AVDD2, which are both referred to AVSS. These supplies are precharge buffers are enabled by default for best performance. The
completely separate from the digital pins IOVDD, DREGCAP, and reference input precharge buffers are disabled in pin control mode.
DGND. To achieve optimal performance and isolation of the ADCs, On power-up or after any change to the configuration in pin con-
more than one device pin supplies the AVDD1 and AVDD2 to the trol mode, the user must provide a sync signal to the AD7768/
internal ADCs. AD7768-4 by applying the appropriate pulse to the START pin or
► AVSS1A (Pin 3) and AVSS2A (Pin 62) are internally connected. SYNC_IN pin to ensure that the configuration changes are applied
correctly to the ADC and digital filters.
► AVSS (Pin 54) is connected to the substrate, and is connected
internally to AVSS1B (Pin 46) and AVSS2B (Pin 51).
Setting the Filter
► The following supply and reference input pins are separate on
chip: AVDD1A, AVDD1B, AVDD2A, AVDD2B, REF1+, REF1−, The filter function chooses between the two filter settings. In pin
REF2+, and REF2−. control mode, all ADC channels use the same filter type, which is
► On the AD7768-4, the following AVSS pins are separate on chip: selected by the FILTER pin, as shown in Table 16.
Pin 7, Pin 8, Pin 9, Pin 10, Pin 39, Pin 40, Pin 41, and Pin 42. Table 16. FILTER Control Pin
The details of which individual supplies are shorted internally are Logic Level Function
given in this section for information purposes. In general, connect 1 Sinc5 filter selected
the supplies as described in the Power Supplies section. 0 Wideband filter selected
DEVICE CONFIGURATION
Setting the Decimation Rate
The AD7768/AD7768-4 have independent paths for reading data
from the ADC conversions and for controlling the device functionali- Pin control mode allows selection from four possible decimation
ty. rates. The decimation rate is selected via the DEC1 pin and DEC0

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Data Sheet AD7768/AD7768-4
APPLICATIONS INFORMATION

pin. The chosen decimation rate is used on all ADC channels. Table the user to reduce the DCLK frequency for lower, less demanding
17 shows the truth table for the DECx pins. power modes and selecting either the one-shot or standard conver-
Table 17. Decimation Rate Control Pins Truth Table
sion modes.
DEC1 DEC0 Decimation Rate See Table 20 for the complete selection of operating modes that are
0 0 ×32
available via the MODEx pins in pin control mode.
0 1 ×64 The power mode setting automatically scales the bias currents of
1 0 ×128 the ADC and divides the applied MCLK signal to the correct setting
1 1 ×1024
for that mode. Note that this is not the same as using SPI control,
where separate bit fields exist to control the bias currents of the
ADC and MCLK division.
Operating Mode
In pin control mode, the modulator rate is fixed for each power
The MODE3 pin to MODE0 pin determine the configuration of all mode to achieve the best performance. Table 19 shows the modu-
channels when using pin control mode. The variables controlled lator division for each power mode.
by the MODEx pins are shown in Table 18. The user selects how
much current the device consumes, the sampling speed of the Table 19. Modulator Rate, Pin Control Mode
ADC (power mode), how fast the ADC result is received by the Power Mode Modulator Rate (fMOD)
digital host (DCLK_DIV), and how the ADC conversion is initiated Fast MCLK/4
(conversion operation). Figure 76 illustrates the inputs used to
Median MCLK/8
configure the AD7768 in pin control mode, and Figure 77 illustrates
the inputs used to configure the AD7768-4 in pin control mode. Low Power MCLK/32

Table 18. MODEx Pins: Variables for Control

Diagnostics
Control Variable Possible Settings
Pin control mode offers a subset of diagnostics features. Internal
Sampling Speed/Power Consumption Power Mode Fast mode
errors are reported in the status header output with the data
Median mode conversion results for each channel.
Low power mode
Internal cyclical redundancy check (CRC) errors, memory map
Data Clock Output Frequency (DCLK_DIV) DCLK = MCLK/1
flipped bits, and external clocks not detected are reported by Bit 7
DCLK = MCLK/2 of the status header and indicate that a reset is required. The status
DCLK = MCLK/4 header also reports filter not settled, filter type, and filter saturated
DCLK = MCLK/8 signals. Users can determine when to ignore data by monitoring
Conversion Operation Standard conversion these error flags. For more information on the status header, see
One-shot conversion the ADC Conversion Output: Header and Data section.

The MODEx pins map to 16 distinct settings. The settings are se-
lected to optimize the use cases of the AD7768/AD7768-4, allowing

Figure 76. AD7768 Pin Configurable Functions

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APPLICATIONS INFORMATION

Figure 77. AD7768-4 Pin Configurable Functions

Table 20. MODEx Selection Details: Pin Control Mode

Mode Hex. MODE3 MODE2 MODE1 MODE0 Power Mode DCLK Frequency Data Conversion
0x0 0 0 0 0 Low power MCLK/1 Standard
0x1 0 0 0 1 Low power MCLK/2 Standard
0x2 0 0 1 0 Low power MCLK/4 Standard
0x3 0 0 1 1 Low power MCLK/8 Standard
0x4 0 1 0 0 Median MCLK/1 Standard
0x5 0 1 0 1 Median MCLK/2 Standard
0x6 0 1 1 0 Median MCLK/4 Standard
0x7 0 1 1 1 Median MCLK/8 Standard
0x8 1 0 0 0 Fast MCLK/1 Standard
0x9 1 0 0 1 Fast MCLK/2 Standard
0xA 1 0 1 0 Fast MCLK/4 Standard
0xB 1 0 1 1 Fast MCLK/8 Standard
0xC 1 1 0 0 Low power MCLK/1 One-shot
0xD 1 1 0 1 Median MCLK/1 One-shot
0xE 1 1 1 0 Fast MCLK/2 One-shot
0xF 1 1 1 1 Fast MCLK/1 One-shot

Configuration Example Minimizing the DCLK frequency means selecting DCLK = MCLK/8,
which results in a 4 MHz DCLK signal. The period of DCLK in this
In the example shown in Table 23, the lowest current consumption case is 1/4 MHz = 250 ns. The data conversion on each DOUTx
is used, and the AD7768/AD7768-4 are connected to an FPGA. pin is 32 bits long. The conversion data takes 32 × 250 ns = 8
The FORMATx pins are set such that all eight data outputs, DOUT0 µs to be output. All 32 bits must be output within the ODR period
to DOUT7, connect to the FPGA. For the lowest power, the lowest of 1/16 kHz, which is approximately 64 µs. In this case, the 8 µs
DCLK frequency is used. The input bandwidth is set through the required to read out the conversion data is well within the 64 µs
combination of selecting decimation by 64 and selecting the wide- between conversion outputs. Therefore, this combination, which is
band filter. summarized in Table 23, is viable for use.
ODR = fMOD ÷ Decimation Ratio
Channel Standby
where:
fMOD is MCLK/32 for low power mode (see Table 19). Table 21 and Table 23 show how the user can put channels into
MCLK = 32.768 MHz. standby mode. Set either ST0 or ST1 to Logic 1 to place banks
Decimation Ratio = 64. of four channels into standby mode. When in standby mode, the
channels are disabled but still hold their position in the output data
Therefore, for this example, where MCLK = 32.768 MHz, stream. The 8-bit header and 24-bit conversion result are set to all
ODR = (32.768 MHz/32) ÷ 64 = 16 kHz zeros when the ADC channels are set to standby.

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APPLICATIONS INFORMATION

The VCM voltage output is associated with the Channel 0 circuitry. CS clocks out the MSB, the falling edge of SCLK is the drive edge,
If Channel 0 is put into standby mode, the VCM voltage output is and the rising edge of SCLK is the sample edge. This means that
also disabled for maximum power savings. Channel 0 must be ena- data is clocked out on the falling/drive edge and data is clocked in
bled while VCM is being used externally to the AD7768/AD7768-4. on the rising/sample edge.
The crystal excitation circuitry is associated with the Channel 4
(Channel 2 on the AD7768-4) circuitry. If Channel 4 (Channel 2 on
the AD7768-4) is put into standby mode, the crystal circuitry is also
disabled for maximum power savings. Channel 4 must be enabled
while the external crystal is used on the AD7768. Channel 2 must
be enabled while the external crystal is used on the AD7768-4.
Figure 78. SPI Mode 0 SCLK Edges
Table 21. Truth Table for the AD7768 ST0 Pin and ST1 Pin
ST1 ST0 Function Accessing the ADC Register Map
0 0 All channels operational.
To use SPI control mode, set the PIN/SPI pin to logic high. The SPI
0 1 Channel 0 to Channel 3 in standby.
control mode operates as a 16-bit, 4-wire interface, allowing read
Channel 4 to Channel 7 operational.
and write access. Figure 80 shows the interface format between the
1 0 Channel 4 to Channel 7 in standby. AD7768/AD7768-4 and the digital host.
Channel 0 to Channel 3 operational.
1 1 All channels in standby.
The SPI serial control interface of the AD7768 is an independent
path for controlling and monitoring the AD7768. There is no direct
Table 22. Truth Table for the AD7768-4 ST0 Pin link to the data interface. The timing of MCLK and DCLK is not
ST0 Function directly related to the timing of the SPI control interface. However,
0 All channels operational.
the user must ensure that the SPI reads and writes satisfy the
minimum t30 specification (see Table 4 and Table 6) so that the
1 Channel 0 to Channel 3 in standby.
AD7768/AD7768-4 can detect changes to the register map.
SPI CONTROL SPI access is ignored during the period immediately after a reset.
The AD7768/AD7768-4 have a 4-wire SPI interface that is compati- Allow the full ADC start-up time after reset (see Table 1) to elapse
ble with QSPI™, MICROWIRE®, and DSPs. The interface operates before accessing the AD7768/AD7768-4 over the SPI interface.
in SPI Mode 0. In SPI Mode 0, SCLK idles low, the falling edge of
Table 23. MODEx Example Selection
Mode Hex MODE3 MODE2 MODE1 MODE0 Power Mode DCLK Frequency Data Conversion
0x3 0 0 1 1 Low power MCLK/8 Standard

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SPI Interface Details SPI CONTROL FUNCTIONALITY

Each SPI access frame is 16 bits long. The MSB (Bit 15) of the SDI SPI control offers the superset of flexibility and diagnostics to the
command is the R/W bit, 1 = read and 0 = write. Bits[14:8] of the user. The following sections highlight the functionality and diagnos-
SDI command are the address bits. tics offered when SPI control is used.
The SPI control interface uses an off frame protocol. This On power up or after any change to these configuration register set-
means that the main (FPGA/DSP) communicates with the AD7768/ tings, the user must provide a sync signal to the AD7768/AD7768-4
AD7768-4 in two frames. The first frame sends a 16-bit instruction through either the SPI_SYNC command, or by applying the appro-
(R/W, address, and data) and the second frame is the response priate pulse to the START pin or SYNC_IN pin to ensure that the
where the AD7768/AD7768-4 send 16 bits back to the main. configuration changes are applied correctly to the ADC and digital
filters.
During the main write command, the SDO output contains eight
leading zeros, followed by eight bits of data, as shown in Figure 80.
Channel Configuration
Figure 80 illustrates the off frame protocol. Register access re-
sponses are always offset by one CS frame. In Figure 79, the The AD7768 has eight fully differential analog input channels. The
response (read RESP 1) to the first command (CMD 1) is output by AD7768-4 has four fully differential analog input channels. The
the AD7768/AD7768-4 during the following CS frame at the same channel configuration registers allow the channel to be individually
time that the second command (CMD 2) is being sent. configured to adapt to the measurement required on that channel.
Channels can be enabled or disabled using the channel standby
register, Register 0x00. Analog input and reference precharge buf-
fers can be assigned per input terminal. Gain, offset, and phase
calibration can be controlled on a per channel basis using the
calibration registers. See the Per Channel Calibration Gain, Offset,
and Sync Phase section for more information.

Figure 79. Off Frame Protocol

SPI Control Interface Error Handling

The AD7768/AD7768-4 SPI control interface detects whether it has
received an illegal command. An illegal command is a write to a
read only register, a write to a register address that does not exist, Figure 80. Write/Read Command
or a read from a register address that does not exist. If any of
these illegal commands are received by the AD7768/AD7768-4, the Channel Modes
AD7768/AD7768-4 respond with an error output of 0x0E00.
In SPI control mode, the user can set up two channel modes, Chan-
SPI Reset Configuration nel Mode A (Register 0x01), and Channel Mode B (Register 0x02).
Each channel mode register can have a specific filter type and
After a power-on or reset, the AD7768/AD7768-4 default configura- decimation ratio. Using the channel mode select register (Register
tion is set to the following low current consumption settings: 0x03), the user can assign each channel to either Channel Mode
A or Channel Mode B, which maps that mode to the required ADC
► Low power mode with fMOD = MCLK/32.
channels. These modes allow different filter types and decimation
► Interface configuration of DCLK = MCLK/8, header output ena- rates to be selected and mapped to any of the ADC channels.
bled, and CRC disabled.
► Filter configuration of Channel Mode A and Channel Mode B is When different decimation rates are selected on different channels,
set to sinc5 and decimation = ×1024. the AD7768/AD7768-4 output a data ready signal at the fastest
► Channel mode select is set to 0x00, and all channels are as- selected decimation rate. Any channel that runs at a lower output
signed to Channel Mode A. data rate is updated only at that slower rate. In between valid result
data, the data for that channel is set to zero and the repeated
► The analog input precharge buffers are enabled and the refer-
data bit is set in the header status bits to distinguish it from a real
ence precharge buffers are disabled on all channels.
conversion result (see the ADC Conversion Output: Header and
► The offset, gain, and phase calibration are set to the zero Data section).
position.
► Continuous conversion mode is enabled. On the AD7768, consider Channel Mode A as the primary group.
In this respect, it is recommended that there always be at least

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Data Sheet AD7768/AD7768-4
APPLICATIONS INFORMATION

one channel assigned to Channel Mode A. If all eight channels Sleep Mode
of the AD7768 are assigned to Channel Mode B, conversion data
is not output on the data interface for any of the channels. This Sleep mode puts the AD7768/AD7768-4 into their lowest power
consideration does not affect the AD7768-4. mode. In sleep mode, all ADCs are disabled and a large portion of
the digital core is inactive.
On the AD7768-4, it is recommended that Channel Mode A be set
to the sinc5 filter whenever possible. There is a small power saving The AD7768/AD7768-4 SPI remains active and is available to the
in IOVDD current when Channel Mode A is set to the sinc5 filter user when in sleep mode. Write to Register 0x04, Bit 7 to exit sleep
compared to setting Channel Mode A to the wideband filter. mode. For the lowest power consumption, select the sinc5 filter
before entering sleep mode.
For example, to assign two channels of the AD7768-4 to the
wideband filter, and the remaining two channels to the sinc5 filter, it Channel Standby
is recommended to assign the two sinc5 filter channels to Channel
Mode A. Set Channel Mode A to the sinc5 filter, set Channel Mode For efficient power usage, users can place the selected channels
B to the wideband filter, and assign the two wideband filter channels into standby mode, effectively disabling them, when not in use. Set-
to Channel Mode B. Similarly, to assign all four channels of the ting the bits in Register 0x00 disables the corresponding channel
AD7768-4 to wideband filter, assign all four channels to Channel (see Table 38 for the AD7768 or Table 64 for the AD7768-4). For
Mode B. Set Channel Mode B to the wideband filter, and keep maximum power savings, switch disabled channels to the sinc5
Channel Mode A set to the sinc5 filter. Assigning the channels in filter using the channel mode configurations, which disables some
this way ensures that the lowest IOVDD current is achieved. clocks associated with the wideband filters of those channels.
Table 24. Channel Mode A/Channel Mode B, Register 0x01 and Register 0x02 For highest power savings when disabling channels on the
Bits Bit Name Setting Description Reset Access AD7768-4, set Channel Mode A to the sinc5 filter, and assign
the disabled channels to Channel Mode A, while keeping any active
3 FILTER_TYPE_x Filter output 0x1 RW channels in Channel Mode B.
0 Wideband filter
The VCM voltage output is associated with the Channel 0 circuitry.
1 Sinc5 filter
If Channel 0 is put into standby mode, the VCM voltage output is
[2:0] DEC_RATE_x Decimation rate 0x5 RW also disabled for maximum power savings. Channel 0 must be ena-
000 to ×32 to ×1024 bled while VCM is being used externally to the AD7768/AD7768-4.
101
The crystal excitation circuitry is associated with the Channel 4
Table 25. Channel Mode Selection, Register 0x03 (Channel 2 on the AD7768-4) circuitry. If Channel 4 (Channel 2 on
Bits Bit Name Setting Description Reset Access the AD7768-4) is put into standby mode, the crystal circuitry is also
[7:0] CH_x_MODE Channel x 0x0 RW disabled for maximum power savings. Channel 4 must be enabled
while the external crystal is used on the AD7768. Channel 2 must
0 Mode A
be enabled while the external crystal is used on the AD7768-4.
1 Mode B
Clocking Selections
Reset over SPI Control Interface
The internal fMOD that is used by each of the ADCs in the AD7768/
Two successive commands must be written to the AD7768/ AD7768-4 is derived from the externally applied MCLK signal. The
AD7768-4 data control register to initiate a full reset of the device MCLK division bits allow the user to control the ratio between the
over the SPI interface. This action fully resets all registers to the MCLK frequency and the internal modulator clock frequency. This
default conditions. Details of the commands and their sequence are control allows the user to select the division ratio that is best for
shown in Table 44 for the AD7768 or Table 70 for the AD7768-4. their configuration.
After a reset over the SPI control interface, the AD7768/AD7768-4 The appropriate clock configuration depends on the power mode,
respond to the first command sent to them with 0x0E00. This the decimation rate, and the base MCLK frequency available in
response, in addition to the fact that all registers have assumed the system. See the Clocking, Sampling Tree, and Power Scaling
their default values, indicates that the software reset succeeded. section for further information on setting MCLK_DIV correctly.
After a reset, it is recommended to wait for the specified ADC
start-up time after reset time to elapse before issuing an SPI write MCLK Source Selection
command.
The following clocking options are available as the MCLK input
source in SPI control mode:
► LVDS

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Data Sheet AD7768/AD7768-4
APPLICATIONS INFORMATION

► External crystal CRC Protection

► CMOS input MCLK
The AD7768/AD7768-4 can be configured to output a CRC mes-
Setting CLK_SEL to logic low configures the AD7768/AD7768-4 for sage per channel every 4 or 16 samples. This function is available
correct operation using a CMOS clock. Setting CLK_SEL to logic only with SPI control. CRC is enabled in the interface configuration
high enables the use of an external crystal. In SPI control mode, the register, Register 0x07 (see the CRC Check on Data Interface
FILTER pin must also be set to Logic 1 for operation of the external section).
crystal.
ADC Synchronization over SPI
If CLK_SEL is set to logic high and Bit 3 of Register 0x04 is
also set, the application of an LVDS clock signal to the MCLK pin The ADC synchronization over SPI allows the user to request a
is enabled. LVDS clocking is exclusive to SPI control mode and synchronization pulse to the ADCs over the SPI interface. To initiate
requires the register selection for operation (see Table 42 for the the synchronization in this manner, write to Bit 7 in Register 0x06
AD7768 or Table 68 for the AD7768-4). twice.
The DCLK rate is derived from MCLK. DCLK division (the ratio be- First, the user must write a 0, which sets SYNC_OUT low, and then
tween MCLK and DCLK) is controlled in the interface configuration write a 1 to set the SYNC_OUT logic high again.
register, Register 0x07 (see Table 45 for the AD7768 or Table 71 for
The SPI_SYNC command is recognized after the last rising edge of
the AD7768-4).
SCLK in the SPI instruction, where the SPI_SYNC bit is changed
from low to high. The SPI_SYNC command is then output synchro-
Interface Configuration
nously to the AD7768/AD7768-4 MCLK signal on the SYNC_OUT
The data interface is a main output interface, where ADC conver- pin. The user must connect the SYNC_OUT signal to the SYNC_IN
sion results are output by the AD7768/AD7768-4 at a rate based on pin on the PCB.
the mode selected. The interface consists of a data clock (DCLK),
the data ready (DRDY) framing output, and the data output pins
(DOUT0 to DOUT7 for the AD7768, DOUT0 to DOUT3 for the
AD7768-4).
On the AD7768, the interface can be configured to output conver-
sion data on one, two, or eight of the DOUTx pins. The DOUTx
configuration for the AD7768 is selected using the FORMATx pins
(see Table 33).
On the AD7768-4, the interface can be configured to output con-
version data on one or four of the DOUTx pins. The DOUTx
configuration for the AD7768-4 is selected using the FORMAT0 pin Figure 81. Connection Diagram for Synchronization Using SPI_SYNC
(see Table 34).
The DCLK rate is a direct division of the MCLK input and can be The SYNC_OUT pin can also be routed to the SYNC_IN pins of
controlled using Bits[1:0] of Register 0x07. The minimum DCLK rate other AD7768/AD7768-4 devices, allowing simultaneous sampling
can be calculated as to occur across larger channel count systems. Any daisy-chained
system of AD7768/AD7768-4 devices requires that all ADCs be
DCLK (Minimum) = Output Data Rate × Channels per DOUTx × 32 synchronized.
bits
In a daisy-chained system of AD7768/AD7768-4 devices, two suc-
where MCLK ≥ DCLK. cessive synchronization pulses must be applied to guarantee that
all ADCs are synchronized. Two synchronization pulses are also
With eight ADCs enabled, an MCLK rate of 32.768 MHz, an ODR of
required in a system of more than one AD7768/AD7768-4 device
256 kSPS, and two DOUTx channels, DCLK (minimum) is
sharing a single MCLK signal, where the DRDY pin of only one
256 kSPS × 4 Channels per DOUTx × 32 bits = 32.768 MHz device is used to detect new data. It is recommended to wait
at least 16 MCLK pulses between issuing the first and second
where DCLK = MCLK/1. synchronization pulses.
For more information on the status header, CRC, and interface As per any synchronization pulse present on SYNC_IN the pin, the
configuration, see the Data Interface section. digital filters of the AD7768/AD7768-4 are reset by the SPI_SYNC
command. The full settling time of the filters must then elapse
before valid data is output on the data interface.

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APPLICATIONS INFORMATION

Analog Input Precharge Buffers Normal ADC conversion is disrupted when this test is run. A syn-
chronization pulse is required after this test is complete to resume
The AD7768/AD7768-4 contain precharge buffers on each analog normal ADC operation.
input to ease the drive requirements on the external amplifier. Each
analog input precharge buffer can be enabled or disabled using the Revision Identification Number
analog input precharge buffer registers (see Table 52 and Table 53
for the AD7768 or Table 78 and Table 79 for the AD7768-4). When The AD7768/AD7768-4 contain an identification register that can be
writing to these registers, the user must write the inverse of the accessed in SPI control mode, the revision identification register.
required bit settings. For example, to clear Bit 1 of this register, the This register is an excellent way to verify the correct operation of
user must write 0x01 to the register. This clears Bit 1 and sets all the serial control interface. Register information is available in the
other bits. If the user reads the register again after writing 0x01, the Revision Identification Register section.
data read is 0xFE, as required.
Diagnostic Meter Mode
Reference Precharge Buffers
The diagnostic metering mode can be used to verify the functionali-
The AD7768/AD7768-4 contain reference precharge buffers on ty of each ADC by internally passing a positive full-scale, midscale,
each reference input to ease the drive requirements on the external or negative full-scale voltage to the ADC. The user can then read
reference and help to settle any nonlinearity on the reference the resulting ADC conversion result to determine that the ADC is
inputs. Each reference precharge buffer can be enabled or disa- operating correctly. To configure ADC conversion diagnostics, see
bled using the reference precharge buffer registers (see Table 54 the ADC Diagnostic Receive Select Register section and the ADC
and Table 55 for the AD7768 or Table 80 and Table 81 for the Diagnostic Control Register section.
AD7768-4).

Per Channel Calibration Gain, Offset, and Sync

Phase
The user can adjust the gain, offset, and sync phase of the
AD7768/AD7768-4. These options are available only in SPI con-
trol mode. Further register information and calibration instructions
are available in the Offset Registers section, the Gain Registers
section, and the Sync Phase Offset Registers section. See the
Calibration section for information on calibration equations.

GPIOs
The AD7768/AD7768-4 have five general-purpose input/output
(GPIO) pins available when operating in SPI control mode. For
further information on GPIO configuration, see the GPIO Function-
ality section.
SPI CONTROL MODE EXTRA DIAGNOSTIC
FEATURES

RAM Built In Self Test

The RAM built in self test (BIST) is a coefficient check for the
digital filters. The AD7768/AD7768-4 DSP path uses some internal
memories for storing data associated with filtering and calibration.
A user may, if desired, initiate a BIST of these memories. Normal
conversions are not possible while BIST is running. The test is
started by writing to the BIST control register, Register 0x08. The
results and status of the test are available in the status register,
Register 0x09 (see Table 47 for the AD7768 or Table 73 for the
AD7768-4).

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CIRCUIT INFORMATION

CORE SIGNAL CHAIN power dissipation for the AD7768/AD7768-4. Table 11 shows the
recommended fMOD frequencies for each power mode, Table 42
Each ADC channel on the AD7768/AD7768-4 has an identical shows the register information for the AD7768, and Table 68 shows
signal path from the analog input pins to the data interface. Figure the register information for the AD7768-4.
83 shows a top level implementation of the core signal chain. Each
ADC channel has its own Σ-Δ modulator that oversamples the
analog input and passes the digital representation to the digital filter
block. The fMOD ranges are explained in the Clocking, Sampling
Tree, and Power Scaling section. The data is filtered, scaled for
gain and offset (depending on user settings), and then output on
the data interface. Control of the flexible settings for the signal
chain is provided by either using the pin control or the SPI control
set at power-up by the state of the PIN/SPI input pin.
The AD7768/AD7768-4 can use up to a 5 V reference and con-
verts the differential voltage between the analog inputs (AINx+ and
AINx−) into a digital output. The analog inputs can be configured
as either differential or pseudo differential inputs. As a pseudo
differential input, either AINx+ or AINx− can be connected to a
constant input voltage (such as 0 V, GND, AVSS, or some other ref-
erence voltage). The ADC converts the voltage difference between Figure 82. ADC Ideal Transfer Functions (FS is Full Scale)
the analog input pins into a digital code on the output. Using a
Table 26. Output Codes and Ideal Input Voltages
common-mode voltage of AVDD1 ÷ 2 for the analog inputs, AINx+
and AINx−, maximizes the ADC input range. The 24-bit conversion Analog Input (AINx+ − Digital Output Code,
result is in twos complement, MSB first, format. Figure 82 shows Description (AINx−)) VREF = 4.096 V Twos Complement (Hex.)
the ideal transfer functions for the AD7768/AD7768-4. FS − 1 LSB 4.095999512 V 0x7FFFFF
Midscale + 1 LSB 488 nV 0x000001
ADC Power Modes Midscale 0V 0x000000
The AD7768/AD7768-4 have three selectable power modes. In pin Midscale − 1 LSB −488 nV 0xFFFFFF
control mode, the modulator rate and power mode are tied together −FS + 1 LSB −4.095999512 V 0x800001
for best performance. In SPI control mode, the user can select the −FS −4.096 V 0x800000
power mode and modulator MCLK divider settings. The choice of
power modes gives more flexibility to control the bandwidth and

Figure 83. Top Level Core Signal Chain and Control

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Data Sheet AD7768/AD7768-4
CIRCUIT INFORMATION

ANALOG INPUTS
Figure 84 shows the AD7768/AD7768-4 analog front end. The
ESD protection diodes that are designed to protect the ADC from
some short duration overvoltage and ESD events are shown on
the signal path. The analog input is sampled at twice the fMOD,
which is derived from MCLK. By default, the ADC internal sampling
capacitors, CS1 and CS2, are driven by a per channel analog input
precharge buffer to ease the driving requirement of the external
network.

Figure 85. Analog Input Current (IAIN) vs. Input Voltage, Analog Input
Precharge Buffer Off, VCM = 2.5 V, fMOD = 8.192 MHz

Figure 84. Analog Front End

The analog input precharge buffers, if enabled, are enabled for

a set period of time for each fMOD cycle. The period of time is
dependent on the power mode of the AD7761. The precharge
buffer is on for approximately 15 ns in fast mode, 29 ns in median
mode, and 116 ns in low mode. For the initial rough charging of
the switched capacitor network, the bypass switches, BPS 0+ and
BPS 0−, remain open during this first phase. For the remaining
phase, the bypass switches are closed, and the fine accuracy
settling charge is provided by the external source. PHI 0 and PHI
1 represent the modulator clock sampling phases that switch the Figure 86. Analog Input Current (IAIN) vs. Input Voltage, Analog Input
input signals onto the sampling capacitors, CS1 and CS2. Precharge Buffer On, VCM = 2.5 V, fMOD = 8.192 MHz
The analog input precharge buffers reduce the switching kickback
from the sampling stage to the external circuitry. The precharge The analog input precharge buffers can be turned on or off by
buffer reduces the average input current by a factor of eight, means of a register write to Register 0x11 and Register 0x12
and makes the input current more signal independent, to reduce (Precharge Buffer Register 1 and Precharge Buffer Register 2).
the effects of sampling distortion. This reduction in drive require- When writing to these registers, the user must write the inverse
ments allows pairing of the AD7768/AD7768-4 with lower power, of the required bit settings. For example, to clear Bit 1 of this
lower bandwidth front end driver amplifiers such as the ADA4940-1/ register, the user must write 0x01 to the register. This clears Bit
ADA4940-2. 1 and sets all other bits. If the user reads the register again after
writing 0x01, the data read is 0xFE, as required. Each analog input
precharge buffer is selectable per channel. In pin control mode,
the analog input precharge buffers are always enabled for optimum
performance.
When the analog input precharge buffers are disabled, the analog
input current is sourced completely from the analog input source.
The unbuffered analog input current is calculated from two compo-
nents: the differential input voltage on the analog input pair, and
the analog input voltage with respect to AVSS. With the precharge
buffers disabled, for 32.768 MHz MCLK in fast mode with fMOD =
MCLK/4, the differential input current is approximately 48 µA/V and
the current with respect to ground is approximately 17 µA/V.

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Data Sheet AD7768/AD7768-4
CIRCUIT INFORMATION

For example, if the precharge buffers are off, with AIN1+ = 5 V, and used for the AD7768/AD7768-4 for most amplifier pairings. The
AIN1− = 0 V, estimate the current in each input pin as follows: RC network performs a variety of tasks. C1 and C2 are charge
reservoirs to the ADC, providing the ADC with fast charge current
AIN1+ = 5 V × 48 µA/V + 5 V × 17 µA/V = 325 µA to the sampling capacitors. Capacitor C3 removes common-mode
AIN1− = −5 V × 48 µA/V + 0 V × 17 µA/V = −240 µA errors between the AINx+ and AINx− inputs. These capacitors, in
combination with input resistance (RIN), form a low-pass filter to
When the precharge buffers are enabled, the absolute voltage filter out glitches related to the input switching. The input resistance
with respect to AVSS determines the majority of the current. The also stabilizes the amplifier when driving large capacitor loads and
maximum input current of approximately −25 µA is measured when prevents the amplifier from oscillating.
the analog input is close to either the AVDD1 or AVSS rails.
The optimum driver amplifiers for each of these power, perform-
With either precharge buffers enabled or disabled, the analog input ance, and supply requirements are as follows:
current scales linearly with the modulator clock rate. The analog
input current vs. input voltage is shown in Figure 85. ► The ADA4805-2 is suited for low power, particularly in low power
mode.
Full settling of the analog inputs to the ADC requires the use
► The ADA4940-1 is suited for single-supply operation and is also
of an external amplifier. Pair amplifiers such as the ADA4805-2
the recommended fully differential amplifier to drive the AD7768/
for low power mode, the ADA4807-2 or ADA4940-1/ADA4940-2 for
AD7768-4.
median mode, and the ADA4807-2 or ADA4896-2 for fast mode
► For optimum performance in fast power mode, the ADA4896-2
with the AD7768/AD7768-4 (see Figure 87 for details). Running the
AD7768/AD7768-4 in median and low power modes or reducing performs best, although the device does not consume the same
the MCLK rate reduces the load and speed requirements of the power as the ADA4899-1. The ADA4896-2 is also suitable for
amplifier. Therefore, lower power amplifiers can be paired with the a general-purpose DAQ module, which can be configured for all
analog inputs to achieve the optimum signal chain efficiency. three power modes.

There is a resistor/capacitor (RC) network between the amplifier For more details, refer to the AN-1384 Application Note.
output and the ADC input. Figure 87 shows a typical RC network

Figure 87. Typical Input Structure for an RC Network

Table 27. Amplifier Pairing Options

Power Mode Amplifier Amplifier Power (mW/channel)1 Analog Input Precharge Buffer Total Power (Amplifier + AD7768) (mW/channel)1
Fast ADA4896-2 40.6 On 87.9
Fast ADA4940-2 13.4 On 64.9
Median ADA4805-2 6.9 On 34.4
Low Power ADA4805-2 6.5 On 15.9

1 Typical power at 25°C.

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Data Sheet AD7768/AD7768-4
CIRCUIT INFORMATION

VCM
The AD7768/AD7768-4 provide a buffered common-mode voltage
output on Pin 59. This output can bias up analog input signals. By
incorporating the VCM buffer into the ADC, the AD7768/AD7768-4
reduce component count and board space. In pin control mode, the Figure 88. Typical Reference Input Configuration Diagram
VCM potential is fixed to (AVDD1 − AVSS)/2, and is enabled by
default. CLOCK SELECTION
In SPI control mode, configure the VCM potential using the general The AD7768/AD7768-4 have an internal oscillator that is used for
configuration register (Register 0x05). The output can be enabled initial power-up of the device. After the AD7768/AD7768-4 have
or disabled, and set to (AVDD1 − AVSS)/2, 1.65 V, 2.14 V, or 2.5 V, completed their start-up routine, the devices normally transfer con-
with respect to AVSS. trol of the internal clocking to the externally applied MCLK. The
The VCM voltage output is associated with the Channel 0 circuitry. AD7768/AD7768-4 count the falling edges of the external MCLK
If Channel 0 is put into standby mode, the VCM voltage output is over a given number of internal clock cycles to determine if the
also disabled for maximum power savings. Channel 0 must be ena- clock is valid and at least a frequency of 1.15 MHz. If there is a
bled while VCM is being used externally to the AD7768/AD7768-4. fault with the external MCLK, the transfer of control does not occur,
the AD7768/AD7768-4 output an error in the status header, and the
REFERENCE INPUT clock error bit is set in the device status register. No conversion
The AD7768/AD7768-4 have two differential reference input pairs. data is output and a reset is required to exit this error state.
On the AD7768 REF1+ and REF1− are the reference inputs for Three clock source input options are available to the AD7768/
Channel 0 to Channel 3, and REF2+ and REF2− are for Channel AD7768-4: external CMOS, crystal oscillator, or LVDS. The clock
4 to Channel 7. On the AD7768-4 REF1+ and REF1− are the is selected on power-up and is determined by the state of the
reference inputs for Channel 0 and Channel 1, and REF2+ and CLK_SEL pin.
REF2− are for Channel 2 and Channel 3. The absolute input
reference voltage range is 1 V to AVDD1 − AVSS. If CLK_SEL = 0, the CMOS clock option is selected and the clock
is applied to Pin 32 (Pin 31 is tied to DGND). Follow the conditions
Like the analog inputs, the reference inputs have a precharge below when using CMOS clock:
buffer option. Each ADC has an individual buffer for each REFx+
and REFx−. The precharge buffers help reduce the burden on the ► CLK_SEL (Pin 58) must be set to 0.
external reference circuitry. ► Connect XTAL1 (Pin 31) to DGND.
► The CMOS clock is applied to Pin 32.
In pin control mode, the reference precharge buffers are off by
default. In SPI control mode, the user can enable or disable the ref- ► The CMOS logic level in this case is between IOVDD and
erence precharge buffers. In the case of unipolar analog supplies, DGND.
in SPI control mode, the user can achieve the best performance If CLK_SEL = 1, the crystal or LVDS option is selected and the
and power efficiency by enabling only the REFx+ buffers. The crystal or LVDS is applied to Pin 31 and Pin 32. The LVDS option
reference input current scales linearly with the modulator clock rate. is available only in SPI control mode. Channel 4 on the AD7768
For 32 MHz MCLK and MCLK/4 fast mode, the differential input must be enabled in the channel standby register to use the crystal
current is ~72 µA/V per channel unbuffered, and ~16 µA/V per because this is linked to the crystal excitation circuitry. On the
channel with the precharge buffers enabled. AD7768-4, Channel 2 must be enabled in the channel standby
register.
With the precharge buffers off, REFx+ = 5 V, and REFx− = 0 V,
To use an external crystal, it is necessary to adhere to the following
REFx± = 5 V × 72 µA/V = 360 µA steps:
With the precharge buffers on, REFx+ = 5 V, and REFx− = 0 V, 1. Channel 4 of the ADC must be enabled. This is because Chan-
REFx± = 5 V × 16 µA/V = 80 µA nel 4 is linked to the crystal excitation circuitry. Powering down
this channel also powers down the crystal excitation circuitry.
For the best performance and headroom, it is recommended to use 2. The CLK_SEL pin must be set to Logic 1.
a 4.096 V reference such as the ADR444 or the ADR4540. 3. The crystal is applied between Pin 31 and Pin 32. Capacitance
For the best performance at high sampling rates, it is recommended of approximately 20 pF is required on each of these pins. This
to use an external reference drive amplifier such as the ADA4841-1 may vary depending on the crystal that is selected.
or the AD8031. See Figure 88 for the configuration diagram of the 4. If the AD7768/AD7768-4 is in SPI control mode then the FIL-
reference connection. TER/GPIO4 pin (Pin 11) must be set to Logic 1.

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Data Sheet AD7768/AD7768-4
CIRCUIT INFORMATION

To enable the LVDS clock, there are two options. Set GPIO4
to an output, then writing to the LVDS bit field in the POWER_
CLOCK register enables the LVDS clock. Or, set GPIO4 to an
input. Then GPIO4 must be tied to Logic 0. An SPI write to Bit 3
of Register 0x04 enables the LVDS clock option and disables the
crystal excitation circuitry.
The following steps must be carried out to enable LVDS clocking to
be used:
1. Set the CLK_SEL pin to Logic 1.
2. Set the FILTER/GPIO4 pin (Pin 11) to Logic 0. This disables the
crystal excitation circuitry.
3. Power up the AD7768 with no external clock applied. Initially, it
will run off the internal clock for SPI writes until Step 4 and Step
5 have been carried out. Figure 89. Sinc5 Filter Frequency Response (Decimation = ×32)
4. Enable this option by writing to the LVDS_Enable bit (Bit 3) in
the Power_Mode register (Register 0x04). The settling times for the AD7768/AD7768-4 when using the sinc5
5. Apply the LVDS signals on Pin 31 and Pin 32. filter are shown in Figure 89.

DIGITAL FILTERING Wideband Low Ripple Filter

The AD7768/AD7768-4 offer two types of digital filters. In SPI The wideband filter has a low ripple pass band, within ±0.005 dB
control mode, these filters can be chosen on a per channel basis. of ripple, of 0.4 × ODR. The wideband filter has full attenuation
In pin control mode, only one filter can be selected for all channels. at 0.499 × ODR (Nyquist), maximizing antialias protection. The
The digital filters available on the AD7768/AD7768-4 are as follows: wideband filter has a pass-band ripple of ±0.005 dB and a stop
► Sinc5 low latency filter, −3 dB at 0.204 × ODR band attenuation of 105 dB from Nyquist out to fCHOP. For more
information on antialiasing and fCHOP aliasing, see the Antialiasing
► Wideband low ripple filter, −3 dB at 0.433 × ODR
section.
Both filters can be operated in one of six different decimation rates, The wideband filter is a very high order digital filter with a group
allowing the user to choose the optimal input bandwidth and speed delay of approximately 34/ODR. After a synchronization pulse,
of the conversion versus the desired power mode or resolution. there is an additional delay from the SYNC_IN rising edge to fully
settled data. The settling times for the AD7768/AD7768-4 when
Sinc5 Filter using the wideband filter are shown in Figure 90. See Table 12 for
Most precision Σ-Δ ADCs use a sinc filter. The sinc5 filter offered the noise performance of the wideband filter across power modes
in the AD7768/AD7768-4 enables a low latency signal path that is and decimation rates.
useful for dc inputs, for control loops, or where other specific post-
processing is required. The sinc5 filter path offers the lowest noise
and power consumption. The sinc5 filter has a −3 dB bandwidth
of 0.204 × ODR. Table 13 contains the noise performance for the
sinc5 filter across power modes and decimation ratios.

Figure 90. Wideband Filter Frequency Response

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Data Sheet AD7768/AD7768-4
CIRCUIT INFORMATION

Filter Settling Time

The AD7768/AD7768-4 digital filters are resynchronized on the
rising edge of the SYNC_IN signal. Provide this resynchronization
after power-up in pin control mode or SPI control mode, and after
any reconfiguration of the device in SPI control mode, prior to
capturing ADC samples. After the SYNC_IN rising edge is provided,
there is a deterministic delay until the first new conversion result is
available, and until the first settled data is available. Table 28 and
Table 29 provide these delays, measured in MCLK cycles, for the
wideband and sinc5 filters, respectively, for each possible setting
of MCLK_DIV. Each table provides the delays for configurations
where all channels are using the exact same configuration (Group
B unused), and for configurations where one or more channels
have a different decimation rate applied (Group B is used).
Figure 91. Wideband Filter Pass-Band Ripple
For example, when the channels are configured with the wideband
filter and MCLK_DIV = MCLK/4, with some channels assigned to
Group A with decimate by 32 and other channels to Group B with
decimate by 64, then the delay until the first DRDY signal after the
SYNC_IN signal is 758 MCLK periods. All active channels output
the first data after 758 MCLK periods. However, due to differing
decimation rates across channels, in this case, the first settled data
is available for the Group A channels 8822 MCLK periods after the
SYNC_IN signal, and after 17,014 MCLK periods for the Group B
channels.

Figure 92. Wideband Filter Step Response

Table 28. Wideband Filter SYNC_IN to Settled Data (DCLK = MCLK)

Delay from First MCLK Rise Delay from First MCLK Rise After SYNC_IN Rise
After SYNC_IN Rise to First to Earliest Settled Data DRDY Rise

MCLK_DIV Filter Type Decimation Factor DRDY Rise MCLK Periods

Setting Group A Group B Group A Group B MCLK Periods Group A Group B
MCLK/4 Wideband Wideband 32 Unused 336 8400 Not applicable
Wideband Wideband 64 Unused 620 16,748 Not applicable
Wideband Wideband 128 Unused 1187 33,443 Not applicable
Wideband Wideband 256 Unused 2325 66,837 Not applicable
Wideband Wideband 512 Unused 4601 133,625 Not applicable
Wideband Wideband 1024 Unused 9153 267,201 Not applicable
Wideband Wideband 32 32 758 8822 8822
Wideband Wideband 32 64 758 8822 17,014
Wideband Wideband 32 128 758 8822 33,526
Wideband Wideband 32 256 758 8822 66,934
Wideband Wideband 32 512 758 8822 133,622
Wideband Wideband 32 1024 758 8822 267,253
Wideband Wideband 64 32 759 17,015 8823
Wideband Wideband 128 32 760 33,528 8824

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Data Sheet AD7768/AD7768-4
CIRCUIT INFORMATION

Table 28. Wideband Filter SYNC_IN to Settled Data (DCLK = MCLK) (Continued)

Delay from First MCLK Rise Delay from First MCLK Rise After SYNC_IN Rise
After SYNC_IN Rise to First to Earliest Settled Data DRDY Rise

MCLK_DIV Filter Type Decimation Factor DRDY Rise MCLK Periods

Setting Group A Group B Group A Group B MCLK Periods Group A Group B
Wideband Wideband 256 32 762 66,938 8826
Wideband Wideband 512 32 782 133,646 8846
Wideband Wideband 1024 32 806 267,302 8870
MCLK/8 Wideband Wideband 32 Unused 656 16,784 Not applicable
Wideband Wideband 64 Unused 1225 33,481 Not applicable
Wideband Wideband 128 Unused 2359 66,871 Not applicable
Wideband Wideband 256 Unused 4635 133,659 Not applicable
Wideband Wideband 512 Unused 9187 267,235 Not applicable
Wideband Wideband 1024 Unused 18,291 534,387 Not applicable
Wideband Wideband 32 32 820 16,948 16,948
Wideband Wideband 32 64 820 16,948 33,588
Wideband Wideband 32 128 820 16,948 66,868
Wideband Wideband 32 256 820 16,948 133,684
Wideband Wideband 32 512 820 16,948 267,316
Wideband Wideband 32 1024 820 16,948 534,580
Wideband Wideband 64 32 822 33,590 16,950
Wideband Wideband 128 32 824 66,872 16,952
Wideband Wideband 256 32 844 133,708 16,972
Wideband Wideband 512 32 836 267,332 16,964
Wideband Wideband 1024 32 852 534,612 16,980
MCLK/32 Wideband Wideband 32 Unused 2587 67,099 Not applicable
Wideband Wideband 64 Unused 4855 133,879 Not applicable
Wideband Wideband 128 Unused 9391 267,439 Not applicable
Wideband Wideband 256 Unused 18,495 534,591 Not applicable
Wideband Wideband 512 Unused 36,703 1,068,895 Not applicable
Wideband Wideband 1024 Unused 73,119 2,137,503 Not applicable
Wideband Wideband 32 32 2587 67,099 67,099
Wideband Wideband 32 64 2587 67,099 134,683
Wideband Wideband 32 128 2587 67,099 267,803
Wideband Wideband 32 256 2587 67,099 535,067
Wideband Wideband 32 512 2587 67,099 1,069,595
Wideband Wideband 32 1024 2587 67,099 2,137,627
Wideband Wideband 64 32 2587 134,683 67,099
Wideband Wideband 128 32 2587 267,803 67,099
Wideband Wideband 256 32 2587 535,067 67,099
Wideband Wideband 512 32 2587 1,069,595 67,099
Wideband Wideband 1024 32 2587 2,137,627 67,099

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Data Sheet AD7768/AD7768-4
CIRCUIT INFORMATION

Table 29. Sinc5 Filter SYNC_IN to Settled Data (DCLK = MCLK)

Delay from First MCLK Rise Delay from First MCLK Rise After SYNC_IN Rise to
After SYNC_IN Rise to First Earliest Settled Data DRDY Rise

MCLK_DIV Filter Type Decimation Factor DRDY Rise Group A Group B

Setting Group A Group B Group A Group B MCLK Periods MCLK Periods MCLK Periods
MCLK/4 Sinc5 Sinc5 32 Unused 199 839 Not applicable
Sinc5 Sinc5 64 Unused 327 1607 Not applicable
Sinc5 Sinc5 128 Unused 583 3143 Not applicable
Sinc5 Sinc5 256 Unused 1095 6215 Not applicable
Sinc5 Sinc5 512 Unused 2119 12359 Not applicable
Sinc5 Sinc5 1024 Unused 4167 24,647 Not applicable
Sinc5 Sinc5 32 32 199 839 839
Sinc5 Sinc5 32 64 199 839 1607
Sinc5 Sinc5 32 128 199 839 3143
Sinc5 Sinc5 32 256 199 839 6215
Sinc5 Sinc5 32 512 199 839 12,359
Sinc5 Sinc5 32 1024 199 839 24,647
Sinc5 Sinc5 64 32 199 1607 839
Sinc5 Sinc5 1024 32 199 24,647 839
MCLK/8 Sinc5 Sinc5 32 Unused 383 1663 Not applicable
Sinc5 Sinc5 64 Unused 639 3199 Not applicable
Sinc5 Sinc5 128 Unused 1151 6271 Not applicable
Sinc5 Sinc5 256 Unused 2175 12,415 Not applicable
Sinc5 Sinc5 512 Unused 4223 24,703 Not applicable
Sinc5 Sinc5 1024 Unused 8319 49,279 Not applicable
Sinc5 Sinc5 32 32 383 1663 1663
Sinc5 Sinc5 32 64 383 1663 3199
Sinc5 Sinc5 32 128 383 1663 6271
Sinc5 Sinc5 32 256 398 1663 12,415
Sinc5 Sinc5 32 512 398 1663 24,703
Sinc5 Sinc5 32 1024 398 1663 49,279
Sinc5 Sinc5 64 32 383 3199 1663
Sinc5 Sinc5 1024 32 398 49,279 1663
MCLK/32 Sinc5 Sinc5 32 Unused 1487 6607 Not applicable
Sinc5 Sinc5 64 Unused 2511 12,751 Not applicable
Sinc5 Sinc5 128 Unused 4559 25,039 Not applicable
Sinc5 Sinc5 256 Unused 8655 49,615 Not applicable
Sinc5 Sinc5 512 Unused 16,847 98,767 Not applicable
Sinc5 Sinc5 1024 Unused 33,231 197,071 Not applicable
Sinc5 Sinc5 32 32 1487 6607 6607
Sinc5 Sinc5 32 64 1487 6607 12,751
Sinc5 Sinc5 32 128 1487 6607 25,039
Sinc5 Sinc5 32 256 1487 6607 49,615
Sinc5 Sinc5 32 512 1487 6607 98,767
Sinc5 Sinc5 32 1024 1487 6607 197,071
Sinc5 Sinc5 64 32 1487 12,751 6607

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Data Sheet AD7768/AD7768-4
CIRCUIT INFORMATION

Table 29. Sinc5 Filter SYNC_IN to Settled Data (DCLK = MCLK) (Continued)
Delay from First MCLK Rise Delay from First MCLK Rise After SYNC_IN Rise to
After SYNC_IN Rise to First Earliest Settled Data DRDY Rise

MCLK_DIV Filter Type Decimation Factor DRDY Rise Group A Group B

Setting Group A Group B Group A Group B MCLK Periods MCLK Periods MCLK Periods
Sinc5 Sinc5 1024 32 1487 197,071 6607

DECIMATION RATE CONTROL Modulator Sampling Frequency

The AD7768/AD7768-4 have programmable decimation rates for The AD7768/AD7768-4 modulator signal transfer function includes
the digital filters. The decimation rates allow the user to reduce a notch, at odd multiples of fMOD, to reject tones or harmonics
the measurement bandwidth, reducing the speed but increasing related to the modulator clock. The modulator itself attenuates
the resolution. When using the SPI control, control the decimation signals at frequencies of fMOD, 3 × fMOD, 5 × fMOD, and so on. For an
rate on the AD7768/AD7768-4 through the channel mode registers. MCLK frequency of 32.768 MHz, the attenuation is approximately
These registers set two separate channel modes with a given deci- 35 dB in fast mode, 41 dB in median mode, and 53 dB in low
mation rate and filter type. Each ADC is mapped to one of these power mode. Attenuation is increased by 6 dB across each power
modes via the channel mode select register. Table 30 details both mode, with every halving of the MCLK frequency, for example,
the decimation rates available, and the filter types for selection, when reducing the clock from 32.768 MHz to 16.384 MHz.
within Mode A and Mode B.
The modulator has no rejection to signals that are at frequencies
In pin control mode, the decimation ratio is controlled by the DEC0 in zones around 2 × fMOD and all even multiples of fMOD. Signals
pin and DEC1 pin. See Table 17 for decimation configuration in pin at these frequencies are aliased by the AD7768/AD7768-4. For the
control mode. AD7768/AD7768-4, the first of these zones that requires protection
Table 30. Channel x Mode Registers, Register 0x01 and Register 0x02
is at 2 × fMOD. Because typical switch capacitor, discrete time Σ-Δ
modulators, provide no protection to aliasing at fMOD, the AD7768/
Bits Name Logic Value Decimation Rate AD7768-4 provide a distinct advantage in this regard.
3 FILTER_TYPE_x 0 Wideband filter
Figure 93 shows the frequency response of the modulator and
1 Sinc5 filter
wideband digital filter to out of band tones at the analog input.
[2:0] DEC_RATE_x 000 32 Figure 93 shows the magnitude of an alias that is seen in band
001 64 vs. the frequency of the signal sampled at the analog input. The
010 128 relationship between the input signal and the modulator frequency
011 256 is expressed in a normalized manner as a ratio of the input sig-
nal frequency (fIN) to the modulator frequency (fMOD). This data
100 512
demonstrates the ADC frequency response relative to out of band
101 1024 tones when using the wideband filter. The input frequency (fIN)
110 1024 is swept from dc to 20 MHz. In fast mode, using an 8.192 MHz
111 1024 fMOD frequency, the x-axis spans ratios of fIN/fMOD from 0 to 2.44
(equivalent to fIN of 0 Hz to 20 MHz). A similar characteristic occurs
ANTIALIASING in median mode and low power mode.
Because the AD7768/AD7768-4 are switched capacitor, discrete The notch appears in Figure 93 with the fIN at fMOD (designated
time ADCs, the user may wish to employ external analog antialias- at fIN/fMOD = 1.00 on the x-axis). An input at this frequency is
ing filters to protect against fold back of out of band tones. attenuated by 35 dB, which adds to the attenuation of any external
Within this section, an out of band tone refers to an input frequency antialiasing filter, thus reducing the frequency roll-off requirement of
greater than the pass band frequency specification of the digital the external filter. If the plot is swept further in frequency, the user
filter that is applied at the analog input. sees the notch recurring at fIN/fMOD = 3.00.
When designing an antialiasing filter for the AD7768/AD7768-4, The point where fIN = 2 × fMOD (designated on the x-axis in Figure
three main aliasing regions must be taken into account. After the 93 at 2.00) offers 0 dB attenuation, indicating that all signals
alias requirements of each zone are understood, the user can falling at this frequency alias directly back into the ADC conversion
design an antialiasing filter to meet the needs of the specific results, in accordance with the sampling theory.
application. The three zones for consideration are related to the The AD7768/AD7768-4 wideband digital filter also offers an added
modulator sampling frequency, the modulator chopping frequency, protection against aliasing. Because the wideband filter has full
and the modulator saturation point. attenuation at the Nyquist frequency (fODR/2, where fODR = fMOD/

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Data Sheet AD7768/AD7768-4
CIRCUIT INFORMATION

decimation rate), input frequencies, and in particular harmonics of chop aliasing, fMOD/16 for modulator saturation, and 2 × fMOD for the
input frequencies, that may fall close to fODR/2, do not fold back into first zone with 0 dB attenuation. It assumes the corner frequency of
the pass band of the AD7768/AD7768-4. the antialiasing filter is at fMOD/64, which is just above the maximum
input bandwidth that the AD7768/AD7768-4 digital filter can pass
when using a decimate by 32 filter setting.
Table 31. External Antialiasing Filter Attenuation
RC Filter fMOD/32 (dB) fMOD/16 (dB) fMOD/8 (dB) 2 × fMOD (dB)
First Order −6 −12 −18 −42
Second Order −12 −24 −36 −84
Third Order −18 −36 −54 −126

Modulator Saturation Point

A Σ-Δ modulator can be considered a standard control loop, em-
ploying negative feedback. The control loop works to ensure that
the average processed error signal is very small over time. The
control loop uses an integrator to remember preceding errors and
Figure 93. AD7768/AD7768-4 Rejection of Out of Band Input Tones, force the mean error to be zero. As the input signal rate of change
Wideband Filter, Decimation = ×32, fMOD = 8.192 MHz, Analog Input Sweep increases with respect to the fMOD, a larger voltage feedback
from DC to 20 MHz error is processed. Above a certain frequency, the error begins to
saturate the modulator.
Modulator Chopping Frequency
For the AD7768/AD7768-4, the modulator may saturate for full-
Figure 93 plots two scenarios that relate to the chopping frequency scale input frequencies greater than fMOD/16 (see Figure 94),
of the AD7768/AD7768-4 modulators. depending on the rate of change of input signal, input signal
The AD7768/AD7768-4 use a chopping technique in the modulator amplitude, and reference input level. A half power input tone at
similar to that of a chopped amplifier to remove offset, offset fMOD/8 may also cause the modulator to saturate. In applications
drift, and 1/f noise. The AD7768/AD7768-4 default chopping rate where there may be high amplitude and frequency out of band
is fMOD/32. In pin control mode, the chop frequency is hardwired tones, a first-order antialiasing filter is required with a −3 dB corner
to fMOD/32. In SPI control mode, the user can select the chop frequency set at fMOD/16 to protect against modulator saturation.
frequency to be either fMOD/32 or fMOD/8. For example, if operating the AD7768/AD7768-4 at full speed and
using a decimation rate of ×32 to achieve an output data rate of 256
As shown in Figure 93, the stop band rejection of the digital filter is kSPS, the modulator rate is equal to 8.192 MHz. In this instance,
reduced at frequencies that relate to even multiples of the fCHOP. All to protect against saturation, set the antialiasing filter −3 dB corner
other out of band frequencies (excluding those already discussed frequency to 512 kHz.
relating to the fMOD) are rejected by the stop band attenuation of
the digital filter. An out of band tone with a frequency in the range
of (2 × fCHOP ) ± f3dB, where f3dB is the filter bandwidth employed,
is attenuated to the envelope determined by the chop frequency
setting (see Figure 93), and aliased into the pass band. Out of band
tones near additional even multiples of fCHOP (that is, N × fCHOP,
where N is an even integer), are attenuated and aliased in the
same way.
Chopping at fMOD/32 offers the best performance for noise, offset,
and offset drift for the AD7768/AD7768-4.
For ac performance, it may be useful to select chopping at fMOD/8
because this moves the first chopping tone to a higher frequency.
However, chopping at fMOD/8 may lead to slightly degraded noise
(approximately 1 dB loss in dynamic range) and offset performance
compared to the default chop rate of fMOD/32. Figure 94. Maximum Input Signal vs. Frequency

Table 31 shows the aliasing achieved by different order antialiasing

filter options at the critical frequencies of fMOD/32 and fMOD/8 for

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Data Sheet AD7768/AD7768-4
CIRCUIT INFORMATION

CALIBRATION a maximum of one conversion cycle, and the resolution of the

correction depends on the decimation rate in use.
In SPI control mode, the AD7768/AD7768-4 offer users the ability to
adjust offset, gain, and phase delay on a per channel basis. Table 32 displays the resolution and register bits used for phase
offset for each decimation ratio.
Offset Adjustment Table 32. Phase Delay Resolution
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_ OFF- Decimation Ratio Resolution Steps Phase Register Bits
SET_LSB registers are 24-bit, signed twos complement registers ×32 1/fMOD 32 [7:3]
for channel offset adjustment. If the channel gain setting is at ×64 1/fMOD 64 [7:2]
its ideal nominal value of 0x555555, an LSB of offset register
×128 1/fMOD 128 [7:1]
adjustment changes the digital output by −4/3 LSBs. For example,
changing the offset register from 0 to 100 changes the digital ×256 1/fMOD 256 [7:0]
output by −133 LSBs. Because offset calibration occurs before gain ×512 2/fMOD 256 [7:0]
calibration, the ratio of 4/3 changes linearly with gain adjustment ×1024 4/fMOD 256 [7:0]
via the Channel x gain registers (see Table 56 and Table 57 for
the AD7768, or Table 82 and Table 83 for the AD7768-4). After a Adjusting the sync phase of channels can affect the time to the first
reset or power cycle, the offset register values revert to the default DRDY pulse after the sync pulse, as well as the time to Bit 6 of the
factory setting. header status (filter not settled data bit) being cleared, that is, the
time to settled data.
Gain Adjustment If all channels are using the Sinc5 filter, the time to the first
Each ADC channel has an associated gain coefficient. The coef- DRDY pulse is not affected by the adjustment of the sync phase
ficient is stored in three single-byte registers split up as MSB, offset, assuming that at least one channel has zero sync phase
MID, and LSB. Each of the gain registers are factory programmed. offset adjustment. If all channels have a nonzero sync phase offset
Nominally, this gain is around the value 0x555555 (for an ADC setting, the time to the first DRDY pulse is delayed according to
channel). The user may overwrite the gain register setting. Howev- the channel that has the least offset applied. Channels with a
er, after a reset or power cycle, the gain register values revert to the sync offset adjustment setting that delays the internal sync signal,
hard-coded programmed factory setting. relative to other channels, may not output settled data until after
the next DRDY pulse. In other words, there may be a delay of one
Calculate the approximate result that is output using the following ODR period between the settled data being output by the AD7768/
formula: AD7768-4 for the channels with added phase delay.
3 × VIN 4, 194, 300 If all channels are using the wideband filter, the time to the first
Data = 21
VREF × 2 − Offset × Gain
4 × (1)
242 DRDY pulse and the time to settled data is delayed according to
where: the channel with the maximum phase delay setting. In this case,
Offset is the offset register setting. the interface waits for the latest channel and outputs data for all
Gain is the gain register setting. channels when that channel is ready.

For example, if Offset is 0x0000FF, Gain is 0x555575, VIN =

1.024 V, and VREF = 4.096 V, then Data = 2,096,822, which
corresponds to a VOUT of 1.024 V.
The LSB of the gain register is about 0.71525659 ppm.

Sync Phase Offset Adjustment

The AD7768/AD7768-4 have one synchronization signal for all
channels. The sync phase offset register allows the user to vary the
phase delay on each of the channels relative to the synchronization
edge received on the SYNC_IN pin.
By default, all ADC channels react simultaneously to the SYNC_IN
pulse. The sync phase registers can be programmed to equalize
known external phase differences on ADC input channels, relative
to one another. The range of phase compensation is limited to

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Data Sheet AD7768/AD7768-4
DATA INTERFACE

SETTING THE FORMAT OF DATA OUTPUT However, there is a trade-off against ADC offset performance with
higher DCLK frequencies. For the best offset and offset drift per-
The data interface format is determined by setting the FORMATx formance, use the lowest DCLK frequency possible. The user can
pins. The logic state of the FORMATx pins are read on power-up choose to reduce the DCLK frequency by an appropriate selection
and determine how many data lines (DOUTx) the ADC conversions of MCLK frequency, DCLK divider, and/or the number of DOUTx
are output on. lines used. Table 1 and Table 2 give the offset and offset drift
Because the FORMATx pins are read on power-up of the AD7768 specifications for ranges of DCLK frequency, and Figure 49 shows
and the device remains in this output configuration, this function the typical offset drift over a range of DCLK frequencies.
must always be hardwired and cannot be altered dynamically. Table 33. FORMATx Truth Table for the AD7768
Table 33, Figure 95, Figure 96, and Figure 98 show the formatting FORMAT1 FORMAT0 Description
configuration for the digital output pins on the AD7768.
0 0 Each ADC channel outputs on its own dedicat-
Calculate the minimum required DCLK rate for a given data inter- ed pin. DOUT0 to DOUT7 are in use.
face configuration as follows: 0 1 The ADCs share the DOUT0 and DOUT1 pins:
DCLK (Minimum) = Output Data Rate × Channels per DOUTx × 32 Channel 0 to Channel 3 output on DOUT0.
Channel 4 to Channel 7 output on DOUT1. The
where MCLK ≥ DCLK. ADC channels share data pins in time division
For example, if MCLK = 32.768 MHz, with two DOUTx lines, multiplexed (TDM) output. DOUT0 and DOUT1
are in use.
DCLK (Minimum) = 256 kSPS × 4 channels per DOUTx × 32 = 1 X All channels output on the DOUT0 pin, in TDM
32.768 Mbps output. Only DOUT0 is in use.
Therefore, DCLK = MCLK/1. Table 34. FORMAT0 Truth Table for the AD7768-4
Alternatively, if MCLK = 32.768 MHz, with eight DOUTx lines, FORMAT0 Description

DCLK (Minimum) = 256 kSPS × 1 channel per DOUTx × 32 = 8.192 0 Each ADC channel outputs on its own dedicated pin.
Mbps DOUT0 to DOUT3 are in use.
1 All channels output on the DOUT0 pin, in TDM output. Only
Therefore, DCLK = MCLK/4. DOUT0 is in use.
Higher DCLK rates make it easier to receive the conversion data
from the AD7768/AD7768-4 with a lower number of DOUTx lines.

Figure 95. AD7768 FORMATx = 00, Eight Data Output Pins

Figure 96. AD7768 FORMATx = 01, Two Data Output Pins

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Data Sheet AD7768/AD7768-4
DATA INTERFACE

Figure 97. AD7768-4 FORMAT0 = 0, Four Data Output Pins

Figure 98. AD7768 FORMATx = 10 or 11, or AD7768-4 FORMAT0 = 1, One Data Output Pin

ADC CONVERSION OUTPUT: HEADER AND unexpectedly changed state, or an internal CRC error has been
DATA detected.
The AD7768 data is output on the DOUT0 pin to DOUT7 pin, In the case where an external clock is not detected, the conversion
depending on the FORMATx pins. The AD7768-4 data is output results are output as all zeros regardless of the analog input
on the DOUT0 pin to DOUT3 pin, depending on the FORMAT0 voltages applied to the ADC channels.
pin. The actual structure of the data output for each ADC result
is shown in Figure 99. Each ADC result is comprised of 32 bits. Filter Not Settled
The first eight bits are the header status bits, which contain status After power-up, reset, or synchronization, the AD7768/AD7768-4
information and the channel number. The names of each of the clear the digital filters and begins conversion. Due to the weighting
header status bits are shown in Table 35, and their functions are of the digital filters, there is a delay from the first conversion to fully
explained in the subsequent sections. This header is followed by a settled data. The settling times for the AD7768/AD7768-4 when
24-bit ADC output in twos complement coding, MSB first. using the wideband and sinc5 filters are shown in Table 28 and
Table 29, respectively. This bit is set if this settling delay has not yet
elapsed.

Repeated Data
If different channels use different decimation rates, data outputs
Figure 99. ADC Output: 8-Bit Header, 24-Bit ADC Conversion Data are repeated for the slower speed channels. In these cases, the
header is output as normal with the repeated data bit set to 1,
Table 35. Header Status Bits
and the following repeated ADC result is output as all zeros. This
Bit Bit Name bit indicates that the conversion result of all zeros is not real. The
7 ERROR_FLAGGED bit indicates that there is a repeated data condition because two
6 Filter not settled different decimation rates are selected. This condition can only
occur during SPI control of the AD7768/AD7768-4.
5 Repeated data
4 Filter type
Filter Type
3 Filter saturated
[2:0] Channel ID[2:0] In pin control mode, all channels operate using one filter selection.
The filter selected in pin control mode is determined by the logic
level of the FILTER pin. In SPI control mode, the digital filters can
ERROR_FLAGGED
be selected on a per channel basis using the mode registers. This
The error flagged bit indicates that a serious error has occurred. If header bit is 0 for channels using the wideband filter, and 1 for
this bit is set, a reset is required to clear this bit. This bit indicates channels using the sinc5 filter.
that the external clock is not detected, a memory map bit has

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Data Sheet AD7768/AD7768-4
DATA INTERFACE

Filter Saturated Each DRDY falling edge starts the output of the new ADC conver-
sion data. The first eight bits output after the DRDY falling edge are
The filter saturated bit indicates that the filter output is clipping at the header bits. The last 24 bits are the ADC conversion result.
either positive or negative full scale. The digital filter clips if the
signal goes beyond the specification of the filter, it does not wrap. Figure 100, Figure 101, Figure 102, and Figure 103 are distinct
The clipping may be caused by the analog input exceeding the examples of the impact of the FORMATx pins on the AD7768 out-
analog input range, or by a step change in the input, which may put operating in standard conversion operation. Figure 104, Figure
cause overshoot in the digital filter. Clipping may also occur when 105, and Figure 106 show examples of the AD7768-4 interface
the combination of the analog input signal and the channel gain configuration.
register setting cause the signal seen by the filter to be higher than Figure 100 through Figure 103 represent running the AD7768 at
the analog input range. maximum data rate for the three FORMATx options.
Channel ID Figure 100 shows FORMATx = 00 and each ADC has its own
data out (DOUT) pin running at the MCLK/4 bit rate. In pin control
The channel ID bits indicate the ADC channel from which the mode, this is achieved by selecting Mode 0xA (fast mode, DCLK
succeeding conversion data originates (see Table 36). = MCLK/4, standard conversion, see Table 20) with the decimation
Table 36. Channel ID vs. Channel Number rate set as ×32.
Channel Channel ID 2 Channel ID 1 Channel ID 0 Figure 101 shows FORMATx = 01 share DOUT1 at the maximum
Channel 0 0 0 0 bit rate. In pin control mode, this is achieved by selecting Mode 0x8
Channel 1 0 0 1 (fast mode, DCLK = MCLK/1, standard conversion) with a decima-
Channel 2 0 1 0
tion rate of ×32.
Channel 3 0 1 1 If running in pin control mode, the example shown in Figure 103
Channel 4 1 0 0 represents Mode 0x4 (median mode, DCLK = MCLK/1, standard
Channel 5 1 0 1 conversion) with a decimation rate of ×32, giving the maximum
output data capacity possible on one DOUTx pin.
Channel 6 1 1 0
Channel 7 1 1 1 Figure 102 (AD7768) and Figure 106 (AD7768-4) show examples
of one configuration where there can be long periods in which
Data Interface: Standard Conversion Operation no data is output by the AD7768. This configuration depends on
the FORMATx, MCLK, and decimation settings. In Figure 102,
In standard mode operation, the AD7768/AD7768-4 operate as the FORMATx = 01, meaning the channels share DOUT0 and DOUT1.
main and stream data to the DSP or FPGA. The AD7768/AD7768-4 In Figure 106, FORMAT0 = 1, meaning all channels share the
supply the data, the data clock (DCLK), and a falling edge framing DOUT0 pin. For both Figure 102 and Figure 106, DCLK = MCLK/4
signal (DRDY) to the subordinate device. All of these signals are and the decimation rate is 512. In pin control mode, this setup is
synchronous. The data interface connections to DSP/FPGA are achieved by selecting Mode 0x0A (fast mode, DCLK = MCLK/4,
shown in Figure 107. The FORMATx pins determine how the data standard conversion mode). With a decimation rate of 512, the ratio
is output from the AD7768/AD7768-4. of ODR to DCLK rate is high enough to show that only ¼ of the or
ODR period is used with output data, and the other ¾ of the period
Figure 100 through Figure 103 show the data interface operating in
DOUTx is low.
standard mode at the maximum data rate. In all instances, DRDY is
asserted one clock cycle before the MSB of the data conversion is
made available on the data pin.

Figure 100. AD7768 FORMATx = 00: Each ADC Has a Dedicated Data Output Pin, Maximum Data Rate

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Data Sheet AD7768/AD7768-4
DATA INTERFACE

Figure 101. AD7768 FORMATx = 01: Channel 0 to Channel 3 Share DOUT0, and Channel 4 to Channel 7 Share DOUT1, Maximum Data Rate

Figure 102. AD7768 FORMATx = 01: Channel 0 to Channel 3 Share DOUT0, and Channel 4 to Channel 7 Share DOUT1, Decimation = 512

Figure 103. AD7768 FORMATx = 11 or 10: Channel 0 to Channel 7 Output on DOUT0 Only, Maximum Data Rate

Figure 104. AD7768-4 FORMAT0 = 0: Each ADC Has a Dedicated Data Output Pin, Maximum Data Rate

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Data Sheet AD7768/AD7768-4
DATA INTERFACE

Figure 105. AD7768-4 FORMAT0 = 1: Channel 0 to Channel 3 Output on DOUT0 Only, Maximum Data Rate

Figure 106. AD7768-4 FORMAT0 = 1: Channel 0 to Channel 3 Output on DOUT0 Only, Decimation = 512

Figure 107. Data Interface: Standard Conversion Operation, AD7768 = Main, DSP/FPGA = Subordinate

Figure 108. AD7768 One Shot Mode

Data Interface: One-Shot Conversion Operation Mode 0xF when in pin control mode. In SPI control mode, set Bit
4 (one shot) of Register 0x06, the data control register. Figure 108
One shot mode is available in both SPI and pin control modes. shows the device operating in one shot mode.
This conversion mode is available by selecting one of Mode 0xC to

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Data Sheet AD7768/AD7768-4
DATA INTERFACE

In one shot mode, the AD7768/AD7768-4 are pseudo subordinates. For the AD7768/AD7768-4, this connection can be implemented by
Conversions occur on request by the main device, for example, the cascading DOUT0 and DOUT1 through a number of devices, or
DSP or FPGA. The SYNC_IN pin initiates the conversion request. just using DOUT0. Whether two data output pins or only one data
In one shot mode, all ADCs run continuously. However, the rising output pin is enabled depends on the FORMATx pins. The ability to
edge of the SYNC_IN pin controls the point in time from which data daisy-chain devices and the limit on the number of devices that can
is output. be handled by the chain is dependent on the power mode, DCLK,
and the decimation rate employed.
To receive data, the main must pulse the SYNC_IN pin to reset
the filter and force DRDY low. DRDY subsequently goes high The maximum usable DCLK frequency allowed when daisy-chain-
to indicate to the main device that the device has valid settled ing devices is limited by the combination of timing specifications in
data available. Unlike standard mode, DRDY remains high for the Table 3 or Table 5, as well as by the propagation delay of the data
number of clock periods of valid data before it goes low again. between devices and any skew between the MCLK signals at each
Therefore, in this conversion mode, it is an active high frame of the AD7768/AD7768-4 device. The propagation delay and MCLK skew
data. are dependent on the PCB layout and trace lengths.
When the main pulses SYNC_IN and the AD7768/AD7768-4 re- This feature is especially useful for reducing component count and
ceive the rising edge of this signal, the digital filter is reset and the wiring connections, for example, in isolated multiconverter applica-
full settling time of the filter elapses before the data is available. tions or for systems with a limited interfacing capacity.
The duration of the settling time depends on the filter path and
decimation rate. Running one-shot mode with the sinc5 filter allows When daisy-chaining, on the AD7768, DOUT6 and DOUT7 become
the fastest throughput, because this filter has a lower settling time serial data inputs, and DOUT0 and DOUT1 remain as serial data
than the wideband filter. outputs under the control of the FORMATx pins. For the AD7768-4
the DIN pin is the daisy chain serial data input pin and DOUT0 is
As soon as settled data is available on any channel, the device the serial data output pin.
outputs data from all channels. The contents of Bit 6 of the channel
header status bits indicates whether the data is fully settled.
The period before the data is settled on all channels (tSETTLE) is
shown in Figure 108. The settling time (tSETTLE) for the AD7768 in
one shot mode is equivalent to the number of clock cycles specified
as Delay from the First MCLK Rise after SYNC_IN Rise to Earliest
Settled Data, DRDY Rise in Table 30. After the data has settled
on all channels, DRDY is asserted high and the device outputs the
required settled data on all channels before DRDY is asserted low.
If the user configures the same filter and decimation rate on each
ADC, the data is settled for all channels on the first DRDY output
frame, which avoids a period of unsettled data prior to the settled
data and ensures that all data is output at the same time on all
ADCs. The device then waits for another SYNC_IN signal before
outputting more data.
Figure 109. Daisy-Chaining Multiple AD7768 Devices
Because all the ADCs are sampling continuously, one shot mode
affects the sampling theory of the AD7768/AD7768-4. Particularly, Figure 109 shows an example of daisy-chaining AD7768 devices
a user periodically sending a SYNC_IN pulse to the device is a when FORMATx = 01. In this case, the DOUT0 and DOUT1 pins
form of subsampling of the ADC output. The subsampling occurs of the AD7768 devices are cascaded to the DOUT6 and DOUT7
at the rate of the SYNC_IN pulses. The SYNC_IN pulse must be pins, respectively, of the next device in the chain. Data readback is
synchronous with the main clock to ensure coherent sampling and analogous to clocking a shift register where data is clocked on the
to reduce the effects of jitter on the frequency response. rising edge of DCLK.
The scheme operates by passing the output data of the DOUT0
Daisy-Chaining pin and DOUT1 pin of an AD7768 upstream device to the DOUT6
Daisy-chaining devices allows numerous devices to use the same and DOUT7 inputs, respectively, of the next AD7768 device down-
data interface lines by cascading the outputs of multiple ADCs from stream in the chain. The data then continues through the chain
separate AD7768/AD7768-4 devices. Only one ADC device has its until it is clocked onto the DOUT0 pin and DOUT1 pin of the final
data interface in direct connection with the digital host. downstream device in the chain.
The devices in the chain must be synchronized by using one of the
following methods:
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Data Sheet AD7768/AD7768-4
DATA INTERFACE

► Applying a synchronous signal to the SYNC_IN pin of all devices chronization pulse that is truly synchronous with the base MCLK
in the chain signal.
► By routing the SYNC_OUT pin of the first device to the SYNC_IN
Two synchronization pulses are required in a system of more than
pin of that same device and to the SYNC_IN pins of all other one AD7768/AD7768-4 device sharing a single MCLK signal, to
devices in the chain and applying an asynchronous signal to the ensure that all devices are in close phase alignment, or where the
START input. DRDY pin of only one device is used to detect new data.
► Issuing an SPI_SYNC command over the SPI control interface.
If the user cannot provide a signal that is synchronous to the base
Figure 109 shows the configuration where an asynchronous signal MCLK signal, one of the following two methods can be employed:
is applied to the START pin, and the SYNC_OUT pin of the first
device is connected to the SYNC_IN pins of all devices in the chain ► Apply a START pulse to the first AD7768 or AD7768-4 device.
The first AD7768 or AD7768-4 device samples the asynchronous
Daisy-chaining can be achieved in a similar manner on the START pulse and generates a pulse on SYNC_OUT of the first
AD7768/AD7768-4 when using only the DOUT0 pin. In this case, device related to the base MCLK signal for distribution locally.
only Pin 21 of the AD7768/AD7768-4 is used as the serial data ► Use synchronization over SPI (only available in SPI control
input pin. mode) to write a synchronization command to the first AD7768
In a daisy-chained system of AD7768/AD7768-4 devices, two suc- or AD7768-4 device. Similarly to the START pin method, the SPI
cessive synchronization pulses must be applied to guarantee that sync generates a pulse on SYNC_OUT of the first device related
all ADCs are synchronized. It is recommended to wait at least 16 to the base MCLK signal for distribution locally.
MCLK pulses between issuing the first and second synchronization In both cases, route the SYNC_OUT pin of the first device to the
pulses. Two synchronization pulses are also required in a system SYNC_IN pin of that same device and to the SYNC_IN pins of all
of more than one AD7768/AD7768-4 device sharing a single MCLK other devices that are to be synchronized (see Figure 110). The
signal, where the DRDY pin of only one device is used to detect SYNC_OUT pins of the other devices must remain open circuit. Tie
new data. all unused START pins to a Logic 1 through pull-up resistors.
The maximum DCLK frequency that can be used when daisy-chain-
ing devices is a function of the AD7768/AD7768-4 timing specifica-
tions (t4 and t11 in Table 3 and Table 5) and any timing differences
between the AD7768/AD7768-4 devices due to layout and spacing
of devices on the PCB.
Use the following formula to aid in determining the maximum
operating frequency of the interface:
1
fMAX = 2 × (t11 + t4 + tP + tSKEW) (2)

where:
fMAX is the maximum useable DCLK frequency.
t11 and t4 are the AD7768/AD7768-4 timing specifications (see
Table 3 and Table 5).
tP is the maximum propagation delay of the data between succes-
Figure 110. Synchronizing Multiple AD7768/AD7768-4 Devices Using
sive AD7768/AD7768-4 devices in the chain.
SYNC_OUT
tSKEW is the maximum skew in the MCLK signal seen by any pair of
AD7768/AD7768-4 devices in the chain. If the user can provide a signal that is synchronous to the base
MCLK, this signal can be applied directly to the SYNC_IN pin.
Synchronization Route the signal from a star point and connect it directly to the
The basic provision for synchronizing multiple devices is that each SYNC_IN pin of each AD7768/AD7768-4 device (see Figure 111).
device is clocked with the same base MCLK signal and that the The signal is sampled on the rising MCLK edge. Setup and hold
user can provide a synchronization signal to at least one of the times are associated with the SYNC_IN input and are relative to the
devices by one of the methods described in this section. AD7768/AD7768-4 MCLK rising edge.

The AD7768/AD7768-4 offer three options to allow ease of system In this case, tie the START pin to Logic 1 through a pull-up resistor.
synchronization. Choosing between the options depends on the SYNC_OUT is not used and can remain open circuit.
system, but is determined by whether the user can supply a syn-

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Data Sheet AD7768/AD7768-4
DATA INTERFACE

after a synchronization. For the channels operating at a relatively

slower ODR, the CRC is still calculated and emitted every 4 or 16
DRDY cycles, even if this means that the nulled data is included.
Therefore, a CRC is calculated for only nulled samples or for a
combination of nulled samples and actual conversion data.
The AD7768/AD7768-4 use a CRC polynomial to calculate the
CRC message. The 8-bit CRC polynomial used is x8 + x2 + x + 1.
The following code is a snippet of the C code, which shows how
the CRC value can be calculated for a given set of ADC conversion
results. Running this code on sets of 4 or 16 conversion results
gives the CRC value that the AD7768 generates, per channel. The
user can then compare the computed value from this code to the
actual CRC value read from the AD7768, and so confirm that the
Figure 111. Synchronizing Multiple AD7768/AD7768-4 Devices Using Only
data was read without error.
SYNC_IN
#include <stdio.h>
CRC Check on Data Interface FILE *fi1;
FILE *fo1;
The AD7768/AD7768-4 deliver 32 bits per channel as standard, main(){
which, by default, consists of 8 status header bits and 24 bits of int num_data_bits=24; // 24 or 16
data. int num_data_words=4; //4 or 16
int data;
The header bits default per the description in Table 35. However, int crc[8],crc_new[8];
there is also the option to employ a CRC check on the ADC conver- int i,j,n,k,num,bit,result;
sion data. This functionality is available only when operating in SPI const int num_crc_bits=8;
control mode. The function is controlled by CRC_ SELECT in the int bit_sel[num_data_bits];
interface configuration register (Register 0x07). When employed, bit_sel[23] = 0x800000;
the CRC message is calculated internally by the AD7768/AD7768-4 bit_sel[22] = 0x400000;
on a per channel basis. The CRC then replaces the 8-bit header bit_sel[21] = 0x200000;
every four samples or every 16 samples. bit_sel[20] = 0x100000;
bit_sel[19] = 0x080000;
The following is an example of how the CRC works for four-sample bit_sel[18] = 0x040000;
mode (see Figure 112): bit_sel[17] = 0x020000;
1. After a synchronization pulse is applied to the AD7768/ bit_sel[16] = 0x010000;
AD7768-4, the CRC register is cleared to 0xFF. bit_sel[15] = 0x008000;
2. The next four 24-bit conversion data samples (N to N + 3) for a bit_sel[14] = 0x004000;
given channel stream into the CRC calculation. bit_sel[13] = 0x002000;
bit_sel[12] = 0x001000;
3. For the first three samples that are output after the synchroniza- bit_sel[11] = 0x000800;
tion pulse (N to N + 2), the header contains the normal status bit_sel[10] = 0x000400;
bits. bit_sel[9] = 0x000200;
4. For the fourth sample after the synchronization pulse (N + 3), bit_sel[8] = 0x000100;
the 8-bit CRC is sent out instead of the normal header status bit_sel[7] = 0x000080;
bits, followed by the sample conversion data. This CRC calcu- bit_sel[6] = 0x000040;
lation includes the conversion data that is output immediately bit_sel[5] = 0x000020;
after the CRC header. bit_sel[4] = 0x000010;
5. The CRC register is then cleared back to 0xFF and the cycle bit_sel[3] = 0x000008;
begins again for the fifth to eighth samples after the synchroni- bit_sel[2] = 0x000004;
zation pulse. bit_sel[1] = 0x000002;
bit_sel[0] = 0x000001;
It is possible to have channels outputting at different rates (for fi1 = fopen("adcdata.txt", "r");
example decimation by 32 on Channel 0 and decimation by 64 on fo1 = fopen("crc_out.txt", "w");
Channel 1). In such cases, the CRC header still appears across j = 1;
all channels at the same time, that is, at every fourth DRDY pulse //initialise CRC to FF

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Data Sheet AD7768/AD7768-4
DATA INTERFACE

for (i=0;i<num_crc_bits;i++) crc[i]=1; crc_new[0]=data^crc[7];

result = ((crc[7]<<7) & 0x0080) //debug printf(" qq(0) = %1d ",qq[0]);
| ((crc[6]<<6) & 0x0040) crc_new[1]=data^crc[7]^crc[0];
| ((crc[5]<<5) & 0x0020) crc_new[2]=data^crc[7]^crc[1];
| ((crc[4]<<4) & 0x0010) crc_new[3]=crc[2];
| ((crc[3]<<3) & 0x0008) crc_new[4]=crc[3];
| ((crc[2]<<2) & 0x0004) crc_new[5]=crc[4];
| ((crc[1]<<1) & 0x0002) crc_new[6]=crc[5];
| ((crc[0]<<0) & 0x0001); crc_new[7]=crc[6];
printf("CRC Initialised to 0x%.02X \n",result); //debug printf("%8d ",j);
fprintf(fo1,"-------------------------------- for (i=num_crc_bits-1;i>=0;i--){
\n"); crc[i]=crc_new[i];
fprintf(fo1,"CRC Initialised to 0x%.02X \n",re► printf("%1d",crc[i]);
sult); }
//run CRC on data //debug printf("\n");
for (n = 0; n < num_data_words; n++){ result = ((crc[7]<<7) & 0x0080)
fprintf(fo1,"-------------------------------- | ((crc[6]<<6) & 0x0040)
\n"); | ((crc[5]<<5) & 0x0020)
fprintf(fo1,"Loop %d start\n",n+1); | ((crc[4]<<4) & 0x0010)
fprintf(fo1,"-------------------------------- | ((crc[3]<<3) & 0x0008)
\n"); | ((crc[2]<<2) & 0x0004)
fprintf(fo1,"ADC Data values\n"); | ((crc[1]<<1) & 0x0002)
fprintf(fo1,"-------------------------------- | ((crc[0]<<0) & 0x0001);
\n"); printf(" intermediate res is 0x%.02X\n",re►
fscanf(fi1,"%x\n",&num); sult);
fprintf(fo1,"0x%.06X\n",num); fprintf(fo1,"intermediate res is 0x%.02X\n",re►
fprintf(fo1,"-------------------------------- sult);
\n"); if (k == 0) {
fprintf(fo1,"CRC values\n"); printf("loop %d:res is 0x%.02X\n",n,result);
fprintf(fo1,"-------------------------------- }
\n"); }
for (k=num_data_bits-1;k>=0;k--){ }
//for (i=7;i>=0;i--){ fprintf(fo1,"--------------------------------
// printf("%1d",crc[i]); \n");
//} printf("Final CRC value = 0x%.02X\n",result);
bit = (num & bit_sel[k]); // msb first fprintf(fo1,"CRC value = 0x%.02X\n",result);
data = bit>>(k); }
printf(" bit_sel is: %.06X - data is :
%X ",bit_sel[k], data);

Figure 112. CRC 4-Bit Stream

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Data Sheet AD7768/AD7768-4
FUNCTIONALITY

GPIO FUNCTIONALITY
The AD7768/AD7768-4 have additional GPIO functionality when
operated in SPI mode. This fully configurable mode allows the
device to operate five GPIOs. The GPIOx pins can be set as inputs
or outputs (read or write) on a per pin basis.
In write mode, these GPIO pins can be used to control other circuits
such as switches, multiplexers, buffers, over the same SPI interface
as the AD7768/AD7768-4. Sharing the SPI interface in this way
allows the user to use a lower overall number of data lines from
the controller compared to a system where multiple control signals
are required. This sharing is especially useful in systems where
reducing the number of control lines across an isolation barrier is
important. See Figure 113 and Figure 114 for details of the GPIO
pin options available on the AD7768 and AD7768-4, respectively. Figure 114. AD7768-4 GPIO Functionality
Similarly, a GPIO read is a useful feature because it allows a
Configuration control and readback of the GPIOx pins are set in
peripheral device to send information to the input GPIO and then
Register 0x0E, Register 0x0F, and Register 0x10 (see Table 49,
this information can be read from the SPI interface of the AD7768/
Table 50, and Table 51 for more information for the AD7768, and
AD7768-4.
Table 75, Table 76, and Table 77 for the AD7768-4).

Figure 113. AD7768 GPIO Functionality

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

AD7768 REGISTER MAP

See Table 63 and the AD7768-4 Register Map Details (SPI Control) section for the AD7768-4 register map and register functions.

Table 37. Detailed AD7768 Register Map

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x00 Channel Standby CH_7 CH_6 CH_5 CH_4 CH_3 CH_2 CH_1 CH_0 0x00 RW
0x01 Channel Mode A Unused FILTER_ DEC_RATE_A 0x0D RW
TYPE_A
0x02 Channel Mode B Unused FILTER_ DEC_RATE_B 0x0D RW
TYPE_B
0x03 Channel Mode CH_7_ CH_6_ CH_5_ CH_4_ CH_3_MODE CH_2_ CH_1_ CH_0_ 0x00 RW
Select MODE MODE MODE MODE MODE MODE MODE
0x04 POWER_MODE SLEEP_ Unused POWER_MODE LVDS_ Unused MCLK_DIV 0x00 RW
MODE ENABLE
0x05 General Unused CLK_QUAL_ RETIME_ VCM_PD Reserved Unused VCM_VSEL 0x08 RW
Configuration DIS EN
0x06 Data Control SPI_SYNC Unused SINGLE_ Unused SPI_RESET 0x80 RW
SHOT_EN
0x07 Interface Unused CRC_SELECT DCLK_DIV 0x0 RW
Configuration
0x08 BIST Control Unused RAM_BIST_ 0x0 RW
START
0x09 Device Status Unused CHIP_ERROR NO_CLOCK_ RAM_BIST_ RAM_BIST_ 0x0 R
ERROR PASS RUNNING
0x0A Revision ID REVISION_ID 0x06 R
0x0B Reserved Reserved 0x00 R
0x0C Reserved Reserved 0x00 R
0x0D Reserved Reserved 0x00 R
0x0E GPIO Control UGPIO_ Unused GPIOE4_ GPIOE3_ GPIOE2_ GPIOE1_
GPIO0_ 0x00 RW
ENABLE FILTER MODE3 MODE2 MODE1
MODE0
0x0F GPIO Write Data Unused GPIO4_WRITE GPIO3_WRITE GPIO2_WRITE GPIO1_WRITE GPIO0_ 0x00 RW
WRITE
0x10 GPIO Read Data Unused GPIO4_READ GPIO3_READ GPIO2_READ GPIO1_READ GPIO0_ 0x00 R
READ
0x11 Precharge CH3_ CH3_ CH2_ CH2_ CH1_ CH1_ CH0_ CH0_ 0xFF RW
Buffer 1 PREBUF_ PREBUF_ PREBUF_ PREBUF_ PREBUF_ PREBUF_ PREBUF_ PREBUF_
NEG_EN POS_EN NEG_EN POS_EN NEG_EN POS_EN NEG_EN POS_EN
0x12 Precharge CH7_ CH7_ CH6_ CH6_ CH5_ CH5_ CH4_ CH4_ 0xFF RW
Buffer 2 PREBUF_ PREBUF_ PREBUF_ PREBUF_ PREBUF_ PREBUF_ PREBUF_ PREBUF_
NEG_EN POS_EN NEG_EN POS_EN NEG_EN POS_EN NEG_EN POS_EN
0x13 Positive CH7_ CH6_ CH5_ CH4_REFP_ CH3_REFP_ CH2_REFP_ CH1_REFP_ CH0_REFP_ 0x00 RW
Reference REFP_BUF REFP_BUF REFP_BUF BUF BUF BUF BUF BUF
Precharge
Buffer
0x14 Negative CH7_ CH6_ CH5_ CH4_ CH3_ CH2_ CH1_ CH0_ 0x00 RW
Reference REFN_ REFN_ REFN_ REFN_ REFN_ REFN_ REFN_ REFN_
Precharge BUF BUF BUF BUF BUF BUF BUF BUF
Buffer

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 37. Detailed AD7768 Register Map (Continued)

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x1E Channel 0 Offset CH0_OFFSET_MSB 0x00 RW
0x1F CH0_OFFSET_MID
0x20 CH0_OFFSET_LSB
0x21 Channel 1 Offset CH1_OFFSET_MSB 0x00 RW
0x22 CH1_OFFSET_MID
0x23 CH1_OFFSET_LSB
0x24 Channel 2 Offset CH2_OFFSET_MSB 0x00 RW
0x25 CH2_OFFSET_MID
0x26 CH2_OFFSET_LSB
0x27 Channel 3 Offset CH3_OFFSET_MSB 0x00 RW
0x28 CH3_OFFSET_MID
0x29 CH3_OFFSET_LSB
0x2A Channel 4 Offset CH4_OFFSET_MSB 0x00 RW
0x2B CH4_OFFSET_MID
0x2C CH4_OFFSET_LSB
0x2D Channel 5 Offset CH5_OFFSET_MSB 0x00 RW
0x2E CH5_OFFSET_MID
0x2F CH5_OFFSET_LSB
0x30 Channel 6 Offset CH6_OFFSET_MSB 0x00 RW
0x31 CH6_OFFSET_MID
0x32 CH6_OFFSET_LSB
0x33 Channel 7 Offset CH7_OFFSET_MSB 0x00 RW
0x34 CH7_OFFSET_MID
0x35 CH7_OFFSET_LSB
0x36 Channel 0 Gain CH0_GAIN_MSB 0xXX RW
0x37 CH0_GAIN_MID
0x38 CH0_GAIN_LSB
0x39 Channel 1 Gain CH1_GAIN_MSB 0xXX RW
0x3A CH1_GAIN_MID
0x3B CH1_GAIN_LSB
0x3C Channel 2 Gain CH2_GAIN_MSB 0xXX RW
0x3D CH2_GAIN_MID
0x3E CH2_GAIN_LSB
0x3F Channel 3 Gain CH3_GAIN_MSB 0xXX RW
0x40 CH3_GAIN_MID
0x41 CH3_GAIN_LSB
0x42 Channel 4 Gain CH4_GAIN_MSB 0xXX RW
0x43 CH4_GAIN_MID
0x44 CH4_GAIN_LSB
0x45 Channel 5 Gain CH5_GAIN_MSB 0xXX RW
0x46 CH5_GAIN_MID
0x47 CH5_GAIN_LSB
0x48 Channel 6 Gain CH6_GAIN_MSB 0xXX RW

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 37. Detailed AD7768 Register Map (Continued)

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x49 CH6_GAIN_MID
0x4A CH6_GAIN_LSB
0x4B Channel 7 Gain CH7_GAIN_MSB 0xXX RW
0x4C CH7_GAIN_MID
0x4D CH7_GAIN_LSB
0x4E Channel 0 Sync CH0_SYNC_OFFSET 0x00 RW
Offset
0x4F Channel 1 Sync CH1_SYNC_OFFSET 0x00 RW
Offset
0x50 Channel 2 Sync CH2_SYNC_OFFSET 0x00 RW
Offset
0x51 Channel 3 Sync CH3_SYNC_OFFSET 0x00 RW
Offset
0x52 Channel 4 Sync CH4_SYNC_OFFSET 0x00 RW
Offset
0x53 Channel 5 Sync CH5_SYNC_OFFSET 0x00 RW
Offset
0x54 Channel 6 Sync CH6_SYNC_OFFSET 0x00 RW
Offset
0x55 Channel 7 Sync CH7_SYNC_OFFSET 0x00 RW
Offset
0x56 Diagnostic CH7_RX CH6_RX CH5_RX CH4_RX CH3_RX CH2_RX CH1_RX CH0_RX 0x00 RW
Receiver
0x57 Diagnostic Mux Unused GRPB_SEL Unused GRPA_SEL 0x00 RW
Control
0x58 Modulator Delay Unused CLK_MOD_DEL_EN Reserved 0x02 RW
Control
0x59 Chop Control Unused GRPA_CHOP GRPB_CHOP 0x0A RW

CHANNEL STANDBY REGISTER

Address: 0x00, Reset: 0x00, Name: Channel Standby
Each of the ADC channels can be put into standby mode independently by setting the appropriate bit in the channel standby register. When a
channel is in standby mode, its position in the data output stream is held. The 8-bit header is all zeros, as is the conversion result output of 24
zeros.
The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also
disabled for maximum power savings. Channel 0 must be enabled while VCM is being used externally to the AD7768.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into standby mode, the crystal circuitry is also
disabled for maximum power savings. Channel 4 must be enabled while the external crystal is used on the AD7768.

Table 38. Bit Descriptions for Channel Standby

Bits Bit Name Settings Description Reset Access
7 CH_7 Channel 7 0x0 RW
0 Enabled
1 Standby
6 CH_6 Channel 6 0x0 RW

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 38. Bit Descriptions for Channel Standby (Continued)

Bits Bit Name Settings Description Reset Access
0 Enabled
1 Standby
5 CH_5 Channel 5 0x0 RW
0 Enabled
1 Standby
4 CH_4 Channel 4 0x0 RW
0 Enabled
1 Standby
3 CH_3 Channel 3 0x0 RW
0 Enabled
1 Standby
2 CH_2 Channel 2 0x0 RW
0 Enabled
1 Standby
1 CH_1 Channel 1 0x0 RW
0 Enabled
1 Standby
0 CH_0 Channel 0 0x0 RW
0 Enabled
1 Standby

CHANNEL MODE A REGISTER

Address: 0x01, Reset: 0x0D, Name: Channel Mode A
Two mode options are available on the AD7768 ADCs. The channel modes are defined by the contents of the Channel Mode A and Channel
Mode B registers. Each mode is then mapped as desired to the required ADC channel. Channel Mode A and Channel Mode B allow different
filter types and decimation rates to be selected and mapped to any of the ADC channels.
When different decimation rates are selected, the AD7768 outputs a data ready signal at the fastest selected decimation rate. Any channel that
runs at a lower output data rate is updated only at that slower rate. In between valid result data, the data for that channel is set to zero and the
repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the ADC Conversion Output: Header and
Data section).

Table 39. Bit Descriptions for Channel Mode A

Bits Bit Name Settings Description Reset Access
3 FILTER_TYPE_A Filter Selection 0x1 RW
0 Wideband filter
1 Sinc5 filter
[2:0] DEC_RATE_A Decimation Rate Selection 0x5 RW
000 ×32
001 ×64
010 ×128
011 ×256
100 ×512
101 ×1024
110 ×1024

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 39. Bit Descriptions for Channel Mode A (Continued)

Bits Bit Name Settings Description Reset Access
111 ×1024

CHANNEL MODE B REGISTER

Address: 0x02, Reset: 0x0D, Name: Channel Mode B

Table 40. Bit Descriptions for Channel Mode B

Bits Bit Name Settings Description Reset Access
3 FILTER_TYPE_B Filter Selection 0x1 RW
0 Wideband filter
1 Sinc5 filter
[2:0] DEC_RATE_B Decimation Rate Selection 0x5 RW
000 ×32
001 ×64
010 ×128
011 ×256
100 ×512
101 ×1024
110 ×1024
111 ×1024

CHANNEL MODE SELECT REGISTER

Address: 0x03, Reset: 0x00, Name: Channel Mode Select
This register selects the mapping of each ADC channel to either Channel Mode A or Channel Mode B.

Table 41. Bit Descriptions for Channel Mode Select

Bits Bit Name Settings Description Reset Access
7 CH_7_MODE Channel 7 0x0 RW
0 Mode A
1 Mode B
6 CH_6_MODE Channel 6 0x0 RW
0 Mode A
1 Mode B
5 CH_5_MODE Channel 5 0x0 RW
0 Mode A
1 Mode B
4 CH_4_MODE Channel 4 0x0 RW
0 Mode A
1 Mode B
3 CH_3_MODE Channel 3 0x0 RW
0 Mode A
1 Mode B
2 CH_2_MODE Channel 2 0x0 RW
0 Mode A
1 Mode B

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 41. Bit Descriptions for Channel Mode Select (Continued)

Bits Bit Name Settings Description Reset Access
1 CH_1_MODE Channel 1 0x0 RW
0 Mode A
1 Mode B
0 CH_0_MODE Channel 0 0x0 RW
0 Mode A
1 Mode B

POWER MODE SELECT REGISTER

Address: 0x04, Reset: 0x00, Name: POWER_MODE

Table 42. Bit Descriptions for POWER_MODE

Bits Bit Name Settings Description Reset Access
7 SLEEP_MODE In sleep mode, many of the digital clocks are disabled and all of the ADCs are disabled. The analog 0x0 RW
LDOs are not disabled.
The AD7768 SPI is live and is available to the user. Writing to this bit brings the AD7768 out of sleep
mode again.
0 Normal operation.
1 Sleep mode.
[5:4] POWER_MODE Power Mode. The power mode bits control the power mode setting for the bias currents used on all 0x0 RW
ADCs on the AD7768. The user can select the current consumption target to meet the application.
The power modes of fast, median, and low power give optimum performance when mapped to the
correct MCLK division setting. These power mode bits do not control the MCLK division of the ADCs.
See the MCLK_DIV bits for control of the division of the MCLK input.
00 Low power mode.
10 Median mode.
11 Fast mode.
3 LVDS_ENABLE LVDS Input Clock. 0x0 RW
0 LVDS input clock disabled.
1 LVDS input clock enabled.
[1:0] MCLK_DIV MCLK Division. The MCLK division bits control the divided ratio between the MCLK applied at the 0x0 RW
input to the AD7768 and the clock used by each of the ADC modulators. The appropriate division ratio
depends on the following factors: power mode, decimation rate, and the base MCLK available in the
system. See the Clocking, Sampling Tree, and Power Scaling section for more information on setting
MCLK_DIV correctly.
00 MCLK/32: with a base MCLK of 32.768 MHz, set to MCLK/32 for low power mode.
10 MCLK/8: with a base MCLK of 32.768 MHz, set to MCLK/8 for median mode.
11 MCLK/4: with a base MCLK of 32.768 MHz, set to MCLK/4 for fast mode.

GENERAL DEVICE CONFIGURATION REGISTER

Address: 0x05, Reset: 0x08, Name: General Configuration

Table 43. Bit Descriptions for General Configuration

Bits Bit Name Settings Description Reset Access
6 CLK_QUAL_DIS Clock Qualification Disable Bit. Allows the user to disable the external clock source qualification. 0x0 RW
After reset, the external MCLK frequency is checked to be at least approximately 1.15 MHz,
before being accepted as valid and before the AD7768 hands control over to the external clock

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 43. Bit Descriptions for General Configuration (Continued)

Bits Bit Name Settings Description Reset Access
source. If this qualification check fails, the NO_CLOCK_ERROR bit is set and the AD7768
continues to run using the internal startup clock. Users can disable this qualification check to
force the AD7768 to accept and hand control over to an external clock source with a lower
frequency. This bit functions as expected for the recommended fMOD ranges as mentioned in
Table 11.
0 Enabled. Clock qualification check is performed.
1 Disabled. Clock qualification check is not performed.
5 RETIME_EN SYNC_OUT Signal Retime Enable Bit. 0x0 RW
0 Disabled. Normal timing of SYNC_OUT.
1 Enabled. SYNC_OUT signal derived from alternate MCLK edge.
4 VCM_PD VCM Buffer Power-Down. 0x0 RW
0 Enabled. VCM buffer normal mode.
1 Powered down. VCM buffer powered down.
[1:0] VCM_VSEL VCM Voltage. These bits select the output voltage of the VCM pin. This voltage is derived from 0x0 RW
the AVDD1 supply and can be output as half of that AVDD1 voltage, or other fixed voltages, with
respect to AVSS. The VCM voltage output is associated with the Channel 0 circuitry. If Channel
0 is put into standby mode, the VCM voltage output is also disabled for maximum power savings.
Channel 0 must be enabled while VCM is being used externally to the AD7768.
00 (AVDD1 − AVSS)/2 V.
01 1.65 V.
10 2.5 V.
11 2.14 V.

DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER

Address: 0x06, Reset: 0x80, Name: Data Control

Table 44. Bit Descriptions for Data Control

Bits Bit Name Settings Description Reset Access
7 SPI_SYNC Software Synchronization of the AD7768. This command has the same effect as sending a signal 0x1 RW
pulse to the START pin. To operate the SPI_SYNC, the user must write to this bit two separate
times. First, write a zero, putting SPI_SYNC low, and then write a 1 to set SPI_SYNC logic high
again. The SPI_SYNC command is recognized after the last rising edge of SCLK in the SPI
instruction where the SPI_SYNC bit is changed from low to high. The SPI_SYNC command is
then output synchronous to the AD7768 MCLK on the SYNC_OUT pin. The user must connect the
SYNC_OUT signal to the SYNC_IN pin on the PCB. The SYNC_OUT pin can also be routed to
the SYNC_IN pins of other AD7768 devices, allowing larger channel count simultaneous sampling
systems. As per any synchronization pulse seen by the SYNC_IN pin, the digital filters of the
AD7768 are reset. The full settling time of the filters must elapse before data is output on the data
interface. In a daisy-chained system of AD7768 devices, two successive synchronization pulses
must be applied to guarantee that all ADCs are synchronized. Two synchronization pulses are also
required in a system of more than one AD7768 device sharing a single MCLK signal, where the
DRDY pin of only one device is used to detect new data.
0 Change to SPI_SYNC low.
1 Change to SPI_SYNC high.
4 SINGLE_SHOT_EN One Shot Mode. Enables one shot mode. In one shot mode, the AD7768 outputs a conversion 0x0 RW
result in response to a SYNC_IN rising edge.
0 Disabled.

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 44. Bit Descriptions for Data Control (Continued)

Bits Bit Name Settings Description Reset Access
1 Enabled.
[1:0] SPI_RESET Soft Reset. These bits allow a full device reset over the SPI port. Two successive commands must 0x0 RW
be received in the correct order to generate a reset: first, write 0x03 to the soft reset register, and
then write 0x02 to the soft reset register. This sequence causes the digital core to reset and all
registers return to their default values. Following a soft reset, if the SPI main sends a command to
the AD7768, the devices respond on the next frame to that command with an output of 0x0E00.
00 No effect.
01 No effect.
10 Second reset command.
11 First reset command.

INTERFACE CONFIGURATION REGISTER

Address: 0x07, Reset: 0x00, Name: Interface Configuration

Table 45. Bit Descriptions for Interface Configuration

Bits Bit Name Settings Description Reset Access
[3:2] CRC_SELECT CRC Select. These bits allow the user to implement a CRC on the data interface. When selected, the 0x0 RW
CRC replaces the header every fourth or 16th output sample depending on the CRC option chosen. There
are two options for the CRC. Both options use the same polynomial: x8 + x2 + x + 1. The options offer the
user the ability to reduce the duty cycle of the CRC calculation by performing it less often: in the case of
having it every 16th sample or more often in the case of every fourth conversion. The CRC is calculated
on a per channel basis and it includes conversion data only.
00 No CRC. Status bits with every conversion.
01 Replace the header with CRC message every 4 samples.
10 Replace the header with CRC message every 16 samples.
11 Replace the header with CRC message every 16 samples.
[1:0] DCLK_DIV DCLK Divider. These bits control division of the DCLK clock used to clock out conversion data on the 0x0 RW
DOUTx pins. The DCLK signal is derived from the MCLK applied to the AD7768. The DCLK divide mode
allows the user to optimize the DCLK output to fit the application. Optimizing the DCLK per application
depends on the requirements of the user. When the AD7768 are using the highest capacity output on
the fewest DOUTx pins, for example, running in decimate by 32 using the DOUT0 and DOUT1 pins, the
DCLK must equal the MCLK. Therefore, in this case, choosing the no division setting is the only way
the user can output all the data within the conversion period. There are other cases, however, when the
ADC may be running in fast mode with high decimation rates, or in median or low power mode where the
DCLK does not need to run at the same speed as MCLK. In these cases, the DCLK divide allows the user
to reduce the clock speed and makes routing and isolating such signals easier.
00 Divide by 8.
01 Divide by 4.
10 Divide by 2.
11 No division.

DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER

Address: 0x08, Reset: 0x00, Name: BIST Control

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 46. Bit Descriptions for BIST Control

Bits Bit Name Settings Description Reset Access
0 RAM_BIST_START RAM BIST. Filter RAM BIST is a built in self test of the internal RAM. Normal ADC 0x0 RW
conversion is disrupted when this test is run. A synchronization pulse is required after
this test is complete to resume normal ADC operation. The test can be run at intervals
depending on user preference. The status and result of the RAM BIST is available in the
device status register. See the RAM_BIST_PASS and RAM_BIST_RUNNING bits in Table
47.
0 Off.
1 Begin RAM BIST.

STATUS REGISTER
Address: 0x09, Reset: 0x00, Name: Device Status

Table 47. Bit Descriptions for Device Status

Bits Bit Name Settings Description Reset Access
3 CHIP_ERROR Chip Error. Chip error is a global error flag that is output within the status byte of each ADC 0x0 R
conversion output. The following bits lead to the chip error bit being set to logic high: CRC
check on internally hard coded settings after power-up does not pass. XOR check on the
internal memory does not pass (this check runs continuously in the background), and clock
error is detected on power-up.
0 No error present.
1 Error has occurred.
2 NO_CLOCK_ERROR External Clock Check. This bit indicates whether the externally applied MCLK is detected 0x0 R
correctly. If the MCLK is not applied correctly to the ADC at power-up, this bit is set and the
DCLK frequency is approximately 16 MHz. If this bit is set, the chip error bit is set to logic high
in the status bits of the data output headers, and the conversion results are output as all zeros
regardless of the analog input voltages applied to the ADC channels.
0 MCLK detected.
1 No MCLK detected.
1 RAM_BIST_PASS BIST Pass/Fail. RAM BIST result status. This bit indicates the result of the most recent RAM 0x0 R
BIST. The result is latched to this register and is only cleared by a device reset.
0 BIST failed or not run.
1 BIST passed.
0 RAM_BIST_RUNNING BIST Status. Reading back the value of this bit allows the user to poll when the BIST test has 0x0 R
finished.
0 BIST not running.
1 BIST running.

REVISION IDENTIFICATION REGISTER

Address: 0x0A, Reset: 0x06, Name: Revision ID

Table 48. Bit Descriptions for Revision ID

Bits Bit Name Description Reset Access
[7:0] REVISION_ID ASIC Revision. 8-bit ID for revision details. 0x06 R

GPIO CONTROL REGISTER

Address: 0x0E, Reset: 0x00, Name: GPIO Control

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 49. Bit Descriptions for GPIO Control

Bits Bit Name Setting Description Reset Access
7 UGPIO_ENABLE User GPIO Enable. The GPIOx pins are dual-purpose and can be operated only when the device is in 0x0 RW
SPI control mode. By default, when the AD7768 are powered up in SPI control mode, the GPIOx pins
are disabled. This bit is a universal enable/ disable for all GPIOx input/outputs. The direction of each
general-purpose pin is determined by Bits[4:0] of this register.
0 GPIO disabled.
1 GPIO enabled.
4 GPIOE4_FILTER GPIO4 Direction. This bit assigns the direction of GPIO4 as either an input or an output. For SPI 0x0 RW
control, GPIO4 maps to Pin 11, which is the FILTER/GPIO4 pin.
0 Input.
1 Output.
3 GPIOE3_MODE3 GPIO3 Direction. This bit assigns the direction of GPIO3 as either an input or an output. For SPI 0x0 RW
control, GPIO3 maps to Pin 15, which is the MODE3/GPIO3 pin.
0 Input.
1 Output.
2 GPIOE2_MODE2 GPIO2 Direction. This bit assigns the direction of GPIO2 as either an input or an output. For SPI 0x0 RW
control, GPIO2 maps to Pin 14, which is the MODE2/GPIO2 pin.
0 Input.
1 Output.
1 GPIOE1_MODE1 GPIO1 Direction. This bit assigns the direction of GPIO1 as either an input or an output. For SPI 0x0 RW
control, GPIO1 maps to Pin 13, which is the MODE1/GPIO1 pin.
0 Input.
1 Output.
0 GPIO0_MODE0 GPIO0 Direction. This bit assigns the direction of GPIO0 as either an input or an output. For SPI 0x0 RW
control, GPIO0 maps to Pin 12, which is the MODE0/GPIO0 pin.
0 Input.
1 Output.

GPIO WRITE DATA REGISTER

Address: 0x0F, Reset: 0x00, Name: GPIO Write Data
This register writes the values to be set on each of the general-purpose pins when selected as general-purpose outputs. Each bit, from
Bits[4:0], maps directly to the GPIOx pins.

Table 50. Bit Descriptions for GPIO Write Data

Bits Bit Name Description Reset Access
4 GPIO4_WRITE GPIO4/FILTER 0x0 RW
3 GPIO3_WRITE GPIO3/MODE3 0x0 RW
2 GPIO2_WRITE GPIO2/MODE2 0x0 RW
1 GPIO1_WRITE GPIO1/MODE1 0x0 RW
0 GPIO0_WRITE GPIO0/MODE0 0x0 RW

GPIO READ DATA REGISTER

Address: 0x10, Reset: 0x00, Name: GPIO Read Data
This register reads back the value of the logic input level at the general-purpose pins when selected to operate as general-purpose inputs. Each
bit, from Bits[4:0], maps directly to the GPIO0 pin to GPIO4 pin.

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AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 51. Bit Descriptions for GPIO Read Data

Bits Bit Name Description Reset Access
4 GPIO4_READ GPIO4/FILTER 0x0 R
3 GPIO3_READ GPIO3/MODE3 0x0 R
2 GPIO2_READ GPIO2/MODE2 0x0 R
1 GPIO1_READ GPIO1/MODE1 0x0 R
0 GPIO0_READ GPIO0/MODE0 0x00 R

ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3

Address: 0x11, Reset: 0xFF, Name: Precharge Buffer 1
This register turns on or off the precharge buffers on the analog inputs. When writing to these registers, the user must write the inverse of the
required bit settings. For example, to clear Bit 1 of this register, the user must write 0x01 to the register. This clears Bit 1 and sets all other bits.
If the user reads the register again after writing 0x01, the data read is 0xFE, as required.

Table 52. Bit Descriptions for Precharge Buffer 1

Bits Bit Name Settings Description Reset
7 CH3_PREBUF_NEG_EN 0 Off 0x1
1 On
6 CH3_PREBUF_POS_EN 0 Off 0x1
1 On
5 CH2_PREBUF_NEG_EN 0 Off 0x1
1 On
4 CH2_PREBUF_POS_EN 0 Off 0x1
1 On
3 CH1_PREBUF_NEG_EN 0 Off 0x1
1 On
2 CH1_PREBUF_POS_EN 0 Off 0x1
1 On
1 CH0_PREBUF_NEG_EN 0 Off 0x1
1 On
0 CH0_PREBUF_POS_EN 0 Off 0x1
1 On

ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7

Address: 0x12, Reset: 0xFF, Name: Precharge Buffer 2
This register turns on or off the precharge buffers on the analog inputs. When writing to these registers, the user must write the inverse of the
required bit settings. For example, to clear Bit 1 of this register, the user must write 0x01 to the register. This clears Bit 1 and sets all other bits.
If the user reads the register again after writing 0x01, the data read is 0xFE, as required.

Table 53. Bit Descriptions for Precharge Buffer 2

Bits Bit Name Settings Description Reset
7 CH7_PREBUF_NEG_EN 0 Off 0x1
1 On
6 CH7_PREBUF_POS_EN 0 Off 0x1
1 On
5 CH6_PREBUF_NEG_EN 0 Off 0x1

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Data Sheet AD7768/AD7768-4
AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 53. Bit Descriptions for Precharge Buffer 2 (Continued)

Bits Bit Name Settings Description Reset
1 On
4 CH6_PREBUF_POS_EN 0 Off 0x1
1 On
3 CH5_PREBUF_NEG_EN 0 Off 0x1
1 On
2 CH5_PREBUF_POS_EN 0 Off 0x1
1 On
1 CH4_PREBUF_NEG_EN 0 Off 0x1
1 On
0 CH4_PREBUF_POS_EN 0 Off 0x1
1 On

POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER

Address: 0x13, Reset: 0x00, Name: Positive Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference positive input to each of the ADCs from Channel 0 to Channel 7.

Table 54. Bit Descriptions for Positive Reference Precharge Buffer

Bits Bit Name Settings Description Reset
7 CH7_REFP_BUF 0 Off 0x0
1 On
6 CH6_REFP_BUF 0 Off 0x0
1 On
5 CH5_REFP_BUF 0 Off 0x0
1 On
4 CH4_REFP_BUF 0 Off 0x0
1 On
3 CH3_REFP_BUF 0 Off 0x0
1 On
2 CH2_REFP_BUF 0 Off 0x0
1 On
1 CH1_REFP_BUF 0 Off 0x0
1 On
0 CH0_REFP_BUF 0 Off 0x0
1 On

NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER

Address: 0x14, Reset: 0x00, Name: Negative Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference negative input to each of the ADCs from Channel 0 to Channel 7.

Table 55. Bit Descriptions for Negative Reference Precharge Buffer

Bits Bit Name Settings Description Reset
7 CH7_REFN_BUF 0 Off 0x0
1 On

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AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 55. Bit Descriptions for Negative Reference Precharge Buffer (Continued)
Bits Bit Name Settings Description Reset
6 CH6_REFN_BUF 0 Off 0x0
1 On
5 CH5_REFN_BUF 0 Off 0x0
1 On
4 CH4_REFN_BUF 0 Off 0x0
1 On
3 CH3_REFN_BUF 0 Off 0x0
1 On
2 CH2_REFN_BUF 0 Off 0x0
1 On
1 CH1_REFN_BUF 0 Off 0x0
1 On
0 CH0_REFN_BUF 0 Off 0x0
1 On

OFFSET REGISTERS
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_OFFSET_LSB registers at addresses 0x1E to 0x35 form 24-bit signed twos
complement registers for channel offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset
register adjustment changes the digital output by −4/3 LSBs. For example, changing the offset register from 0 to 100 changes the digital output
by −133 LSBs. As offset adjustment occurs before gain adjustment, the ratio of 4/3 changes linearly with gain adjustment via the CHx_GAIN_x
registers. After a reset or power cycle, the register values revert to the default factory setting.

Table 56. Per Channel 24-Bit Offset Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB
Address Reset
MSB Mid LSB Name Description MSB Mid LSB Access
0x1E 0x1F 0x20 Channel 0 Offset Channel 0 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x21 0x22 0x23 Channel 1 Offset Channel 1 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x24 0x25 0x26 Channel 2 Offset Channel 2 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x27 0x28 0x29 Channel 3 Offset Channel 3 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x2A 0x2B 0x2C Channel 4 Offset Channel 4 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x2D 0x2E 0x2F Channel 5 Offset Channel 5 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x30 0x31 0x32 Channel 6 Offset Channel 6 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x33 0x34 0x35 Channel 7 Offset Channel 7 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW

GAIN REGISTERS
Each ADC channel has an associated gain coefficient. The coefficient is stored in three single-byte registers split up as MSB, MID, and LSB.
Each of the gain registers are factory programmed. Nominally, this gain is around the value 0x555555 (for an ADC channel). The user may
overwrite the gain register setting. However, after a reset or power cycle, the gain register values revert to the hard coded programmed factory
setting.

Table 57. Per Channel 24-Bit Gain Registers, 3 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB
Address Reset
MSB Mid LSB Name Description MSB Mid LSB Access
0x36 0x37 0x38 Channel 0 Gain Channel 0 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x39 0x3A 0x3B Channel 1 Gain Channel 1 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW

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AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 57. Per Channel 24-Bit Gain Registers, 3 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB (Continued)
Address Reset
MSB Mid LSB Name Description MSB Mid LSB Access
0x3C 0x3D 0x3E Channel 2 Gain Channel 2 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x3F 0x40 0x41 Channel 3 Gain Channel 3 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x42 0x43 0x44 Channel 4 Gain Channel 4 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x45 0x46 0x47 Channel 5 Gain Channel 5 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x48 0x49 0x4A Channel 6 Gain Channel 6 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x4B 0x4C 0x4D Channel 7 Gain Channel 7 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW

SYNC PHASE OFFSET REGISTERS

The AD7768 has one synchronization signal for all channels. The sync phase offset register allows the user to vary the phase delay on each of
the channels relative to the synchronization edge received on the SYNC_IN pin. See the Sync Phase Offset Adjustment section for details on
the use of this function.

Table 58. Per Channel 8-Bit Sync Phase Offset Registers

Address Name Description Reset Access
0x4E Channel 0 sync offset Channel 0 sync phase offset register 0x00 RW
0x4F Channel 1 sync offset Channel 1 sync phase offset register 0x00 RW
0x50 Channel 2 sync offset Channel 2 sync phase offset register 0x00 RW
0x51 Channel 3 sync offset Channel 3 sync phase offset register 0x00 RW
0x52 Channel 4 sync offset Channel 4 sync phase offset register 0x00 RW
0x53 Channel 5 sync offset Channel 5 sync phase offset register 0x00 RW
0x54 Channel 6 sync offset Channel 6 sync phase offset register 0x00 RW
0x55 Channel 7 sync offset Channel 7 sync phase offset register 0x00 RW

ADC DIAGNOSTIC RECEIVE SELECT REGISTER

Address: 0x56, Reset: 0x00, Name: Diagnostic Receiver
The AD7768 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can be
converted to verify the correct operation of the ADC channel. This register enables the diagnostic. Enable the receive for each channel and set
each bit in this register to 1. The diagnostic requires the analog input pins to be disconnected from external drive/sources to accurately measure
the internal nodes.
The ADC diagnostic feature depends on some features of the analog input precharge buffers. The user must ensure that the analog input
precharge buffers are enabled on the channels that are selected to receive the diagnostic voltages internally.

Table 59. Bit Descriptions for Diagnostic Receiver

Bits Bit Name Settings Description Reset Access
7 CH7_RX Channel 7 0x0 RW
0 Not in use
1 Receive
6 CH6_RX Channel 6 0x0 RW
0 Not in use
1 Receive
5 CH5_RX Channel 5 0x0 RW
0 Not in use
1 Receive

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AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 59. Bit Descriptions for Diagnostic Receiver (Continued)

Bits Bit Name Settings Description Reset Access
4 CH4_RX Channel 4 0x0 RW
0 Not in use
1 Receive
3 CH3_RX Channel 3 0x0 RW
0 Not in use
1 Receive
2 CH2_RX Channel 2 0x0 RW
0 Not in use
1 Receive
1 CH1_RX Channel 1 0x0 RW
0 Not in use
1 Receive
0 CH0_RX Channel 0 0x0 RW
0 Not in use
1 Receive

ADC DIAGNOSTIC CONTROL REGISTER

Address: 0x57, Reset: 0x00, Name: Diagnostic Mux Control
The AD7768 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can be
converted to verify the correct operation of the ADC channel. This register controls the voltage that is applied to each of the ADC channels for
the diagnostic. There are three input voltage options that the user can select. The voltage selected is mapped to the channels based on which
mode (Mode A or Mode B) they belong to, which is set according to the channel mode select register (Register 0x03).
Set Bits[7:0] to 1 in the ADC diagnostic receive select register, then select the voltage check desired for the channels on Mode A and the
channels on Mode B through Bits[2:0] and Bits[6:4], respectively.

Table 60. Bit Descriptions for Diagnostic Mux Control

Bits Bit Name Settings Description Reset Access
[6:4] GRPB_SEL Mux B. 0x0 RW
000 Off.
011 Positive full-scale ADC check. A voltage close to positive full scale is applied internally to
the ADC channel.
100 Negative full-scale ADC check. A voltage close to negative (or minus) full scale is applied
internally to the ADC channel.
101 Zero-scale ADC check. A voltage close to 0 V is applied internally to the ADC channel.
[2:0] GRPA_SEL Mux A. 0x0 RW
000 Off.
011 Positive full-scale ADC check. A voltage close to positive full scale is applied internally to
the ADC channel.
100 Negative full-scale ADC check. A voltage close to negative (or minus) full scale is applied
internally to the ADC channel.
101 Zero-scale ADC check. A voltage close to 0 V is applied internally to the ADC channel.

MODULATOR DELAY CONTROL REGISTER

Address: 0x58, Reset: 0x02, Name: Modulator Delay Control

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AD7768 REGISTER MAP DETAILS (SPI CONTROL)

Table 61. Bit Descriptions for Modulator Delay Control

Bits Bit Name Settings Description Reset Access
[3:2] CLK_MOD_DEL_EN Enable Delayed Modulator Clock. 0x0 RW
00 Disable delayed clock for all channels.
01 Enable delayed clock for Channel 0 to Channel 3 only on the AD7768.
10 Enable delayed clock for Channel 4 to Channel 7 only on AD7768.
11 Enable delayed clock for all channels.
[1:0] Reserved 10 Not a User Option. Must be set to 0x2. 0x2 RW

CHOPPING CONTROL REGISTER

Address: 0x59, Reset: 0x0A, Name: Chop Control

Table 62. Bit Descriptions for Chop Control

Bits Bit Name Settings Description Reset Access
[3:2] GRPA_CHOP Group A Chopping 0x2 RW
01 Chop at fMOD/8
10 Chop at fMOD/32
[1:0] GRPB_CHOP Group B Chopping 0x2 RW
01 Chop at fMOD/8
10 Chop at fMOD/32

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

AD7768-4 REGISTER MAP

Table 63. Detailed AD7768-4 Register Map
Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x00 Channel Standby Unused CH_3 CH_2 CH_1 CH_0 0x00 RW
0x01 Channel Mode A Unused FILTER_ DEC_RATE_A 0x0D RW
TYPE_A
0x02 Channel Mode B Unused FILTER_ DEC_RATE_B 0x0D RW
TYPE_B
0x03 Channel Mode Reserved CH_3_ CH_2_ CH_3_ CH_2_ CH_1_ CH_0_ 0x00 RW
Select MODE MODE MDE_EN MDE_EN MODE MODE
0x04 POWER_MODE SLEEP_ Unused POWER_MODE LVDS_ Unused MCLK_DIV 0x00 RW
MODE ENABLE
0x05 General Unused CLK_QUAL_ RETIME_ VCM_PD Reserved Unused VCM_VSEL 0x08 RW
DIS
Configuration EN
0x06 Data Control SPI_SYNC Unused SINGLE_ Unused SPI_RESET 0x80 RW
SHOT_EN
0x07 Interface Unused CRC_SELECT DCLK_DIV 0x0 RW
Configuration
0x08 BIST Control Unused RAM_BIST_ 0x0 RW
START
0x09 Device Status Unused CHIP_ERROR NO_CLOCK_ RAM_BIST_ RAM_BIST_ 0x0 R
ERROR PASS RUNNING
0x0A Revision ID REVISION_ID 0x06 R
0x0B Reserved Reserved 0x00 R
0x0C Reserved Reserved 0x00 R
0x0D Reserved Reserved 0x00 R
0x0E GPIO Control UGPIO_ Unused GPIOE4_ GPIOE3_ GPIOE2_ GPIOE1_ GPIO0_ 0x00 RW
ENABLE FILTER MODE3 MODE2 MODE1 MODE0
0x0F GPIO Write Data Unused GPIO4_WRITE GPIO3_WRITE GPIO2_WRITE GPIO1_WRITE GPIO0_ 0x00 RW
WRITE
0x10 GPIO Read Data Unused GPIO4_READ GPIO3_READ GPIO2_READ GPIO1_READ GPIO0_ 0x00 R
READ
0x11 Precharge Reserved CH1_ CH1_ CH0_ CH0_ 0xFF RW
Buffer 1 PREBUF_ PREBUF_ PREBUF_ PREBUF_
NEG_EN POS_EN NEG_EN POS_EN
0x12 Precharge Reserved CH3_ CH3_ CH2_ CH2_ 0xFF RW
Buffer 2 PREBUF_ PREBUF_ PREBUF_ PREBUF_
NEG_EN POS_EN NEG_EN POS_EN
0x13 Positive Reserved CH3_ CH2_ Reserved CH1_ CH0_ 0x00 RW
Reference REFP_ REFP_ REFP_ REFP_
Precharge BUF BUF BUF BUF
Buffer
0x14 Negative Reserved CH3_ CH2_ Reserved CH1_ CH0_ 0x00 RW
Reference REFN_ REFN_ REFN_ REFN_
Precharge BUF BUF BUF BUF
Buffer
0x1E Channel 0 Offset CH0_OFFSET_MSB 0x00 RW

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 63. Detailed AD7768-4 Register Map (Continued)

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x1F CH0_OFFSET_MID
0x20 CH0_OFFSET_LSB
0x21 Channel 1 Offset CH1_OFFSET_MSB 0x00 RW
0x22 CH1_OFFSET_MID
0x23 CH1_OFFSET_LSB
0x24 Reserved Reserved 0x00 RW
0x25 Reserved
0x26 Reserved
0x27 Reserved Reserved 0x00 RW
0x28 Reserved
0x29 Reserved
0x2A Channel 2 Offset CH2_OFFSET_MSB 0x00 RW
0x2B CH2_OFFSET_MID
0x2C CH2_OFFSET_LSB
0x2D Channel 3 Offset CH3_OFFSET_MSB 0x00 RW
0x2E CH3_OFFSET_MID
0x2F CH3_OFFSET_LSB
0x30 Reserved Reserved 0x00 RW
0x31 Reserved
0x32 Reserved
0x33 Reserved Reserved 0x00 RW
0x34 Reserved
0x35 Reserved
0x36 Channel 0 Gain CH0_GAIN_MSB 0xXX RW
0x37 CH0_GAIN_MID
0x38 CH0_GAIN_LSB
0x39 Channel 1 Gain CH1_GAIN_MSB 0xXX RW
0x3A CH1_GAIN_MID
0x3B CH1_GAIN_LSB
0x3C Reserved Reserved 0xXX RW
0x3D Reserved
0x3E Reserved
0x3F Reserved Reserved 0xXX RW
0x40 Reserved
0x41 Reserved
0x42 Channel 2 Gain CH2_GAIN_MSB 0xXX RW
0x43 CH2_GAIN_MID
0x44 CH2_GAIN_LSB
0x45 Channel 3 Gain CH3_GAIN_MSB 0xXX RW
0x46 CH3_GAIN_MID
0x47 CH3_GAIN_LSB
0x48 Reserved Reserved 0xXX RW
0x49 Reserved

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 63. Detailed AD7768-4 Register Map (Continued)

Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x4A Reserved
0x4B Reserved Reserved 0xXX RW
0x4C Reserved
0x4D Reserved
0x4E Channel 0 Sync CH0_SYNC_OFFSET 0x00 RW
Offset
0x4F Channel 1 Sync CH1_SYNC_OFFSET 0x00 RW
Offset
0x50 Reserved Reserved 0x00 RW
0x51 Reserved Reserved 0x00 RW
0x52 Channel 2 Sync CH2_SYNC_OFFSET 0x00 RW
Offset
0x53 Channel 3 Sync CH3_SYNC_OFFSET 0x00 RW
Offset
0x54 Reserved Reserved 0x00 RW
0x55 Reserved Reserved 0x00 RW
0x56 Diagnostic Reserved CH3_RX CH2_RX Reserved CH1_RX CH0_RX 0x00 RW
Receiver
0x57 Diagnostic Mux Unused GRPB_SEL Unused GRPA_SEL 0x00 RW
Control
0x58 Modulator Delay Unused CLK_MOD_DEL_EN Reserved 0x02 RW
Control
0x59 Chop Control Unused GRPA_CHOP GRPB_CHOP 0x0A RW

CHANNEL STANDBY REGISTER

Address: 0x00, Reset: 0x00, Name: Channel Standby
Each of the ADC channels can be put into standby mode independently by setting the appropriate bit in the channel standby register. When a
channel is in standby mode, its position in the data output stream is held. The 8-bit header is all zeros, as is the conversion result output of 24
zeros.
The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also
disabled for maximum power savings. Channel 0 must be enabled while VCM is being used externally to the AD7768-4.
The crystal excitation circuitry is associated with the Channel 2 circuitry. If Channel 2 is put into standby mode, the crystal circuitry is also
disabled for maximum power savings. Channel 2 must be enabled while the external crystal is used on the AD7768-4.

Table 64. Bit Descriptions for Channel Standby

Bits Bit Name Settings Description Reset Access
3 CH_3 Channel 3 0x0 RW
0 Enabled
1 Standby
2 CH_2 Channel 2 0x0 RW
0 Enabled
1 Standby
1 CH_1 Channel 1 0x0 RW
0 Enabled

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 64. Bit Descriptions for Channel Standby (Continued)

Bits Bit Name Settings Description Reset Access
1 Standby
0 CH_0 Channel 0 0x0 RW
0 Enabled
1 Standby

CHANNEL MODE A REGISTER

Address: 0x01, Reset: 0x0D, Name: Channel Mode A
Two mode options are available on the AD7768-4 ADCs. The channel modes are defined by the contents of the Channel Mode A and Channel
Mode B registers. Each mode is then mapped as desired to the required ADC channel. Mode A and Mode B allow different filter types and
decimation rates to be selected and mapped to any of the ADC channels.
When different decimation rates are selected, the AD7768-4 output a data ready signal at the fastest selected decimation rate. Any channel that
runs at a lower output data rate is updated only at that slower rate. In between valid result data, the data for that channel is set to zero and the
repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the ADC Conversion Output: Header and
Data section).

Table 65. Bit Descriptions for Channel Mode A

Bits Bit Name Settings Description Reset Access
3 FILTER_TYPE_A Filter Selection 0x1 RW
0 Wideband filter
1 Sinc5 filter
[2:0] DEC_RATE_A Decimation Rate Selection 0x5 RW
000 ×32
001 ×64
010 ×128
011 ×256
100 ×512
101 ×1024
110 ×1024
111 ×1024

CHANNEL MODE B REGISTER

Address: 0x02, Reset: 0x0D, Name: Channel Mode B

Table 66. Bit Descriptions for Channel Mode B

Bits Bit Name Settings Description Reset Access
3 FILTER_TYPE_B Filter Selection 0x1 RW
0 Wideband filter
1 Sinc5 filter
[2:0] DEC_RATE_B Decimation Rate Selection 0x5 RW
000 ×32
001 ×64
010 ×128
011 ×256
100 ×512

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AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 66. Bit Descriptions for Channel Mode B (Continued)

Bits Bit Name Settings Description Reset Access
101 ×1024
110 ×1024
111 ×1024

CHANNEL MODE SELECT REGISTER

Address: 0x03, Reset: 0x00, Name: Channel Mode Select
This register selects the mapping of each ADC channel to either Channel Mode A or Channel Mode B.

Table 67. Bit Descriptions for Channel Mode Select

Bits Bit Name Settings Description Reset Access
5 CH_3_MODE Channel 3. 0x0 RW
0 Mode A.
1 Mode B.
4 CH_2_MODE Channel 2. 0x0 RW
0 Mode A.
1 Mode B.
3 CH_3_MDE_EN Channel 3 Mode Enable. This bit must be same as CH_3_MODE bit. 0x0 RW
0 Mode A.
1 Mode B.
2 CH_2_MDE_EN Channel 2 Mode Enable. This bit must be same as CH_2_MODE bit. 0x0 RW
0 Mode A.
1 Mode B.
1 CH_1_MODE Channel 1. 0x0 RW
0 Mode A.
1 Mode B.
0 CH_0_MODE Channel 0. 0x0 RW
0 Mode A.
1 Mode B.

POWER MODE SELECT REGISTER

Address: 0x04, Reset: 0x00, Name: POWER_MODE

Table 68. Bit Descriptions for POWER_MODE

Bits Bit Name Settings Description Reset Access
7 SLEEP_MODE In sleep mode, many of the digital clocks are disabled and all of the ADCs are disabled. The analog 0x0 RW
LDOs are not disabled.
The AD7768-4 SPI is live and is available to the user. Writing to this bit brings the AD7768-4 out of
sleep mode again.
0 Normal operation.
1 Sleep mode.
[5:4] POWER_MODE Power Mode. The power mode bits control the power mode setting for the bias currents used on all 0x0 RW
ADCs on the AD7768-4. The user can select the current consumption target to meet the application.
The power modes of fast, median, and low power give optimum performance when mapped to the
correct MCLK division setting. These power mode bits do not control the MCLK division of the ADCs.
See the MCLK_DIV bits for control of the division of the MCLK input.

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 68. Bit Descriptions for POWER_MODE (Continued)

Bits Bit Name Settings Description Reset Access
00 Low power.
10 Median.
11 Fast.
3 LVDS_ENABLE LVDS Input Clock. 0x0 RW
0 LVDS input clock disabled.
1 LVDS input clock enabled.
[1:0] MCLK_DIV MCLK Division. The MCLK division bits control the divided ratio between the MCLK applied at the 0x0 RW
input to the AD7768-4 and the clock used by each of the ADC modulators. The appropriate division
ratio depends on the following factors: power mode, decimation rate, and the base MCLK available
in the system. See the Clocking, Sampling Tree, and Power Scaling section for more information on
setting MCLK_DIV correctly.
00 MCLK/32: with a base MCLK of 32.768 MHz, set to MCLK/32 for low power mode.
10 MCLK/8: with a base MCLK of 32.768 MHz, set to MCLK/8 for median mode.
11 MCLK/4: with a base MCLK of 32.768 MHz, set to MCLK/4 for fast mode.

GENERAL DEVICE CONFIGURATION REGISTER

Address: 0x05, Reset: 0x08, Name: General Configuration

Table 69. Bit Descriptions for General Configuration

Bits Bit Name Settings Description Reset Access
6 CLK_QUAL_DIS Clock Qualification Disable Bit. Allows the user to disable the external clock source qualification. After 0x0 RW
reset, the external MCLK frequency is checked to be at least approximately 1.15 MHz, before being
accepted as valid and before the AD7768 hands control over to the external clock source. If this
qualification check fails, the NO_CLOCK_ERROR bit is set and the AD7768 continues to run using
the internal startup clock. Users can disable this qualification check to force the AD7768 to accept and
hand control over to an external clock source with a lower frequency. This bit functions as expected for
the recommended fMOD ranges as mentioned in Table 11.
0 Enabled. Clock qualification check is performed.
1 Disabled. Clock qualification check is not performed.
5 RETIME_EN SYNC_OUT Signal Retime Enable Bit. 0x0 RW
0 Disabled. Normal timing of SYNC_OUT.
1 Enabled. SYNC_OUT signal derived from alternate MCLK edge.
4 VCM_PD VCM Buffer Power-Down. 0x0 RW
0 Enabled: VCM buffer normal mode.
1 Powered down: VCM buffer powered down.
3 Reserved 1 Not a User Option. This bit must be set to 1. 0x1 RW
[1:0] VCM_VSEL VCM Voltage. These bits select the output voltage of the VCM pin. This voltage is derived from the 0x0 RW
AVDD1 supply and can be output as half of that AVDD1 voltage, or other fixed voltages, with respect
to AVSS. The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into
standby mode, the VCM voltage output is also disabled for maximum power savings. Channel 0 must
be enabled while VCM is being used externally to the AD7768-4.
00 (AVDD1 − AVSS)/2 V.
01 1.65 V.
10 2.5 V.
11 2.14 V.

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER

Address: 0x06, Reset: 0x80, Name: Data Control

Table 70. Bit Descriptions for Data Control

Bits Bit Name Settings Description Reset Access
7 SPI_SYNC Software Synchronization of the AD7768-4. This command has the same effect as sending a 0x1 RW
signal pulse to the START pin. To operate the SPI_SYNC, the user must write to this bit two
separate times. First, write a zero, putting SPI_SYNC low, and then write a 1 to set SPI_SYNC
logic high again. The SPI_SYNC command is recognized after the last rising edge of SCLK in the
SPI instruction where the SPI_SYNC bit is changed from low to high. The SPI_SYNC command is
then output synchronous to the AD7768-4 MCLK on the SYNC_OUT pin. The user must connect
the SYNC_OUT signal to the SYNC_IN pin on the PCB. The SYNC_OUT pin can also be routed
to the SYNC_IN pins of other AD7768-4 devices, allowing larger channel count simultaneous
sampling systems. As per any synchronization pulse seen by the SYNC_IN pin, the digital filters
of the AD7768 are reset. The full settling time of the filters must elapse before data is output on
the data interface. In a daisy-chained system ofAD7768-4 devices, two successive synchronization
pulses must be applied to guarantee that all ADCs are synchronized. Two synchronization pulses
are also required in a system of more than one AD7768-4 device sharing a single MCLK signal,
where the DRDY pin of only one device is used to detect new data.
0 Change to SPI_SYNC low.
1 Change to SPI_SYNC high.
4 SINGLE_SHOT_EN One Shot Mode. Enables one shot mode. In one shot mode, the AD7768-4 outputs a conversion 0x0 RW
result in response to a SYNC_IN rising edge.
0 Disabled.
1 Enabled.
[1:0] SPI_RESET Soft Reset. These bits allow a full device reset over the SPI port. Two successive commands must 0x0 RW
be received in the correct order to generate a reset: first, write 0x03 to the soft reset register, and
then write 0x02 to the soft reset register. This sequence causes the digital core to reset and all
registers return to their default values. Following a soft reset, if the SPI main sends a command to
the AD7768-4, the device responds on the next frame to that command with an output of 0x0E00.
00 No effect.
01 No effect.
10 Second reset command.
11 First reset command.

INTERFACE CONFIGURATION REGISTER

Address: 0x07, Reset: 0x00, Name: Interface Configuration

Table 71. Bit Descriptions for Interface Configuration

Bits Bit Name Settings Description Reset Access
[3:2] CRC_SELECT CRC Select. These bits allow the user to implement a CRC on the data interface. When selected, the 0x0 RW
CRC replaces the header every fourth or 16th output sample depending on the CRC option chosen. There
are two options for the CRC. Both use the same polynomial: x8 + x2 + x + 1. The options offer the user the
ability to reduce the duty cycle of the CRC calculation by performing it less often: in the case of having it
every 16th sample, or more often in the case of every fourth conversion. The CRC is calculated on a per
channel basis and it includes conversion data only.
00 No CRC. Status bits with every conversion.
01 Replace the header with CRC message every 4 samples.
10 Replace the header with CRC message every 16 samples.

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 71. Bit Descriptions for Interface Configuration (Continued)

Bits Bit Name Settings Description Reset Access
11 Replace the header with CRC message every 16 samples.
[1:0] DCLK_DIV DCLK Divider. These bits control division of the DCLK clock used to clock out conversion data on the 0x0 RW
DOUTx pins. The DCLK signal is derived from the MCLK applied to the AD7768-4. The DCLK divide
mode allows the user to optimize the DCLK output to fit the application. Optimizing the DCLK per
application depends on the requirements of the user. When the AD7768-4 is using the highest capacity
output on the fewest DOUTx pins, for example, running in decimate by 32 using the DOUT0 pin and
DOUT1 pin, the DCLK must equal the MCLK. Therefore, in this case, choosing the no division setting
is the only way the user can output all the data within the conversion period. There are other cases,
however, when the ADC may be running in fast mode with high decimation rates, or in median or low
power mode where the DCLK does not need to run at the same speed as MCLK. In these cases, the
DCLK divide allows the user to reduce the clock speed and makes routing and isolating such signals
easier.
00 Divide by 8.
01 Divide by 4.
10 Divide by 2.
11 No division.

DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER

Address: 0x08, Reset: 0x00, Name: BIST Control

Table 72. Bit Descriptions for BIST Control

Bits Bit Name Settings Description Reset Access
0 RAM_BIST_START RAM BIST. Filter RAM BIST is a built in self test of the RAM storage of the coefficients used by 0x0 RW
the digital filter. Normal ADC conversion is disrupted when this test is run. A synchronization pulse
is required after this test is complete to resume normal ADC operation. The test can be run at
intervals depending on user preference. The status and result of the RAM BIST is available in the
device status register. See the RAM_BIST_PASS and RAM_BIST_RUNNING bits in Table 73.
0 Off.
1 Begin RAM BIST.

STATUS REGISTER
Address: 0x09, Reset: 0x00, Name: Device Status

Table 73. Bit Descriptions for Device Status

Bits Bit Name Settings Description Reset Access
3 CHIP_ERROR Chip Error. Chip error is a global error flag that is output within the status byte of each ADC 0x0 R
conversion output. The following bits lead to the chip error bit being set to logic high: CRC
check on internally hard coded settings after power-up does not pass. XOR check on the
memory map does not pass (this check runs continuously in the background). Clock error is
detected on power-up.
0 No error present.
1 Error has occurred.
2 NO_CLOCK_ERROR External Clock Check. This bit indicates whether the externally applied MCLK is detected 0x0 R
correctly. If the MCLK is not applied correctly to the ADC at power-up, this bit is set and the
DCLK frequency is approximately 16 MHz. If this bit is set, the chip error bit is set to logic high
in the status bits of the data output headers, and the conversion results are output as all zeros
regardless of the analog input voltages applied to the ADC channels.
0 MCLK detected.

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 73. Bit Descriptions for Device Status (Continued)

Bits Bit Name Settings Description Reset Access
1 No MCLK detected.
1 RAM_BIST_PASS BIST Pass/Fail. RAM BIST result status. This bit indicates the result of the most recent RAM 0x0 R
BIST. The result is latched to this register and is only cleared by a device reset.
0 BIST failed or not run.
1 BIST passed.
0 RAM_BIST_RUNNING BIST Status. Reading back the value of this bit allows the user to poll when the BIST test has 0x0 R
finished.
0 BIST not running.
1 BIST running.

REVISION IDENTIFICATION REGISTER

Address: 0x0A, Reset: 0x06, Name: Revision ID

Table 74. Bit Descriptions for Revision ID

Bits Bit Name Description Reset Access
[7:0] REVISION_ID ASIC Revision. 8-bit ID for revision details. 0x06 R

GPIO CONTROL REGISTER

Address: 0x0E, Reset: 0x00, Name: GPIO Control

Table 75. Bit Descriptions for GPIO Control

Bits Bit Name Setting Description Reset Access
7 UGPIO_ENABLE User GPIO Enable. The GPIOx pins are dual-purpose and can be operated only when the device is 0x0 RW
in SPI control mode. By default, when the AD7768-4 are powered up in SPI control mode, the GPIOx
pins are disabled. This bit is a universal enable/disable for all GPIOx input/outputs. The direction of
each general-purpose pin is determined by Bits[4:0] of this register.
0 GPIO disabled.
1 GPIO enabled.
4 GPIOE4_FILTER GPIO4 Direction. This bit assigns the direction of GPIO4 as either an input or an output. For SPI 0x0 RW
control, GPIO4 maps to Pin 11, which is the FILTER/GPIO4 pin.
0 Input.
1 Output.
3 GPIOE3_MODE3 GPIO3 Direction. This bit assigns the direction of GPIO3 as either an input or an output. For SPI 0x0 RW
control, GPIO3 maps to Pin 15, which is the MODE3/GPIO3 pin.
0 Input.
1 Output.
2 GPIOE2_MODE2 GPIO2 Direction. This bit assigns the direction of GPIO2 as either an input or an output. For SPI 0x0 RW
control, GPIO2 maps to Pin 14, which is the MODE2/GPIO2 pin.
0 Input.
1 Output.
1 GPIOE1_MODE1 GPIO1 Direction. This bit assigns the direction of GPIO1 as either an input or an output. For SPI 0x0 RW
control, GPIO1 maps to Pin 13, which is the MODE1/GPIO1 pin.
0 Input.
1 Output.
0 GPIO0_MODE0 GPIO0 Direction. This bit assigns the direction of GPIO0 as either an input or an output. For SPI 0x0 RW
control, GPIO0 maps to Pin 12, which is the MODE0/GPIO0 pin.

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 75. Bit Descriptions for GPIO Control (Continued)

Bits Bit Name Setting Description Reset Access
0 Input.
1 Output.

GPIO WRITE DATA REGISTER

Address: 0x0F, Reset: 0x00, Name: GPIO Write Data
This register writes the values to be set on each of the general-purpose pins when selected as general-purpose outputs. Each bit, from
Bits[4:0], maps directly to the GPIOx pins.

Table 76. Bit Descriptions for GPIO Write Data

Bits Bit Name Description Reset Access
4 GPIO4_WRITE GPIO4/FILTER pin. 0x0 RW
3 GPIO3_WRITE GPIO3/MODE3 pin. 0x0 RW
2 GPIO2_WRITE GPIO2/MODE2 pin. 0x0 RW
1 GPIO1_WRITE GPIO1/MODE1 pin. 0x0 RW
0 GPIO0_WRITE GPIO0/MODE0 pin. 0x0 RW

GPIO READ DATA REGISTER

Address: 0x10, Reset: 0x00, Name: GPIO Read Data
This register reads back the value of the logic input level at the general-purpose pins when selected to operate as general-purpose inputs. Each
bit, from Bits[4:0], maps directly to the GPIO0 pin to GPIO4 pin.

Table 77. Bit Descriptions for GPIO Read Data

Bits Bit Name Description Reset Access
4 GPIO4_READ GPIO4/FILTER pin. 0x0 R
3 GPIO3_READ GPIO3/MODE3 pin. 0x0 R
2 GPIO2_READ GPIO2/MODE2 pin. 0x0 R
1 GPIO1_READ GPIO1/MODE1 pin. 0x0 R
0 GPIO0_READ GPIO0/MODE0 pin. 0x00 R

ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1

Address: 0x11, Reset: 0xFF, Name: Precharge Buffer 1
This register turns on or off the precharge buffers on the analog inputs. When writing to this register, the user must write the inverse of the
required bit settings. For example, to clear Bit 1 of this register, the user must write 0x01 to the register. This clears Bit 1 and sets all other bits.
If the user reads the register again after writing 0x01, the data read is 0xFE, as required.

Table 78. Bit Descriptions for Precharge Buffer 1

Bits Bit Name Settings Description Reset
3 CH1_PREBUF_NEG_EN 0 Off 0x1
1 On
2 CH1_PREBUF_POS_EN 0 Off 0x1
1 On
1 CH0_PREBUF_NEG_EN 0 Off 0x1
1 On
0 CH0_PREBUF_POS_EN 0 Off 0x1

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 78. Bit Descriptions for Precharge Buffer 1 (Continued)

Bits Bit Name Settings Description Reset
1 On

ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3

Address: 0x12, Reset: 0xFF, Name: Precharge Buffer 2
This register turns on or off the precharge buffers on the analog inputs. When writing to this register, the user must write the inverse of the
required bit settings. For example, to clear Bit 1 of this register, the user must write 0x01 to the register. This clears Bit 1 and sets all other bits.
If the user reads the register again after writing 0x01, the data read is 0xFE, as required.

Table 79. Bit Descriptions for Precharge Buffer 2

Bits Bit Name Settings Description Reset
3 CH3_PREBUF_NEG_EN 0 Off 0x1
1 On
2 CH3_PREBUF_POS_EN 0 Off 0x1
1 On
1 CH2_PREBUF_NEG_EN 0 Off 0x1
1 On
0 CH2_PREBUF_POS_EN 0 Off 0x1
1 On

POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER

Address: 0x13, Reset: 0x00, Name: Positive Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference positive input to each of the ADCs from Channel 0 to Channel 3.

Table 80. Bit Descriptions for Positive Reference Precharge Buffer

Bits Bit Name Settings Description Reset
5 CH3_REFP_BUF 0 Off 0x0
1 On
4 CH2_REFP_BUF 0 Off 0x0
1 On
1 CH1_REFP_BUF 0 Off 0x0
1 On
0 CH0_REFP_BUF 0 Off 0x0
1 On

NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER

Address: 0x14, Reset: 0x00, Name: Negative Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference negative input to each of the ADCs from Channel 0 to Channel 3.

Table 81. Bit Descriptions for Negative Reference Precharge Buffer

Bits Bit Name Settings Description Reset
5 CH3_REFN_BUF 0 Off 0x0
1 On
4 CH2_REFN_BUF 0 Off 0x0
1 On

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 81. Bit Descriptions for Negative Reference Precharge Buffer (Continued)
Bits Bit Name Settings Description Reset
1 CH1_REFN_BUF 0 Off 0x0
1 On
0 CH0_REFN_BUF 0 Off 0x0
1 On

OFFSET REGISTERS
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_OFFSET_LSB registers in addresses 0x1E to 0x35 form 24-bit, signed twos
complement registers for channel offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset
register adjustment changes the digital output by −4/3 LSBs. For example, changing the offset register from 0 to 100 changes the digital output
by −133 LSBs. As offset adjustment occurs before gain adjustment, the ratio of 4/3 changes linearly with gain adjustment via register addresses
0x36 to 0x4D. After a reset or power cycle, the register values revert to the default factory setting.

Table 82. Per Channel 24-Bit Offset Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB
Address Reset
MSB Mid LSB Name Description MSB Mid LSB Access
0x1E 0x1F 0x20 Channel 0 Offset Channel 0 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x21 0x22 0x23 Channel 1 Offset Channel 1 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x2A 0x2B 0x2C Channel 2 Offset Channel 2 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x2D 0x2E 0x2F Channel 3 Offset Channel 3 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW

GAIN REGISTERS
Each ADC channel has an associated gain coefficient. The coefficient is stored in three single-byte registers split up as MSB, MID, and LSB.
Each of the gain registers are factory programmed. Nominally, this gain is around the value 0x555555 (for an ADC channel). The user may
overwrite the gain register setting. However, after a reset or power cycle, the gain register values revert to the hard coded programmed factory
setting.

Table 83. Per Channel 24-Bit Gain Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB
Address Reset
MSB Mid LSB Name Description MSB Mid LSB Access
0x36 0x37 0x38 Channel 0 Gain Channel 0 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x39 0x3A 0x3B Channel 1 Gain Channel 1 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x42 0x43 0x44 Channel 2 Gain Channel 2 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x45 0x46 0x47 Channel 3 Gain Channel 3 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW

SYNC PHASE OFFSET REGISTERS

The AD7768-4 has one synchronization signal for all channels. The sync phase offset register allows the user to vary the phase delay on each
of the channels relative to the synchronization edge received on the SYNC_IN pin. See the Sync Phase Offset Adjustment section for details on
the use of this function.

Table 84. Per Channel 8-Bit Sync Phase Offset Registers

Address Name Description Reset Access
0x4E Channel 0 sync offset Channel 0 sync phase offset register 0x00 RW
0x4F Channel 1 sync offset Channel 1 sync phase offset register 0x00 RW
0x52 Channel 2 sync offset Channel 2 sync phase offset register 0x00 RW
0x53 Channel 3 sync offset Channel 3 sync phase offset register 0x00 RW

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

ADC DIAGNOSTIC RECEIVE SELECT REGISTER

Address: 0x56, Reset: 0x00, Name: Diagnostic Receiver
The AD7768-4 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can be
converted to verify the correct operation of the ADC channel. This register enables the diagnostic. Enable the receive for each channel and set
each bit in this register to 1. The diagnostic requires the analog input pins to be disconnected from external drive/sources to accurately measure
the internal nodes.
The ADC diagnostic feature depends on some features of the analog input precharge buffers. The user must ensure that the analog input
precharge buffers are enabled on the channels that are selected to receive the diagnostic voltages internally.

Table 85. Bit Descriptions for Diagnostic Receiver

Bits Bit Name Settings Description Reset Access
5 CH3_RX Channel 3 0x0 RW
0 Not in use
1 Receive
4 CH2_RX Channel 2 0x0 RW
0 Not in use
1 Receive
1 CH1_RX Channel 1 0x0 RW
0 Not in use
1 Receive
0 CH0_RX Channel 0 0x0 RW
0 Not in use
1 Receive

ADC DIAGNOSTIC CONTROL REGISTER

Address: 0x57, Reset: 0x00, Name: Diagnostic Mux Control
The AD7768-4 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can be
converted to verify the correct operation of the ADC channel. This register controls the voltage that is applied to each of the ADC channels for
the diagnostic. There are three input voltage options that the user can select. The voltage selected is mapped to the channels based on which
mode (Mode A or Mode B) they belong to, which is set according to the channel mode select register (Register 0x03).
Set Bits[7:0] to 1 in the ADC diagnostic receive select register, then select the voltage check desired for the channels on Mode A and the
channels on Mode B through Bits[2:0] and Bits[6:4], respectively.

Table 86. Bit Descriptions for Diagnostic Mux Control

Bits Bit Name Settings Description Reset Access
[6:4] GRPB_SEL Mux B. 0x0 RW
000 Off.
011 Positive full-scale ADC check. A voltage close to positive full scale is applied internally to the ADC channel.
100 Negative full-scale ADC check. A voltage close to negative (or minus) full scale is applied internally to the
ADC channel.
101 Zero-scale ADC check. A voltage close to 0 V is applied internally to the ADC channel.
[2:0] GRPA_SEL Mux A. 0x0 RW
000 Off.
011 Positive full-scale ADC check. A voltage close to positive full scale is applied internally to the ADC channel.
100 Negative full-scale ADC check. A voltage close to negative (or minus) full scale is applied internally to the
ADC channel.

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Data Sheet AD7768/AD7768-4
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)

Table 86. Bit Descriptions for Diagnostic Mux Control (Continued)

Bits Bit Name Settings Description Reset Access
101 Zero-scale ADC check. A voltage close to 0 V is applied internally to the ADC channel.

MODULATOR DELAY CONTROL REGISTER

Address: 0x58, Reset: 0x02, Name: Modulator Delay Control

Table 87. Bit Descriptions for Modulator Delay Control

Bits Bit Name Settings Description Reset Access
[3:2] CLK_MOD_DEL_EN Enable Delayed Modulator Clock. 0x0 RW
00 Disabled delayed clock for all channels.
01 Enable delayed clock for Channel 0 and Channel 1 only on the AD7768-4.
10 Enable delayed clock for Channel 2 and Channel 3 only on the AD7768-4.
11 Enable delayed clock for all channels.
[1:0] Reserved 10 Not a User Option. Must be set to 0x2. 0x2 RW

CHOPPING CONTROL REGISTER

Address: 0x59, Reset: 0x0A, Name: Chop Control

Table 88. Bit Descriptions for Chop Control

Bits Bit Name Settings Description Reset Access
[3:2] GRPA_CHOP Group A Chopping 0x2 RW
01 Chop at fMOD/8
10 Chop at fMOD/32
[1:0] GRPB_CHOP Group B Chopping 0x2 RW
01 Chop at fMOD/8
10 Chop at fMOD/32

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Data Sheet AD7768/AD7768-4
OUTLINE DIMENSIONS

Package Drawing (Option) Package Type Package Description

ST-64-2 LQFP 64-Lead Low Profile Quad Flat Package

For the latest package outline information and land patterns (footprints), go to Package Index.
Updated: July 14, 2022
ORDERING GUIDE
Model1 Temperature Range Package Description Packing Quantity Package Option
AD7768-4BSTZ −40°C to +105°C 64-Lead LQFP (10 mm × 10 mm) Tray, 160 ST-64-2
AD7768-4BSTZ-RL −40°C to +105°C 64-Lead LQFP (10 mm × 10 mm) Reel, 1500 ST-64-2
AD7768-4BSTZ-RL7 −40°C to +105°C 64-Lead LQFP (10 mm × 10 mm) Reel, 300 ST-64-2
AD7768BSTZ −40°C to +105°C 64-Lead LQFP (10 mm × 10 mm) Tray, 160 ST-64-2
AD7768BSTZ-RL −40°C to +105°C 64-Lead LQFP (10 mm × 10 mm) Reel, 1500 ST-64-2
AD7768BSTZ-RL7 −40°C to +105°C 64-Lead LQFP (10 mm × 10 mm) Reel, 300 ST-64-2
1 Z = RoHS Compliant Part.

EVALUATION BOARDS

Model1 Description
EVAL-AD7768FMCZ Evaluation Board
EVAL-AD7768-4FMCZ AD7768-4 Evaluation Board
EVAL-SDP-CH1Z Controller Board

1 Z = RoHS Compliant Part.

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registered trademarks are the property of their respective owners.
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