International Journal of Industrial Electronics and Electrical Engineering, ISSN: 2347-6982 Volume-2, Issue-11, Nov.

-2014

DESIGN AND IMPLEMENTATION OF 64 BIT MULTIPLIER BY

USING CARRY SAVE ADDER
1
MOHAMMAD JAVEED, 2GELLA RAVIKANTH
1
Project Lead, ORBIT Technology Research Pvt. Ltd. ,
2
Associate Professor, Laqshya Inst. Of technology and science
E-mail: [email protected], [email protected]

Abstract- In this paper we have shown the design and implementation of 64 bit multiplier by using multi bit flip flop shift
register andcarry save adder . In arithmetic operations addition and multiplication are having a major role.When the number
of bits increases, the complexity of adder circuits increases and speed performance decreases.Our proposed system uses two
64 bit numbers and multiply to form a 128 bit number, which is for larger applications. Proposed carry save adder based
multiplier, On comparing with the carry look ahead adder based 64 bit multiplier, the results showing time (speed)decreased
by93.5% approximately and when comparing with the carry select adder based 64 bit multipliertime (speed) decreased up to
88%. The code is written in VHDL and synthesizedthe design in Xilinx ISE 10.1Version and hardware implementation is in
Spartan 3E FPGA family.

Keywords- Shift Register, Single Bit Flip Flop, Multi Bit Flip Flop, Carry Look Ahead Adder, Carry Select Adder, Carry
Save Adder, VLSI, VHDL, Spartan.

I. INRODUCTION multiplication algorithm with multi bit flip flop shift

register. Section VI illustrates the simulation results
A digital designer has to concentrate on many criteria and section VII concludes the paper.
like Circuit speed, power consumption, area and
cost.While designing the digital circuits, the II. CARRY LOOK AHEAD ADDER
fundamental arithmetic operations like addition and
multiplication are the main optimizations. Our design Carry look ahead adder generates carries parallel at a
concentrates on multiplication of binary numbers for time. For this we should have the extra circuitry.
larger applications. For the multiplication operation, Because of these extra circuits and storage elements
adding as well as shifting of bits is necessary. Carry Look Ahead adder needs more area and the
Considering these two operations, we have designed a power using by the whole circuit is high. The below
64 bit multiplier by using carry save adder for equations describes the pattern how a carry look
addition and multi bit flip flop based shift register for ahead generates the carries. Figure 1 shows the block
shifting of bits. In this paper we have shown the diagram for carry look ahead adder.
comparison among the adders for multiplication
based on the time. On comparison with carry look
ahead adder (CLAA) and carry select adder (CSLA),
carry save adder (CSA) based multiplier is less
complex and results have shown that CSA based
multiplier is very faster than the other two
multipliers. A shift register isvery important digital Figure 1. Carry look ahead adder
building block. It has a large amount of applications.
Registers are often used to momentarily store binary Let Gi be the generating the function and Pi be the
information appearing at the output. Shift registers propagating function then we can write the carries as
are the logic types which are used basically for the Ci+1=A.B+ (A xor B).Ci, Where (1)
storage and transfer of digital data. The basic storage Gi = A.B (2)
elements are the flip flops. The most of the registers Pi= (A xor B).Ci (3)
use D flip flops due to its simplicity.
From the equations (1) (2) (3), we can understand that
Basically a flip flop stores a single bit data. In our the sum of adder circuit does not depend on the carry
proposed design the flip flop stores a multi bit data. generation so we can generate all the carries at a time
By using the multi bit flip flops, we have shown a as
shift registerwhich is serial in serial out (SISO). C1= A0.B0+(A0 xor B0). C0
Finally we have designed a 64 bit multiplier by using C2=A1.B1+(A1 xor B1). C1
carry save adder and multi bit flip flop shift register. C3=A2.B2+(A2 xor B2). C2 ………………..
This paper is scheduled as first it discusses and C64=A63.B63+(A63 xor B63).C63
compares the about the different adders in sections II, The sum of the adder is written as
III and IV. After that in section V it shows the SUM= A xor B xor C

Design And Implementation of 64 Bit Multiplier By Using Carry Save Adder

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International Journal of Industrial Electronics and Electrical Engineering, ISSN: 2347-6982 Volume-2, Issue-11, Nov.-2014

III. CARRY SELECT ADDER V. MULTIPLICATION ALGORITHM

Carry select adder is a different from the carry look Let the product size be 128.Multiplier and
ahead adder, in which we select the carry as 0 once multiplicand are 64 bit.Clear the most significant half
and again select the carry as 1. After that, we perform of the product register. Store the multiplier in the
the addition operation for the both cases and give least significant half of the product register. The
these outputs to the 2:1 multiplexer. Finally we repeat the following steps 64 times.
receive the single output. So, we do not need to wait  If the least significant bit of the product
for previous addition result to the next step [3]. The register is “1” then add the multiplicand to
figure 2 represents the carry select adder. The the most significant half of the product
multiplexer output equations for sum and carriesare register.
Sum function is as follows  Shift the content of the product register one
If carry =1 then, bit to the right (ignore the shifted-out bit.)
SUM0= A0 xor B0 xor Carry  Shift-in the carry bit into the most
If carry =0 then, significant bit of the product register. The
SUM0=A0 xor B0 multiplication algorithm shows in figure 4.

Figure 2. Carry select adder

Figure 4. Multiplication algorithm
These two SUMs will be given to the multiplexer. Here the important issue is to shift the bits. We are
Here, to perform the operation need not to wait for proposing a shift register by using the multi bit flip
the previous stage carry. So, the time taken to flops. Generally for the storage of bits the memory
perform the addition operation decreases. We can see elements are latches and flip flops. The flip flop
a significant improvement in time. casually stores a single bit value. Here in our
proposed system the flip flop stores the multi bits.
IV. CARRY SAVE ADDER Finally we designed a shift register by using the multi
bit two flip flops. The diagram for the shift register,
The carry save addition further can decrease the serial in serial out is shown in the figure 5. The edge
timing performance of the addition. In this carry save triggering D flip flop output takes the input value
addition the carry is neglected first and only sum will when clock goes high in positive edge triggering and
be considered [4]. Let us see one example for the takes the input value when clock goes low in negative
carry save addition with two numbers A and B edge triggering. The multi bit flip flop works under
A: 3456 the technique of merging the clock pulses [8]. The
B: 4365 timing diagram for multi bit flip flop is shown in
Sum: 7711 figure 6 which is having the operation for negative
The carries generated by the addition are neglected edge triggering D flip flop as…
here are 0 0 1 1. Now these carries can be shifted to  Initially Q1 and Q2 are assumed to be high, D1
the left and add to the sum, as and D2 are low, and clock (CLK) is low.
Shifted Carries: 0 1 1
 At the negative going edge of the first clock
Sum: 7711
pulse, D1 and D2 are low, so, Q1 and Q2 are
Total sum: 7821
also low.
Carry save adder does not have more complexity as
carry select adder and carry look ahead adder. So, we  At the second negative going pulse of clock, D1
have implemented 64 bit multiplier by using the carry and D2 are high, so, Q1 and Q2 are also high.
save adder. Even though it needs large amount of  At the negative transition edge of the second
registers to store the carries separately, this can be clock pulse, D is high and Q1 and Q2 are high.
advantageous in it’s speed performance. The main  And the same will continue…
advantage of carry save addition is it can add three
bits at a time. But in our design we are not
considering multi operand redundant addition. The
third bit is considering as zero. Figure 3 represents Figure 5. Multi bit flip flop shift register
the carry save adder block diagram.

Figure 3. Carry save adder Figure 6. Timing diagram for multi bit flip flop

Design And Implementation of 64 Bit Multiplier By Using Carry Save Adder

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International Journal of Industrial Electronics and Electrical Engineering, ISSN: 2347-6982 Volume-2, Issue-11, Nov.-2014

VI. SIMULATION RESULTS respectively by using multi bit flip flopshift register.
Table 1 shows the clear timing details for the
The analysis of 64 bit multiplier designed based on multiplier. Fig 10, Fig 11, Fig 12 shows the wave
carry save adder by using multi bit flip flop shift forms generated for the three different multipliers.
register. The design is simulated in Xilinx ISE 10.1 Fig 13 (a) and (b) shows the RTL schematics for the
version.The results are shown in the following carry save adder based 64 bit multiplier by using
figures. Fig. 7, Fig., 8, Fig 9 are the timing details of multi bit flip flop shift register. Proposed design
the multiplier based on CLAA, CSLA and CSA implemented on Spartan 3e tool.

CLA CSL CSA

A A
TIM 37.27 20.80 2.37
E 1 4 9
(ns)
Figure 7. Timing performance of carry
look ahead adder based multiplier

Figure 12. Wave form generation for

carry save adder based multiplier

Figure 8. Timing performance of carry

select adder based multiplier Figure 10. Wave form generation for
carry look ahead adder based multiplier

(a)

(b)
Figure 13. RTL views for carry save
adder based multiplier
Figure 9. Timing performance of carry Figure 11. Wave form generation for
save adder based multiplier carry select adder based multiplier

TABLE I TIMING ANALYSIS

CONCLUSION International Journal of Soft Computing and Engineering
(IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, Jan- 2013
A design and implementation of 64 bit multiplier with [3] DeepthiObul Reddy, P.RameshYadav“Carry Select Adder
different adders have shown in this paper. VHDL with Low Power and Area Efficiency”.International Journal
of Engineering Research and Development, Volume 3, Issue
language is used to simulate and synthesize the 3 (August 2012), PP. 29-35.
multiplier. By using the carry save adder improved
the overall speed of the design. We have shown that [4] D.R Lutz, D.N. JayaSimha, “The power of carry save
addition”, Department of computer and Information
proposed multiplier increased its speed by 93.5 % Science, The Ohio State University, 1991.
when compared with the CLAA and 88% when
[5] HasanKrad* and AwsYousif** “Design and Implementation
compared with CSLA. A fast adder can significantly of a Fast Unsigned 32-bit Multiplier Using VHDL” Qatar
improve the performance of the multiplier. Over all University/Department of Computer Science &
the speed performance of the multiplier based on Engineering, Doha, Qatar.
carry save adder is high. Even though the area [6] W. Stallings, Computer Organization and Architecture
increases by using the carry save adder, it is Designing for Peljormance, 71h ed., Prentice Hall, Pearson
negligible when compared to the speed performance. Education International, USA, 2006, ISBN: 0-13-185644-8.
[7] V.Vijayalakshmil, R.Seshadd, Dr.S.Ramakrishnan3 “Design
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Design And Implementation of 64 Bit Multiplier By Using Carry Save Adder

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