Low Cost, Dual, High Current Output

Line Driver with Shutdown

ADA4311-1
FEATURES PIN CONFIGURATION
High speed ADA4311-1
−3 dB bandwidth: 310 MHz, G = +5, RLOAD = 50 Ω +VS 1 10 OUT B

NC 2 9 –IN B
Slew rate: 1050 V/μs, RLOAD = 50 Ω
OUT A 3 8 +IN B
Wide output swing
–IN A 4 7 PD1
20.6 V p-p differential, RLOAD of 100 Ω from 12 V supply +IN A 5 6 PD0

06940-001
High output current
NC = NO CONNECT
Low distortion
Figure 1. Thermally Enhanced, 10-Lead MINI_SO_EP
−98 dBc typical at 1 MHz, VOUT = 2 V p-p, G = +5, RLOAD = 100 Ω
−72 dBc typical at 10 MHz, VOUT = 2 V p-p, G = +5, RLOAD = 100 Ω TYPICAL APPLICATION
Power management and shutdown
Control inputs CMOS level compatible 1/2

Shutdown quiescent current: 1 mA/amplifier ADA4311-1

Selectable quiescent current: 1 mA to 11.8 mA/amplifier VMID*

APPLICATIONS
1/2
Home networking line drivers
ADA4311-1
Twisted pair line drivers

06940-002
VCC – GND
Power line communications (PLC) *VMID = 2
Video line drivers Figure 2. Typical PLC Driver Application
ARB line drivers
I/Q channel amplifiers

GENERAL DESCRIPTION
The ADA4311-1 is comprised of two high speed, current The ADA4311-1 is available in a thermally enhanced, 10-lead
feedback operational amplifiers. The high output current, high MSOP with an exposed paddle for improved thermal conduction.
bandwidth, and fast slew rate make it an excellent choice for The ADA4311-1 is rated to work in the extended industrial
broadband applications requiring high linearity performance temperature range of −40°C to +85°C.
while driving low impedance loads.
The ADA4311-1 incorporates a power management function
that provides shutdown capabilities and the ability to optimize
the quiescent current of the amplifiers. The CMOS-compatible,
power-down control pins (PD1 and PD0) enable the ADA4311-1
to operate in four different modes: full power, medium power,
low power, and complete power-down. In power-down mode, the
quiescent current drops to only 1.0 mA/amplifier, while the outputs
go to a high impedance state.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
ADA4311-1

TABLE OF CONTENTS
Features .............................................................................................. 1 Theory of Operation ...................................................................... 10
Applications....................................................................................... 1 Application Information................................................................ 11
Pin Configuration............................................................................. 1 Feedback Resistor Selection...................................................... 11
Typical Application........................................................................... 1 Power Control Modes of Operation ........................................ 11
General Description ......................................................................... 1 Exposed Thermal Pad Connections ........................................ 11
Revision History ............................................................................... 2 Powerline Application ............................................................... 11
Specifications..................................................................................... 3 Board Layout............................................................................... 12
Absolute Maximum Ratings............................................................ 5 Power Supply Bypassing ............................................................ 12
Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 13
ESD Caution.................................................................................. 5 Ordering Guide .......................................................................... 13
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7

REVISION HISTORY
8/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 16
 ADA4311-1

SPECIFICATIONS
VS = 12 V, RF = 499 Ω (@ TA = 25°C, G = +5, RL = 100 Ω to VS/2), unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT = 0.1 V p-p, PD1 = 0, PD0 = 0, RLOAD = 50 Ω 310 MHz
VOUT = 0.1 V p-p, PD1 = 0, PD0 = 1, RLOAD = 50 Ω 220 MHz
VOUT = 0.1 V p-p, PD1 = 1, PD0 = 0, RLOAD = 50 Ω 140 MHz
Full Power Bandwidth VOUT = 10.2 V p-p, PD1 = 0, PD0 = 0, RLOAD = 50 Ω 12.9 MHz
Slew Rate VOUT = 2 V p-p, PD1 = 0, PD0 = 0 1050 V/μs
VOUT = 2 V p-p, PD1 = 0, PD0 = 1 1050 V/μs
VOUT = 2 V p-p, PD1 = 1, PD0 = 0 1000 V/μs
NOISE/DISTORTION PERFORMANCE
Differential Distortion (Worst fC = 1 MHz, VOUT = 2 V p-p
Harmonic)
PD1 = 0, PD0 = 0 −98 dBc
PD1 = 0, PD0 = 1 −95 dBc
PD1 = 1, PD0 = 0 −86 dBc
fC = 10 MHz, VOUT = 2 V p-p
PD1 = 0, PD0 = 0 −72 dBc
PD1 = 0, PD0 = 1 −63 dBc
PD1 = 1, PD0 = 0 −52 dBc
fC = 20 MHz, VOUT = 2 V p-p
PD1 = 0, PD0 = 0 −56 dBc
PD1 = 0, PD0 = 1 −49 dBc
PD1 = 1, PD0 = 0 −43 dBc
Input Voltage Noise f = 100 kHz 2.4 nV/√Hz
Input Current Noise f = 100 kHz 17 pA/√Hz
DC PERFORMANCE
Input Offset Voltage −3 +1 +3 mV
Input Bias Current
Noninverting Input −9 −2 +3 μA
Inverting Input −4 +4.5 +16 μA
Open-Loop Transimpedance RLOAD = 50 Ω 4 14 MΩ
RLOAD = 100 Ω 15 35 MΩ
Common-Mode Rejection 57 62 dB
INPUT CHARACTERISTICS
Input Resistance +IN, f < 100 kHz 500 kΩ
OUTPUT CHARACTERISTICS
Single-Ended, +Swing RLOAD = 50 Ω 11 11.1 VP
Single-Ended, −Swing RLOAD = 50 Ω 0.9 1 VP
Single-Ended, +Swing RLOAD = 100 Ω 11 11.1 VP
Single-Ended, −Swing RLOAD = 100 Ω 0.8 0.9 VP
Differential Swing RLOAD = 100 Ω 20.2 20.6 V p-p
POWER SUPPLY
Single Supply 12 V
Supply Current PD1 = 0, PD0 = 0 10.5 11.8 13 mA/amp
PD1 = 0, PD0 = 1 7 7.9 9 mA/amp
PD1 = 1, PD0 = 0 4.3 5.2 6.3 mA/amp
PD1 = 1, PD0 = 1 0.9 1.3 mA/amp

Rev. 0 | Page 3 of 16
ADA4311-1
Parameter Test Conditions/Comments Min Typ Max Unit
POWER-DOWN PINS
PD1, PD0 Threshold Referenced to GND 1.5 V
High Level Input Voltage, VIH 2 5 V
Low Level Input Voltage, VIL 0 0.8 V
PD1, PD0 = 0 Pin Bias Current PD1 or PD0 = 0 V −1.5 −0.2 +1.5 μA
PD1, PD0 = 1 Pin Bias Current PD1 or PD0 = 3 V 40 63 80 μA
Enable/Disable Time 130/116 ns
Power Supply Rejection Ratio −63 −70 dB

Rev. 0 | Page 4 of 16
 ADA4311-1

ABSOLUTE MAXIMUM RATINGS

Maximum Power Dissipation
Table 2.
The maximum safe power dissipation for the ADA4311-1 is
Parameter Rating
limited by the associated rise in junction temperature (TJ) on
Supply Voltage 13.6 V
the die. At approximately 150°C, which is the glass transition
Power Dissipation (TJMAX − TA)/θJA
temperature, the plastic changes its properties. Even temporarily
Storage Temperature Range −65°C to +125°C
exceeding this temperature limit can change the stresses that the
Operating Temperature Range −40°C to +85°C
package exerts on the die, permanently shifting the parametric
Lead Temperature (Soldering 10 sec) 300°C
performance of the amplifiers. Exceeding a junction temperature of
Junction Temperature 150°C
150°C for an extended period can result in changes in silicon
Stresses above those listed under Absolute Maximum Ratings devices, potentially causing degradation or loss of functionality.
may cause permanent damage to the device. This is a stress rating
Figure 3 shows the maximum safe power dissipation in
only; functional operation of the device at these or any other
the package vs. the ambient temperature for the 10-lead
conditions above those indicated in the operational section of
MINI_SO_EP (44°C/W) on a JEDEC standard 4-layer board.
this specification is not implied. Exposure to absolute maximum
θJA values are approximations.
rating conditions for extended periods may affect device reliability.
5.0
THERMAL RESISTANCE 4.5

MAXIMUM POWER DISSIPATION (W)

Thermal resistance (θJA) is specified for the worst-case conditions, 4.0
that is, θJA is specified for device soldered in circuit board for 3.5
surface-mount packages. MINI_SO_EP-10
3.0

Table 3. 2.5

Package Type θJA Unit 2.0

10-Lead MINI_SO_EP 44 °C/W 1.5

1.0

0.5

06940-003
–35 –15 5 25 45 65 85
AMBIENT TEMPERATURE (°C)

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

Rev. 0 | Page 5 of 16
ADA4311-1

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADA4311-1
+VS 1 10 OUT B

NC 2 9 –IN B
OUT A 3 8 +IN B
–IN A 4 7 PD1
+IN A 5 6 PD0

06940-004
NC = NO CONNECT

Figure 4. Pin Configuration

Table 4. Pin Function Description

Pin No. Mnemonic Description
1 +VS Positive Power Supply Input.
2 NC No Connection.
3 OUT A Amplifier A Output.
4 −IN A Amplifier A Inverting Input.
5 +IN A Amplifier A Noninverting Input.
6 PD0 Power Dissipation Control.
7 PD1 Power Dissipation Control.
8 +IN B Amplifier B Noninverting Input.
9 −IN B Amplifier B Inverting Input.
10 OUT B Amplifier B Output.
11 (Exposed Paddle) GND Ground (Electrical Connection Required).

Rev. 0 | Page 6 of 16
 ADA4311-1

TYPICAL PERFORMANCE CHARACTERISTICS

9 –40
VOUT = 100mV p-p VOUT = 2V p-p HD2
RL = 50Ω RL = 100Ω HD3
6 PD1, PD0 = 0, 0 –50
G = +5
G = +5
3

HARMONIC DISTORTION (dBc)

–60
PD1, PD0 = 1, 0
NORMALIZED GAIN (dB)

0 –70
PD1, PD0 = 0, 1
–3 –80 PD1, PD0 = 0, 0
G = +10
–6 –90

–9 –100
G = +20
–12 –110

–15 –120

–18 –130

06940-005

06940-008
1 10 100 1000 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response for Various Closed-Loop Gains Figure 8. Differential Harmonic Distortion vs. Frequency

9 –60
VOUT = 100mV p-p f = 5MHz
6 RL = 50Ω RL = 100Ω
PD1, PD0 = 0, 0
G = +5 G = +5
3 –70
HARMONIC DISTORTION (dBc)
0 HD2
–80
–3
PD1, PD0 = 0, 1
GAIN (dB)

–6
–90
–9

–12 PD1, PD0 = 1, 0 HD3

–100
–15

–18 –110
–21

–24 –120

06940-021
06940-006

1 10 100 1000 0.1 1 10

FREQUENCY (MHz) OUTPUT VOLTAGE (V p-p)
Figure 6. Small Signal Frequency Response for Various Modes Figure 9. Differential Harmonic Distortion vs. Output Voltage

0.20 –40
G = +5 VOUT = 2V p-p
RL = 50Ω f = 5MHz
0.15 10ns/DIV –50 G = +5
HARMONIC DISTORTION (dBc)

0.10
–60

0.05
OUTPUT (V)

–70
HD2
0
–80
–0.05

–90
–0.10 HD3

–0.15 –100
06940-010

–0.20 –110
06940-022

10 100 1000
LOAD RESISTANCE (Ω)
Figure 7. Small Signal Transient Response Figure 10. Differential Harmonic Distortion vs. Load Resistance

Rev. 0 | Page 7 of 16
ADA4311-1
100M 0 1000
RL = 100Ω PD1, PD0 = 0, 0

10M –45
100

OUTPUT IMPEDANCE (Ω)

TRANSIMPEDANCE (Ω)

PHASE
1M –90

PHASE (Degrees)
10

100k –135

1
MAGNITUDE
10k –180

0.1
1k –225

100 –270 0.01

06940-007
0.01 0.1 1 10 100 1000

06940-013
100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz) FREQUENCY (MHz)

Figure 11. Open-Loop Transimpedance and Phase vs. Frequency Figure 14. Closed-Loop Output Impedance vs. Frequency

0 1M
PD1, PD0 = 0, 0 PD1, PD0 = 1, 1
RL = 100Ω
–10
100k
COMMON-MODE REJECTION (dB)

OUTPUT IMPEDANCE (Ω)

–20
10k

–30
1k
–40

100
–50

10
–60

–70 1
06940-011

0.01 0.1 1 10 100 1000

06940-015
0.01 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 12. Common-Mode Rejection vs. Frequency Figure 15. Output Impedance vs. Frequency (Disabled)

–10 100
PD1, PD0 = 0, 0
RL = 100Ω

–20
POWER SUPPLY REJECTION (dB)

VOLTAGE NOISE (nV/ Hz)

–30

+PSR

–40 10

–50

–60

–70 1
06940-012

0.01 0.1 1 10 100 1000 10 100 1k 10k 100k 1M 10M 100M 1G

06940-009

FREQUENCY (MHz) FREQUENCY (Hz)

Figure 13. Power Supply Rejection vs. Frequency Figure 16. Voltage Noise vs. Frequency

Rev. 0 | Page 8 of 16
 ADA4311-1
–20 0
PD1, PD0 = 1, 1

–20
–40
FEEDTHROUGH (dB)

CROSSTALK (dB)
–40

–60

–60

–80
–80

–100 –100

06940-014

06940-017
1 10 100 1000 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (Hz)

Figure 17. Feedthrough vs. Frequency Figure 19. Crosstalk vs. Frequency

8 12

7
VOUT 11
6

10
5
VOLTAGE (V)

VOUT (p-p)
4 9

3
8
VPD1 , VPD0
2

7
1
06940-016

0 6

06940-020
0 1 2 3 4 5 6 30 100 1000
TIME (1μs/DIV) LOAD (Ω)

Figure 18. Power-Down Turn On/Turn Off Figure 20. Single-Ended Output Swing vs. Load

Rev. 0 | Page 9 of 16
ADA4311-1

THEORY OF OPERATION
The ADA4311-1 is a dual-current feedback amplifier with high Because G × RIN << RF for low gains, a current feedback amplifier
output current capability. With a current feedback amplifier, the has relatively constant bandwidth vs. gain, the 3 dB point being
current into the inverting input is the feedback signal, and the set when |TZ| = RF.
open-loop behavior is that of a transimpedance, dVO/dIIN or TZ. For a real amplifier, there are additional poles that contribute
The open-loop transimpedance is analogous to the open-loop excess phase, and there is a value for RF below which the amplifier
voltage gain of a voltage feedback amplifier. Figure 21 shows a is unstable. Tolerance for peaking and desired flatness determines
simplified model of a current feedback amplifier. Because RIN is the optimum RF in each application.
proportional to 1/gm, the equivalent voltage gain is TZ × gm, RF
where gm is the transconductance of the input stage. Basic
analysis of the follower with gain circuit yields RG

RIN
VOUT TZ ( s )
=G× IIN
TZ VOUT
VIN TZ ( s ) + G × RIN + RF RN

where: VIN

06940-018
R
G = 1+ F Figure 21. Simplified Block Diagram
RG
1
R IN = ≈ 50 Ω
gm

Rev. 0 | Page 10 of 16
 ADA4311-1

APPLICATION INFORMATION
FEEDBACK RESISTOR SELECTION Table 6. Power Modes
The feedback resistor has a direct impact on the closed-loop Total Supply Output
PD1 PD0 Power Mode Current (mA) Impedance
bandwidth and stability of the current feedback op amp.
Reducing the resistance below the recommended value can Low Low Full Power 23.6 Low
make the amplifier response peak and even become unstable. Low High ¾ Power 15.8 Low
Increasing the size of the feedback resistor beyond the recom- High Low ½ Power 10.4 Low
mended value reduces the closed-loop bandwidth. Table 5 High High Power-Down 1.8 High
provides a convenient reference for quickly determining the
feedback and gain resistor values, and the corresponding EXPOSED THERMAL PAD CONNECTIONS
bandwidth, for common gain configurations. The recommended The exposed thermal pad on the 10-lead MSOP is both the
feedback resistor value for the ADA4311-1 is 499 Ω. reference for the PD pins and the only electrical connection for
the negative supply voltage. Therefore, in the 10-lead MSOP,
Table 5. Recommended Values and Frequency Performance1
the ADA4311-1 can only be used on a single supply. The exposed
Gain RF (Ω) RG (Ω) −3 dB SS BW (MHz)
thermal pad must be connected to ground. Failure to do so
+5 499 124 310
renders the part inoperable.
+5 1k 250 220
+10 499 55.4 175 A requirement for this package is that the thermal pad be
+20 499 26.1 84 connected to a solid plane with low thermal resistance, ensuring
1
adequate heat transfer away from the die and into the board.
Conditions: VS = ±12 V, TA = 25°C, RL = 50 Ω, PD1, PD0 = 0, 0.

POWER CONTROL MODES OF OPERATION POWERLINE APPLICATION

The ADA4311-1 features four power modes: full power, ¾ Applications (that is, powerline AV modems) requiring greater
power, ½ power, and shutdown. The power modes are controlled than 10 dBm peak power should consider using an external
by two logic pins, PD0 and PD1. The power-down control pins line driver, such as the ADA4311-1. Figure 22 shows an example
are compatible with standard 3 V and 5 V CMOS logic. Table 6 interface between the TxDAC® output and the ADA4311-1 biased
shows the various power modes and associated logic states. In for single-supply operation. The peak-to-peak differential
the power-down mode, the output of the amplifier goes into a output voltage swing of the TxDAC should be limited to
high impedance state. 2 V p-p, with the gain of the ADA4311-1 configured to realize
the additional voltage gain required by the application. A low-
pass filter should be considered to filter the DAC images
inherent in the signal reconstruction process. In addition, dc
blocking capacitors are required to level-shift the output signal
of the TxDAC to the common-mode level of the ADA4311-1
(that is, VMID = VCC − GND/2).

0.1µF RSET
REFIO

REFADJ

TxDISABLE

OPTIONAL 1/2
LCLPF
IOUTP+ ADA4311-1
VMID
TxDAC
IOUTP–

0dB TO –7.5dB
1/2
06940-019

ADA4311-1

Figure 22. TxDAC Output Directly via Center-Tap Transformer

Rev. 0 | Page 11 of 16
ADA4311-1
BOARD LAYOUT POWER SUPPLY BYPASSING
As is the case with all high speed applications, careful attention The ADA4311-1 operates on supplies from 6 V to 12 V. The
to printed circuit board (PCB) layout details prevents associated ADA4311-1 circuit should be powered with a well-regulated
board parasitics from becoming problematic. Proper RF design power supply. Careful attention must be paid to decoupling the
technique is mandatory. The PCB should have a ground plane power supply. High quality capacitors with low equivalent series
covering all unused portions of the component side of the resistance (ESR), such as multilayer ceramic capacitors (MLCCs),
board to provide a low impedance return path. Removing the should be used to minimize supply voltage ripple and power
ground plane on all layers from the area near the input and dissipation. In addition, 0.1 μF MLCC decoupling capacitors
output pins reduces stray capacitance, particularly in the area of should be located no more than ⅛-inch away from each of the
the inverting inputs. Signal lines connecting the feedback and power supply pins. A large, usually tantalum, 10 μF capacitor is
gain resistors should be as short as possible to minimize the required to provide good decoupling for lower frequency signals
inductance and stray capacitance associated with these traces. and to supply current for fast, large signal changes at the
Termination resistors and loads should be located as close as ADA4311-1 outputs. Bypassing capacitors should be laid out
possible to their respective inputs and outputs. Input and in such a manner as to keep return currents away from the
output traces should be kept as far apart as possible to minimize inputs of the amplifiers, which minimizes any voltage drops that
coupling (crosstalk) though the board. Wherever there are can develop due to ground currents flowing through the ground
complementary signals, a symmetrical layout should be provided plane. A large ground plane also provides a low impedance path
to the extent possible to maximize balanced performance. for the return currents.
When running differential signals over a long distance, the
traces on the PCB should be close. Doing this reduces the
radiated energy and makes the circuit less susceptible to RF
interference. Adherence to stripline design techniques for long
signal traces (greater than about 1 inch) is recommended.
For more information on high speed board layout, see A
Practical Guide to High-Speed Printed-Circuit-Board Layout.

Rev. 0 | Page 12 of 16
 ADA4311-1

OUTLINE DIMENSIONS
3.10 *2.27
3.00 2.17
2.90 2.07

10 6
3.10 5.05 *1.83
TOP 4.90 1.73
3.00 VIEW
2.90 4.75 1.63
1
5
EXPOSED
PIN 1 PAD
INDICATOR
0.50 BSC BOTTOM VIEW
0.50 BSC
0.94 0.23
0.86 1.10 MAX 0.18
0.78 0.13
0.70
0.15 SEATING 0.55
0.30 8°
0.10 PLANE 0.40
0.23 0°
0.05
0.15
COPLANARITY
0.10

073007-B
*COMPLIANT TO JEDEC STANDARDS MO-187-BA-T
EXCEPT FOR EXPOSED PAD DIMENSIONS.

Figure 23. 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP]
(RH-10-1)
Dimensions shown in millimeters

ORDERING GUIDE
Package
Model Temperature Range Package Description Option Branding
ADA4311-1ARHZ 1 −40°C to +85°C 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] RH-10-1 1A
ADA4311-1ARHZ-RL1 −40°C to +85°C 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] RH-10-1 1A
ADA4311-1ARHZ-R71 −40°C to +85°C 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] RH-10-1 1A
1
Z = RoHS Compliant Part.

Rev. 0 | Page 13 of 16
ADA4311-1

NOTES

Rev. 0 | Page 14 of 16
 ADA4311-1

NOTES

Rev. 0 | Page 15 of 16
ADA4311-1

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06940-0-8/07(0)

Rev. 0 | Page 16 of 16