November 9, 2022

CS 303 Logic and Digital System Design

/20 /10 /10 /10 /16 /10 /14 /10 /100

Name: ID:

Notes:
1) Please answer the questions in the provided space after each question.
2) Duration is 110 minutes
3) Closed books and closed notes.

1. (20 pts) Fill in the following tables.

Decimal Binary Hexadecimal

Decimal Signed 4-bit binary in 2’s complement form, 4 bits in the fraction
-4.3750 1011.1010
5.8750 0101.1110
-3.625 1100.0110
3.5625 0110.1001

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2. (10 pts) Calculate the binary equivalent of 1225/512 using only six (6) bits in the fraction.
Then convert the resulting binary number back to decimal. What is the error in the binary
representation? How many bits are needed to fully represent the 1225/512 in binary
number system?

1225/512 = 2 + 201/512 = 2 + 128/512 + 64/512 + 8/512 + 1/512

010.011001001 (full precision)

Error= 1/512

12 bits required for full precision.

3. (10 pts) Assume that you are using 8-bit, two’s complement scheme to represent signed
integers.

a) Show the range of integers that can be represented. (2 pts)

[-128, 127]

b) Do the following arithmetic operations and detect overflows. (8 pts)

01011101 11101101
+ 00101111 + 10101101
0 10001100 1 10011010
Overflow? Yes No

00011010 10011100
- 00101111 - 11011010

Overflow?

00011010 10011100
+ 11010001 + 00100110
0 11101011 0 11000010
Overflow? No No

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4. (10 pts) Express the following function as a sum of minterms and as a product of maxterms
and implement the function using only NAND gates.

F(x,y,z,t) = x’z + x’y’t + y’zt

F = S (1,2,3,6,7,11)

F = P (0,4,5,8,9,10,13,12,14,15)

5. (16 pts) Optimize the following Boolean function.

F(x, y, z, t) = Ð (0, 2, 8, 10, 13, 15)

a) Use the “1”s in the K-map, find all prime implicants in the truth table. (4 pts)

zt
xy 00 01 11 10
00 0 1 1 0
01 1 1 1 1
11 1 0 0 1
10 0 1 1 0

Prime implicants: y’t, yt’, x’y, and x’t

b) Use the “1”s in the K-map, list all essential prime implicants. (4 pts)

Essential prime implicants:

y’t due to m9 and m11;

c) Use the “1”s in the K-map, list all possible Boolean expressions for F. (4 pts)

F = y’t + yt’ + x’y or F = y’t + yt’ + x’t

d) Express the function in product of sums. Use the “0”s in the K-map. (4 pts)

F’ = xyt + y’t’
F = [xyt + y’t’]’ = (xyt)’(y’t’)’ = (x’+y’+t’)(y+t)

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6. (10 pts) Consider the logic gate G below and its truth table.

x y z
L L H
L H L
H L L
H H L
Two-input gate

x
G z
y

Consider also the following circuit, using the gates of type G.

x G
G F

y G

a) If the positive logic is used, find the simplified Boolean expression for the function F. (5 pts)

If the positive logic is used, then the gate G is NOR. Then the function is

F = ((x’ + y’)’ + x’)’= x(x’+y’) = xy’

b) If the negative logic is used, find the simplified Boolean expression for the function F. (5
pts)

If the negative logic is used, then the gate G is NAND. Then the function is

F = ((x’y’)’x’)’= x+(x’y’) = (x+x’)(x+y’) = x+y’

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7. (14 pts) Consider the combinational circuit below.

x1
y 1’
F
x0
y 1’
y 0’

x1
x0
y 0’

Answer the following questions:

a) Find the Boolean expression for the circuit in terms of sum of products. (5 pts)

F = x1y1’ + x0y1’y0’ + x1x0y0’.

b) Obtain the truth table. (5 pts)

x1 x0 y1 y0 F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

c) Provide the verbal description for what the circuit does. (4 pts)

F function implements the Greater Than function. It compares two binary numbers of two bits,
X = (x1x0) and Y = (y1y0) and outputs “logic-1” when X > Y, “logic-0” otherwise.

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8. (10 pts) Design a parity generator that takes 5-bit input (A4A3A2A1A0) and generates a
parity bit “P” such that there are odd number of ones in total (when the parity bit is
combined with the input (A4A3A2A1A0P) ).

If there is odd number of ones in the 5-bit input the parity bit P should be zero (0) to have
odd number of ones in total, which means P is an even function.

P = (A5 Å A4 Å A3 Å A2 Å A1)’

So, we need a 5-input XNOR gate to generate P. We can also combine two-input XNOR
gates to construct a 5-input XNOR gate.