An Introduction to Power Supply

Simulations with SIMPLIS

Christophe Basso
Business Development Manager
IEEE Senior Member

February 2022 – Rev 0.22

 Agenda
 SPICE and Power Converters
 The SIMPLIS Approach
 Transfer Functions
 Power Factor Correction
 Interactions with EMI Filter
 Monte Carlo Analysis
 Digital Compensation
 Design Example of a Flyback Converter
 The SPICE Engine
 SPICE is a linear solver in essence: any nonlinear behavior must be linearized
 SPICE samples at a variable timestep: it adjusts its course based on signals shapes
 Flat type of waveform: large timesteps are taken
 Change occurs: timestep reduction until enough precision is obtained
1

Reduction o Timestep control algorithm is an essential

in steps part of the engine:
 It controls the number of iterations to find a
solution
vDS  t   It checks that timestep reduction brings a
precise solution – jump to next point or fail!

Large steps
Reduction
in steps
Highly time-consuming process!
 A Piece-Wise Linear Approach – Diode Example
 A diode is a nonlinear device affected by a variable dynamic resistance rd
 SPICE will have to linearize the component at every change in operating point
A
13.4m  nVvF 
I F  I s  e  1
T

VF  
10.0m I F 1 rd 1   
rd 1
I F IF1

IF 6.64m
VF
vˆ
3.26m VF iˆF  I F F
I F rd 2  nVT
1 I F IF 2
0
VF rd 2
399m 499m 599m 699m 799m
V
Operating points
nVT
VF rd 
IF
 A Switching Converter is a Nonlinear System
 A switching converter is exhibiting linear characteristics during ton and toff
Vout Vout
rDS  on  L rL L rL
Vin C Rload Vin rd C Rload

on time off time

 The toggling event between the two networks introduces a discontinuity

linear The PWM switch
Singularity
Averaged
Cannot model a c
differentiate
DTsw 1  D  Tsw d
linear linear PWM switch VM p
vDRV  t  on time off time
 The Need for an Averaged Model
 An averaged model excludes the switching component by construction
 The simulation time is flashing and some models operate in ac and transient analyses
 What if I don’t have an averaged model for my particular converter?
L1 rL
100uH 10m out
a a a c c c
5.00V
Vout
4
5.01V 5.01V

12.0V
417mV d rC
15
PWM switch VM p 30m
Vin CoL LoL R3
1k X1 5.00V
5
{Vin} 1k PWMCCMVM 6
0V
12 417mV parameters C2
14
Vstim 47uF
AC = 1
Vin=12

E1 Vref
100 5

R5 5.00V o Always verify bias point!

13
100m
417mV
10 out  Target is 5 V: Vout = 5 V
 An Accurate Bode Plot
 When the simulation is fine-tuned, matching with laboratory experiments is excellent
 One of the keys for success is to precisely extract parasitics such as capacitors ESRs
Peaking mismatch

Hf
SPICE
H  fc 

H  f 
H  f c 
SPICE

 Once the model is validated, you can explore stability margins on the computer

ESR: equivalent series resistance

 A Frequency Response Analyzer with SPICE
 Some SPICE packages such as LTspice offer a means to measure the loop
 The circuit is switching and a signal is injected for ac-modulating the converter
 The source must be of sufficiently-low amplitude to avoid saturation

 Works ok for a narrow analysis

band around crossover – starts
at 15 kHz up to 30 kHz in this
example
 Simulation time can be long,
especially if one wants to
reveal sharp resonances
 How to simulate PFC stages
with sweep starting below 1
Hz and a 10-Hz crossover?
 Agenda
 SPICE and Power Converters
 The SIMPLIS Approach
 Transfer Functions
 Power Factor Correction
 Interactions with EMI Filter
 Monte Carlo Analysis
 Digital Compensation
 Design Example of a Flyback Converter
 A Time-Domain Simulator
 SIMPLIS is a time-domain simulator and operates with switching components
 Ac analysis is carried over a switching converter: no need for an averaged model
 Frequency response is revealed the same way as if it were carried in the laboratory
OUT IN
=OUT/IN

AC 1 0
Vmod1
Output voltage
5

Ac source
Vaux {C2}
R16
{RLED} R12
C5 {Rupper}
U8 {C1}
Optocoupler {R2}

FB R6 C4

U7
OPSIMP
R15
V5
{Rlower} Isolation transformer
{Vref}

R.D. Middlebrook, Measurement of Loop Gain in Feedback Systems, Int. J. Electronics, 1975, vol. 38, No. 4, 485-512
 Two Segments are Enough for a Diode
 SIMPLIS uses a PWL approach where a component is modeled through segments
 Any change in operating point is modeled as a transition to another segment
 At any instant in simulation time, the system is always linear!

More
1
1 segments
rd 2
rd 1
1
rd 1

A two-segment model A three-segment model

 Piece-Wise Linear Modeling of all Components
 Components can be modeled with accuracy to reflect real operating waveforms
 By selecting different levels, it is possible to gradually improve precision
10m 1u Vout
IL R1 L1 C1
220u R3
IC=1 250m
12
V2 R9 R2
V1 20m

VDS Part models

INT
Q1
IRF530 2m 4.7u Vout

IL R1 L1

C1
10 220u
R4 R3
12 D1 500m
V2
VGS
R2
20m
V1
 Passive Elements include Parasitics
 Typical elements such as capacitors can embark parasitics such as ESR or ESL
 Select the model level between 0 (the simplest) and 3 (the most comprehensive)
P P P P

C1 R1 C2 R2 C3 R5 C4
{CAP} {RLK} {CAP} {RLK} {CAP} {RLK} {CAP}

2 2
R3 R4
{RESR} {RESR}

N N 3
L1
{ESL} R6
Level 0 Level 1 N
{ESL_SHUNT}

Level 2
 Avoid over-populating your schematic with hidden properties
N

 You can also model bias-dependent capacitors Level 3

 Voltage- or Current-Dependent Passive Elements
 You can model any sort of behavior with a PWL element: resistor, capacitor or inductor
 A PWL resistor models a diode with a specific threshold and a dynamic resistance rd
 A saturating inductor showing the effects of too high a peak current
 Use realistic numbers for slopes, e.g. 10-100 m not 1 p!

I f A
-100n Reverse bias 1
VT0 = 100 mV rd

0.2  0.1
rd  1Ω
100m  1u
Avalanche at 5 V

Vf V
 A Saturating Inductor is Easy to Model
 It is important to visualize the effects of core saturation in a simple way
 SPICE models featuring hysteresis effects like Jiles-Atherton are complicated to handle
 A few PWL lines and you have the shape of a saturating inductor
(A) (V.s)

L4
Lsat
IL IC=1
VDS
R9

V3
10 I sat
200
S2 V2
V1 Lmag
iL  t 
 Constant-Power Current Source
 A constant-power source is useful to determine the ripple current in a bulk capacitor
 Using Excel, it is possible to determine the absorbed current based on the on-going bias
Vbulk constant

D1 D2 Ibulk Pin
mur840 mur840
Pout
C1 IC=1 i t  
120u R1
vbulk  t 
D3 D4
mur840 mur840

variable

 You can assess the rms current in the capacitor in worst-case situations
 Check the valley voltage corresponding to the minimum rectified dc input voltage
 Peak and Valley Voltages
 The valley voltage at the lowest input mains (85 V rms) is 64 V dc

iC  t  Ripple current
in the capacitor:
IC,rms = 1.6 A
Pin  90 W Constant power
absorbed by the
dc-dc converter
td Peak  120 V dc
Rectified ripple
Valley = 64 V voltage
vbulk  t 

 Design the converter for operating down to 64 V ( 55 V with margins)

 Failure to do so: output ripple, loss of regulation, protection latch
 Transient Time and Steady-State Operations
 A converter needs time to reach its steady-state regulated output
 Depending on compensation, the op-amp rails up and takes time to recover
 There can be a large overshoot which may need hundred of millisecond to damp

iL  t 
(A)

Transient period Steady state

(V)
vout  t 

 Analysis should take place once the transient period is over: how long can it take?
 Periodic Operating Point or POP
 SIMPLIS uses a unique algorithm to meet the steady-state point in a record time
 The POP determines with the highest precision when the circuit is stabilized:
Average voltage across inductors is 0 V and average current in capacitors is 0 A

Place the pop trigger

on the schematic

 The POP trigger will synchronize the engine with the start of each periodic cycle
 A typical output can be a clock or a driver output for instance
 Find Steady-State Operation in a few Seconds
 When launched, the process finds the operating point very rapidly
 Once at steady-state, small-signal analysis can be initiated
X1

(A)
Clock POP Trigger iC  t 

10m 1u Vout iL  t 
IL R1 L1 C1
(A)
220u
Clock
12 R3
V2
IC=1
R2
20m
250m
vout  t 
R9 (V)
V1

IC

 The process is extremely precise with a convergence precision down to 1 pA and 1 pV

 The Process of Finding the Right Point
 Select maximum switching period and instruct the engine when it starts its POP process
 The clock here is 100 kHz, then choose 15 µs and go for 5 switching cycles
Starts Done!
POP

>

>

>

>

>
1 2 3 4 5

You can select various analyses from this panel

 Topology Changes
 SIMPLIS while performing POP calculation explores so-called topologies
 A topology represents a unique state which is solved and recorded
 As simulation progresses, known topologies are retrieved and reused to proceed

S2 L1 During simulation, multiple topologies are explored

C1
Vg R3
D1
R2
One topology

S2 L1 1st pass unsuccessful

C1
Vg R3
2nd pass successful

D1
R2
Another topology
 Agenda
 SPICE and Power Converters
 The SIMPLIS Approach
 Transfer Functions
 Power Factor Correction
 Interactions with EMI Filter
 Monte Carlo Analysis
 Digital Compensation
 Design Example of a Flyback Converter
 Running Small-Signal Analysis
 As long as a POP analysis is successful, small-signal analysis can be obtained
 Obtain frequency response like control-to-output, or loop gain/phase in seconds
 Work with all switching converters and those without an averaged model (LLC)

 A pulse-width modulator (PWM) is added to the sketch for duty ratio modulation
 Set source V3 to 1 and SIMPLIS automatically controls its amplitude
 The Steady-State Waveforms are First Obtained
 You can immediately verify that variables are within the expected range
 Measurements are available such as rms, average or peak values

(A)
iC  t 

(A) iL  t 

(V)
vsaw  t 

(V)
vout  t 
 Power Stage Response is the First Step
 The Bode plot for the power stage is obtained in a fraction of seconds
 Same for the PWM section which shows the effects of the propagation delay
 The 100-ns pure delay makes the converter a non-minimum phase system

H0 = 15.2 dB D f 
Verr  f  - 6 dB
(dB) Vout  f 
(dB)
Verr  f 

Vout  f  D f 
  Effects of
Verr  f  Verr  f  prop. delay
(°) (°) 0° phase

Control-to-output transfer function Pulse-width modulator ac response

V RL 
H 0  20 log  in 
V R r
 p L L 
 Stepping Components Values
 It is interesting to assess the effects of varying a component value
 Multi-stepping provides a means to sweep a component value in transient or ac analyses
Simulator menu – Multi Step setup

 See the effects of varying the load from 100 mΩ to 1 Ω

 Check the impact of the equivalent series resistance
 Simulation Results are Quickly Obtained
 You can immediately see the impact of parasitics on the transfer function
 Adopt the right compensation strategy to neutralize these variations

RL  1 

RL  100 m
(dB) (dB)
Vout  f  Vout  f  rC  100 m

Verr  f  Verr  f  rC  10 m

(°) (°)
RL  1 
RL  100 m
rC  100 m
Vout  f  Vout  f 
 
Verr  f  Verr  f  rC  10 m

Sweeping the load Sweeping the ESR

100 mΩ to 1 Ω 10 mΩ to 100 mΩ
 Closed-Loop Simulations
Vsw
S2
100u IC=0 IL VOUT VOUT

rL
1u
L1
F1
R1
50m
R3
I1
 In the laboratory, it is difficult
{Vin}
Vin
D1
Ideal_Diode
{Ri}

+ C13
1
to physically open the loop
680u IC=0
especially in high-gain systems
Qdrv  Perturbing the system while
X1

S
U3
Q
DRV
V4
AC 1 0
operating in closed-loop is the
R
QN Slope way to go
comp.
U2
{kr}
FB
OPIN
 The ac source is of fixed
U4
1K
{C2} IC=0

C3 R8
amplitude and does not need
Vclock maxDC
R4
G1
{R2}

R6
{C1} IC=0 {Rupper}
adjustment
100p IC=0 R2 C5

 The same circuit can be used

C2 1
Vsaw
FB

330m R5
for ac or transient tests
IC=1 OPSIMP
FB 1 U1
R7
FB VOUT V1 R11
IN OUT {Rlower}
{Vref1}
G2 =OUT/IN
VCS
OPIN FB
IN OUT
=OUT/IN
A buck converter operated in CM
 Current Mode and Subharmonic Oscillations
 If the current loop is not properly compensated, instability at Fsw/2 can happen
 By reducing the gain of the inner current loop, oscillations can be tamed
Control-to-output transfer function Control-to-output transfer function
Peaking at Fsw/2 Vout  f 
(dB) (dB) Verr  f 
Vout  f 
Verr  f  Vin  Vout
Sn  Ri
L
Vout  f 

Verr  f 
(°) Se (°)
Vout  f  mc  1 
 Sn
Verr  f 
External
ramp
No slope compensation 50% slope compensation
mc = 1 mc = 1.5
 Automatic Compensation is Possible
 It is possible to write macros automating components values calculations
 Read the power stage magnitude and phase at the selected crossover frequency
*
.VAR Vin=12
* Enter the Values for Vout and Bridge Bias Current *
.VAR Vout=5
*
.VAR L=100u
.VAR Ibias=1m *
.VAR Ri=160m
.VAR Vref1=2.5 { '*' }
.VAR Ts=10u * please update clock and ramp generators *
.VAR Rlower={Vref1/Ibias} { '*' }
*
.VAR Rupper={(Vout-Vref1)/Ibias} { '*' } Rupper = {Rupper}
.VAR Gfc=-20 * magnitude at crossover *
* { '*' } Rlower = {Rlower}
.VAR PS=-40 * phase lag at crossover *
* Do not edit the below lines * { '*' } R2 = {R2}
*
.VAR boost=PM-PS-90 { '*' } C2 = {C2}
* Enter Design Goals Information Here *
.VAR G=10^(-Gfc/20) { '*' } C1 = {C1}
*
.VAR fp=(tan(boost*pi/180)+sqrt((tan(boost*pi/180))^2+1))*fc { '*' } Boost = {boost}
.VAR fc=10k * targetted crossover *
.VAR fz=fc^2/fp { '*' } Fz = {Fz}
.VAR PM=60 * choose phase margin at crossover *
.VAR a=sqrt((fc^2/fp^2)+1) { '*' } Fp = {Fp}
*
.VAR b=sqrt((fz^2/fc^2)+1) { '*' } Sn = {Sn}
.VAR Sn={((Vin-Vout)/L)*Ri}
.VAR R2=((a/b)*G*Rupper*fp)/(fp-fz) { '*' } Se = {Se}
.VAR Sramp={1/Ts}
.VAR C1=1/(2*pi*R2*fz) { '*' } kr = {kr}
.VAR mc=1.5 * set this value for ramp comp *
.VAR C2=C1/(C1*R2*2*pi*fp-1) { '*' }
.VAR Se={(mc-1)*Sn} Display values
*
.VAR kr={Se/Sramp} Pole-zero calculation In the netlist
* Determine the amount of compensation
 Meeting the Right Crossover in a few Seconds
 SIMPLIS calculates the compensation values based on the adopted strategy
 It is then easy to explore other approaches with different crossover, margins etc.
Simulator menu
Tf

fc
*
* Rupper = 2500
* Rlower = 2500
* R2 = 84484.6310392954
* C2 = 5.34187416193801e-10
T  f  * C1 = 2.24506484641772e-10
m * Boost = 10
* Fz = 8390.9963117728
* Fp = 11917.5359259421
* Sn = 11200
* Se = 5600
* kr = 0.056
*
Compensated loop gain T(f)
 SIMPLIS is a Time-Domain Simulator
 With a clock source, cheat SIMPLIS and obtain ac-response of non-switching circuits
 A typical application is an automated compensator .VAR Gfc=-10 * magnitude at crossover *
.VAR PS=-150 * phase lag at crossover *
*
* Enter Design Goals Information Here *
*

VB
VA 12 V Vreg .VAR fc=1k * targeted crossover *
.VAR PM=70 * choose phase margin at crossover *
*
* Enter the Values for Vout and Bridge Bias Current *
VA VB *
IN OUT VB .VAR Vout=12
=OUT/IN .VAR Ibias=2m
VFB .VAR Vref1=2.5
{C2} .VAR Rlower=Vref1/Ibias
LOL
1k .VAR Rupper=(Vout-Vref1)/Ibias
C2 R1 R3 *
{R2} {C1} {Rupper} {R3} * Do not edit the below lines *
X1 .VAR boost=PM-PS-90
R2 C1 .VAR Kf=(tan((boost/4+45)*pi/180))^2
C3 COL
OPSIMP {C3} 1k .VAR fz1=fc/sqrt(Kf)
100 .VAR fz2=fc/sqrt(Kf)
Verr .VAR fp1=fc*sqrt(Kf)
.VAR fp2=fc*sqrt(Kf)
*
.VAR G=10^(-Gfc/20)
U2
2.5 .VAR a=sqrt((fc^2/fp1^2)+1)
E1
V3 V1 V2 .VAR b=sqrt((fc^2/fp2^2)+1)
R4 AC 1 .VAR c=sqrt((fz1^2/fc^2)+1)
{Vref1} {Rlower}
Vclock .VAR d=sqrt((fc^2/fz2^2)+1)
.VAR R2=((a*b/(c*d))/(fp1-fz1))*Rupper*G*fp1
.VAR C1=1/(2*pi*fz1*R2)
Automatic bias point calculation .VAR C2=C1/(C1*R2*2*pi*fp1-1)
Clock generator – Nyquist .VAR C3=(fp2-fz2)/(2*pi*Rupper*fp2*fz2)
criterion applies .VAR R3=Rupper*fz2/(fp2-fz2)
.VAR G0=((R2*C1)/(Rupper*(C1+C2)))*c*d/(a*b) * Gain at fc sanity check *
*
 Confirming Bias Point and Frequency Response
 The simulation confirms the applied voltage for regulation is 12 V
 Frequency response shows the wanted 10-dB gain at 1 kHz

(V) (dB) Verr  f 

10 dB
 Op-amp output within its linear range VFB  f  1 kHz

Verr  f  boost

(V) (°) VFB  f  130°
 Bias applied at the op-amp divider

Dc value confirming the 12-V target Compensator response

 Explore Complicated Converters
 Any converter can be simulated to determine the control-to-output transfer function
 Start with a simple circuit for which the POP is easily obtained
 Then add more comprehensive models to see 2nd- and 3rd-order effects
Vin

VAL VAR
IC=1 IC=1
A S3 R3 B S2 R9

IMUL HBL IMUR L1 {7.2}

V3 18u IC=0 RPrim Ip N:1:1
400 OUT
HBL 1m Is1
HBR

IMLL IMLR HBR Imag

TX1
VBL VBR VCres 10u
RLK=100Meg I1
A P1 S1
ESR=4.84m 658m
56u IC=0 C2 R10
B S4 IC=1 S1 IC=1 QTY=20
LP RSecondary
R2 R1
2m Ic
S2
TX2 Ires
C1
42.3n IC=190 Is2
230
OUT
R11
R6
50k CMP OUT
U1 1n IN OUT
V1 NCP4390_SIMPLE
AC 1 =OUT/IN
SROUT1 A C4
FB
OPIN SROUT2 B SONiC - 3.5 kW - 48 V/73 A
COMP Christophe Basso - Future Electronics
R4 CMP
{Rupper} COMP ICS NCP4390 controller
R5 GND VCS October 2021 - Rev. 0.1
C7 {R2}
{C2}
R8 C3 C6 Duty ratio
{Rlower} 100p {C1} IN
VTRANS Duty Cycle

1
HBL

HBR
Frequency
OUT E1 IN Frequency
OPIN IN OUT OPIN IN OUT CMP
=OUT/IN =OUT/IN

Charge-controlled LLC with NCP4390

 Obtain the Transfer Function Instantly
 Any converter can be simulated to determine the control-to-output transfer function
 Start with a simple circuit for which the POP is easily obtained
 Then add more comprehensive models to see 2nd- and 3rd-order effects

Hf Tf

fc

H  f 
T  f 
m

Power stage small-signal response Compensated loop gain (10 kHz fc)
 Agenda
 SPICE and Power Converters
 The SIMPLIS Approach
 Transfer Functions
 Power Factor Correction
 Interactions with EMI Filter
 Monte Carlo Analysis
 Digital Compensation
 Design Example of a Flyback Converter
 Power Factor Correction
 Power factor correction simulation places a heavy burden on computers
 High-frequency events spread across several tens of mains cycles imply simulation power
 SPICE users simulate only a small portion of the operations
Vrect
rect

parameter
Simplified Borderline Conduction Mode ICoil R10 ratio=1
B1 Power Factor Correction circuit 100m Fline=50*ratio
Voltage
abs(V(line)) 2 Vin=230
B2 Vout=48
Vline Vaux D2 Vout
Current L=700u
mbrb20200ctt4
I(Lp)*V(line)/V(rect) RAT IO = -266m Pout=100
line 20 13 23
R6
1.3Meg R1 X4
Iin Lp
XFMR
10k C5
22p
15
{L}
RAT IO = -266m
7 mn
X3
V1
MUL Vdrain 10
T ran Generators = SIN
K = 3*0.65 R2 R11
Verr 4 1 8 Id
A
18 182k 250m
K*A*B 2 7 C3
14 6
10p 22 Rl oad
B Vdrv
1
9 3 6 {Vout*Vout/Pout}

16 4 5 3
FreeR un
X1 X2
G1
FreeRunDT PSW1
100u D1 R5
toffmin = 1u Fsw
7
1N751 1k
V3 Vsense 12
R3 C4
2.5V 10k
R7 19
R4 21 {3.3m /ratio}
V4 C6 B3 IC = 47
12k 250m
0.49 100p Voltage

C2 ({Vin}^2/({L}*2*{Pout}))*(1-V(rect)/{Vout})
{0.68u/ratio}
IC = 0.330

48-V/100-W single-stage QR flyback converter

 Averaged Model Alternative
 Averaged models are an alternative for transient and ac analyses
 The switching component has disappeared and they simulates fast
 Convergence issues are likely to appear depending on model robustness
Iin
X2
PWMBCMCM
QR
X1 Vrect L=L
PWM

PWM switch BCM

vc
a
KBU4J Ri = Ri
Vton

ton
28

3
10
+
X2x switch Vout
Vfsw XFMR

Fsw (kHz)
Cin 30
Vin Vin RATIO = -266m


IN
{VRMS} 1u 16
11 7

p
R1

c
-
8
1.3Meg 5

L1 R10
4 {L} 50m Rload
{Vout*Vout/Pout}
9
23
C5
R4
R6 3.3m
R2 182k
100m IC = {VOUT}
12k C3
10n

K = 0.6 Vmul
A

B
K*A*B
2 1s
Verr 13 6

parameter D1 D2
Vrms=230 N = 0.01 N = 0.01 12
R5 C2
Pout=100 G1
15 14 1G 0.68u R3
Vout=48 10u V4
V3 V5 2.5 10k
Ri=0.25 10 10m
L=700u

Averaged model of the single-stage QR flyback converter

 Cycle-by-Cycle Simulations with SIMPLIS
 SIMPLIS lets you examine the frequency response using a fixed dc bias
 This dc level equals the rms value of the input voltage, e.g. 230 V dc for a 230-Vac input
 You can test the operating point and obtain the small-signal response in a few seconds
mr756

D1
R8
100m FB
IN OUT VB

V1
230
230 V dc for a IL
VA
=OUT/IN
 Works for operating point
230-V rms input IN OUT VB
TX2

S1 P1
200u IC=0
L1 VA
IN
=OUT/IN

OUT
determination
FB
=OUT/IN
 Can give the small-signal
mr756 VOUT

response of the control-

R2

22k
D2
IC=1 + C10
R3 22p IC=1
Duty ratio to-output transfer
QR engine DRV
IN Duty Cycle VB

X1
V5
AC 1 + C13
function
 Simulates in 1 s!
150u IC=0
Frequency
IN Frequency
U2 U35 VA
DRV
DRV S1 IC=1 I2 R1
D Q S Q R31 1K
C8
R 47p IC=0
QN QN R6
U3 {Rupper}

Compensator
SET
DRV RST
R4
G1 250m
I1 FB VB
V2 275u
100m U1 IC=1 IC=1 R5
Ct R9 R10 {R2}
C2 {gm}
FB {C2} IC=1
+ R11
+ V6 V4
Ct V3 {Rlower}
C3 {Vref1}
S2 10m {C1}

1n IC=0

Constant on-time VM boost converter

 Operating Point and Ac Response
 The operating point lets you check that the converter regulates properly
 The POP process works fine with the dc input but would fail with a sinewave input
 Use multi-tone ac analysis instead Compensated loop gain, Vin = 230 V

Tf

fc

T  f 

m

vout  t 

POP of the CrM boost converter

 Transient Simulations
 With a sinusoidal input you can run simulations in the long range
 Check input current distortion and transient response in different conditions
5m Vrect
Iin mr756

L3 D1
R8
C7 C5 100m
V1 100n 470n

C4 + IL
R13 R14 1u IC=0

Ac source 30m 30m

TX1

5m
S1 P1

L4

EMI filter Rectification mr756

R2 VOUT

22k
D2
IC=1 + C10
R3 22p IC=1
Duty ratio
IN Duty Cycle
DRV

+ C13
200u IC=0
Frequency
IN Frequency
U2 U35
DRV
DRV S1 IC=1 I2 R1
D Q S Q R31 1K
C8
R 47p IC=0
QN QN R6
U3 SET {Rupper}
DRV RST
R4
G1 250m
I1 FB VB
V2 275u
100m U1 IC=1 IC=1 R5
Ct R9 R10 {R2}
C2 {gm}
FB {C2}
+ V4 R11
V6
Ct V3 {Rlower}
C3 {Vref1}
S2 10m {C1}

1n IC=0
 Dynamic Performance
 The transient response can be quickly assessed at low- and high-line input voltages
 The available granularity allows you to zoom-in and precisely look at switching events

200-mA load step at Vin = 265 V rms 200-mA load step at Vin = 100 V rms
 Explore Distortion and Harmonics
 SIMPLIS lets you interpolate data and choose different apodization windows
 You can also easily evaluate the input current distortion
iIN  t 

(A)

Vin = 100 V rms

(Hz)
 Agenda
 SPICE and Power Converters
 The SIMPLIS Approach
 Transfer Functions
 Power Factor Correction
 Interactions with EMI Filter
 Monte Carlo Analysis
 Digital Compensation
 Design Example of a Flyback Converter
 Impedance Association
 A converter fed by an EMI filter will see its transfer functions affected:
 The control-to-output transfer function can have degraded margins
 The output impedance of the converter can be significantly changed
 Always confirm stability is not at stake when the filter is installed

H1  s  Z th  s  Z in  s  H2 s
vˆout
vˆg
Vin  s 

d̂
G s
 A Negative Resistance
 The incremental or small-signal resistance of a closed-loop converter is negative
 When associated with an EMI filter, a mechanism for oscillations exists
 Considering a 100%-efficient converter, we have: Pout  Pin I inVin  I outVout
 In closed-loop operations, Pout is constant, no link to Vin
Infinite rejection
P
I in Vin   out
Vin
1 Calculate P 
slope d  out 
dI in Vin  V P
0.8   in    out2
dVin dVin Vin
I in  A  0.6

0.4 The incremental input Vin 2

resistance is negative
Rin  
0.2
Pout
10 15 20 25 30

Vin  V 
 A Simple Example
 Losses in the EMI filter are illustrated by a damping ratio  or a quality factor Q
 If losses are exactly compensated by a negative resistance, you built an oscillator
1  s z 1 If ohmic losses are gone, the
H  s  H0 Q 
s2 s 2 damping ratio is zero, Q is infinite.
  1
0 2 0Q
(V)
150 Input voltage

rL L Vout
rC 130
Output voltage
(V) Sustained
Vin I 110
oscillations

C 90.0

70.0
 0
P (constant)  0  0 RHPP
I  out Negative resistance
Vout Infinite bandwidth 3.64m 10.9m 18.2m 25.5m 32.7m
 Conditions for Stability
 The front-end filter and the downstream converter can be modeled with a minor loop
 This loop reflects the action of an impedance divider
Vin  s  1 +
Z th  s  Vin  s   Vth  s  Vth  s  Vin  s 
Z s
Vth  s  Z in  s  1  th -
converter Z in  s 
Z th Z in
gain

 In this particular arrangement, the Nyquist criterion applies for stability assessment

Z th  s 
1  1
Vin  s   Vth  s  Z in  s  Conditions for
Z s oscillations
1  th
Z in  s  Z th  s  Z s
 1 and  th  180
Z in  s  Z in  s 

R. D. Middlebrook, Input Filter Considerations in Design and Application of Switching Regulators, IEEE Proceedings, 1976
 Simulating an Output Impedance
 Once the EMI filter has been determined, you must plot its output impedance
 Check the presence of peaks in the transfer function
 Calculate the necessary damping in case of too high a peaking
100 Ω
Z out  f  10 Ω
OUT IN
=OUT/IN (dBΩ)
POP Trigger

H1
1

100u Z out  f 
10m (°)
R2
R1 L1 150m
V1 AC 1 0
V2 120 I1
C1
4.7u

Output impedance
magnitude and phase
 Simulate the Closed-Loop Input Impedance
 You must now check the input impedance of the converter once stabilized
 Identify the overlap areas and check if sufficient margins exist
 If margins are too thin or if overlaps exist, filter damping is mandatory
OUT IN
=OUT/IN
Z in  f 
H1
1

AC 1 MBR20200CTP Iout
VOUT VOUT

V3
L2
TX1 D3 R21
30m If overlap exists,
Input impedance 600u IC=0
P1 S1 R1
{Rload}

measurement C13
1.36m IC=0 check argument of
Vin
120
Isec Zout/Zin
Idrain VOUT
X1

Vdrain

R4
{R3}
U35
Qdrv OPOUT {C2} IC=0 R5
S1
S Q {Rupper}
R
QN
IC=1
R31
C8
47p IC=0
{R2}
C3
{C1} IC=0
C2
{C3}
Z out ,max  42 dBΩ
R6 C5
U3
 126 
Vclock VCS
U4
1K

100p
R2
R3
250m
OPSIMP
U1

V1 R11
Z out  f 
{Rlower}
V2 C1 {Vref1}
1

330m
FB
Vramp IC=1
1
R8
R9 target
G2 Z out ,max  20 dBΩ  10 
U5
VFB
 Check Input Voltage in Load Step
 Once the filter is installed, check the transient response to see the effects
 With current-mode control, oscillations may be observed on the input rail

iout  t  iout  t 

vFB  t  vFB  t 
vin  t 
vin  t 

vout  t  vout  t 

Transient response without EMI filter Transient response with EMI filter
 Optimally Damping the Filter
 It is possible to show that an optimal RC damper exists to reduce the peaking
 Determine the values of R and C to meet a maximum peak of 20 dBΩ or 10 Ω
 Based on R.D. Middlebrook method, R = 6 Ω and C = 5.45 µF
result

Optimal damping calculations (dBΩ) Z out  f  Z out ,max  20 dBΩ  10 

L1
Z0mm  10 target R0 
C3
 4.613

Z0mm

R0 R0 
2 2
R0  4 Z0mm
2 ( 2  n )    1.16
n 
R0 2 2
n Z0mm
(°) Z out  f 
( 4  3 n ) ( 2  n )
Qopt   1.305 Cdamp  C3 n  5.45 F
2
2 n  ( 4  n )

Rdamp  R0 Qopt  6.02

 Rather than determining R alone and

making C 10x the EMI cap., determine the
Damped output impedance
optimal RC couple to meet the wanted peak
magnitude and phase
C. Basso, Input Filter Interactions with Switching Regulators, APEC Professional Seminar, Tampa (FL), 2017
 Damper is Installed and Oscillations are Tamed
 The RC network is installed across the original capacitor
 Watch for power dissipation as R12 will dissipate ac power

iout  t 

vFB  t 

vin  t 

vout  t 
The damper is installed across
the original EMI capacitor The transient response is clean
 Cascading Converters
 When power stages are associated, check interaction between converters
 The criterion involving the output and input impedance applies
Vsw
47u IC=0
IL
Vsw VOUT_B distribution rail S2
100u IC=0 IL VOUT_BUCK

R21 L2
R15
Iout
15 V rL L1 R1
5V
50m 1u
50m F1
120m
50m
1A
F2 R19
Vin 12.5k R3
+ C7
7 D1 800m
220u IC=0
80m Ideal_Diode + C13
680u IC=4

1.15n IC=0

U35 C6 Qdrv
clock X1
S
R
Q 21.586k 12.85n IC=0
clock
U3 V4
AC 1 0
Open-loop gain
QN R14 C4 S Q
R
QN
DRV
frequency response
U2
Vclock1 OPSIMP
U7 U6
1K V3 R16
2.5k 12.4n IC=0
2.5 R9
U4
R10 1K R8 25
G3
R12 C3 2.5k
100p
C8 1 R4 3.963k 100n IC=0 C1
Vsaw
100p IC=0 126n
V2 R2 R6 C5
C2
1
1
330m 68.085106m
G2 R18
IC=1
1
R17
Vramp
R5 1 OPSIMP
1 IC=1 R11
R7 U1 V1 2.5k
2.5

Boost CM – 7 V to 15 V U5 G1
VFB

Buck CM – 5 V/1 A
 A Stable Response
 You must individually plot output and input impedances of the boost and buck stages
 Then check the stability of the downstream converter in different operating conditions
(dB)
(dBΩ) Tf

Buck Zin
margin fc
capacitive
Z out  f  (°)
T  f 
Boost Zout inductive m

resistive

Closed-loop output/input Buck open-loop gain after

impedances overlap check addition of the damped filter
 Agenda
 SPICE and Power Converters
 The SIMPLIS Approach
 Transfer Functions
 Power Factor Correction
 Interactions with EMI Filter
 Monte Carlo Analysis
 Digital Compensation
 Design Example of a Flyback Converter
 Transfer Function Sensitivity
 The loop gain of a converter involves a power stage and a compensator
 The power stage response is affected by parasitics and the modulator stage
 The compensator response depends on components tolerances including the op-amp
 How will crossover, phase and gain margins be preserved along the production cycle?
CM buck power stage Type 2 filter
s z
1 1
T  s   H0
z 1
1
G0 s Sensitivity
analysis to
 T  Ri 
2
s s  s  s all elements!
1 1
 p1 1    
n Q  n  p Ri
f  fc
Artificial
R 1 1 Se ramp
H0 
Ri 1  RTsw  m 1  D  0.5
c 
 z1 
rC C3
mc  1 
S n Inductor on- T  Ri 
L2   slope

 p1 
1 T
 sw  mc 1  D   0.5 n 

Q
1 Ri f  fc
RC3 L2C3 Tsw   mc 1  D   0.5
 Statistical Parameters Variations
 A Monte Carlo analysis is a multivariate modeling technique
 Assign tolerances to components, see how combinations affect a variable
 Check dispersion on crossover frequency, phase and gain margins

 Chose distribution type like gaussian (normal), uniform or corner (WCA)

gauss(tol) unif(tol) WC(tol)

C. Hymowitz, Monte Carlo Gone Wrong, https://www.edn.com/monte-carlo-gone-wrong/
 Monte Carlo Steps
 You need to place specific probes instructing what parameters to record
 We want to check margins versus components variations

Transfer function Measurement

Goal functions
measurement probes

 Install special probes with a dedicated goal function

 Pick the right goal function in the list like PhaseMargin, GainMargin etc.
 Running the Simulations
 Simulations can be run through the Monte Carlo menu using several computing cores
Vsw {100u*gauss(0.05)} IC=0
(dB)
S2 PhaseMargin(V(out)/V(in))
IL VOUT DVM Phase Margin Histogram
out

Tf
rL L1 BODE_OUT
{10m*gauss(0.05)} BODE_IN in

8
Vin
D1
Ideal_Diode
F1
120m

+
R3
800m GainMargin(V(out)/V(in))
Gain Margin Histogram
fc
C13 out
{680u*gauss(0.2)} IC=4 BODE_OUT
BODE_IN in

XatNthYn(db(V(out)/V(in)) , 0 , 1)
BODE_OUT Crossover Histogram

Qdrv BODE_OUT out

BODE_IN in
X1 V4
U3 AC 1 0
DRV
S Q
R
BODE_IN PM
QN
measurement
(°)
{12.4n*gauss(0.05)} IC=0
U2
R9
C3 {25*gauss(0.01)}
R8

T  f 
U4
1K {100n*gauss(0.05)} IC=0 {2.5k*gauss(0.01)}
{3.963k*gauss(0.01)}

Vclock
V2
R4
100p IC=0
C2
R2
{1*gauss(0.01)}
R6
U1
OPSIMP
C5
C1
{126n*gauss(0.05)} m
1

Vramp
R5 1
1 IC=1
R7
V1 R10
{2.5k*gauss(0.01)}
2.5
U5 G1
VFB

Open-loop gain and

phase variations
 Histogram Representation
 SIMPLIS will build the histogram representation of the parameters we’ve selected
 In this example, all the margins are safe and crossover variations remain narrow

Crossover Phase margin Gain margin

 Agenda
 SPICE and Power Converters
 The SIMPLIS Approach
 Transfer Functions
 Power Factor Correction
 Interactions with EMI Filter
 Monte Carlo Analysis
 Digital Compensation
 Design Example of a Flyback Converter
 Analogue and Digital Compensation
 Stabilizing a control system implies the implementation of a compensation strategy
vout vout

verr


Op amp TL431

 Passive components suffer drawbacks:  No tolerance or age issues Learning

curve
1. Tolerance, aging  Flexibility and optimization
2. Sensitivity to temperature, humidity  Lower crossover systems

Analogue version Digital implementation

 Testing the Digital Filter Structure
 Verify the ac response of the filter before engaging the coding process
 Use a delay line to replicate the block diagram and check the ac response

Y  z Expand
1  z 1 Y  z   Y  z  b1 z 1  U  z  G0  U  z  G0 z 1
 G0
U  z 1  b1 z 1 Rearrange
1 1
Y  z   U  z  G0  U  z  G0 z  Y  z  b1 z

y  n   u  n  G0  u  n  1 G0  y  n  1 b1 Difference equation

 Assemble the blocks to realize the complete architecture

2
1
How can we test
u n G0 z 1 + y  n this
3
configuration?
z 1 b1
 SPICE Can Simulate Delays Efficiently
 We know that z 1 can be modeled via a delay line in SIMetrix®

 Then follow the flow-graph blocks to assemble the filter 1

G s 
s
Input Output 1
p
ba_z^-1
U1
*
u  n u  n  1 G0
y n .param Fs=40k
.param Ts={1/Fs}
.param fp=10k
u  n  G0 .param wp={2*pi*fp}
y  n  1 b1 y  n  1 .param wpw={(2/Ts)*tan(wp*Ts/2)}
.param G0={1-2/(Ts*wpw+2)}
.param b1={(Ts*wpw-2)/(Ts*wpw+2)}
*
Continuous-time
Laplace TF
 Plot Continuous-Time and Sampled Responses
 Pole frequency pre-warping offers an excellent matching with the analogue filter
Analogue
-3 dB
Analogue

Phase / degrees
Gain / dB

-45°

Tustin
Tustin
G f  G  f 

1  The 10-kHz pole is faithfully reproduced by the digital filter

G s   The filter response is validated before coding begins
s
1  Phase response extends beyond -90° with digital implementation
p
 SIMPLIS® Includes 1st-Order Filters Blocks
 A pole-zero equation implemented in SIMPLIS follows the below equation
N 0 1
1
1 z Expand Y  z   Y  z  D0 z 1  U  z  N1  U  z  N 0 z 1
N1  N 0 z N1
T  z   N1 Rearrange
1  D0 z 1 1  D0 z 1 1
Y  z   U  z  N1  U  z  N 0 z  Y  z  D0 z 1

y  n   u  n  N1  u  n  1 N 0  y  n  1 D0

 This is the way the difference equation is implemented

N1

u n N0 z 1 + y  n ? ?

z 1  D0
ZOH included
 Simulate the Filter with a Clock Generator
 A pole-zero equation implemented in SIMPLIS follows the below circuit
POP trigger

 The z-coefficient calculations can be automated

* *
.VAR fp=10k * pole position * .VAR N10=H00*wp*(Tsw*wz+2)/(wz*(Tsw*wp+2)) *
.VAR fz=1k * zero position * .VAR N00=H00*wp*(Tsw*wz-2)/(wz*(Tsw*wp+2)) * N1 = 7.84848498750381
.VAR H0=0 * dc gain in dB * .VAR D00=1-4/(Tsw*wp+2) * N0 = -7.37037054028243
.VAR Fsw=100k * sampling frequency * * .GLOBALVAR N00=0
*
* D0 = -0.521885552778623
* if no zero, set N00= 0 and update N10 with below line * *
.VAR Tsw=1/Fsw * .GLOBALVAR N10=H00*(wp*Tsw)/(1+(Tsw*wp/2))
.VAR H00=10^(H0/20) *
.VAR wp=2*pi*fp
.VAR wz=2*pi*fz
 Sampling Frequency Affects the Respone
 The phase drops faster at a 100-kHz sampling frequency
Sampled data Continuous time-domain
20 20
Fs  1 MHz
G f  G f 

(dB) 10 (dB) 10
1
s
z
Fs  100 kHz G  s   H0
s
f z  1 kHz 1
0 p
0 f p  10 kHz
90 90

G  f  Fs  1 MHz G  f 
45 45

(°) 0 (°) 0

-45
Fs  100 kHz -45

-90 -90
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
 Simulating a PID Compensator
 We have to map the Laplace-domain PID equation in the z-domain

P k p  t 

+  t  vc  t 
u t   I ki    t  
-
d t 
y t  D kd
dt

 A type 3 compensator is a filtered PID with an extra pole!

 s  s 
     1   1  
1  s  d   i   s 2  d i   d i 
N   N  Equivalent  
Gtype3  s   
z1   z2 
GPID  s  
    s  Extra s  s  s 
s i  1  d s  1   1   1 
kp  N    p2  pole  po   p1    p2 
Filter
 A Ready-Made PID Block in SIMPLIS
From type
3 conversion

Ki K d Ad  z  kd
G z  Kp   Kp  kp K i  kiTs Kd 
Ai  z   K d Ad  z   1 Ts Forward-Euler
1
1
  0   p1 ,z  1  kd  0 Backward-Euler
Internal z transfer functions  p1 kd Pole must lie
computed with forward- or
in unity circle
0.5 Tustin
backward-Euler or Tustin

f c  1 kHz G0  1.99
Ts  1 µs
G fc  0 dB K p  k p  2.643
K i  kiTs  2.509m
f z1  200 Hz
kd
f z2  600 Hz Kd   510
Ts
f p1  21 kHz 1 You can choose and
   15m
f p2  21 kHz  p1 k d combine mapping
Externally
functions
Compute PID
implemented
coefficients
 The Sampled PID Response is Close to that of Type 3
 Responses between the PID block and the time-continuous function are very close
 With a 1-MHz sampling frequency, phase degradation is beyond the 1-kHz crossover
G @ f c  0 dB Continuous
time
(dB) G f 
Sampled PID
SIMPLIS
SIMetrix
G  f 

Continuous
(°)
time
Sampled PID
SIMPLIS
SIMetrix
 Practical Implementation with a Buck Converter
 This buck converter is compensated for a 10-kHz crossover and switches at 250 kHz

IL
Vref  k  Vout

Loop delay
FB

Anti-aliasing
filter
 Open-Loop Gain in a Fraction of Seconds
 The crossover is close to our 10-kHz target with an excellent phase margin

(dB)
f c  9.8 kHz
GM  11 dB

Tf

Fs  250 kHz

 m  60
(°)

T  f 
 Digital Control with System Designer
 You can go one step beyond with System Designer for hardware-like compensation
 The program lets you assemble digital blocks representative of the final implementation
X1 FIXED_VAL=1

5
VCC
FIXED_VAL=1

12

PVCC
U3
VBOOT1

330.0n
CB1
IDQ1
FDS6299S_3T
 Compatible with ac
and POP for small-
VCC BOOT VGQ1
12.0 LOUT VOUT
PVCC UGATE
IC=7.7000000000000002
Q1 DCR=560u
PHASE ILOUT ILOAD

IDQ2 390n

signal studies
VGQ2
PWM LGATE vPHASE ICOUT
FDS6299S_3T DELAY=100u
DIGITAL CONTROLLER GND
IFINAL=10
ISTART=0
LOAD
WITH PID COMPENSATOR HIP6601B

 Adjust the number of

Q2 RISE=10u
680u 100n RSRC=119m
AC 1 ESR=6.3m CHFOUT
IC=1.205
4x
CBOUT
V1

IN
=OUT/IN
OUT

Differential Differential Channel PWM1 U1

Trailing Edge PWM
clock cycles linked to
Gain LPF
Error N0
SD Bus Probe
SUBTRACTOR_1 GAIN_1 ADDER_2 SHIFT_2

1
U_DELAY_3

SD Bus Probe
PWM_OUT FROM_PID [0..19]
specific operations
z^-1

 Closer to the real

+ RIGHT
D

- {floor(4186*BIN_SIZE*(512/5))}
error

U_DELAY_2 SD Bus Probe SD Bus Probe SD Bus Probe

ADC z^-1
Error N1

Integral Channel
I PID Sum

SD Bus Probe
hardware
GAIN_2 SHIFT_1 ADDER_3 U_DELAY_1 SHIFT_5 ADDER_4 REG_1 SHIFT_3 Duty cycle
_ 1 7 DATA 4
RIGHT
z^-1 RIGHT REG RIGHT
+ ADC_1 ADDER_1 {floor(272*BIN_SIZE*(512/5))}

DAC_1
CONSTANT_1
{floor(VOUT_NOM/(5/512))}
Integral
Gain
Next
step
SD Bus Probe
GAIN_3 P
Proportional Channel
ERROR

Proportional {floor(160*BIN_SIZE*(512/5))}

Gain
 Agenda
 SPICE and Power Converters
 The SIMPLIS Approach
 Transfer Functions
 Power Factor Correction
 Interactions with EMI Filter
 Monte Carlo Analysis
 Digital Compensation
 Design Example of a Flyback Converter
 Designing a Flyback Converter
 We are going to design a universal-mains 60-W flyback converter delivering 12 V/5 A
 The study is divided in three parts: front-end, converter and control loop
Vbulk 1:0.2
Vout
.
Lp C6x 12 V
600 µH . RLED R1 5A
Cbulk
R2

primary secondary

U1B
Front-end
1 6 Q1 C1
Isolation
2 5 aux barrier
R5
3 4

NCP12510
R6
Rsense
C2 C4
U1A
C3
Control section Regulation
 The Front-End Rectifying Section
 The mains is rectified with a diode bridge and converted to a dc voltage
 A bulk capacitor plays the role of an energy reservoir when the input sine decreases
 The utmost important parameter is the worst-case rms current

 V 
 sin 1  min  
 1 V
2 Pout    peak 
2 Fline 
 4 Fline 
  2
Cbulk     93 µF I C , rms  I avg  1  1.2 A rms
 V peak 2  Vmin 2  3Fline td
Choose 100 µF Vin = 85 V rms

60 V
 Chose the component based on its rms capability at the worst-case temperature
tan 
(µF) (L)
ripple endurance Panasonic rC   3.4 
(D) tan  (hours) 2 120 100u
(mA rms) part-number
Pd  1.162  3.4  4.6 W
sims
 Implement a Constant-Power Load
 The load is the downstream converter which keeps a constant output power
 This is important to increase the absorbed current as the rectified voltage drops

Vbulk

D1 D2 Pin
mur840 mur840
Ibulk

C1 IC=1 P  67 W
100u R1

D3 D4
mur840 mur840

 A PWL resistance mimics the constant-power load with values calculated by Excel
 Determining the Valley Voltage
 The converter shall deliver its nominal current down the rectified valley voltage
 It can imply an oversize of the converter if the ripple is too large – OPP issue
 Increasing the bulk capacitance is a possibility to increase the minimum voltage

iC  t 

Valley
voltage
is 70 V
vC  t 

OPP: overpower protection

 Check Hold-Up Time
 If the mains disappears, the bulk capacitor must maintain the dc rail for some time
 The converter shall continue operation for 10 ms in the worst case
 You may need to increase the capacitance to meet this goal
Vin  100 V rms

Mains
disappears

 The 180-µF capacitor brings 14 ms of hold-up time

50 V BO
vC  t 
 Rms current is 1.1 A and 88 V is the valley at 85 Vac
 Determine Primary Inductance Value
 The primary-side inductance sets the operating mode at nominal load current
 Too small an inductance yields to a high peak current and large conduction losses
 Too high the inductance will lead to slow converter with a low-frequency RHPZ
Adjust ripple I L
 Ir  1 Determine RHP zero position
I L , avg

kc Vout  Vf  transformer turns
Nturns   0.103
BVdss  kd  Vos  Vbulkmax ratio 2
1  Dmax  Rload
2 f RHPZ   34 kHz
 Vout  Vf 
2 2 Dmax Lp Nturns 2
 Vbulkmin   
Lp 
 Nturns   556.424H

  Vout  Vf   Vout  Vf   f c  30%  f RHPZ
I r Fsw  Pout  Vbulkmin         Vbulkmin
Adjust  88 V  Nturns   Nturns  
ripple f c  10 kHz
Lleak  Lp  kleak  3.339 H leakage
BVDSS = 650 V ID,rms = 0.87 A rms
IPP65R190C7
inductance

Vout  Vf
Vclamp  kc  157.5V selected clamp
Nturns voltage PD,cond  0.4 W Choose 2-3 kHz

RHPZ: right-half-plane zero

 Determine Secondary-Side Ripple
 It is important to assess the secondary-side rms current
 Determine power dissipated in the diode  Determine rms current in the capacitor

iCout  t 

Peak Inverse PIV  Vbulkmax Nturns  38.536V

Voltage: Vr
Maximum ESR RESR   0.014 ESR at 100 kHz
value: Isecpeak
ILpeakM
Secondary Peak Isecpeak   17.41A
Current: Nturns Capacitor rms 2 2
ICrms  Isecrms  Iout  6.098A
current:
 2 
 2 Isecpeak  I L I L
  7.886A 2
Secondary rms Isecrms   1  Dmax Isecpeak   Capacitor PC  ICrms  RESR  0.534W
current:  Nturns 2 
Nturns  3 dissipation:
 
20 22 24 26 28 30
Diode power Pdiode  Iout  Vf  2.25W
dissipation:
Vf 1 1

Pd  VT 0 I d , avg  rd I d , rms 2
Pd  V f I out Secondary rms current
rd VT 0 sizes the wire gauge
 Simulating the Basic Converter
 The current-mode structure compensation can be automated
 Verify the operating point is correct at the lowest input voltage (88 V)
MBR20200CTP Iout
VOUT VOUT

Vclp C4 R10 TX1 D3 R21

10n 15k L2 30m
556u IC=0 I2 R1
P1 S1
{Rload}
IC=1 C13 +
R9 680u IC=0
3u
Vin
88 Isec
OPIN FB
L1
1:0.1
IN OUT
=OUT/IN
Leakage and VOUT

clamping network
FB VOUT
IN OUT
Vmod
=OUT/IN Idrain AC 1 0

X1 OPIN
Vdrain
R4 R5
{RLED} {Rupper}
Copto = 2 nF
CTR = 0.3
U35 Optocoupler
DRV S1 U1
S Q
IC=1 C8
FB FB
R R31 47p IC=0
QN

R7
{C1a} IC=10
{Rpullup}
V2 VCS R2 S2
19k + C2
{Ccol} IC=0 C3
U4
U2
-100u
FB TL431_CB
R15 DRV V3
+ {Rr} Vramp 5
R3 IC=1 C1 R6
3.3k R8 100p IC=0 400m {Rlower}
R29
G1
 Vout = 12 V
 Iout = 5 A
 Looking at the Compensation Strategy
 A current-mode converter can be stabilized with a type 2 compensator
 It can boost the phase up to 90° with a zero and a pole adequately placed
 Start with the frequency response at the lowest dc input voltage

H  2 kHz   7 dB From Bode plot

Hf Automate
calculations

H  2 kHz   75

H  f  Vin = 88 V, Iout = 5 A
 The Compensation Path Includes the Optocoupler
 The type 2 compensator can be built around a TL431 and an optocoupler
 The optocoupler exhibits a current transfer ratio and a low-frequency pole
 Always thoroughly characterize the optocoupler including its ac response
VOUT

Copto = 2 nF R4 R5
3k 38k
CTR = 0.3
Optocoupler
FB U1
FB

R7
4.7n IC=10
20k
+

Characterize
+ TL431_CB C2
270p IC=0 C3 U2 the opto O  s 
2.2k Vdd

R13
O s
C7 R6
2u 10k

-3 dB
4 kHz
 Assess Compensated Open-Loop Gain
 Once the stabilization strategy is selected, check crossover and phase margin
 Verify margins in low- and high-line operating conditions
Compensated loop gain Compensated loop gain

Tf  Tf
fc fc

m m

T  f  T  f 

Vin = 88 V Vin = 375 V

 Transient Response at Low- and High-Line Inputs
 Once the converter is stabilized and shows good margins, run transient tests
 Check undershoots are acceptable for the downstream load

(V) vFB  t  (V) vFB  t 

(A) iout  t  (A) iout  t 

(V)
vclp  t  (V)
vclp  t 

vCS  t  800 mV
vCS  t  600 mV

(V) (V)

(V) (V)
vout  t  vout  t 

Vin = 88 V Vin = 375 V

 Look at the Big Picture
 It is now interesting to look at the same converter but powered from the mains
 See the effect of input ripple on variables VBulk
MBR20200CTP Iout
VOUT VOUT

Vclp C4 R10 TX1 D3 R21

D1 D2 C5 R12 10n 15k 30m
mur840 mur840 180u 100k Start-up 556u IC=0
P1 S1 I2 R1
Lp 2.4
current IC=1 C13 +
R11 U5 R9 680u IC=0
3.4 Vcc Vdd
V1 Vcc 3u
D4 D5
mur840 mur840 UVLO
Isec
Ic + C6 I1 Lleak
50u VOUT
V4 UVLO Idrain

10u IC=8 10 UVLO circuit Vdrain

Copto = 2 nF R4 R5
Circuit consumption 3k 38k
CTR = 0.3
U35 Optocoupler
200u DRV S1 U1
S Q FB FB
IC=1 C8
Vcc Vdd R R31 47p IC=0
QN
V2

G2 R7
U3 4.7n IC=10
20k
VCS R2 S2
19k + TL431_CB C2
270p IC=0 C3 U2
UVLO U4
2.2k Vdd
-100u
FB
R15 DRV R13
+ 2k Vramp
R3 IC=1 C1 C7 R6
3.3k R8 100p IC=0 420m 2u 10k
R29
G1
 Looking at the Start-Up Sequence
 The start-up sequence takes a simulation time of 30 s for a 100-ms run
Bulk capacitor current

Output current

Sec-side current

High-voltage rail

Clamp voltage Clamp voltage overshoot

CS voltage

Check BVDSS
margin

Output voltage
Vin = 85 V rms
 Check the Contribution of the Combined Currents
 The bulk rms current is made of low- and high-frequency ripple

iCbulk  t 
100 kHz
(A)

vbulk  t 

(V)

Vin = 85 V rms
 Conclusion

 Simulating your power supply is an important part of the design flow

 SPICE simulation is an option but simulation time and lack of switching ac analysis is a problem

 SIMPLIS with its PWL engine delivers results in a flashing time

 An averaged model is no longer necessary and ac response is available from switching circuits

 It is a particularly-interesting features for resonant converters for which modeling is difficult

 Having the ability to test digital compensators before coding is an advantage

 Quick simulation is also a tremendous advantage for power correction circuits