DVCon India 2025 Design Contest - Problem Statement

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DVCon India 2025 Design Contest - Problem Statement

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balasaravanan4165

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Problem Statement

Artificial Intelligence (AI) applications are becoming pervasive in all domains

of human existence. AI is increasingly woven into the fabric of daily life,
transforming how we work, communicate, and even think. From voice
assistants and smart devices to personalized recommendations on
streaming platforms, AI constantly enhances convenience and efficiency. In
industries like healthcare, finance, and education, AI is driving innovation
and improving outcomes. It is also reshaping job markets, creating new roles
while automating routine tasks. As AI continues to evolve, its influence
grows, shaping everything from social interactions to global economies.

However, running these applications efficiently on resource-constraint

devices still remains a significant design challenge. In this Design Contest
we will be testing your hardware design skills in implementing an AI
application of your choice on a resource-constraint edge device having
VEGA Processor, indigenously developed by CDAC Trivandrum at the heart
of it. You will essentially be designing an acceleration IP to support complex
computation of your AI application running on VEGA processor. This contest
is divided into three stages.

In stage 1 you will first propose an AI based application useful in solving real-
world challenges. You will propose a design plan on how this application can
run on the VEGA processor, for which you will familiarize yourself with the
VEGA processor and Genesys-2 board. You will understand the available
hardware resources on Genesys-2 board using which you may design your
novel acceleration IP. You may also identify any sensors (camera,
temperature, proximity etc.) that your AI application may require.

In stage 2, you will design a novel acceleration module (IP) or accelerator

that can be integrated with the VEGA Processor and gives a significantly
better performance on running the AI application compared to the original
system without acceleration unit. This is a simulation stage, where you will
test your design using simulation tools.
In stage 3, you will be implementing the complete design on Genesys-2
board. You will demonstrate that your novel IP is working well when
interfaced with VEGA processor and sensors giving better performance.

Stage-1

Tasks to be completed:
1. Familiarize with the architecture of VEGA Processor, interfaces and
software packages.
2. Familiarize with Genesys-2 board and its available ports.
3. Propose the AI based application with real-world application
(healthcare, autonomous driving, robotics, smart city, Industrial
automation, Business & Finance etc.)
4. Discuss your big design idea on how to accelerate the AI application
of your choice on the VEGA processor. What kind of compute
acceleration IP you envision to design and your rationale for the
same.
5. A detailed report with the relevant block diagrams should be
submitted that includes design idea, supporting preliminary study or
experimental results.

Stage-2