Manaboti Balaji
Phone & WhatsApp: +91 6281347613
Email: [email protected]
Gender: Male | Date of birth: 26/07/2003 | Nationality: Indian
OBJECTIVE:
Recent graduate with specialized training in physical design, including floor planning, power planning,
placement, clock tree synthesis (CTS), routing, and Timing Analysis. Eager to apply my hands-on experience
with EDA tools and my strong understanding of IC design principles to contribute to the development and
optimization of high-performance semiconductor products. Seeking an opportunity to work as a Physical
Design Engineer in a dynamic organization where I can further enhance my skills and contribute to impactful
projects.
INDUSTRIAL EXPERIENCE:
[6 Months]
VLSI Physical Design Intern
Maven Silicon
City: Bangalore | Country: India
• Gained hands-on experience in optimizing digital designs using industry standard EDA tools.
• Worked on converting RTL code into an optimized gate-level netlist, ensuring high-performance
designs.
• Good Understanding in Static Timing Analysis (STA) to evaluate timing constraints and optimize
designs for functionality and speed.
• Gained practical knowledge in place and route for VLSI designs, focusing on floor planning,
placement, routing and Timing analysis of standard cells while minimizing power consumption, area,
and delay.
• Collaborated with senior engineers to analyse and optimize designs, ensuring they met both
performance and area requirements.
• Developed some automated scripts to smoother the design and good understanding in verification
concepts, including Design Rule Checking (DRC) and Layout Versus Schematic (LVS).
TECHNICAL SKILLS:
• PNR Tool: Innovus & ICC2
• STA: Primetime
• Synthesis: Design Compiler & Fusion Compiler
• Languages: Tcl
• Operating Systems: Linux, Windows
PROJECTS:
Project1: Block-Level Implementation (TSMC 28nm)
• Description: The project involved a block-level design with 55k gates and 26 hard macros.
• Technology : TSMC 28nm
• No of Clocks :4
• Clock Frequency :500Mhz
• Tools : ICC2 , Prime Time
• Metal Stack :9
• Role & Challenges
o Responsible for Block level PnR Implementation.
o Involved in PnR and ECO stages includes Sanity Checks, Floor Plan, Placement, Timing
Optimization, CTS, Routing, Timing Analysis.
o Performed sanity checks and did various iterations of Floor planning.
o Generated the reports of each stage in PNR tool.
o Analysing the timing and resolved them to meet.
o Performed various iterations to resolve the Floorplan issues.
o Placement has been challenging for reduction congestion tried different types of macro
placement.
o Did place experiments by doing path groups to improve QOR.
o Carried out post route ECOs like cell upsizing/downsizing, buffer insertion, load splitting net
improvement techniques to fix timing violations.
Project-2 : Block-Level Implementation (TSMC 28nm)
• Description: The project involved a block-level design with 35k gates and 8 hard macros.
• Technology / Layers : TSMC 28nm / 9 layers
• No of Clocks :4
• Tools : Innovus
• Frequency : 1Ghz
• Role & Challenges
o Block level PNR includes Floorplan, placement, CTS, and Routing .
o Validate inputs like netlist, libs and constraints after importing design.
o Performing the best Floor plan which includes placing the macros.
o Multiple Macro Placements done for meeting timing and Congestion.
o Reduced congestion by adding blockage and padding .
o Applied various strategies to meet skew and Latency in CTS stage.
EDUCATION:
o B.Tech in ECE from Rajeev Gandhi Memorial College of Engineering & Technology, Nandyal with
8 points.
o Polytechnic (Diploma) in ECE from S.V Govt polytechnic, Thirupathi with 76%.
DECLARATION:
I hereby declare that the information furnished above is true to the best of my knowledge.
Signature: Balaji Manaboti Place: Bangalore
