Cells in ASIC Physical Design

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 Cells in ASIC Physical Design
Cells in ASIC Physical Design
• Special Cell Requirements in IC Design is to minimize
the possible CMOS issues
• More no. of transistors than are necessary for
basic functioning. e.g.,
— To limit the Overshoots and Undershoots
— To protect the components from destruction
— To isolates 2 components by PN Junction
• Common Special Cells used in CMOS IC Design:
▪ Standard Cells
▪ ICG Cells
▪ Well taps (Tap Cells)
▪ End caps
▪ Filler Cells
▪ Decap Cells
▪ ESD Clamps
▪ Spare Cells
▪ Tie Cells
▪ Delay Cells
▪ Metrology Cells 34
 Cells in ASIC Physical Design
Standard Cells
• A Standard Cell is a group of transistor and its interconnect
structures that provides a Boolean logic function (e.g., AND, OR,
XOR, XNOR, Inverters) or a storage function (Flip-flop or Latch)
• Std. Cell methodology
has helped designers to
scale ASICs from
comparatively simple
single-function ICs, to
complex multi-million
gate SoCs
• Cell-based methodology
makes designer to focus on
the implementation
(physical) aspects
A Standard Cell Layout 35
 Cells in ASIC Physical Design
Standard Cells
\emdash The cell's Boolean logic function is called its logical
view: functional behavior is captured in the form of a truth
table or Boolean algebra equation (for combinational logic), or
a state transition table (for sequential logic)
\emdash AOIs (AND-OR-INVERTER) provide a way at the gate
level to use less transistors than separate ANDs and a NORs
\emdash ASIC design logic builds upon a standard logic cell
library, therefore, do not optimize transistors only logic gates
\emdash Types of Standard Cells
— Buffers (Inverting and Non-inverting )
— Combinational (AND, OR, NAND, NOR, AOI, OAI, OA, AO, MUX)
— Arithmetic (XOR, full-adder, half-adder), Sequential (latches, clock-
gates, D-type flip/flops with any optional combination of scan input,
set and reset)
— Miscellaneous (ICG Cells, Well Taps, Tie Cells, End Caps, Decaps, Filler
Cells, Spare Cells, Delay Cells, Antenna Diode, ESD diodes)
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 Cells in ASIC Physical Design
ICG Cells
• Integrated Clock Gating Cells (ICG Cells)
— During idle modes, the clocks can be gated-off to save dynamic power dissipation on flip-flops
— Proper circuit is essential to achieve a gated clock state to prevent false glitches on clock path
— Use a combination of AND and a Latch to avoid any glitches on the clocks. A glitch can propagate a false
edge on to the design
• Insertion of ICG
— Manual insertion of ICG
The clock gating can be implemented through logic circuits and ICG’s
Most of Clock Gating Cells from vendor libraries have a RTL code
— Automated Insertion of ICG –
Some power aware tools insert the ICG’s
through automated software algorithms
\emdash Types of Clock Gating Cells
— Latch Based Clock Gating Buffer for Neg-edge Latch Based Clock
The circuit employs a latch and OR gate with one input inverted Gating Buffer Negedge
The output clock is always clock gated low when Enable is low
— Latch Based Clock Gating Buffer for Pos-edge
The circuit employs a latch with inverted clock input and a AND gate
The output clock is always clock gated HIGH when Enable is low
• ICG module IO’s
— 3 input ports – clock, clock enable and test
— 1 output port – clock for gated clock
Latch Based Clock
Gating Buffer Posedge
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 Cells in ASIC Physical Design
Well Taps
• Physical only cell which helps to tie MOS Substrate and N-Wells to VDD
and GND levels, and thus avoid latch-up possibilities
• Switching circuits dump current into Well/ Substrate and if there is a high
resistance between Well/ Substrate and the VDD/ GND grids the Substrate
can be at different potential than VDD/ GND which causes latch-up
• Well Tap Cells reduce resistance between
VDD/ GND to wells of the Substrate
• Tap Cells are usually placed on the
Power Rails of the Standard Cells
• Standard Cells do not have internal
tap to N-well (P substrate process) to
reduce design complexity of Standard Cells
• These library cells do not have any
signal connectivity
• Hence Tap to Wells is done by external
cells called "Tap cells" which are sprinkled
all over Core Area at regular distance as decided by the foundry
• More Taps reduces resistance, but will also increases core area, so we
need a trade-off which will be provided by the foundry
• Place well taps at regular intervals throughout the design with the
specified distances and snaps them to legal positions
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 Cells in ASIC Physical Design
End Caps
\emdash End-cap cells are preplaced physical-only cells required to meet
certain design rules and placed at the ends of the site rows by satisfying well
tie-off requirements for the core rows
\emdash These library cells do not have any signal connectivity
\emdash They connect only to the power and ground rails once power
rails are created in the design
\emdash They also ensure that gaps do not occur between the well and
implant layers i.e. well proximity effect
\emdash This prevents DRC violations by satisfying well tie-off requirements
for the core rows
\emdash Each end of the core row, left and right, can have only one end
cap cell specified
\emdash However, you can specify a list of different end caps for inserting
horizontal end cap lines, which terminate the top and bottom boundaries of
objects such as macros
\emdash End caps have a fixed attribute and cannot be moved by
optimization steps
\emdash A core row can be fragmented (contains gaps), since rows do not
intersect objects such as power domains. For this, the tool places end cap cells
on both ends of the un-fragmented segment
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 Cells in ASIC Physical Design
Filler Cells
• Physical only cells which provide N-Well
continuity and avoid N-Well spacing DRC
• Filler cells are inserting for density rules, to meet
Core Utilization targets and to avoid sagging of layer
• Filler cells are inserting at the last stage
of Placement and Routing
• Some of the small cells also don’t have the
Bulk/Substrate connection because of their
Filler Cell Layout
small size (thin cells)
\emdash In those cases, the abutment of cells through inserting
Filler Cells can connect those Substrates of small cells to VDD/ GND
nets
\emdash i.e. those thin cells can use the bulk connection of the other cells
\emdash Filler cells are used to make up the Poly density (if that filler
cell is having any poly structure inside), but certainly not for metal
density
\emdash Filler cells are also useful for ECO
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 Cells in ASIC Physical Design
Decap Cells
\emdash Decaps are on-chip decoupling capacitors (Extrinsic Capacitances) that are
attached to the power mesh to decrease noise effects (dynamic I.R. Drop)
\emdash Supply voltage variations caused by Instantaneous Voltage Drop
(IVD) lead to problems related to spurious transitions and delay variations
\emdash Decap cells are typically poly gate transistors where source and drain are
connected to the ground rail, and the gate is connected to the power rail
\emdash Decap helps to smoothen out the Glitches and Ground bounce
\emdash 3% to 8% of the core physical area is required for Decaps refered as decap density
\emdash It is important to place only the necessary amount of decaps since they
normally come with a quite serious down- side as they are leaky devices
\emdash Another drawback, which many designers ignore, is the interaction of the
decap cells with the package RLC network
\emdash Since the die is essentially a capacitor with very small R and L, and the package is a
hug RL network, the more decap cells placed the more chance of tuning the circuit into its
resonance frequency. That would be trouble, since both VDD and GND will be oscillating
\emdash NMOS Decaps are superior to PMOS decaps because of the high frequency
operation and large REFF and CEFF for the same area

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CMOS Decap
 Cells in ASIC Physical Design
ESD Clamps
• ESD Clamp/ ESD Diode is the primary protection device that protects
against ESD surges at the I/O pad by clamping the voltage and allowing the
high ESD current to be discharged safely to the ground terminal
• The main function of ESD Clamp is to protect the Gate oxide
• Snap back device (Diode implementation between the grounds)
provides Snapback voltage (ESD Voltage) to get grounded thus the ESD current
won’t be getting in to Gate
• The design of ESD Clamp must ensure that Electrical Overstress
(EOS) events do not cause failure
• The ESD Clamp is essential for HBM, MM, and CDM

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 Cells in ASIC Physical Design
Spare Cells
\emdash Pre-placed inactive (with inputs tied off) gates in the empty areas
of a design (or even in the crowded areas) before tape-out (Mostly NAND Gates)
\emdash ECO Cells/ Spare Cells are collection of Gates coming in different
sizes for doing small functional ECO and connect them with minimal mask
changes called a metal-only ECO
\emdash Provides new functions on a design which exhibits post-
production problems
\emdash No change is made to the diffusion
layer, M1 and a contact layer only
need to change
• Disadvantages:
— They are connected to VSS and VDD and
despite having their inputs tied off, they
are still drawing Static Current
— The designer may not have the right cell
in the right place at the time of the ECO
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 Cells in ASIC Physical Design
Tie Cells
• Tie-high and Tie-Low cells are used to connect the
Gate of the transistor to either Power or Ground
• In deep sub micron process, if the Gate is connected
Output
to Power/ Ground, the transistor might be turned Input
ON/ OFF due to Power or Ground Bounce
• The suggestion from foundry is to use Tie Cells for
the purpose
• The cells which require VDD, comes and connect to
Tie High (so Tie High is a Power Supply Cell), while the Tie-up Cell
cells which wants VSS connects itself to Tie-Low
• Without Tie Cells, unused inputs are tied to logic-high
or logic-low, and these connections are made by routing
the input pin right to the Power/ Ground grid
Input
• With Tie Cells, unused inputs in the original netlist Output
are tied to logic-high or logic-low, and somewhere during
the physical design process, Tie Cells are inserted
\emdash The unused inputs are then connected to a
Tie-high or Tie-low Cell
Tie-down Cell 44
 Cells in ASIC Physical Design
Delay Cells
• Delay cells
— Are buffer cells with slower transition time
— Can drive high currents
— Are helpful in reducing Slew Rate (0-1 or 1-0 Transition Time)
— Are of wider channel
— Have delay starting from 20ps to few Nano seconds
— Will have constant delay
• Delay cell insertion is the conventional way to fix hold time
violation tends to penalized in area percentage increment
• Lesser number of delay cells are required for hold time fixing as
compared to buffers but it will have area much greater than normal
buffers
• Increasing gate width reduces gate capacitance hence
reduces delay, but results in higher leakage
• It has inverter in input and a inverter in output and in between
these two inverters it has a combination of a inverter and pass
transistors. Pair of inverter and pass transistor provide at large delay
• Depending on the delay of the cell, pair of inverter and
pass transistor can be repeated multiple times
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 Cells in ASIC Physical Design
Metrology Cells
• To enable the reliable re-productivity of micro-scale
devices used in high volume and low cost
• To measure and monitor the process parameters
during manufacturing
• The effect of process variations during fabrication time can
be identified and measured

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IO Design

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 IO Design

IO Pads
\emdash Input Output Pads
— Input/ Output circuits (I/O Pads) are
intermediate structures connecting
internal signals from the core of the
integrated circuit to the external
pins of the chip package
— Typically I/O pads are organized into
a rectangular Pad Frame
— The input/output pads are spaced
with a Pad Pitch
— Pads will have pins on all metal layers
used in design for easy access while
routing the design
— Number of layers depends on
technology
— Multiple Power Pads are often used to reduce the power
— Pads consists of some logic cells like level shifters and buffers which will
control the voltages of input and output signals and to increase/
decrease drive strength
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 IO Design
IO Pads
• Structure of Pads
— Bonding Pad
Area to which the bond wire is soldered
The wire goes from the bonding pad to a chip pin
— ESD (Electrostatic Discharge) protection circuitry consisting of a pair of
big PMOS, NMOS in a reverse biased diode structure
— Driving and Logic Circuitry for which the area of is designated

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 IO Design

IO Pad Design
• Implementation Guidelines
— Isolate sensitive asynchronous inputs such as Clock or Bidirectional Pins from
other switching pads with Power/Ground Pads
— Group Bidirectional Pads together such that all are in the input/ output mode
— Avoid continuous placing of simultaneous switching pads
— 2 extra pins = 1 extra pad on 2 sides and 4 extra pins = 1 extra pad on each
side
— Power supply pads must be evenly distributed
— The number of Power Pads required are calculated based on the IO Signal
Pads power requirement and Core Power requirement (IR drop limit)
— No. of IO Power Pads required in a design,

Thumb Rule: One Pair of Power Pads for every 4 or 6 Signal Pads
— No. of Core Power Pads required in a design,

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 IO Design
IO Pad Design
• Pad Limited design
— The area of Pad limits the size of Die
— No. of IO pads are more or larger in size
(technology dependent)
— Pad limited designs pose several challenges
for design implementation and to the
backend designers, if Die area is a constraint
— The Solution would be to use Flip Chip or
Staggered IO placement techniques
• Core Limited Design
— The area of Core limits the size of Die
— No. of IO Pads are lesser
— In these designs Inline IOs will be used
— It can be either due to large no. of Macros the design or due to larger logic
• Types of Pads according to Logic directions
— Input Pad
— Output Pad
— Bidirectional Pad
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 IO Design
Types of IO Pad
\emdash Types of Pads according to Logic Styles
— Signal Pads
— Power Pads (Core Power and IO Power)
— Corner Pads
Corner pads contains only connections
in all metal layers defined in technology
These pad used only for IO Ring continuity
and chip metal density on corners and to maintain yield
— Filler Pads
IO Filler Cells contains only the geometrical information of the Power Rings
in all metal layers
Continuity of Power Rings which is responsible for uniform distribution
of power
Electrostatic Discharge protection

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 IO Design
Types of IO Pad
• According to the Pad locations
— Peripheral IO Pads
— Area IO Pads

• Types of Pads according

to Implementation Styles
— Inline Area IO Pads
— Staggered Peripheral IO Pads
CUP (Circuit-Under-Pad)
Non-CUP (Circuit-Under-Pad)
— Flip Chip

• Inline IO Pads
— Pads are placed next to each other,
with the corresponding bond
pads lined up against each other
having a small gap in between Inline IO Pads
— Minimum Pitch is determined by foundry/vendor and is technology dependent
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 IO Design
Types of IO Pad
• Staggered IO Pads
— CUP (Circuit-Under-Pad)
Bonding Pad over the IO body itself Inner PAD Inner PAD
Bonding Pad have to connected to
the PAD Pin of IO
Pad pin is located close to the center Outer PAD

of the IO body for easier routing, signal integrity, and

space saving
⬧ Reduce the die size since the Bonding Pad does not take any extra
space in addition to the IO body itself
⬧ Advantages include more no. of IO’s, Optimal area utilization, Lower cost
— Non-CUP (Circuit-Under-Pad)
⬧ Useful technique if design is “Pad Limited”
⬧ Place an inner and outer Bond Pad alternately
⬧ A larger number of pads can be accommodated
⬧ Disadvantage is that the overall height of
the pad structure increases significantly
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