Institute of Electronics

Technische Universität Graz

Circuit Simulation

Delivery 4

Markus Hannes Mayr

Rene Denifl

21. Juni 2022

Inhaltsverzeichnis
1 Exercise 1: Cyclic ADC 2
1.1 Sample and hold stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Comperator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6 Subtraction circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.7 Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.8 Full assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.9 8 bit conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Exercise 2: individual circuit. DCDC boost-converter 11

2.1 Operation of the boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 dimensoning the circuit of the boost converter . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 output voltage and output ripple of the boost converter . . . . . . . . . . . . . . . . . . . 13
2.4 effects of a varying duty-cycle on the output voltage and ripple . . . . . . . . . . . . . . . 14
2.5 Power conversion efficiency for a specific duty-cycle . . . . . . . . . . . . . . . . . . . . . . 17
2.6 Power conversion efficiency for different duty-cycles . . . . . . . . . . . . . . . . . . . . . . 18
2.7 Stability of the output voltage on a load resistance step . . . . . . . . . . . . . . . . . . . 19

1
1 Exercise 1: Cyclic ADC
A cyclic analog to digital converter works by recursively executing a comparison operation. A voltage is
compared to the reference voltage. The reference voltage is chosen to be half of the full range voltage (=
half the max voltage), which results in our case to 2.5V. Basically, a binary tree search is done to narrow
in on the input voltage. The feedback loop first subtracts the ref voltage or nothing, depending on the
comparator output. Then the resulting voltage is multiplied by two and feed it into the next comparison
loop. This works only for analog input range starting at 0V (going up to a arbitrary upper limit).

1.1 Sample and hold stage

A sample and hold stage is an idealized component, which stores the input voltage at the exact moment
when receiving the sample signal and afterwards holding this exact voltage indefinitely at the output.
This circuit has a one time trigger like for example a rising edge. On the other hand, the track and hold
circuit receives a binary signal. If the input signals track-mode, the input voltage is passed through to the
output. When the signal switches to hold mode, the most recent input voltage is kept stable at the output.

Fundamentally, both of these ideal stages can’t be build with analog circuits. The track and hold stage
can be build with relatively little differences to an ideal stage. It consists of a transmission gate which is
switched by the input signal and a capacitor to hold the voltage. To improve the circuit (high impedance
input and low impedance output) voltage-follower-opamps could be used at the in- and output.

Building a ideal sample and hold stage on the other hand is a much more complex task.
First, to get an impulse to trigger the sampling from a clock signal, the inverting gate and a AND gate
is used. To make this (and all other digital elements) work, the digital parts have the following settings:
Vhigh = 5, Td= 1n. Vhigh sets the true output voltage to 5V and the input true/false threshold to 2.5V.
Td sets a timedelay from input to output. This then triggers a SR-flipflop which switches the transmission
gate (N- and PMOS) on and off. To make the input impedance high, a opamp is used (luckily, the general
ltspice opamps have ideal rail to rail properties, otherwise some kind of booster circuit has to be utilized).
Through the transmission gate a capacitor is charged. The capacity is chosen in a compromise between a
high impedance to provide a stable output and a low impedance to charge fast. At the end there is another
opamp to provide a low output impedance. The interesting part comes into play when deciding when to
switch the transmission gate off again. There could be a timedelay which factors in the worst case charging
time of the capacitor. But in a more fortunate case (the capacitor voltage only differs slightliy from the
input voltage), there is a time when the stage operates in tracking mode. To mitigate this problem, the
transmission gate can be switched off, when capacitor voltage and input voltage are sufficiently close.
In this specific implementation the hold stage is switched off when the absolute difference (two cases:
Vinput > Vcapacitor or Vinput < Vcapacitor , both build separately and connected with OR) of input and
capacitor voltage is sufficiently small. To increase accuracy, the difference is multiplied by 100 before
being interpreted by an logic gate. If both signals are low ( not(Sig1 or Sig2) ) a reset signal is send to
the Flipflop stopping the transmission and holding the sampled voltage.

2
 Abbildung 1: Sample and hold stage schematic

Abbildung 2: Sample and hold stage plot

1.2 Clock
The clock uses counter circuits to subdivide the main clock. At first, the main clock is subdivided once and
then, with the help of inverters and AND-gates recombined to create subclocks with shifts to sequence
the operations of the adc. Then there are further subdivide counters to automatically create the reset
signal to start new conversions.

3
 Abbildung 3: Clock schematic

Abbildung 4: Clock plot

1.3 Comperator
To build a comperator, a simple opamp without feedback is used. To be precise, there is a small error
introduced by this design. The digital inputs of the register and the multiplexer shift at a voltage of 2.5V.
This means, Vin1 is only recognized as being greater than Vin2 , if (Vin1 − Vin2 ) · AOP AM P > 2.5V . Due
to the high amplification of the opamp, this error is negligible.

Abbildung 5: Comperator schematic

4
1.4 Multiplexer
The multiplexer creates (with the nand gate) a normal and inverted signal, which each powers a separate
transmission gate. When switching the input, both transmission gates switch state and the output signal
follows the other input.

Abbildung 6: Multiplexer schematic

Abbildung 7: Multiplexer plot

5
1.5 Multiplier
The multiplier uses a non inverting amplifier to create a two times multiplier (and 100 times multipliers
for the sample and hold stage). The factor minus one results in the final amplification.

Abbildung 8: Multiplier schematic

Abbildung 9: Multiplier plot

1.6 Subtraction circuit

The subtraction circuit utilizes a summing inverting amplifier circuit to subtract one signal from another
without any amplification. To increase the input impedance, voltage followers are used at both inputs.

6
 Abbildung 10: Subtract circuit schematic

Abbildung 11: Subtract circuit plot

1.7 Shift register

To store the four most recent results of the cyclic adc a shift register is used. It uses a series of D-Flipflops.
In reality there should be some concerns about sequencing, but in the simulation this works fine.

Abbildung 12: Shift register schematic

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 Abbildung 13: Shift register plot

1.8 Full assembly

The full ADC functions by repeating the same operation multiple times (one time for each bit of reso-
lution). It needs two sample and hold stages, one to hold the actual input voltage and one to buffer the
error voltage of the previous conversion to feed back into the adc.

Abbildung 14: Full adc schematic

To visualize the result, the following formula is used:

(V (d0) · 20 + V (d1) · 21 + V (d2) · 22 + V (d3) · 23 )/15 (1)

With this formula the resulting value of 0 - 15 (= 4 bit) is scaled to 0V - 5V. This allows a direct visual
comparison of analog input and digital output.

The output of the adc can be read when the conversion is finished. This can be seen in the plot by looking
at the most recent value of the output when the clk start signal triggers a new conversion. (To make the
result more easily visible in the 500 sample plot, the output is set to 0 whenever the result is invalid)

8
 Abbildung 15: 3V adc conversion plot

3V
The adc gives the expected result of 5V · 15 = 9.

Abbildung 16: 500 samples adc plot

When analysing the plot it might seem like there is a inherit nonlinearity in the plot. (switching from
0-1 too late and from 14-15 to early). But in fact this is a problem which is a result from the non-perfect
sample and hold stages. The trigger mechanism ending the ttracking-modeöf the sample stages can be
triggered by either narrowing in on the offset from a positive or negative difference. Therefore, the sam-
pled value is, to a certain degree, dependent on the most recently sampled voltage (in case of this adc
it is the voltage for the comparison of determining the state of the least significant bit of the previous
conversion).

Additionally, the input voltage is only rising, so the switches from e.g. 3 to 4 seems to be at an exact
voltage when in reality, voltages that are on the edge between two different results (e.g. 2.5V could result
in 7 or 8) will be randomly fluctuating in some range around the edge case voltages (e.g. +-50mV)
depending on the previous conversion as described above.

1.9 8 bit conversion

To change the adc from 4 to 8 bit there are only little changes necessary. At first, the signal triggering
a new conversion is subdivided once more, so it only triggers every eight main clock cycles (making the
conversions half as fast). The other change is expanding the output shift register to hold eight bits.

Abbildung 17: 8 bit clock schematic

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 Abbildung 18: Expanded shift register schematic

Abbildung 19: 3V 8bit adc conversion plot

The adc gives the expected result of 3V

5V · 255 = 153. To improve the precision, the multiplication factor
of the multipliers in the sample and hold stage can be increased. Generally, the accuracy of the adc is at
its limits because the error from each conversion sums up and with eight repetitions it is substantial.

10
2 Exercise 2: individual circuit. DCDC boost-converter
The individual circuit chosen for the second exercise is a DCDC boost-converter that should take a 5V
input voltage from a Microcontroller or any other voltage source and output a 12V output voltage that
can be used to power a relay or other electronics requiring such voltages without having to use a rectifier
circuit or another higher voltage source.

2.1 Operation of the boost converter

Abbildung 20: circuit of an ideal boost-converter

In figure 20 one can see the circuit of an ideal boost converter with ideal components. The boost converter
uses the coil, as well as the switch, the diode and the output capacitor in order to create an output voltage
vout > vin .
In the ON-Stage when the switch is closed the voltage on the coil equals the input voltage vS . The
current flowing
R t +t through the coil will rise in a linear fashion since the voltage on the coil is constant
iL = L1 · t00 vS · dt ≈ L1 · vS · t.

In the OFF-Stage when the switch is open the current of the coil wont suddenly drop, but instead
it will flow through the diode and charge the capacitor. The voltage on the coil will reverse its polarity
and the resulting output voltage
R t +t is higher than the input voltage. The current flowing through the coil
can be written as iL = L1 · t00 (vS − vo ) · dt ≈ L1 · (vS − vo ) · t

The Boost converter has two distinct modes of operation, continuous and discontinuous mode. The
key difference lies in the current flowing thought the coil in the OFF-Stage of the boost-converter. If in
the steady-state the current flowing through the coil never goes back to zero than the converter runs in
continuous mode. If the current goes back to zero before the next ON-Stage than the boost-converter
runs in discontinuous mode.
Both modes provide different behaviour and different equations for the relationship between the input
and the output voltage. For the circuit used only the continuous mode of operation is of interest since it
features lower dynamic switching power loss mechanisms.

In continuous mode the duty cycle of the circuit is defined as D = tONt+t ON

OF F
. This duty cycle defi-
nes the relation between the input and the output voltage. Ideally in the steady-state of the circuit the
change in the current flowing through the coil will be zero on average, so ∆iL,ON + ∆iL,OF F = 0. This
relation can be used in order to derive the relationship between the input and the output voltage for the
ideal boost converter.

∆iL,ON + ∆iL,OF F = 0
1 1
· vS · tON+ · (vS − vo ) · tOF F = 0
L L
1 1
· vS · D · T + · (vS − vo ) · (1 − D) · T = 0
L L
vS · D + (vS − vo ) · (1 − D) = 0
vS · D + vS · (1 − D) − vo · (1 − D) = 0
vS − vo · (1 − D) = 0
vS
vo = (2)
(1 − D)

11
This is the ideal relationship between the input and the output voltage if one where to neglect all non-ideal
effects of the components. This relation only stays true when the boost-converter stays in continuous mo-
de. To ensure this the inductance value of the coil needs to exceed a certain value for a fixed load-resistance.

Since the converter will go into discontinuous mode once the coil current goes back to zero during the
OFF-Stage one can derive the minimum value for the inductance needed to ensure that the converter
stays in continuous mode.
in discontinuous mode the coil current during the OFF-Stage can be written as ∆iL,OF F = L1 · (vS −
vo ) · D1 · T , with D1 being the cycle were the coil current is not yet zero. Here D1 can be derived with
the current flowing through the Diode ID = Imax2 ·D1 = Rvload o
and Imax = vS ·D·T
L one gets the following
expression for D1 :
vo 2L
D1 = ·
vS Rload · D · T
The converter goes into discontinuous mode once D + D1 = 1 which gives the following expression for
the critical inductance.

1 = D + D1

vo 2Lcrit
1=D+ ·
vS Rload · D · T

Rload · D · (1 − D) · vS · T
Lcrit = (3)
2 · vo
With the critical inductance known one can start designing a boost-converter for the desired output
voltage and load resistance.

The output ripple vo,ripple is another important aspect of the circuit. It can be derived using the Capacitor
value at the output. During the charging stage in the OFF-stage the capacitance charge is ∆Q = io ·D ·T .
The change in the voltage on the capacitor is defined as:
∆Q io · D · T
vo,ripple = ∆vo = = .
C C

2.2 dimensoning the circuit of the boost converter

The boost-converter should be able to take a 5V input voltage and output a 12V output voltage. The
control voltage used to switch the MOSFET of the boost-converter is a PWM-Signal with a switching
frequency of fS = 500kHz or a Period of T = 2µs. The output power of the boost-converter should
be around 3W, which is an arbitrarily chosen value. This desired output power means that the load
)2
resistance has to be about R = (12V
3W = 48Ω.

In order to get an output voltage of 12V from an input voltage of 5V one needs to set the duty-cycle
accordingly too. The duty-cycle can be derived from equation 2 and for an input voltage of 5V and an
output voltage of 12V one gets a duty-cycle of D = 0.583. This duty-cycle combined with a Period of
T = 2µs gives an ON-time of tON = D · T = 1.166µs.

The inductance needed in order to maintain continuous mode is:

Rload · D · (1 − D) · vS · T
Lcrit =
2 · vo

48Ω · 0.583 · (1 − 0.583) · 5V · 2µs

Lcrit = = 4.862µH
2 · 12V
In order to meet this criteria a coil with an inductance of L = 10µH is chosen.

To keep the output ripple under about 100mV one can derive the necessary capacitance value for the

12
output capacitor:
io · D · T
vo,ripple =
C

io · D · T
C=
vo,ripple

vo
Rload ·D·T
C=
vo,ripple

12V
48Ω · 0.583 · 2µs
C= = 2.915µF
100mV
A capacitor with a capacitance value of C = 4.7µF is chosen. The resulting circuit looks as follows:

Abbildung 21: circuit of the dimensioned boost-converter

2.3 output voltage and output ripple of the boost converter

The output voltage and the coil current for the set duty-cycle can be seen in the following figure:

Abbildung 22: output voltage and coil current with start-up time

The output voltage in the steady-state of the converter is about 12V as requested. The small deviation can
be attributed to the voltage-drop on the diode as well as the ON-resistances of the diode, the MOSFET
and the coil. These resistances as well as the voltage-drop on the diode result in a slightly lower output
voltage than the desired 12V, since these factors are not taken into account during the calculations.

13
 Abbildung 23: output voltage ripple

In figure 23 one can see a close up of the output voltage and the output ripple. The ripple are measure
with the differential cursor to be about 63mV which is smaller than the maximum ripple of 100mV.
Both the output voltage in the steady-state as well as the output voltage ripple can be measures with
the .meas statements:
1 . meas TRAN V_out AVG V ( out ) FROM 0.6 m TO 10 m
2 . meas TRAN V_out_ripple PP V ( out ) FROM 0.6 m TO 10 m

The output from the spice error log is as follows:

1 v_out : AVG ( v ( out ) ) =11.8795 FROM 0.0006 TO 0.01
2 v_out_ripple : PP ( v ( out ) ) =0.0669241 FROM 0.0006 TO 0.01

2.4 effects of a varying duty-cycle on the output voltage and ripple

If one were to take the same circuit, but with a changed duty cycle then the expectation is that the
output voltage changes accordingly to the derived formula in 2.

For example if one would want to change the output voltage from 12V to 24V then the necessary duty-
cycle would be D = 0.792 which results in an ON-time of tON = D · T = 1.584µs.
But it must also be ensured that the chosen inductance is still high enough so that the converter still
works in continuous mode. The new critical inductance for a duty-cycle of D = 0.792 is:

Rload · D · (1 − D) · vS · T
Lcrit =
2 · vo

48Ω · 0.792 · (1 − 0.792) · 5V · 2µs

Lcrit = = 1.647µH
2 · 24V
With this result the chosen 10µH are still valid. The output voltage can yet again be simulated and looks
as follows:

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 Abbildung 24: output voltage for a duty-cycle of D = 0.792

One can see in the figure that the output voltage is of 24V is reached even better than the one for 12V,
but on the other hand the coil current is much bigger since the resistance stays the same. Depending on
the coil or diode used the components might not be able to handle such large currents and might need to
be replaced with others. Another thing that can be noted is that the initial voltage spike is about 37V.
The MOSFET used cant switch such large voltages so another Model with a VDS,max > 2 · vo must be
chosen in order to be able to generate such large voltages.

The output ripple can also be seen in figure 25.

Abbildung 25: output voltage ripple for a duty-cycle of D = 0.792

This time the ripple is about 170mV which is bigger than the desired maximum of 100mV. In order to
decrease the output ripple a larger capacitor at the output is needed.
The same values can again be obtained by using the same .meas statements before with the duty-cycle
of 0.583.
1 v_out : AVG ( v ( out ) ) =24.0268 FROM 0.001 TO 0.01
2 v_out_ripple : PP ( v ( out ) ) =0.170544 FROM 0.00358 TO 0.003519

If one were to choose a smaller voltage at the output like 8V then the duty-cycle needed to generate such
a voltage would be D = 0.375 and the corresponding ON-time would be tON = D · T = 0.75µs.

15
The critical inductance value needed for this output voltage in order to stay in the continuous mode is:
Rload · D · (1 − D) · vS · T
Lcrit =
2 · vo

48Ω · 0.375 · (1 − 0.375) · 5V · 2µs

Lcrit = = 7.031µH
2 · 8V
The chosen inductance value of L = 10µH still applies and does not need to be changed.

The output voltage with the set duty-cycle is depicted in figure 26

Abbildung 26: output voltage ripple for a duty-cycle of D = 0.375

It can be seen that the desired output voltage of 8V is not met, instead the output voltage is about 7.85V.
This is a common occurrence of a boost-converter, the smaller the voltage difference between input and
output the larger the deviation between the desired output voltage and the actual output voltage. The
output voltage can be corrected by increasing the inductance value, but this in turn also increases the
current in the coil and the diode. Another way to ensure that the boost-converter produces the desired
output voltage is to use a feedback loop to change the duty-cycle.

Abbildung 27: output voltage ripple for a duty-cycle of D = 0.375

On the other hand the ripple on the output voltage got smaller which shows that the relationship between

16
 the output ripple and the accuracy of the desired output voltage is mirror-inverted.
The spice error log shows the following results:
1 v_out : AVG ( v ( out ) ) =7.8439 FROM 0.001 TO 0.01
2 v_out_ripple : PP ( v ( out ) ) =0.0301514 FROM 0.00358 TO 0.003519

2.5 Power conversion efficiency for a specific duty-cycle

The circuit shown in figure 20 is an ideal representation of a boost converter with 100% efficiency. But a
real boost converter will inevitably have losses. The losses in the boost converter come from the ohmic
losses in the coil with its series resistance rL and the ohmic losses in the MOSFET with its ON-resistance
rON as well as the switching losses on the MOSFET. The diode also has forward losses and switching
losses.

The losses in the converter can be summed up as follows:

PLoss = PrL + PSW + P D

Here PrL is the ohmic loss on the coil, PSW represent both the conduction loss due to the switch and
dynamic switching losses and PD is the conduction loss on the diode. The losses can be calculated as
such:

PLoss = PrL + PSW + P D

CSW · vo2
PLoss = rL · IL2 + D · rON · IL2 + + (1 − D) · VD IL
2·T

vo
with IL =
Rload · (1 − D)

 2  2
vo vo
PLoss = rL · + D · rON · + ...
Rload · (1 − D) Rload · (1 − D)

CSW · vo2
 
vo
+ (1 − D) · VD (4)
2·T Rload · (1 − D)

In the circuit 21 the components all have their parasitic values defined directly from LTSpice. The values
that are used for the calculation of the losses are:

rL = 1mΩ
rON = 0.7mΩ
CSW = COSS + CD = 110pF + 180pF = 290pF
VD = 0.3V

With these values known one can calculate the losses for a duty-cycle of D = 0.583 and an output voltage
of 12V.
2 2
CSW · vo2
   
vo vo vo
PLoss = rL · + D · rON · + + (1 − D) · VD
Rload · (1 − D) Rload · (1 − D) 2·T Rload · (1 − D)

 2  2
12V 12V
PLoss = 1mΩ · + 0.583 · 0.7mΩ · + ...
48Ω · (1 − 0.583) 48Ω · (1 − 0.583)

290pF · (12V )2
 
12V
+ (1 − 0.583) · 0.3V = 0.0859461W
2 · 2µs 48Ω · (1 − 0.583)

17
 With the losses known one can calculate the power efficiency coefficient η:
Po
η= (5)
Po + PLoss

vo2
Rload
η= vo2
Rload + PLoss

(12V )2
48Ω
η= (12V )2
= 97.215%
48Ω + 0.0859461W

This shows that the boost-converter has a very high efficiency. This power conversion efficiency coefficient
can also be measured in the simulation using the .meas statements. The following statements are used in
order to measure the input and output power during the steady state of the converter:
1 . meas TRAN P_out_full AVG ( V ( out ) * I ( R_Load ) ) FROM 1 m TO 10 m
2 . meas TRAN P_in_full AVG ( I ( L1 ) * V ( in ) ) FROM 0 TO 10 m

The output in the spice Error log looks as follows:

1 p_out_full : AVG ( v ( out ) * i ( r_load ) ) =2.94004 FROM 0.001 TO 0.01
2 p_in_full : AVG ( i ( l1 ) * v ( in ) ) =3.11411 FROM 0.001 TO 0.01

With these values one gets an η of:

Po
η=
Pin

2.94004W
η= = 94.41%
3.11411W
With this one can see that the simulated result for the power conversion efficiency coefficient are not too
far off from the calculated results. Both are in a range of 94% to 97% which shows the high efficiency of
the conversion.

It should be noted that the calculated and simulated efficiency only applies to this specific duty-cycle
and the used components. If one were to change the duty-cycle then the efficiency would also change.

The deviation between the simulated and calculated power conversion efficiency coefficient can be at-
tributed to the losses that were not considered in the calculation. Especially dynamic losses during
switching are not covered which also affect the efficiency.

2.6 Power conversion efficiency for different duty-cycles

If one changes the duty cycle from the part 2.5 and then calculates the power conversion efficiency coef-
ficient η again, different values are gained. This is because the coefficient η is highly dependant on the
duty-cycle.

For example if a duty-cycle of D = 0.792 is chosen again to get an output voltage of 24V then the
coefficient η will change accordingly and can be calculated via the equation in 5 with the losses of the
circuit calculated in 4.

With these equation and the new duty-cycle the calculate coefficient η is:

η = 98.355%

The simulated value gained from using the same .meas statements as in 2.5 are:
1 p_out_full : AVG ( v ( out ) * i ( r_load ) ) =12.0269 FROM 0.001 TO 0.01
2 p_in_full : AVG ( i ( l1 ) * v ( in ) ) =12.5726 FROM 0.001 TO 0.01

This yields a coefficient η of:

Po 12.0269
η= = = 95.66%
Pin 12.5726

18
 Again one can see that the calculated coefficients η are very similar, though now they are higher than
the ones obtained with a duty-cycle of D = 0.583. This shows that the efficiency gets higher the higher
the output voltage is compared to the input voltage.

The measurement and calculation can be repeated for a duty-cycle of D = 0.375. The calculated co-
efficients η is:
η = 96.056%
The values obtained by the simulation are:
1 p_out_full : AVG ( v ( out ) * i ( r_load ) ) =1.28181 FROM 0.001 TO 0.01
2 p_in_full : AVG ( i ( l1 ) * v ( in ) ) =1.37774 FROM 0.001 TO 0.01

which correspond to a power conversion coefficient η:

Po 1.28181
η= = = 93.037%
Pin 1.37774
These results show that the power conversion coefficient η goes down if the output voltage and the input
voltage closer together.

2.7 Stability of the output voltage on a load resistance step

Up until now all simulations were done for a constant load resistance of Rload = 48Ω. For the ideal
boost-converter the load resistance does not need to be constant in order to get a certain output voltage.
The only thing that needs to stay constant is the duty-cycle.

For the non-ideal boost-converter used in the simulation a bigger Load resistance means that the current
on the load will get smaller. The critical inductance therefor needs to be higher to ensure that the that
the converter stays in continuous mode.

If the load resistance changes then the output voltage should stay constant, which should hold true
as long as the converter stays in the continuous mode. For a desired output voltage of 12V and a corre-
sponding duty cycle of D = 0.583 as well as an inductance value of L = 10mH the load resistance should
be able to increase till:
L · 2 · vo
Rload,max =
D · (1 − D) · vS · T

L · 2 · 12V
Rload,max = = 98.72Ω
0.583 · (1 − 0.583) · 5V · 2µs

This calculation means that the output voltage should be a stable 12V as long as the load resistance does
not exceed Rload,max = 98.72Ω.

In order to determine if this is true the load resistance will get stepped from a small value of Rload = 1Ω
to the maximum value and the output voltage in the steady stage will be investigated using a .meas
statement in order to print the output voltage over the load-resistance. The .meas statement used is:
1 . meas TRAN V_out AVG V ( out ) FROM 1 m TO 5 m

This investigation results in an output of:

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 Abbildung 28: output voltage over load resistance for a steady state of the converter

The figure shows how the output voltage changes drastically with the load resistance. With the chosen
duty-cycle one would expect the output voltage to be close to 12V for all load-resistances, but the simu-
lation shows that this is not the case. The reason is that with a smaller load resistance causes a higher
load current. The coil needs to supply a larger current which can only be supplied if the duty-cycle were
to increase, but since it is fixed the energy in the coil cant increase beyond a certain point. Because of
that the output voltage is smaller than the desired 12V.

This problem can only be circumvented by making the duty-cycle variable with and regulated with a
feedback loop. The fastest way to do that is to take out the MOSFET and replace it with a Step-up IC
regulated by a voltage divider from the output. The circuit used can be seen in figure 29.

Abbildung 29: circuit of the boost converter using an LT1370HV switching regulator IC

It uses a switching regulator IC from linear technologies with a voltage feedback from the output. The
voltage divider is chosen such that the output voltage will be regulated to 12V.

The load resistance step with this circuit results in the following output curve:

20
 Abbildung 30: output voltage over the load resistance with the regulator IC

In the figure one can see that the output voltage is much more regulated for a load resistance over
Rload = 5Ω and results in a constant 12V output voltage. The output voltage for a load resistance under
Rload = 5Ω is lower than 12V since the maximum switching frequency of the Step-up regulator is 600kHz
and the IC cant regulate the voltage for the necessary current with a load resistance of less than 5Ω.

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Abbildungsverzeichnis
1 Sample and hold stage schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Sample and hold stage plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Clock schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Clock plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Comperator schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Multiplexer schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Multiplexer plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Multiplier schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Multiplier plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
10 Subtract circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
11 Subtract circuit plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Shift register schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Shift register plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
14 Full adc schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
15 3V adc conversion plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
16 500 samples adc plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
17 8 bit clock schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
18 Expanded shift register schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
19 3V 8bit adc conversion plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
20 circuit of an ideal boost-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
21 circuit of the dimensioned boost-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
22 output voltage and coil current with start-up time . . . . . . . . . . . . . . . . . . . . . . 13
23 output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
24 output voltage for a duty-cycle of D = 0.792 . . . . . . . . . . . . . . . . . . . . . . . . . . 15
25 output voltage ripple for a duty-cycle of D = 0.792 . . . . . . . . . . . . . . . . . . . . . . 15
26 output voltage ripple for a duty-cycle of D = 0.375 . . . . . . . . . . . . . . . . . . . . . . 16
27 output voltage ripple for a duty-cycle of D = 0.375 . . . . . . . . . . . . . . . . . . . . . . 16
28 output voltage over load resistance for a steady state of the converter . . . . . . . . . . . 20
29 circuit of the boost converter using an LT1370HV switching regulator IC . . . . . . . . . . 20
30 output voltage over the load resistance with the regulator IC . . . . . . . . . . . . . . . . 21

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