bb bb bb bb bb

te e e e e
A B C D E
e te te te te
ot oto oto oto oto
NN NN NN NN

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat at
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em
e m eme m em
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1

te
ot
e
o
b bo
ok
o
Sc
kS
h
ch
LCFC Confidential
eb
ot t
NNo
o
eb
ok
o o
Sc
kS
h
ch

eb
ot t
NNo
o
eb
ok
o o
Sc
kS
h
ch

eb
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NNo
o
eb
ok
o o
Sc
kS
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ch

ot
NN o
e bo
te
bo
k
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1

mm mm mm mm
co o co o co o co o
s.s.c s.s.c s.s.c s.s.c

em
at
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cic
GS454/GS554(NMD031) MB Schematics Document
em
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h h h h h h h h ch
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okok okok okok okok o o k
te
bb
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o ICL U42 with DDR4 + Nvidia N16V-GM
eb
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ot ot t ot t ot t ot t
NNo NNo NNo NNo
2019-10
2
mm mm mm mm 2

c.o
.s co c.o
.s co c.o
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at
s
icic
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s
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s
icic
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e mm e mm e mm e mm
e e e e
chch chch ch
ch ch
ch chc
o kSkS o kSkS o kS
kS o kSkS o kSkS
o o o o o
bo o bobo bobo bo
bo eb
o o
te eb ete ete ete eb
ot oto oto oto ot t
NN NN NN NNo

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i ic i ic i ic
at
at at
at at
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e mm e mm e mm e mm
e e e e
chch chch chch ch
ch chc
o kS kS o kSkS o kSkS o kSkS o kSkS
o o o o o
bo o
eb
oo
eb
oo
eb
oo boo
te eb eb eb eb e eb
ot ot t ot t ot t ot t
3 3

NNo NNo NNo NNo

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat atat atat atat
h em
e m
h eme m
h eme m
h eme m
h
Sc ch Sc ch Sc ch Sc ch ScSc
ok
o kS oko kS oko kS oko kS k
oo k
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b bo o o o o o o bo
ebeb eb eb eb eb bo
te e
ot t ot t ot t ot
ete
ot NNo NNo NNo NN o

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at at at
4 4

h emem h emem h emem h em em

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o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

NN 2016/08/20 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 1 of 60

omm omm omm omm

A B C D E
 bb bb bb bb bb
te e e e e
A B C D E
e te te te te
otLCFC oto oto oto oto
confidential NN NN NN NN

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i c
i NV N16x/N17x i i c i i c i i c
atat at
at Memory Bus at
at atat
h em
e m Package: FCBGA595
h em e m
h em
e m DDR4 SO-DIMM+MDx4
h em
e m
h
Sc ch Sc
h
PCI-Express
Sc Sc
1.2V ch
DDR4 Page 17/18
Sc ch ScSc
kS kS kS
1 1

o ok
o o oko
4x k
Gen3 o oko o oko
k
oo k
b bo eb
o
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o bobo
te e VRAM: 256*32 eb eb eb ete
ot ot ot ot t otot ot
N
GDDR5*2: 2GB N NNo x1
NN NN o

USB3.0 USB3.0 Conn

HDMI (DDI 1) x1
mm HDMI Conn. mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat x1 atat atat
h emem eDP x2
h emem h emem h emem
Sc
h eDP Conn
Sc
h
Sc
h USB3.0 Conn
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h ch
Sc Sc Sc Sc Sc
x1
ok ok ok ok kS
o o ok o o ok o o ok o o ok o o
o o k
bb eb eb eb eb
te e eb Intel MCP eb eb eb
ot ot t ot t ot t ot t
NNo NNo x1 NNo NNo
SATA x1 USB2.0 Conn
SATA HDD
Ice Lake-U42 15W USB2.0
2
mm mm mm mm 2

c.o
.s co c.o
.s co c.o
.s co c.o
.s co
s s s s
icic icic icic icic
at
at NGFF PCI-Express at
at at
at Finger print at
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e mm e mm e mm e mm
e 4x Gen3 e e e
chch
SSD ch ch ch
ch ch
ch chc
o kSkS o kSkS BGA1526 o kS
kS o kSkS o kSkS
o o o o o
bo o bo o bobo bo bo eb
o o
te eb te eb PCIe x1 50mm*25mm ete ete eb
o t NGFFo t ot ot ot t
NNo USB2.0 x1 NN o NN o NNo
WLAN&BT

SPI SPI ROM (16MB)

mm mm m m mm
co o co o co o
W25Q128JVSIQ co o
c s.s.c c s.s.c c s.s.c Page 07 c s.s.c
iticConn. i ic i ic i ic
at
aSPK at
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at at
at
e mm e mm e mm e mm
e Page 30
e e e
chch ch ch chch ch
ch ch
HD Audio x1
S c
ok
S Realtek kSkS kSkS kSkS kSkS
ok RTS5199 oo o o o o o o o
bo bo o USB2.0 x1 oo oo oo
HP&Mic
e
t t e eb eb eb eb eb eb
b
e eb
ot t ot t ot t ot t
3 Combo Conn. 3

o Page 30 NNo Page 43 NNo NNo NNo

I2C Touch Pad
Page 45
Page 3~16
mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i c
i Conn. i i c i i c i i c
atat SD atat LPC atat atat
h em
e m
h eme m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch Sc ch ScSc
ok
o kS IO Board oko kS EC oko
GPIO kS oko kS k
oo k
o
b bo o o o o o o bo
ebeb
ITE IT8227E-LQFP128
eb eb
HALL Sensor eb eb bo
te e
ot t o44t t ot t ot
ete
ot NNo NNo
Page
NNo NN o
Int.KBD
Page 45 Thermal Sensor
F75303M Page 39
mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at at at
4 4

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

NN 2016/08/20 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Tuesday, December 10, 2019 2 of 60

omm omm omm omm

A B C D E
 bb bb bb bb bb
te e ete ete ete ete
A B C D E

ot oto oto oto oto

NN NN NN NN
Voltage Rails ( O --> Means ON , X --> Means OFF )
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

mm mm mm mONm
co o co o co o co o
Full ON HIGH HIGH HIGH ON ON ON
Power Plane
c s.s.c c s.s.c c s.s.c s.s.c
i i c i i c i i c ONticic
at at at at atat a at
+3VALW S3 (Suspend to RAM) LOW HIGH HIGH ON OFF OFF

eme m +1.2V em
e m em
eS4m
hONe
mm
h h h he h
+5VALW (Suspend to Disk) LOW LOW LOW OFF OFF OFF
Sc ch Sc ch +5VS Sc ch Sc Sc ScSc
kS kS kS
1 1

o oko V9B+ +3VALW_PCH oko

+2.5V_DDR
o
+3VS
o oko S5 (Soft OFF) LOW LOW ok
o k
LOW ON OFF OFF OFF k
oo k
b bo b bo +1.8VS b bo bobo bobo
te e t e e t e e t e e
ot
ete
ot +1.8VALWo ot +VCCST
NN
+CPU_CORE o t
NNo
o t
NNo NN o
VCC_AUX +0.6VS
State +VCCSTG
HSIO PORT Function BOM Structure BTO Item
mm mm mm mm
co o co o c.o
co co o
s.s.c s.s.c s.s.c
1 USB3.0 .Conn @ Un-stuff
c c ss
cicConn c part
i ic i i c 2 it 14@
tic
ti14"
atat atat
t
USB3.0 For
aa aa
em em mmNC em
3 15@
em em em
For 15" part
4e eUSB3.0
cch h h h h h h h ch
OScSc ScSc5
c c Sc
NC
SS0
S kS kS
okok
O O okok
O okok kS k
b o o bo o o o oooo o o
o o
b b eb eb
b b ebeb
6
te e ee
ot t ot t
ee
ot t ot t
ot
ONNo NNo NNo NNo
1 USB3.0 Conn
S3 O O X 2 USB3.0 Conn
3 NC CD@ For cost down
S3 4 NC
O omm O O mm X om om
om om
Battery only USB2.0 5 Camere EMC@
c.o
2 For EMC part 2

c.co
.s .s co 6 c.c
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.s c
s
cic s TouchsScreen For EMCs15"
t i icic icic cic
tiEMC
a at at
at at
at Print at un-stuff
EMC_NS@
S5 S4 7
Finger a
For part
AC h emem
Only O O X e mmX
e e mmCard Reader
e
8
e mm
e
S cc h chch ch
c9h ch
ch chc
kS kS kS kS
USB2.0 conn
S kS kS 10 kS kS
ok k o o o o
oo o o o o
S5 S4
bo oo X o bo o
Bluetooth
O X teb X o bo o
e
t te
bBattery only eb ebeb ete eb eb
o ot ot t ot ot t
5~8
o NN NNo X4
DGPU
NN o NNo
S5 S4 9 WLAN
ME@ For ME part
AC & Battery X X X X PCIE 10 NC
don't exist
mm mm SATA HDD om m For UMA partom
co o co o 11
.c co
UMA@
.c c om
c s.s.c c s.s.c NC cs s. OPT@ cs
.
GPUspart
i ic i ic 12
ti ic c
titiN16S-GTR
For NV
at
SMBUS Control Table
at atat 13~16 a at a
ForaNV
OPTN16@ GPU part
e mm e mm e mmPCIE/SATA SSD mm
e e e he e For NV N17S-G1 GPU part
OPTN17@
chch
hh chch h ch
X4
IT8227E Memory Sc c c c c
kSkS k kS kSkS kSkS kSkS
SOURCE BATT Charger DGPU PCH PMIC SODIMM Thermal WLAN
o
oo o o
Down
oo o Sensor WiMAX o
oo o o
oo o o
oo o
b eb eb b b
t3e eb eb eb e eb e eb 3
ot EC_SMB_CK1 otot otot ot t ot t
IT8227E V V N
X N V X X X X X NNX NNo NNo
EC_SMB_DA1 +3VL_EC +3VL_EC

EC_SMB_CK0 IT8227E X Xmm V V X X X X mmV X mm mm

EC_SMB_DA0 +3VS
c.o
co
+3VG_AON +3VS
c.oco co o TS@ For touch.c o opart
.s .s s.s.c c
screen
s s s .
t cic
it t cic
it i ci c TP@ cics
For iTOuch
at at
Pad Part
EC_SMB_CK3 IT8227Eaa aa at at
mm X X X V X X mm V X X X
em m em m
EC_SMB_DA3 he e he
c h
+3VAWL
c he h
ch
e h
ch
e h
SS c
kS S c Sc Sc ScSc
ok k ok ok kS ok kS k k
o oo ooo o
X ebbo o o oo
bo
oo
bo
PCH_SMB_CLK PCH
b b X X X X b b X V X V X eb
te e PCH_SMB_DATA +3VALW_PCH ee e eb ete
ot ot t +3VALW_PCH +3VS
ot t ot t ot
NNo NNo NNo NN o

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address

mm mm mm mm
co o c.o co co o co o
s.s.c .s s.s.c s.s.c
Device Address Device Address Device Address Device Address
c c s c c
i ic i i c i i c i i c
at at at at
Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
4
0001 0010 bm at at at at 4

e em emem emem em em
Charger DGPU need to update
h h h h h h h h ch
Sc
Sc Sc
Sc Sc Sc ScSc kS Sc
o ok ok o ok ok o ok ok o ok ok o o o k
bb o o o o o
te e ebeb eb eb te
bb
e eb eb
ot ot t ot tSecurity Classification LC Future Center Secret o ot ot t
NNo NNo NNo
Data Title
NN
Issued Date 2015/08/20 2016/08/20
Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
omm omm omm om
E m
Date: Friday, December 06, 2019
Sheet 3 of 60
A B C D
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
UC1A
CPU_EDP_TX0- Y5 BB5
33 CPU_EDP_TX0- CPU_EDP_TX0+ DDIA_TXN_0 TCP0_TX_N0
mm mm mmAV6 mm
Y3 BB6
33 CPU_EDP_TX0+ DDIA_TXP_0 TCP0_TX_P0

co o co o
CPU_EDP_TX1-

co co o
Y1
33 CPU_EDP_TX1- DDIA_TXN_1
o
TCP0_TX_N1

s.s.c s.s.c c s.s.c

CPU_EDP_TX1+

s.s.TCP0_TXRX_N0
Y2 AV5
33 CPU_EDP_TX1+ DDIA_TXP_1 TCP0_TX_P1 BH2
V2
ici c i ci c V1 DDIA_TXN_2
i ci c BH1
i ci c
atat at at at
at atat
V3 DDIA_TXP_2 TCP0_TXRX_P0 BF1
V5 DDIA_TXN_3 TCP0_TXRX_N1 BF2

em m mm em m em m
DDIA_TXP_3 TCP0_TXRX_P1

h e h eCPU_EDP_AUX#
e CPU_EDP_AUX#
h e h e h
ch h ch ch
W4 AY5

Sc cc Sc Sc Sc
33

Sc
CPU_EDP_AUX W3 DDIA_AUX_N TCP0_AUX_N AY6
S
kS S kS kS
D 33 CPU_EDP_AUX DDIA_AUX_P TCP0_AUX_P D

ok k k ok ok k k
CPU_HDMI_TXN2

oo oo
AE3
o o oo
34 CPU_HDMI_TXN2
o o o o
bo
CPU_HDMI_TXP2 AE5 DDIB_TXN_0
b bo b bo o bo
HDMI D2 AR5
b eb
34 CPU_HDMI_TXP2 DDIB_TXP_0 TCP1_TX_N0
b eb
CPU_HDMI_TXN1 AE2 AR6

te e e e te e ete
34 CPU_HDMI_TXN1 CPU_HDMI_TXP1 AE1 DDIB_TXN_1 TCP1_TX_P0 AL5
t ot ot
ot t ot ot
HDMI D1 34 CPU_HDMI_TXP1
o oHDMI AC3 o
AC5 DDIB_TXP_1
CPU_HDMI_TXN0 TCP1_TX_N1 AL3

NN
34 CPU_HDMI_TXN0 CPU_HDMI_TXP0
N
DDIB_TXN_2
AC1 N
TCP1_TX_P1 BD2
N NN o
D0 34
34
CPU_HDMI_TXP0
CPU_HDMI_CLKN
CPU_HDMI_CLKN
CPU_HDMI_CLKP
DDIB_TXP_2
AC2 DDIB_TXN_3
TCP1_TXRX_N0 BD1
TCP1_TXRX_P0 BB1
N
HDMI CLK 34 CPU_HDMI_CLKP DDIB_TXP_3 TCP1_TXRX_N1 BB2
AD3 TCP1_TXRX_P1
AD4 DDIB_AUX_N AN3
DDIB_AUX_P TCP1_AUX_N AN5
DP15 TCP1_AUX_P
mm mm DJ17 GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN
mmBF6 mm
co o c.o co co o co o
GPP_E23/DDPA_CTRLDATA/BK4/SBK4

s.s.c .s s.s.c s.s.c

PCH_HDMI_DDC_CLK TCP2_TX_N0
sPCH_HDMI_DDC_DATA
34 PCH_HDMI_DDC_CLK DL40 BF5
c c c c
GPP_H16/DDPB_CTRLCLK TCP2_TX_P0 BJ5
c c c c
DP42
i i i i i i i i
at at at at
34 PCH_HDMI_DDC_DATA GPP_H17/DDPB_CTRLDATA TCP2_TX_N1 BJ6

at at at at
DL17 TCP2_TX_P1 BL1

em em em em
DK17 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP2_TXRX_N0 BL2

em em em em
GPP_E19
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP2_TXRX_P0 BM2
h h h h h h TCP2_TXRX_N1 BM1
h h ch
Sc c Sc Sc
DN17

Sc c Sc Sc Sc
DP17 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP2_TXRX_P1
SS kS
GPP_E21

okok okok ok ok okok k

GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD BG6

o o
DK34
o
TCP2_AUX_N BG5
o o o o
bb o bb o GPP_D10
o
DL34 GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD
bb
TCP2_AUX_P
o o
eb
eb ebeb
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD
te e
ot
ete te e
ot ot t
ot ot ot
DN33 BP6
o DL33 o
NNo
GPP_D12 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD TCP3_TX_N0 BP5
NN CPU_EDP_HPD
N
DW11
N
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD TCP3_TX_P0 BV5
TCP3_TX_N1 BV6
NN
33 CPU_EDP_HPD CPU_HDMI_HPD CV42 GPP_E14/DPPE_HPDA/DISP_MISCA TCP3_TX_P1 BR1
34 CPU_HDMI_HPD GPP_A18/DDSP_HPDB/DISP_MISCB TCP3_TXRX_N0
CV39 BR2
CY43 GPP_A19/DDSP_HPD1/DISP_MISC1 TCP3_TXRX_P0 BT2
USB_OC1# CR41 GPP_A20/DDSP_HPD2/DISP_MISC2 TCP3_TXRX_N1 BT1
41 USB_OC1# USB_OC2# CT41 GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3 TCP3_TXRX_P1
42 USB_OC2# GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4
C
mm mm DV14
mmBT6 mm C

c.o c.o c.o c.o

GPP_E17 TCP3_AUX_N

co co co co
BT5
.s .s .s .s
PCH_ENVDD DN21 TCP3_AUX_P
s s s s
33 PCH_ENVDD
PCH_ENBKL DL19 EDP_VDDEN AY1 TCRCOMP_N RC401 1 2 1/20W_150_1%_0201
icic cic 1 DSI_DE_TE_2
it icic icic
33,44 PCH_ENBKL
PCH_EDP_PWM EDP_BKLTEN TC_RCOMP_N AY2 TCRCOMP_P

at at at at
DU19

at at GPP_A17/DISP_MISCC CT38 at
33 PCH_EDP_PWM
J3 EDP_BKLTCTL TC_RCOMP_P
+3VS a RSVD_1
mm mm mm mm
TP401 @

e e e e
DISP_UTILS
e e e e
1 D2 CV43

ch ch ch ch ch
R2 DISP_UTILS GPP_A21 CV41

ch1 RPC401 4 ch ch ch
TP402 @ EDP_COMP
DISP_RCOMP GPP_A22
c
kSkS kSkS kS
kS kSkS kSkS
1 0f 19

1
PCH_HDMI_DDC_CLK

o o ICELAKE-U_BGA1526 o o o
PCH_HDMI_DDC_DATA
o o o o o
2 3 RC402
o o bo bo bo o
bo bo bo o
1/20W_150_1%_0201
bb eb eb
2.2K_0404_4P2R_5% @
e
t te ete e te e
te
ot ot ot ot t

2
o NN o NN o NN o NNo
+3VALW_PCH

1/20W_4.7K_1%_0201 2 @ 1 RC403 GPP_E19

om om GPP_E21
mm mm mm
1 RC404 2
co o co o co o
1/20W_20K_5%_0201 @

1/20W_4.7K_5%_0201 2 .c
c s [email protected] RC405 c s.s.c c s.s.c c s.s.c
i ic i ic i ic i ic
at at at
at at
at at
at
1/20W_20K_5%_0201 2 @ 1 RC406

e m m
1/20W_4.7K_5%_0201 2 @ 1 RC407 GPP_D10
e mm e mm e mm
e e e e
chch 1/20W_20K_5%_0201
2 @ 1 RC408
chch chch ch
ch chc
o kS kS 1/20W_4.7K_5%_0201 2 @ 1 RC409 GPP_D12
o kSkS o kSkS o kSkS o kSkS
o o o o o
bo o
eb
oo
eb
oo
eb
oo boo
eb eb eb eb e eb
1/20W_20K_5%_0201 2 @ 1 RC410

te ot ot t ot t ot t
ot ot
B B

N NNo NNo NNo

An external pull-up resistor is required if the pin is
used as HDMI Display I2C, instead of TBT LSx
0 = DDPx I2C / TBT LSx pins at 1.8V N
1 = DDPx I2C / TBT LSx pins at 3.3V

+1.8VALW_PCH
mm mm GPIO Group Power Supply mm mm
co o co o co o co o
RC411
c
1s.s.c USB_OC1#
2 10K_0201_5%
c s.s.c c s.s.c c s.s.c
t i i c i i c GPP_A 1.8V
i i c i i c
RC412 1
aa 2 t10K_0201_5% USB_OC2#
atat atat atat
mm em m GPP_B/C/D/E 3.3V
em m em m
hehe h e h e h e h
c c Sc ch c ch Sc ch ScSc
kS kS
GPP_F 1.8V(only)
kS ok kS kS ok kS k
2 100K_0201_5%CPU_EDP_HPD
k
RC413 1

oooo o oo
b booo o o oo
bo
oo
b eb bo
GPP_G/H 3.3V
te eb eb te te eb eb ete
ot ot t ot t ot
CC401
o
NNo NNo NNo o
2 1 GPP_R/S 1.8V
0.33U 10V K X5R 0402
NN
@ GPD 3.3V(only)
RPC402
4 1 PCH_ENVDD
3 2 PCH_ENBKL

mm mm mm mm
co o co o co o co o
100K_0404_4P2R_5%

c s.s.c CC402
c s.s.c c s.s.c c s.s.c
i i
tX5Rt0402c 2 1
i i c i i c i i c
0.33Ua
10V Ka atat at at at at
A A

emem emem emem em em

@

h h h h h h h h ch
ScSc ScSc Sc Sc ScSc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 4 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
DDRA_DQS#[0..7] DDRB_CLK0#
18 DDRA_DQS#[0..7]
DDRA_DQS[0..7]
18 DDRA_DQS[0..7] 1
CC502
DDRB_DQS#[0..7]
mm mm mm mm
330P_0402_50V8J
17 DDRB_DQS#[0..7]

co o co o co o co o
@
DDRB_DQS[0..7]

s.s.c s.s.c s.s.c s.s.c

2
17 DDRB_DQS[0..7] DDRB_CLK0
SO_DIMM
ic i c i c i c i c i c i ci c
atat at at atat MD atat
em m em m em m em m
UC1B

h e h e 17 DDRB_DQ[0..63]
h e h e h
ch ch h ch
UC1C

Sc Sc Sc Sc Sc
18 DDRA_DQ[0..63]

Sc DDRB_DQ0 Sc
DDRA_DQ0 CA48 BL48 DDRA_CLK0#

kS kS BF42 kS
DDRA_CLK0# 18
D DDRA_DQ1 CA47 DDRA_DQ0_0/DDR0_DQ0_0 DDRA_CLK_N/DDR0_CLK_N_0 BL47 DDRA_CLK0 AK48 Y48 DDRB_CLK0# D

ok ok k k ok k k
DDRA_CLK0 18 DDRB_CLK0# 17
DDRA_DQ2 CA49 DDRA_DQ0_1/DDR0_DQ0_1 DDRA_CLK_P/DDR0_CLK_P_0 DDRA_CLK1# DDRB_DQ1 AK45 DDRC_DQ0_0/DDR1_DQ0_0 DDRC_CLK_N/DDR1_CLK_N_0 Y47 DDRB_CLK0

o o o o DDRA_CLK1# 18 oo o DDRB_CLK0 17 oo
bo o bo
DDRA_DQ3 BV49 DDRA_DQ0_2/DDR0_DQ0_2 DDRB_CLK_N/DDR0_CLK_N_1 DDRA_CLK1 DDRB_DQ2 DDRC_DQ0_1/DDR1_DQ0_1 DDRC_CLK_P/DDR1_CLK_P_0
o o bo o M42 bo
BF43 AK49 M43
b b b
DDRA_DQ0_3/DDR0_DQ0_3 DDRB_CLK_P/DDR0_CLK_P_1 DDRA_CLK1 18
AG47 DDRC_DQ0_2/DDR1_DQ0_2 DDRD_CLK_N/DDR1_CLK_N_1
b b b
DDRA_DQ4 CA45 DDRB_DQ3

te e e e e te ete ete
DDRA_DQ5 DDRA_DQ0_4/DDR0_DQ0_4 DDRA_CKE0 DDRB_DQ4 AK47 DDRC_DQ0_3/DDR1_DQ0_3 DDRD_CLK_P/DDR1_CLK_P_1
t ot ot ot
BV47 BG49

ot t DDRA_CKE0 18
BV48 DDRA_DQ0_6/DDR0_DQ0_6o o
DDRA_DQ6 DDRA_DQ0_5/DDR0_DQ0_5 DDRA_CKE0/DDR0_CKE0 BJ47 DDRB_DQ5 AG45 DDRC_DQ0_4/DDR1_DQ0_4 DDRB_CKE0
o NNo DDRC_CKE1/NC o
BV45 U45
DDRA_CKE1/NC BF38 DDRB_CKE0 17
AG48 DDRC_DQ0_5/DDR1_DQ0_5 DDRC_CKE0/DDR1_CKE0
NN N NN
DDRA_DQ7 DDRB_DQ6
N
V46
DDRA_DQ8 CC42 DDRA_DQ0_7/DDR0_DQ0_7 DDRB_CKE0/NC BF41 DDRA_CKE1 DDRB_DQ7 AG49 DDRC_DQ0_6/DDR1_DQ0_6 M41
DDRA_DQ9 CC39 DDRA_DQ1_0/DDR0_DQ1_0 DDRB_CKE1/DDR0_CKE1 DDRA_CKE1 18 DDRB_DQ8 AJ38 DDRC_DQ0_7/DDR1_DQ0_7 DDRD_CKE0/NC P43
DDRA_DQ10 CC43 DDRA_DQ1_1/DDR0_DQ1_1 BM38 DDRA_CS0# DDRB_DQ9 AL39 DDRC_DQ1_0/DDR1_DQ1_0 DDRD_CKE1/DDR1_CKE1
DDRA_DQ11 DDRA_DQ1_2/DDR0_DQ1_2 DDRA_CS_0/DDR0_CS_N_0 DDRA_CS0# 18 DDRB_DQ10 DDRC_DQ1_1/DDR1_DQ1_1 DDRB_CS0#
CE38 BM42 AJ39 V42
DDRA_DQ12 CC38 DDRA_DQ1_3/DDR0_DQ1_3 DDRA_CS_1/NC BP42 DDRB_DQ11 AL43 DDRC_DQ1_2/DDR1_DQ1_2 DDRC_CS_0/DDR1_CS_N_0 V39 DDRB_CS0# 17
DDRA_DQ13 CE39 DDRA_DQ1_4/DDR0_DQ1_4 DDRB_CS_0/NC BG42 DDRA_CS1# DDRB_DQ12 AL38 DDRC_DQ1_3/DDR1_DQ1_3 DDRC_CS_1/NC Y39
DDRA_DQ14 DDRA_DQ1_5/DDR0_DQ1_5 DDRB_CS_1/DDR0_CS_N_1 DDRA_CS1# 18 DDRB_DQ13 DDRC_DQ1_4/DDR1_DQ1_4 DDRD_CS_0/NC
CE42 AJ42 T39
mm m mm mm
om
DDRA_DQ15 CE43 DDRA_DQ1_6/DDR0_DQ1_6 BM43 DDRA_BS0# DDRB_DQ14 AL42 DDRC_DQ1_5/DDR1_DQ1_5 DDRD_CS_1/DDR1_CS_N_1

co o co DDRA_BS1# co o co o
DDRA_DQ16 BT48 DDRA_DQ1_7/DDR0_DQ1_7 DDRB_CA4/DDR0_BA0 DDRA_BS0#
BG39 DDRA_BS1# 18 DDRB_DQ15 AJ43 DDRC_DQ1_6/DDR1_DQ1_6 T38 DDRB_BS0#

s.s.c s.s.cDDRA_BG0 s.s.c s.s.c 17

DDRA_DQ17 DDRA_DQ2_0/DDR0_DQ2_0 NC/DDR0_BA1 18 DDRB_DQ16 DDRC_DQ1_7/DDR1_DQ1_7 DDRD_CA4/DDR1_BA0 DDRB_BS0#
DDRB_BS1# 17
BT47 AB49 T42
DDRB_BS1#
c c c c
DDRA_DQ18 DDRA_DQ2_1/DDR0_DQ2_1 DDRA_BG0 DDRB_DQ17 DDRC_DQ2_0/DDR1_DQ2_0 NC/DDR1_BA1
c c c c
BT49 BB49 AB48
i i i i i i i i
at at at t t DDRB_BG0
DDRA_DQ2_2/DDR0_DQ2_2 DDRA_CA5/DDR0_BG0 18 DDRC_DQ2_1/DDR1_DQ2_1

at at at
DDRA_DQ19 BN49 BD47 DDRA_BG1 DDRB_DQ18 AE49 R45 DDRB_BG0
DDRA_DQ20 BT45 DDRA_DQ2_3/DDR0_DQ2_3 NC/DDR0_BG1 DDRA_BG1 18 DDRB_DQ19 AE47 DDRC_DQ2_2/DDR1_DQ2_2 DDRC_CA5/DDR1_BG0 N47 a a DDRB_BG1 17
DDRB_BG1 17

em NC/DDR0_MA0 BL49m
em DDRB_MA0 m
DDRA_DQ2_4/DDR0_DQ2_4 DDRC_DQ2_3/DDR1_DQ2_3 NC/DDR1_BG1

em m m m
DDRA_DQ21 BN47 BB48 DDRA_MA0 DDRB_DQ20 AE48
NC/DDR0_MA1 e
BG38eDDRA_MA2 e he he
DDRA_DQ22 DDRA_DQ2_5/DDR0_DQ2_5 DDRA_MA1 DDRA_MA0 18 DDRB_DQ21 DDRC_DQ2_4/DDR1_DQ2_4
BN45 AB47 P42
h h DDRA_DQ23 DDRA_DQ2_6/DDR0_DQ2_6
h h
DDRA_MA1 18
h h DDRB_DQ22 DDRC_DQ2_5/DDR1_DQ2_5 NC/DDR1_MA0 Y49 DDRB_MA1 DDRB_MA0 17
ch
Sc c c BL45 DDRA_MA3 Sc
NC/DDR1_MA1 U48 c
BN48 AB45

Sc Sc c Sc
DDRA_DQ2_7/DDR0_DQ2_7 DDRB_CA5/DDR0_MA2 DDRA_MA2 18 DDRC_DQ2_6/DDR1_DQ2_6 DDRB_MA1 17
S SS kS
DDRA_DQ24 DDRB_DQ23 DDRB_MA2
S
BV42 AE45

ok k ok kU47
DDRA_MA3 18 DDRB_MA2 17

ok k ok k k
DDRA_DQ25 BV39 DDRA_DQ3_0/DDR0_DQ3_0 NC/DDR0_MA3 BJ46 DDRA_MA4 DDRB_DQ24 AD38 DDRC_DQ2_7/DDR1_DQ2_7 DDRD_CA5/DDR1_MA2 Y45 DDRB_MA3

o
DDRA_DQ26 BV43 DDRA_DQ3_1/DDR0_DQ3_1
o o o NC/DDR0_MA4 BG48 DDRA_MA5 DDRA_MA4 18
o
DDRB_DQ25 AD39 DDRC_DQ3_0/DDR1_DQ3_0
o
NC/DDR1_MA4o
NC/DDR1_MA3
o
DDRB_MA4 DDRB_MA3 17
o o o
bb o DDRA_DQ27 DDRA_DQ3_2/DDR0_DQ3_2
b oDDRA_CA0/DDR0_MA5 DDRA_MA6 DDRA_MA5 18
o DDRB_DQ26 DDRC_DQ3_1/DDR1_DQ3_1
o DDRB_MA5 DDRB_MA4 17
o
eb b eb
BW38 BE45 AE39 R49
DDRA_DQ3_3/DDR0_DQ3_3
b DDRA_CA2/DDR0_MA6 BG45 DDRA_MA7 DDRA_MA6 18
eb
DDRC_DQ3_2/DDR1_DQ3_2
b
DDRC_CA0/DDR1_MA5 DDRB_MA5 17
eb
te e e
DDRA_DQ28 DDRB_DQ27 DDRB_MA6
e e DDRA_CA3/DDR0_MA8 BG47 e
BV38 AE43 U49
t ot t ot t
ot t ot t
DDRA_DQ29 DDRA_DQ3_4/DDR0_DQ3_4 DDRA_CA4/DDR0_MA7 DDRA_MA8 DDRA_MA7 18 DDRB_DQ28 DDRC_DQ3_3/DDR1_DQ3_3 DDRC_CA2/DDR1_MA6 DDRB_MA7 DDRB_MA6 17
BW39 AE38 M47
oo oo
NNo
DDRA_DQ30 DDRA_DQ3_5/DDR0_DQ3_5 DDRA_MA9 DDRA_MA8 18 DDRB_DQ29 DDRC_DQ3_4/DDR1_DQ3_4 DDRC_CA4/DDR1_MA7 M45 DDRB_MA8 DDRB_MA7 17
BW42 BE47 AD43
DDRA_DQ31
DDRA_DQ32
BW43
AY48
NN
DDRA_DQ3_6/DDR0_DQ3_6
DDRA_DQ3_7/DDR0_DQ3_7
DDRA_CA1/DDR0_MA9 BJ38
NC/DDR0_MA10 BB47
DDRA_MA10
DDRA_MA11
DDRA_MA9
DDRA_MA10 18 NN
18 DDRB_DQ30
DDRB_DQ31
AD42
AE42
DDRC_DQ3_5/DDR1_DQ3_5
DDRC_DQ3_6/DDR1_DQ3_6 NN DDRC_CA1/DDR1_MA9 P39 DDRB_MA9
DDRC_CA3/DDR1_MA8 R47
DDRB_MA10
DDRB_MA8
DDRB_MA9
17
17
DDRA_DQ33 AY47 DDRB_DQ0_0/DDR0_DQ4_0 NC/DDR0_MA11 BE48 DDRA_MA12 DDRA_MA11 18 DDRB_DQ32 J48 DDRC_DQ3_7/DDR1_DQ3_7 NC/DDR1_MA10 N46 DDRB_MA11 DDRB_MA10 17
DDRA_DQ34 DDRB_DQ0_1/DDR0_DQ4_1 NC/DDR0_MA12 DDRA_MA13 DDRA_MA12 18 DDRB_DQ33 DDRD_DQ0_0/DDR1_DQ4_0 NC/DDR1_MA11 DDRB_MA12 DDRB_MA11 17
AY49 BM39 J45 R48
DDRA_DQ35 DDRB_DQ0_2/DDR0_DQ4_2 DDRB_CA0/DDR0_MA13 DDRA_MA14_WE# DDRA_MA13 18 DDRB_DQ34 DDRD_DQ0_1/DDR1_DQ4_1 NC/DDR1_MA12 DDRB_MA13 DDRB_MA12 17
AU45 BG43 J49 Y41
DDRA_DQ36 DDRB_DQ0_3/DDR0_DQ4_3 DDRB_CA2/DDR0_MA14WE_N DDRA_MA15_CAS# DDRA_MA14_WE# 18 DDRB_DQ35 DDRD_DQ0_2/DDR1_DQ4_2 DDRD_CA0/DDR1_MA13 DDRB_MA14_WE# DDRB_MA13 17
AY45 BJ42 G47 V41
DDRA_DQ37 AU47 DDRB_DQ0_4/DDR0_DQ4_4 DDRB_CA1/DDR0_MA15CAS_N BM41 DDRA_MA16_RAS# DDRA_MA15_CAS# 18 DDRB_DQ36 J47 DDRD_DQ0_3/DDR1_DQ4_3 DDRD_CA2/DDR1_MA14WE_N Y42 DDRB_MA15_CAS# DDRB_MA14_WE# 17
DDRA_DQ38 DDRB_DQ0_5/DDR0_DQ4_5 DDRB_CA3/DDR0_MA16RAS_N DDRA_MA16_RAS# 18 DDRD_DQ0_4/DDR1_DQ4_4 DDRD_CA1/DDR1_MA15CAS_N DDRB_MA15_CAS# 17
mm om
DDRB_DQ37
mm
DDRB_MA16_RAS#
AU48 G45 V47
mm
om
C C
DDRB_MA16_RAS# 17

c.o c.o c.o

DDRA_DQ39 DDRB_DQ0_6/DDR0_DQ4_6 DDRA_ODT0 DDRB_DQ38 DDRD_DQ0_5/DDR1_DQ4_5 DDRD_CA3/DDR1_MA16RAS_N

co co co
AU49 BJ39 G48
.c.cDDRA_ODT1
DDRA_ODT0 18
.s .s .s
DDRA_DQ40 AY42 DDRB_DQ0_7/DDR0_DQ4_7 NC/DDR0_ODT_0 BB45 DDRA_ODT1 DDRB_DQ39 E48 DDRD_DQ0_6/DDR1_DQ4_6 V43 DDRB_ODT0
s DDRA_DQ41 AY38 DDRB_DQ1_0/DDR0_DQ5_0
DDRA_DQS#0cs s
NC/DDR0_ODT_1 18
s DDRB_DQ40 J38 DDRD_DQ0_7/DDR1_DQ4_7 NC/DDR1_ODT_0 V38
s
DDRB_ODT0 17

icic DDRA_DQ42 DDRB_DQ1_1/DDR0_DQ5_1

itic icic DDRB_DQ41 DDRD_DQ1_0/DDR1_DQ5_0 NC/DDR1_ODT_1
cic
tit
at t at
AY43 BY47 G39

at at
DDRB_DQ1_2/DDR0_DQ5_2DDRA_DQSN_0/DDR0_DQSN_0 BY46 DDRD_DQ1_1/DDR1_DQ5_1
aa a
DDRA_DQ43 DDRA_DQS0 DDRB_DQ42 AH46 DDRB_DQS#0
a
BB39 G38
DDRA_DQ44 DDRB_DQ1_3/DDR0_DQ5_3 DDRA_DQSP_0/DDR0_DQSP_0 CC41 DDRA_DQS#1 DDRB_DQ43 DDRD_DQ1_2/DDR1_DQ5_2 DDRC_DQSN_0/DDR1_DQSN_0 AH47 DDRB_DQS0
mm m mm mm
AY39 G42
e DDRA_DQSP_1/DDR0_DQSP_1 e m e he
DDRA_DQ45 DDRB_DQ1_4/DDR0_DQ5_4DDRA_DQSN_1/DDR0_DQSN_1 CE41 DDRA_DQS1 DDRB_DQ44 DDRD_DQ1_3/DDR1_DQ5_3 DDRC_DQSP_0/DDR1_DQSP_0 AJ41 DDRB_DQS#1
e BR47eDDRA_DQS#2 e he
BB38 J39

ch h ch ch
DDRB_DQ1_5/DDR0_DQ5_5 DDRD_DQ1_4/DDR1_DQ5_4 DDRC_DQSN_1/DDR1_DQSN_1 AL41

ch h ch
DDRA_DQ46 BB42 DDRB_DQ45 J42 DDRB_DQS1

Sc Sc BV41 DDRC_DQSN_2/DDR1_DQSN_2 AC46 c c c

DDRA_DQ47 BB43 DDRB_DQ1_6/DDR0_DQ5_6DDRA_DQSN_2/DDR0_DQSN_2 BR46 DDRA_DQS2 DDRB_DQ46 G43 DDRD_DQ1_5/DDR1_DQ5_5 DDRC_DQSP_1/DDR1_DQSP_1 AC47 DDRB_DQS#2

kSkS kS
kS
S
kS kSkS
DDRA_DQ48 DDRB_DQ1_7/DDR0_DQ5_7 DDRA_DQSP_2/DDR0_DQSP_2 DDRA_DQS#3 DDRB_DQ47 DDRD_DQ1_6/DDR1_DQ5_6 DDRB_DQS2

ok ok
AR48 J43
o ok
DDRB_DQ2_0/DDR0_DQ6_0DDRA_DQSN_3/DDR0_DQSN_3
o
DDRD_DQ1_7/DDR1_DQ5_7 DDRC_DQSP_2/DDR1_DQSP_2
o
DDRA_DQ49 BW41 DDRA_DQS3 DDRB_DQ48 DDRB_DQS#3
o o ooAD41 o
AR47 B43 AE41

bo o bo bo o
DDRB_DQ2_1/DDR0_DQ6_1 DDRA_DQSP_3/DDR0_DQSP_3 DDRD_DQ2_0/DDR1_DQ6_0 DDRC_DQSN_3/DDR1_DQSN_3
o o bo o
DDRA_DQ50 AR49 AV46 DDRA_DQS#4 DDRB_DQ49 D43 DDRB_DQS3
b eb
eb b b eb
DDRA_DQ51 AM45 DDRB_DQ2_2/DDR0_DQ6_2DDRB_DQSN_0/DDR0_DQSN_4 AV47 DDRA_DQS4 DDRB_DQ50 A43 DDRD_DQ2_1/DDR1_DQ6_1 DDRC_DQSP_3/DDR1_DQSP_3 H47 DDRB_DQS#4

te t e e
ot
ete t e e
ot t
DDRA_DQ52 DDRB_DQ2_3/DDR0_DQ6_3 DDRB_DQSP_0/DDR0_DQSP_4 DDRA_DQS#5 DDRB_DQ51 DDRD_DQ2_2/DDR1_DQ6_2 DDRD_DQSN_0/DDR1_DQSN_4 DDRB_DQS4

ot t t
AR45 AY41 C40 H46
o o DDRB_DQSP_1/DDR0_DQSP_5 AN46 DDRA_DQS5
DDRB_DQ2_4/DDR0_DQ6_4DDRB_DQSN_1/DDR0_DQSN_5 BB41
o
DDRD_DQ2_3/DDR1_DQ6_3
oo
DDRD_DQSP_0/DDR1_DQSP_4

NNo
DDRA_DQ53 AM47 DDRB_DQ52 C43 G41 DDRB_DQS#5

NN NN NN
DDRA_DQ54 AM48 DDRB_DQ2_5/DDR0_DQ6_5 DDRA_DQS#6 DDRB_DQ53 D40 DDRD_DQ2_4/DDR1_DQ6_4 DDRD_DQSN_1/DDR1_DQSN_5 J41 DDRB_DQS5
DDRA_DQ55 AM49 DDRB_DQ2_6/DDR0_DQ6_6DDRB_DQSN_2/DDR0_DQSN_6 AN47 DDRA_DQS6 DDRB_DQ54 B40 DDRD_DQ2_5/DDR1_DQ6_5 DDRD_DQSP_1/DDR1_DQSP_5 C42 DDRB_DQS#6
DDRA_DQ56 AT42 DDRB_DQ2_7/DDR0_DQ6_7 DDRB_DQSP_2/DDR0_DQSP_6 DDRA_DQS#7 AR41 DDRB_DQ55 A40 DDRD_DQ2_6/DDR1_DQ6_6 DDRD_DQSN_2/DDR1_DQSN_6 DDRB_DQS6
D42
DDRA_DQ57 AT39 DDRB_DQ3_0/DDR0_DQ7_0 DDRB_DQSN_3/DDR0_DQSN_7 AT41 DDRA_DQS7 DDRB_DQ56 B35 DDRD_DQ2_7/DDR1_DQ6_7 DDRD_DQSP_2/DDR1_DQSP_6 D36 DDRB_DQS#7
DDRA_DQ58 AR43 DDRB_DQ3_1/DDR0_DQ7_1 DDRB_DQSP_3/DDR0_DQSP_7 DDRB_DQ57 D35 DDRD_DQ3_0/DDR1_DQ7_0 DDRD_DQSN_3/DDR1_DQSN_7 C36 DDRB_DQS7
DDRA_DQ59 AT38 DDRB_DQ3_2/DDR0_DQ7_2 BF39 DDRA_PAR DDRB_DQ58 A35 DDRD_DQ3_1/DDR1_DQ7_1 DDRD_DQSP_3/DDR1_DQSP_7
DDRA_DQ60 DDRB_DQ3_3/DDR0_DQ7_3 NC/DDR0_PAR DDRA_ACT# DDRA_PAR 18 DDRB_DQ59 DDRD_DQ3_2/DDR1_DQ7_2 DDRB_PAR
AR38 BE49 D38 P38
DDRA_DQ61 DDRB_DQ3_4/DDR0_DQ7_4 NC/DDR0_ACT_N DDRA_ALERT# DDRA_ACT# 18 DDRB_DQ60 DDRD_DQ3_3/DDR1_DQ7_3 NC/DDR1_PAR DDRB_ACT# DDRB_PAR 17
AR39 BD46 C35 M48

om om om om
mm m m
DDRA_DQ62 DDRB_DQ3_5/DDR0_DQ7_5 NC/DDR0_ALERT_N 18 DDRA_ALERT# DDRB_DQ61 DDRD_DQ3_4/DDR1_DQ7_4 NC/DDR1_ACT_N DDRB_ALERT# DDRB_ACT# 17
AR42 C38 M49
c.o co co o
DDRB_DQ3_6/DDR0_DQ7_6 DDRD_DQ3_5/DDR1_DQ7_5 NC/DDR1_ALERT_N 17 DDRB_ALERT#
c c
DDRA_DQ63 DDRB_DQ62
c c s.s.c
AT43 M38 B38

s .s . DDRB_DQ3_7/DDR0_DQ7_7 RSVD_73 C44

.
DDR_SB_VREFCA s s
DDR_SA_VREFCA
. s .s DDRB_DQ63 A38 DDRD_DQ3_6/DDR1_DQ7_6

c c c c
DDR_SA_VREFCA 18
itic E46 DDR_RCOMP_1 i ic i ic i ic
RC501 1 2 1/20W_100_1%_0201 DDR_RCOMP_0 D47 DDR0_VREF_CA B45 DDRD_DQ3_7/DDR1_DQ7_7
2 1/20W_100_1%_0201t
at at at
at@ ICELAKE-U_BGA1526 at
at
DDR_RCOMP_1 DDR_RCOMP_0 DDR1_VREF_CA DDR_VTT_CNTL DDR_SB_VREFCA 17
RC502 1 M39
aa
3 of 19
RC503 1 2 1/20W_100_1%_0201 DDR_RCOMP_2 C47 DDR_VTT_CTL DK47 CPU_DRAMRST#_R

e mm DDR_RCOMP_2 DRAM_RESET_N
2 of 19

e mm e mm e mm
e e e e
ch ch ch ch chch ch
ch ch
ICELAKE-U_BGA1526
c
kS kS kS kS kSkS kSkS kSkS
@

o o o o o o o o o o
bo o
eb
oo
eb
oo
eb
oo boo
te eb eb eb eb e eb
ot ot t ot t ot t ot t
B B

NNo NNo NNo NNo

+3VALW

mm mm mm mm

1
co o co o co o100K_0402_5% co o
RC504

c s.s.c c s.s.c c s.s.c c s.s.c

i i c i i c i i c i i c
atat at at atat atat

2
em m em m em m em m
+1.2V
CPU_DRAMPG_CNTL 55

h e h e h e h e h
Sc ch Sc ch Sc ch Sc ch Sc
+1.2V

Sc
1

ok kS ok kS ok kS ok kS k

1
k
RC505 RC506 C

o o 1/16W_470_1%_0402
o o o o 1 2 2 QC501
o o oo
b bo o o o bobo
1K_0402_5% MMBT3904WH_SOT323-3

eb eb eb
B

te eb eb eb e
E
e 2 t t te
ot t ot ot
RC507
2

3
ot CPU_DRAMRST#_R 1
N
o o NNo N ot NN o
N N
CPU_DRAMRST# 17,18
0_0402_5% DDR_VTT_CNTL
@ 1
CC501

2
0.1U_6.3V_K_X5R_0201
@
2 RC508

mm mm mm mm
10K_0402_5%

co o co o co o co o
@

1
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at at at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019Sheet 5 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
+VCCSTG_TERM
NN NN NN NN
RC601 1 2 51_0402_5% PCH_JTAG_TDO_CPU

RC602 1 @ 2 51_0402_5% PCH_JTAG_TDI_CPU

PCH_JTAG_TMS_CPU
mm mm mm mm
RC603 1 @ 2 51_0402_5%

co o co o co o co o
s.s.c s.s.c s.s.c s.s.c
RC604 1 H_PROCHOT#
2 1K_0402_5%

i c c
t ti PCH_TCK_JTAGX_CPU i ci c i c i c i ci c
RC605 1 a a
2 51_0402_5% at
at at at atat
h eme m
h eme m
h em
e m
h em
e m
h
c h ch ch c ch
kS
c Sc Sc kS ScSc
kS kS kS kS
D D

ok ok k
UC1D
k
oo
PCH_TCK_JTAGX_CPU o oo
oo o o o o o o
b boo o
bobo
CATERR# J4 P3
b eb RC606 1 eb
CATERR_N PROC_TCK
b eb 2 b
H_PECI CD5 K5 PCH_JTAG_TDI_CPU

te e e te e ete
44 H_PECI
499_0402_1% H_PROCHOT#_R C3 PECI PROC_TDI K3 PCH_JTAG_TDO_CPU

ot t ot ot
+3VALW_PCH

ot ot ot
13,44,55 H_PROCHOT#
E3 PROCHOT_N
o
H_THRMTRIP# PROC_TDO P4 PCH_JTAG_TMS_CPU

NNo o
THRMTRIP_N PROC_TMS N1
RC608 N N NN
GPP_E6 XDP_TRST_CPU_N
1 N 2 1/20W_49.9_1%_0201 PROC_OPI_RCOMP N
RC607 1 2 100K_0402_5% 1 TP601 @
CJ41 PROC_TRST_N
RC609 1 @ 2 4.7K_0402_5% RC610 1 2 1/20W_49.9_1%_0201 PCH_OPI_RCOMP DU3 PROC_POPIRCOMP N5 XDP_TRST_CPU_N
RC611 1 @ 2 1/20W_49.9_1%_0201 EDRAM_OPIO_RCOMP A14 PCH_OPIRCOMP PCH_TRST_N R5 PCH_JTAG_TCK 1 TP602 @
RC612 1 @ 2 1/20W_49.9_1%_0201 CPU_EOPIO_RCOMP B14 RSVD_25 PCH_TCK K1 PCH_JTAG_TDI_CPU
RSVD_26 PCH_TDI K2 PCH_JTAG_TDO_CPU
DBG_PMODE DL15 PCH_TDO N3 PCH_JTAG_TMS_CPU
PM_SLP_S0IX_R_N: DBG_PMODE PCH_TMS N2 PCH_TCK_JTAGX_CPU
External pull-up is required.
mm
This strap should sample HIGH. There should NOT be mm DV11
mm PCH_JTAGX
mm
co o co o co o co o
44 EC_SCI# DT11 GPP_E3/CPU_GP0
P6 PROC_PRDY_N 1 TP603 @

s.s.c s.s.c s.s.c PROC_PREQ_N s.s.c

any on-board device driving it to opposite direction 44 EC_SMI GPP_E7/CPU_GP1
PROC_PRDY_N M6 PROC_PREQ_N
during strap sampling. CR38 1 TP604 @
c c c c
GPP_B3/CPU_GP2
c c c c
CR39
i i i i i i i i
at at atGPP_E6 at
GPP_B4/CPU_GP3

at at GPP_E6
DJ38 a
DT12 t at
em em em em emem emem
RC613 1 @ 2 0_0201_5% GPP_H2
40 PCIE_WAKE#_WLAN_R
DL38 GPP_H2/CNV_BT_I2S_SDO
h h h h h h GPP_H19/TIME_SYNC0
h h ch
Sc Sc Sc Sc
+3VALW_PCH
c c Sc Sc Sc
k S k S
ok ok kS
ICELAKE-U_BGA1526

o ok o ok ok ok k
RC614 1 @ 2 1/20W_4.7K_5%_0201 GPP_H2
4 of 19
o o
bo bo o o o
@
o o o o o
te eb t e eb ebeb eb eb ebeb
t t ot t ot t ot t
GPP_H2(PCIE_WAKE#_WLAN_R):
o oo
NNo NNo NNo
This signal has a 20K+/-30% internal pull-down.
0 = Master Attached Flash Sharing (MAFS) is enabled. (Default) NN
1 = Slave Attached Flash Sharing (SAFS) is enabled.
Notes:
1. The internal pull-down is disabled after RSMRST# de-asserts.
2. This signal is in the primary well

C
mm mm mm mm C

c.o
.s co c.o
.s co c.o
.s co c.o
.s co
cics s s s
icic icic icic
+VCCST_CPU

2 t it
@ a at at at at at
at
H_THRMTRIP#
2 a
RC615 1 1K_0402_5%

mm mm mm mm
RC616 1 1/20W_49.9_1%_0201 CATERR#

e e e e e e e e
ch ch chch ch ch ch
ch chc
o kSkSRC617 1
+3VS

o kSkS o kS
kS UC1G kS kS kSkS
o o o CE46 o o o o
bo o bobo
oo oo o o
2 10K_0402_5% EC_SCI#
1/20W_33_1%_0201 b
GPP_G1/SD_DATA0b
eb b b eb eb
RC618 1 2 HDA_BCLK_R CY46 GPP_G6/SD_CLK CC48

te ete e te e te
30 HDA_BITCLK_AUDIO

ot ot ot ot t
HDA_SYNC_R CV49 GPP_R0/HDA_BCLK/I2S0_SCLK
t
RC619 1 2 1/20W_33_1%_0201 CC49
30 HDA_SYNC_AUDIO
CY47 GPP_R1/HDA_SYNC/I2S0_SFRM GPP_G2/SD_DATA1
o o o o NNo
RC620 1 2 1/20W_33_1%_0201 HDA_SDO_R CC47
NN NN N
30 HDA_SDOUT_AUDIO
CV45 GPP_R2/HDA_SDO/I2S0_TXD GPP_G3/SD_DATA2
N
HDA_SDIN0 CF45
30 HDA_SDIN0
DA47 GPP_R3/HDA_SDI0/I2S0_RXD GPP_G4/SD_DATA3 CC45
GPP_R4/HDA_RST_N GPP_G0/SD_CMD CF49
SD3.0
+1.8VALW_PCH DP33 GPP_G7/SD_WP CE47
GPP_D19/I2S_MCLK GPP_G5/SD_CD_N
DC45 DK38
GPP_A23/I2S1_SCLK GPP_H0/CNV_BT_I2S_SDO @
1

DA49 DG38 WIFI_WAKE_N RC621 1 2 0_0201_5% PCIE_WAKE#_WLAN_R

RC622 DA45 GPP_R5/HDA_SDI1/I2S1_SFRM GPP_H1/SD_PWR_EN_N/CNV_BT_I2S_SDO
m m mm DA48 GPP_R6/I2S1_TXD
mm CJ43 SD_COMP RC623 1 2 1/20W_200_1%_0201 m
m
c.o co co o co o co o
4.7K_0402_5% GPP_R7/I2S1_RXD SD3_RCOMP

s.s.c s.s.c s.s.c

CT49

s1 .RC625
CNVI_RF_RESET#_PCH GPP_A7/I2S2_SCLK
s
@ RC624 1 2 33_0402_5% CT48
c c c c
2

40 CNVI_RF_RESET#
itic itic i ic i ic
HDA_SDO_R 0_0402_5% 2 CV47 GPP_A8/I2S2_SFRM/CNV_RF_RESET_N DG36
t t at at
at at
ME_FLASH 44 CNVI_MODEM_CLKREQ_PCH CT47 GPP_A10/I2S2_RXD GPP_S6/SNDW4_CLK/DMIC_CLK0
RC626 1 2 DG34
GPP_R2(HDA_SDO_R): a a aa
33_0402_5%
40 CNVI_MODEM_CLKREQ GPP_A9/I2S2_TXD/MODEM_CLKREQ
GPP_S7/SNDW4_DATA/DMIC_DATA0
This signal has am 20Km mm CY39
mm CV38 SNDW_RCOMP RC627 1m
m2 1/20W_200_1%_0201
he he e e
±30% internal pull-down.
emeasures e e
CY38 GPP_S0/SNDW1_CLK SNDW_RCOMP
e
h h ch h ch ch ch
0 = Enable security defined in the Flash Descriptor. (Default)
1 =c c
GPP_S1/SNDW1_DATA

Sc high using external Pull-up in manufacturing/debug Sc Sc c

Disable Flash Descriptor Security (override). This strap should only AUDIO

kS kS kS kS kS kSkS
be asserted DB39

ok ok k
DD38 GPP_S2/SNDW2_CLK

oo oo o o o o o o
environments ONLY. GPP_S3/SNDW2_DATA

b o Notes:
b o oo oo oo
eb e eb eb
eb eb eb
b
e eb
DF38
1. The internal pull-down is disabled after PCH_PWROK is high.
te
DD39 GPP_S4/SNDW3_CLK/DMIC_CLK1

ot ot t ot t ot ot ot t
B 2. This signal is in the primary well. GPP_S5/SNDW3_DATA/DMIC_DATA1 B

NNo NNo ICELAKE-U_BGA1526

N N
7 of 19 NNo
@

39P_50V_J_NPO_0402 2 1 CC601 HDA_BCLK_R

CC602m m mm mm mm
@
o oHDA_SYNC_R
2P_25V_C_NPO_0201
c.CC603
2 1
co o co o co o
@ 2P_25V_C_NPO_0201 2 s 1
.s c HDA_SDO_R s.s.c s.s.c s.s.c
i c i c ici c i ci c i ci c
@
at at2 1 CC605
10P_0201_50V8F HDA_SDIN0
atat atat atat
mm
e75K_0402_1% em m em m em m
h e h e h e h e h
ch ch ch ch
2 1 RC631 CNVI_RF_RESET#_PCH

Sc Sc Sc Sc ScSc
ok kS ok kS ok kS ok kS k
CNVI_MODEM_CLKREQ_PCH
k
EMC_NS@ 33P_0201_50V8-J 2 1 CC604

o o o o o o o o oo
b bo eb
o
eb
o
eb
o bobo
te e eb eb eb ete
ot ot t ot t ot t ot
NNo NNo NNo NN o

mm mm mm mm
co o co o co o co o
+3VALW_PCH

RC632 1 @
c s.s.c DBG_PMODE
2 100K_0201_5%
c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
at at atat at at at at
A RC633 @ 1 2 1K_0201_5% A

h em em Rising edge of RSMRST# h emem h emem h em em

h h h h ch
DBG_PMODE(Reserved):
c strap
c has a 20 kohm ± 30% internal pull-up. Sc Sc Sc
Sc Sc Sc Sc
This
SThis
Son-board kS
ok ok ok ok
strap should sample high. There should NOT be

o o okany device driving it to opposite direction

during strap sampling. o o ok o o ok o o ok o o
o o k
bb eb eb eb eb
te eb eb eb eb
Notes:
e
t ot t ot t ot ot ot t
1. The internal pull-up is disabled after RSMRST# deasserts.
o 2. This signal is in the primary well.
NNo NNo
Security Classification LC Future Center Secret Data
N
Title
NNo
Issued Date 2018/12/04 Deciphered Date N 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 6 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i
t ti c i i c i i c
at
UC1E

at aPCH_SPI_CLK
a DB42 at at atat
em m em mPCH_SPI_SI em m GPP_C0/SMBCLK DK27 em m
DD43 SPI0_CLK PCH_SMB_CLK

h e h e PCH_SPI_SO DF43 SPI0_MOSI

h e PCH_SMB_DATA
h e h

SMBUS
ch ch ch ch
DP24

Sc Sc Sc Sc ScSc
PCH_SPI_IO2 SPI0_MISO GPP_C1/SMBDATA PCH_SMB_ALERT#

SPI 0
DF42 DL24

kS kS kS kS
D PCH_SPI_IO3 DD41 SPI0_IO2 GPP_C2/SMBALERT_N D

ok ok ok ok k k
PCH_SPI_CS0# DB43 SPI0_IO3
o o o o o o o o oo
bo
DF41 SPI0_CS0_N PCH_SML0_CLK

b bo o o o bo
DK24

eb eb eb
SPI0_CS1_N GPP_C3/SML0CLK

eb eb eb
DB41 DJ24 PCH_SML0_DATA

te e

SML 0
e te
SPI0_CS2_N GPP_C4/SML0DATA DP22 PCH_SML0_ALERT#

ot ot t ot ot otot ot
GPP_C5/SML0ALERT_N

NNo DV16
N N
DT16 GPP_E11/SPI1_CLK/BK1/SBK1 DN22 N
PCH_SML1_CLK N NN o
DU18 GPP_E13/SPI1_MOSI/BK3/SBK3 GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK DL22

SML1
PCH_SML1_DATA

SPI 1
DT18 GPP_E12/SPI1_MISO/BK2/SBK2 GPP_C7/SML1DATA/SUSACK_N
DW18 GPP_E1/SPI1_IO2
DW16 GPP_E2/SPI1_IO3 CR47 ESPI_CLK_R RC702 2 1 1/20W_49.9_1%_0201
+3VALW_PCH GPP_E10/SPI1_CS_N/BK0/SBK0 GPP_A5/ESPI_CLK ESPI_IO0_R ESPI_CLK 44
DU16 CN45 RC703 1 2 1/20W_10_1%_0201
GPP_E8/SATALED_N/SPI1_CS1_N GPP_A0/ESPI_IO0 ESPI_IO1_R ESPI_IO0 44
CN48 RC704 1 2 1/20W_10_1%_0201
mm m
DV19 m
mm GPP_A1/ESPI_IO1 CN49 ESPI_IO2_R RC705 1 2 1/20W_10_1%_0201 mm ESPI_IO1 44

co o coDW19
o CL_CLK co o co o
ESPI_IO2 44

eSPI
GPP_A2/ESPI_IO2 CN47 ESPI_IO3_R RC706 1 2 1/20W_10_1%_0201

s.s.c s.s.cDT19 CL_DATA s.s.c s.s.c

MLINK
GPP_A3/ESPI_IO3 ESPI_CS#_R ESPI_IO3 44
RPC701 CT45 RC707 1 2 0_0402_5% @
ESPI_CS# 44
c c c c
PCH_SML0_CLK GPP_A4/ESPI_CS_N
c c c c
4 1 CR46
i i i i i i i i
at t at at at
CL_RST_N GPP_A6/ESPI_RESET_N ESPI_RST# 44

at at at
3 2 PCH_SML0_DATA
GPP_C2(PCH_SMB_ALERT#):
2.2K_0404_4P2R_5% a
This signal is used to wake the system or generate SMI#.
mm This signal has a 20K+/-30% internal pull-down. e em
m em em
em em
External Pull-up resistor is required.Rising edge of RSMRST#
h eRPC702
e h h h
h h h h ch
ICELAKE-U_BGA1526

Sc Sc Sc Sc
5 of 19

Sc 1 c Sc Sc Sc
0 = Disable Intel ME Crypto Transport Layer Security (TLS)

kS
PCH_SML1_CLK

kS
2 3 cipher suite (no confidentiality). (Default) @

okok 2.2K_0404_4P2R_5% ok okok okok k

4 PCH_SML1_DATA

o
1 = Enable Intel ME Crypto Transport
o
Layer Security (TLS)
o o
o Intelo
AMTo o o o o o o
cipher suite (with confidentiality). Must be
b b pulled up to supportb
b eb eb eb
eb eb eb
with TLS.
te e
ot
e te is disabled after RSMRST# de-asserts. ot t ot t ot t
ot
RC708 1 2 4.7K_0402_5% PCH_SMB_ALERT# Notes: +3VALW_PCH
o
1. The internal
Nsignal
pull-down
NNo
+3VS
NNo NNo
RC701 1 @ 2 4.7K_0402_5% PCH_SML0_ALERT# 2. This
N is in the primary well. +3VS
GPP_C5(PCH_SML0_ALERT#):
Rising edge of RSMRST#

4
3

4
3
This signal has a 20K+/-30% internal pull-down.
0 = Enable eSPI. (Default) RPC703 RPC704

2
1 = Disable eSPI. 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
C
mm Notes: mm mm mm C

c.o
co c.o
co c.oco 18 c.o
co
QC701A
1. The internal pull-down is disabled after RSMRST# de-asserts.

1
2

1
2
s .s s .s
2. This signal is in the primary well PCH_SMB_CLK 6 s1.s s .s
icic icic icic icic

S
SMB_CLK_S3

at at at at

D
at at at at
2N7002KDWH_SOT363-6

5
mm mm mm mm

G
e e QC701B e e e
+1.8VALW_PCH
e e e
ch ch chch ch h ch
ch ch
kS kS75K_0402_1% 2 @ 1 RC710
1K_0402_5% 2 @ 1 RC709 ESPI_CS#
kSkS
PCH_SMB_DATA
kS Sc 3 4
k2N7002KDWH_SOT363-6 kSkS kSkS
c

S
SMB_DATA_S3 18
o o o o o o o o o o

D
o o bo o bo o
bb bo bb o bo eb eb
o
te e
ot
ete ot t
e e
ot
ete ot t
ot NN o NNo NN o NNo

ESPI_RST# RC712 1 2 75K_0402_1%

@ CC701 1 2 0.033UC_10VC_KC_X5RC_0201
mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i ic i ic i ic
at
at at
at at at at
at
e mm e mm e mm e mm
e e e e
ch ch chch ch h ch
ch ch
kS kS kSkS kS Sc kSkS kSkS
c
+3VALW_PCH +3V_SPI

o o o o o o k o o o o
bo oo oo oo oo
RC711 1 2 0_0402_5% @
o
te eb eb eb
b
e eb eb eb
b
e eb
ot t ot t ot t ot t
DC701

ot
B B

NNo NNo NNo NNo

2 1
+3VALW_PCH
2 1
RB521CM-30T2R_VMN2M-2
150K_0402_5% 2 @ 1 RC714 PCH_SPI_CS0# RC715 1 2 0_0402_5% @ SPI_CS# @

100K_0402_5% 2 1 RC716 PCH_SPI_SI RC717 1 2 49.9_0402_1% SPI_SI

mm mm mm mm
c.o co RC721 co o co o co o
100K_0402_5% 2 1 RC718 PCH_SPI_IO2
RC719 1 2 49.9_0402_1% SPI_IO2 +3V_SPI

100K_0402_5% 2
c
1 RC720s.s PCH_SPI_IO3 1 2 49.9_0402_1%
c s.s.c
SPI_IO3
c s.s.c c s.s.c
i i c i i c i i1 c i i c
at
PCH_SPI_SI / PCH_SPI_WP#(IO2)
a/tPCH_SPI_HOLD#(IO3): atat atat atat
em m em m em m em m
External pull-up is required. Recommend 100K if pulled CC702
up to 3.3V or 75K
h h e
if pulled up to 1.8V.
h e h e 0.1U_6.3V_K_X5R_0201
h e h
ch c ch ch
2
c Sc Sc Sc
This strap should sample HIGH. There should NOT be UC702

SS c SPI_CS# 1
/CS S
8
Sc
kS k kS/HOLD(IO3) 7 kS
any on-board device driving it to opposite direction 44 SPI_CS#
kduring ok ok k
VCC
k strap sampling. k
oooo o oDO(IO1)
o o oo
SPI_SO 2 SPI_IO3
o o o3o
o o bobo
44 SPI_SO
b b b b eb eb
eb4 /WP(IO2) eb
SPI_IO2 SPI_CLK

te e e
6
e t e te
ot t ot t ot
CLK SPI_CLK 44

ot o t
NNo NNo GND DI(IO0)
5 SPI_SI
SPI_SI 44
NNo NN o
PCH_SPI_SO RC722 1 2 49.9_0402_1% SPI_SO RC723 1 @ 2 100K_0402_5% W25Q128JVSIQ_SO8

PCH_SPI_CLK RC724 1 2 49.9_0402_1% SPI_CLK CC703 1 2 5P_50V_B_NPO_0402

EMC_NS@

1 2 100K_0402_5%
mm mm mm mm
RC713

co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at at
at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 7 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN

+3VS

mm mm mm mm
RPC801

co o co o co o
PCH_I2C1_SDA_TP

co o
1 4

s.s.c s.s.c s.s.c s.s.c

PCH_I2C1_SCL_TP 2 3

ic i c i c i c i c i c i c i2 c
at
UC1F

at at RC801 1t
2.2K_0404_4P2R_5%

at at atFPR_DELINK a at 10K_0402_5%
PCH_TP_INT#
PCH_TP_INT# CH48 DV33

em
CF48 GPP_B16/GSPI0_CLKm
m e em GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5 em m2 0_0402_5% em m
45 PCH_TP_INT# GPP_B18 GPP_D13/ISH_UART0_RXD DW33

h h e PCH_WLAN_PERST# CF47 GPP_B18/GSPI0_MOSI

h h
GPP_D14/ISH_UART0_TXD DT33 FPR_RESET_C
h h e FPR_DELINK 45
h e h
c ch RC802 1
RC852 1 @ +3VS
c Sc Sc Sc
40 PCH_WLAN_PERST# FPR_RESET 45
c Sc Sc Sc
PCH_WLAN_OFF# CH49 GPP_B17/GSPI0_MISO DU33
D

k SS 40 PCH_WLAN_OFF# PCH_BEEP CH47 GPP_B15/GSPI0_CS0_N

k
GPP_D16/ISH_UART0_CTS_N/CNV_WCEN
k k S S
UART2_TXD 2 49.9K_0402_1%
k
D

oo k 30 PCH_BEEP
o
CL47o
k
GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1_N DK22
o o k
FB_GC6_EN_R
FB_GC6_EN_R 23,26 k
UART2_RXD
o oFPR_DELINK RC803 1 2 49.9K_0402_1%
oo k
o bo
GPP_C13/UART1_TXD/ISH_UART1_TXD DV24o o
bo bo
GPP_C12/UART1_RXD/ISH_UART1_RXD GPU_EVENT#
o bo bo bo
DW24
b GPP_C14/UART1_RTS_N/ISH_UART1_RTS_N b
GPU_EVENT# 26
CK47 GPP_B20/GSPI1_CLK
b DU24b PXS_RST#_R
PXS_PWREN_R RC804 1 OPT@ 2 1K_0201_5% RC890 1 @ 2 2.2K_0402_5%

te e te te CH45 te e te te ete
PXS_PWREN 23
CK46 GPP_B22/GSPI1_MOSI
ot
RC805 1 2 0_0402_5% @

ot tCN43 PXS_RST# 26
o o o
GPP_B21/GSPI1_MISO GPP_C15/UART1_CTS_N/ISH_UART1_CTS_N

NN o
SML1_ALERT# CL48 GPP_B19/GSPI1_CS0_N
N o N o NN o
DGPU_PWROK DP21
GPP_B23/SML1ALERT_N/PCHHOT_N/GSPI1_CS1_N N
GPP_B5/ISH_I2C0_SDA
GPP_B6/ISH_I2C0_SCL
CN42 N
23,58 DGPU_PWROK GPP_C8/UART0_RXD
DK21 CN41
DL21 GPP_C9/UART0_TXD GPP_B7/ISH_I2C1_SDA CL43
DJ22 GPP_C10/UART0_RTS_N GPP_B8/ISH_I2C1_SCL
GPP_C11/UART0_CTS_N CL41
UART2_RXD DT22 GPP_B9/I2C5_SDA/ISH_I2C2_SDA CJ39
mm
DEBUG UART2_TXD DW22 GPP_C20/UART2_RXD
mm GPP_B10/I2C5_SCL/ISH_I2C2_SCL DU36
mm mm
co o co o co o co o
DV22 GPP_C21/UART2_TXD GPP_D0/ISH_GP0 DV36

s.s.c s.s.c s.s.c s.s.c

DU22 GPP_C22/UART2_RTS_N GPP_D1/ISH_GP1 DW36
c c c c
GPP_C23/UART2_CTS_N GPP_D2/ISH_GP2
c c c c
DT36
i i i i i i i i
at at at at
GPP_D3/ISH_GP3

at at at at
DT24 DU34
TS DT23 GPP_C16/I2C0_SDA GPP_D17/ISH_GP4 DW34
mm 45 PCH_I2C1_SDA_TP em em em
GPP_C17/I2C0_SCL GPP_D18/ISH_GP5

em em em
DT14

h eTP
e PCH_I2C1_SDA_TP DW23
h
GPP_E15/ISH_GP6
h
DU14
h
h h h h ch
PCH_I2C1_SCL_TP DU23 GPP_C18/I2C1_SDA GPP_E16/ISH_GP7

ScSc Sc c ScSc Sc Sc Sc
45 PCH_I2C1_SCL_TP GPP_C19/I2C1_SCL

ok DV41k kS ok ok kS
ok ok ok k
DU41

o SENSOR
o o oGPP_H4/I2C2_SDA o o o o o
bb o o GPP_H5/I2C2_SCL
o o o
te e eb eb DT41 GPP_H6/I2C3_SDA
DW41
eb eb eb eb ebeb
ot ot t ot t ot t ot t
+3VS

NNo NNo NNo NNo

GPP_H7/I2C3_SCL
DT40 PXS_PWREN_R RC807 1 OPT@ 2 10K_0201_5%
DW40 GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD RC808 1 @ 2 10K_0201_5%
6 of 19
ICELAKE-U_BGA1526
@

C
mm mm mm mm C

c.oco c.o
co c.o
co c.o co
+3VS

s .s s .s s .s s .s
PXS_RST#_R
2 10K_0201_5% 1 @
icic icic icic ci2c10K_0201_5%
RC809
it
at at at
at at
at
RC810 1t
aa OPT@

mm mm mm mm
RC811 1 e
@ e2 100K_0201_5% e e e e e e
hh ch ch ch ch
ch ch ch RC812 1 @ 2 10K_0201_5%
PCH_WLAN_PERST#

ScSc kS kS kS kS
c
kS kS kS kS
FB_GC6_EN_R
k
oo k o o o o
o o o o
bo o bo
bo bobo bo
bo eb
o o
te eb e
te ete ete eb
o t ot o oto oto ot t
+3VALW_PCH NN+3VS +3VS NN NN +3VS
NNo
GPU_EVENT# RC813 1 OPT@ 2 10K_0201_5%
RC814 1 @ 2 1/20W_150K_5%_0201 SML1_ALERT# RC815 1 @ 2 4.7K_0402_5% PCH_BEEP RC816 1 @ 2 1/20W_4.7K_5%_0201 GPP_B18
RC817 1 @ 2 10K_0201_5%
RC818 1 2 1/20W_20K_5%_0201 GPP_B14(PCH_BEEP): RC819 1 @ 2 1/20W_20K_5%_0201
Rising edge of PCH_PWROK
The strap has a 20 kohm ± 30% internal pull-down.
mm mm mm mm
co o co o GPP_B18:Rising co o co o
0 = Disable Top Swap mode. (Default) PXS_RST#

s.s.c s.s.c s.s.c s.s.c

GPP_B23(SML1_ALERT#): edge of PCH_PWROK
1 = Enable Top Swap mode. This inverts an address on access to SPI 2 0.01U_6.3V_K_X7R_0201
CC801 1
This signal has a 20K+-30% internal pull-down. The signal has a weak internal pull-down.
and firmware hub, so the processor believes it fetches the alternate
c
i ic
0 = 38.4 MHz clock (direct from crystal) (default)
c
i ic 0 = Disable No Reboot mode. (Default) c
i ic c
i ic OPT@

at at at at
boot block instead of the original boot-block. PCH will invert A16
at at at at
1 = 19.2 MHz clock (derived from 38.4 MHz crystal)
Notes: 1 = Enable No Reboot mode (PCH will disable the
(default) for cycles going to the upper two 64-KB blocks in the FWH
TCO Timer system reboot feature). This function is
mm mm
or the appropriate address lines (A16, A17, or A18) as selected
mm m
1. The internal pull-down is disabled after RSMRST# de-asserts

e e
2.When used as PCHHOT# and strap low, a 150K pull-up
e e
useful when running ITP/XDP.
in Top Swap Block size soft strap.
e e DGPU_PWROK
e e m1 UMA@ 2 10K_0201_5%
ch ch hh ch ch
RC820

ch ch ch CC1445 1 2 0.01U_6.3V_K_X7R_0201
is needed to ensure it does not override the internal pull-down
Notes: Notes:
Sc Sc c
strap sampling.
1. The internal pull-down is disabled after
kS kS kS kS
1. The internal pull-down is disabled after PCH_PWROK is high.
kS kS kS kS
3. This signal is in the primary well

2. This signal is in the primary well. ok k

PCH_PWROK is high.
2. Software will not be able to clear the Top Swap bit until the system
o o o o
EMC_NS@
o o
is rebooted.
o o o
bo o
eb
oo
eb
oo bo bo boo
3. The status of this strap is readable using the Top Swap bit

te eb eb eb e e e eb
(Bus0, Device31, Function0, offset DCh, bit4).

ot ot t ot t ot t ot t
B B
4. This signal is in the primary well.
NNo NNo NNo NNo

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat atat atat atat
h em
e m
h eme m
h eme m
h eme m
h
Sc ch Sc ch Sc ch Sc ch ScSc
ok
o kS oko kS oko kS oko kS k
oo k
o
b bo o o o o o o bo
ebeb eb eb eb eb bo
te e
ot t ot t ot t ot
ete
ot NNo NNo NNo NN o

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at at at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 8 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
20 PCIE_CRX_GTX_N[5..8]

20 PCIE_CRX_GTX_P[5..8]

20 PCIE_CTX_C_GRX_N[5..8]

20
mm
PCIE_CTX_C_GRX_P[5..8]
mm mm mm
co o co o co o co o
c s.s.c c s.s.cUC1H c s.s.c c s.s.c
i i c i i c i i c i i c
atat at at
PCIE_CRX_GTX_N7 CV7 DJ8 at at
USB30_RX_N1 atat
em m m m mm em m
USB30_RX_N1 41
PCIE_CRX_GTX_P7 CV6 PCIE7_RXN PCIE1_RXN/USB31_1_RXN DJ6 USB30_RX_P1
e 2 e e PCIE1_RXP/USB31_1_RXPe
e e
USB30_RX_P1 41
DD3 PCIE7_RXP
h h h h h
PCIE_CTX_C_GRX_N7 PCIE_CTX_GRX_N7 USB30_TX_N1
h 2 h
chDJ1
USB3.0 Port1
ch
OPT@ 0.22U_0201_6.3V6-K 1 CC901 DJ2
c c Sc Sc Sc
USB30_TX_N1 41
c c DD5 PCIE7_TXN
Sc
PCIE_CTX_C_GRX_P7 OPT@ 0.22U_0201_6.3V6-K 1 CC902 PCIE_CTX_GRX_P7 PCIE1_TXN/USB31_1_TXN USB30_TX_P1
SS dGPU SS
kS kS
D PCIE7_TXP PCIE1_TXP/USB31_1_TXP USB30_TX_P1 41 D

ok k ok k ok ok k k
PCIE_CRX_GTX_N8 USB30_RX_N2
oo
CT6 DG9
o o o o o o USB30_RX_N2 41
o o
bo
PCIE_CRX_GTX_P8 CT7 PCIE8_RXN PCIE2_RXN/USB31_2_RXN USB30_RX_P2

b bo bo o o bo
DG7
b eb eb
USB30_RX_P2 41
DA3 PCIE8_RXP PCIE2_RXP/USB31_2_RXP

ebPCIE2_TXP/USB31_2_TXP DJ5 USB30_TX_P2

PCIE_CTX_C_GRX_N8 OPT@ 0.22U_0201_6.3V6-K 1 2 CC903 PCIE_CTX_GRX_N8 DJ3 USB30_TX_N2
USB3.0bPort2
te e ete e ete
USB30_TX_N2 41
PCIE_CTX_C_GRX_P8 2 CC904 PCIE_CTX_GRX_P8 DA5 PCIE8_TXN PCIE2_TXN/USB31_2_TXN
tOPT@ ot t ot ot
1

ot ot
0.22U_0201_6.3V6-K
USB30_TX_P2 41
o
PCIE8_TXP

N o PCIE_PRX_DTX_N9
NNo N NN o
N N
40 PCIE_PRX_DTX_N9 CP7 DE7
PCIE_PRX_DTX_P9 CP6 PCIE9_RXN PCIE3_RXN/USB31_3_RXN DE9
40 PCIE_PRX_DTX_P9
CC905 1 2 0.1U_6.3V_K_X5R_0201 PCIE_PTX_DRX_N9 DA2 PCIE9_RXP PCIE3_RXP/USB31_3_RXP DF3
WLAN 40
40
PCIE_PTX_C_DRX_N9
PCIE_PTX_C_DRX_P9
CC906 1 2 0.1U_6.3V_K_X5R_0201 PCIE_PTX_DRX_P9 DA1 PCIE9_TXN PCIE3_TXN/USB31_3_TXN DF5
PCIE9_TXP PCIE3_TXP/USB31_3_TXP
CM7 DC7
CM6 PCIE10_RXN PCIE4_RXN/USB31_4_RXN DC9
CY3 PCIE10_RXP PCIE4_RXP/USB31_4_RXP DF2
mm omm
CY4 PCIE10_TXN
omm
PCIE4_TXN/USB31_4_TXN DF1
mm
co o SATA_PRX_DTX_N0 CK7 co DA6 PCIE_CRX_GTX_N5 .c co co o
PCIE10_TXP PCIE4_TXP/USB31_4_TXP
c
s.s.c 37 s.s . PCIE11_RXN/SATA0_RXN s s. s.s.c
SATA_PRX_DTX_N0

c c c c
SATA_PRX_DTX_P0 PCIE5_RXN/USB31_5_RXN DA7 PCIE_CRX_GTX_P5
c c c c
CK6
i i i i i i i i
at at at at
37 SATA_PRX_DTX_P0
CW2 PCIE11_RXP/SATA0_RXP PCIE5_RXP/USB31_5_RXP DE4 PCIE_CTX_GRX_N5
t at at at
SATA_PTX_DRX_N0 CC907 2 1 0.22U_0201_6.3V6-K OPT@ PCIE_CTX_C_GRX_N5
HDD
a
37 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 CW1 PCIE11_TXN/SATA0_TXN PCIE5_TXN/USB31_5_TXN DE3 PCIE_CTX_GRX_P5 2 1 0.22U_0201_6.3V6-K OPT@ PCIE_CTX_C_GRX_P5
CC908
dGPU
em em m em
37 SATA_PTX_DRX_P0 PCIE11_TXP/SATA0_TXP PCIE5_TXP/USB31_5_TXP

h em h em CJ6
PCIE6_RXN/USB31_6_RXNe
h
CY7 m
ePCIE_CRX_GTX_N6 h em
h h h h ch
CJ7 PCIE12_RXN/SATA1A_RXN PCIE_CRX_GTX_P6

Sc Sc c c DD1 PCIE_CTX_GRX_N6 PCIE_CTX_C_GRX_N6 c c

CY6

Sc Sc Sc
CW5 PCIE12_RXP/SATA1A_RXP PCIE6_RXP/USB31_6_RXP

kS S kS kS kS
CC909 2 1 0.22U_0201_6.3V6-K OPT@

okok okok ok k
CW3 PCIE12_TXN/SATA1A_TXN PCIE6_TXN/USB31_6_TXN DD2 PCIE_CTX_GRX_P6 CC910 2 1 0.22U_0201_6.3V6-K OPT@ PCIE_CTX_C_GRX_P6
o oo o
oo o
PCIE12_TXP/SATA1A_TXP PCIE6_TXP/USB31_6_TXP

b o o bo o PCIE_PRX_DTX_N13
b o o USB20_N1
b o o
eb
CG7 DN8
b b CG6 PCIE13_RXN b USB2N_1 DP8 USB20_N1 41
USB3.0 b
Port2
eb
te te ee ee
37 PCIE_PRX_DTX_N13 PCIE_PRX_DTX_P13 USB20_P1
e te
ot ot t ot otPort1 ot t
37 PCIE_PRX_DTX_P13 PCIE_PTX_DRX_N13 PCIE13_RXP USB2P_1 USB20_P1 41
CT3
PCIE_PTX_DRX_N13o
NNo NNo NNo
37 PCIE_PTX_DRX_P13 CT5 PCIE13_TXN DK11 USB20_N2
37 PCIE_PTX_DRX_P13
PCIE_PRX_DTX_N14 CE6
PCIE13_TXP USB2N_2 DJ11
USB2P_2
USB20_P2 USB20_N2
USB20_P2
41
41 NN USB3.0
37 PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 CE7 PCIE14_RXN DP13
37 PCIE_PRX_DTX_P14 PCIE_PTX_DRX_N14 CT2 PCIE14_RXP USB2N_3 DN13
PCIE14_TXN USB2P_3
TBT
37 PCIE_PTX_DRX_N14 PCIE_PTX_DRX_P14 CT1
37 PCIE_PTX_DRX_P14 PCIE14_TXP DK10
SSD 37 PCIE_PRX_DTX_N15
PCIE_PRX_DTX_N15 CC5
PCIE15_RXN/SATA1B_RXN
USB2N_4
USB2P_4
DJ10 Type-C B
mm
PCIE_PRX_DTX_P15
mm CC6
m mm
om
C C
37 PCIE_PRX_DTX_P15

c.o c.o c.o c.o

PCIE_PTX_DRX_N15 PCIE15_RXP/SATA1B_RXP
USB20_N5

co co co
CR3 DL5
cUSB20_P5 Camera
37 PCIE_PTX_DRX_N15 USB20_N5 33
.s .s .s .s
PCIE_PTX_DRX_P15 CR4 PCIE15_TXN/SATA1B_TXN
USB2N_5 DL3 USB20_P5
s
cic
37 PCIE_PTX_DRX_P15
s
cic CA5 PCIE16_RXN/SATA2_RXN
PCIE15_TXP/SATA1B_TXP
USB2P_5
s
cic
33
s
t it it
PCIE_PRX_DTX_N16
t it
USB20_N6
t icic
at
CA6 DP11

at
37 PCIE_PRX_DTX_N16
aa 37 PCIE_PRX_DTX_P16 aa
PCIE_PRX_DTX_P16 USB2N_6 DN11 USB20_P6
aa
USB20_N6
USB20_P6
33
33 Touch Screen
PCIE_PTX_DRX_N16 CP1 PCIE16_RXP/SATA2_RXP USB2P_6

emem emem
mm mm
37 PCIE_PTX_DRX_N16
USB2N_7e e
PCIE_PTX_DRX_P16 CP2 PCIE16_TXN/SATA2_TXN USB20_N7
e USB20_P7 e
DK13
h h h hh ch
37 PCIE_PTX_DRX_P16 PCIE16_TXP/SATA2_TXP USB20_N7 45
h h hDJ13 Finger Print
ScSc ScSc Sc c DN6 USB20_N8 Sc c c
USB2P_7 USB20_P7 45
DW12
S Card reader ok kS kSkS
40 PCH_BT_OFF#
CR42 GPP_E0/SATAXPCIE0/SATAGP0
o k k o k k SSD_PCIE_DET# CR43 GPP_A12/SATAXPCIE1/SATAGP1
o k k USB2N_8 DP6 USB20_P8 USB20_N8 30
o
o o o o o
bo bo bo bo o
37 SSD_PCIE_DET# GPP_A13/SATAXPCIE2/SATAGP2 USB2P_8 USB20_P8 30
o o o bo o
b b b eb eb
USB_OC0# DW14 DL2 USB20_N9
e
t te
41
te e
USB_OC0#
te e USB20_N9 42
e te
ot ot t
USB_OC3# CT43 GPP_E9/USB_OC0_N USB2N_9 DL1 USB20_P9
t t USB2.0
o o
GPP_A16/USB_OC3_N USB2P_9 USB20_P9 42
o NNo DU12
NNo DP10 USB20_N10
USB20_N10 40 NN o NNo
DU11 GPP_E4/DEVSLP0 USB2N_10 DN10 USB20_P10
BT
PCH_SATA_2_DEVSLP GPP_E5/DEVSLP1 USB2P_10 USB20_P10 40
CV48
GPP_A11/SATA_DEVSLP2 DL6 USB2_ID 1 2 0_0201_5%
Native OD output USB_ID
RC901 @
DT38
DW38 GPP_H12/M2_SKT2_CFG0 DL11 USB2_VBUSSENSE RC902 1 @ 2 0_0201_5%
DV38 GPP_H13/M2_SKT2_CFG1 USB_VBUSSENSE
+3VALW_PCH DU38 GPP_H14/M2_SKT2_CFG2 DN5 USB2_COMP RC903 1 2 1/16W_113_1%_0402
mm 2 1/20W_100_1%_0201 PCIE_RCOMPN DN1o om
m
GPP_H15/M2_SKT2_CFG3 USB2_COMP
mm mm
co o PCIE_RCOMPP .c co o co o
USB_OC0#

s.s.c .cPCIE_RCOMPN s.s.c s.s.c

RC904 1 2 10K_0201_5% RC905 1 CD3
RSVD_81

c c ss DN3
c c
i ic i ic i ic i ic
PCIE_RCOMPP

at at at at
8 of 19

at at at at
+1.8VALW_PCH
e mm e mm ICELAKE-U_BGA1526
e mm e mm
e e @
e e
ch h1 ch ch ch ch ch
ch ch
USB_OC3#
c c
RC906 2 10K_0201_5%

o kS kS RC907 1 2 10K_0201_5% SSD_PCIE_DET#

o kS kS o kSkS o kSkS o kSkS
o o o o o
bo o
eb
oo bo bo eb
oo boo
PCH_SATA_2_DEVSLP

eb eb eb e eb
RC908 2 1 10K_0201_5%

te ot t
+1.8VALW_PCH te e
ot t ot t
ot o t
B PCH_SATA_DEVSLP B

NNo NNo NNo NNo

PCH_SATA_DEVSLP 37
2

RC909
100K_0402_5%

3
D2
1

5
mm mm mm mm
G2 QC901B

co o co o co o co o
s.s.c s.s.c s.s.c s.s.c

S2
PJT7838_SOT363-6
6

i ci c ic i c i ci c i ci c
4
atat atat atat atat
D1

PCH_SATA_2_DEVSLP 2
G1

em m em m em m em m
QC901A

h e h e h e h e h
S1

Sc ch Sc ch Sc ch Sc ch ScSc
kS kS kS kS
1

PJT7838_SOT363-6

ook
o ooko ooko ooko
k
oo k
b bo eb
o
eb
o
eb
o bobo
te e eb eb eb ete
ot ot t ot t ot t ot
NNo NN@o NNo NN o
PCH_SATA_2_DEVSLP RC910 1 2 0_0402_5% PCH_SATA_DEVSLP

1. DEVSLP is an open-drain pin on the PCH side and is not required external pull-up orpull-down. The PCH will
mm mm mm
tri-state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to pull-up
mm
co o co o co o co o
that’s internal to the SATAdevice, per DEVSLP specification). PCH will drive pin low to signal an exit fromDEVSLP state.

s.s.c s.s.c s.s.c s.s.c

2. DEVSLP is supported in direct connect, mSATA/mPCIe, uSSD, M.2.

icic i ci c i c
3. 1 DEVSLP pin is required to support EACH DEVSLP enabled RAID storage device.
i c i ci c
at at at at
(Example: 2 DEVSLP pins are required to support 2 DEVSLP RAID storage devices).
at at at at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 9 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
UC1I

D12 DP27 BOARD_ID0 +1.8VALW_PCH

C12 CSI_E_CLK_N GPP_F8/EMMC_DATA0 DU30 BOARD_ID1
CSI_E_CLK_P GPP_F9/EMMC_DATA1 BOARD_ID2 CNVI_RGI_RSP
mm mm mm mm
B12 DT30 RC1000 1 @ 2 20K_0402_5%
CSI_E_DN_0 GPP_F10/EMMC_DATA2

co o co o
BOARD_ID3

co o 2 20K_0402_5% o o
A12 DT29
c
CSI_E_DP_0 GPP_F11/EMMC_DATA3

s.s.c s.s.c s.s.c s.s.c

G13 DV30 BOARD_ID4 CNVI_BRI_RSP RC1001 1 @
F13 CSI_E_DN_1 GPP_F12/EMMC_DATA4 DU29 BOARD_ID5

ic c CSI_E_DP_1
i c c GPP_F13/EMMC_DATA5
i c c i c c

eMMC
BOARD_ID6
i i i i
DW30

atat at
at at
at at at
K10 GPP_F14/EMMC_DATA6 DW29 BOARD_ID7
L10 CSI_F_CLK_N GPP_F15/EMMC_DATA7 DV28 BOARD_ID8

em m em m em m em m
L8 CSI_F_CLK_P GPP_F7/EMMC_CMD DW28 BOARD_ID9

h e M8 CSI_F_DN_0
h e GPP_F16/EMMC_RCLK BOARD_ID10
h e h e +1.8VALW_PCH
h
ch ch c ch h
DN27

Sc Sc Sc ScRC1002 1 @ ScSc
M11 CSI_F_DP_0 GPP_F17/EMMC_CLK DT28 BOARD_ID11
S
kS kS kS
D
L11 CSI_F_DN_1 GPP_F18/EMMC_RESET_N DU28 EMMC_COMP RC1003 1 2 200_0402_1% 2 4.7K_0402_5% D

ok ok ok k k k k
CSI_F_DP_1 EMMC_RCOMP

o o o o o o oo oo
bo bo
CNVI_BRI_DT_R

b bo bo o bo bo
D9 RC1004 1 @ 2 1/20W_20K_5%_0201

A7 b CNV_WT_D0P b b CNV_WT_D0N
C9 CSI_D_CLK_N DV45 CNV_WT_D0N

te e e e ee ete ete
CSI_D_CLK_P CNV_WT_D0N 40

ot B7t CSI_D_DP_0 ot ot ot
DU45

ot ot
CSI_D_DN_0 CNV_WT_D0P CNV_WT_D1N CNV_WT_D0P 40

NNoB9 o o
DU44
CNV_WT_D1N CNV_WT_D1N 40
DL42 N NN NN
CNV_WT_D1P
N
DT44 GPP_F0 /CNV_BRI_DT /UART0_RTS#
CNV_WT_D1P 40
A9 CSI_D_DN_1 CNV_WT_D1P CNV_WT_CLKN
XTAL Frequency Selection, Rising edge of RSMRST#
CNV_WT_CLKN 40
D7 CSI_D_DP_1 CNV_WT_CLKN DK42 CNV_WT_CLKP
This strap has a 20 kohm ± 30% internal pull-down.
CSI_D_DN_2/CSI_C_DN_0 CNV_WT_CLKP CNV_WT_CLKP 40
C7 This strap should not be pulled high since 24 MHz crystal is not

CSI2
D8 CSI_D_DP_2/CSI_C_DP_0 DP44 CNV_WR_D0N
CSI_D_DN_3/CSI_C_CLK_N CNV_WR_D0N CNV_WR_D0P CNV_WR_D0N 40 supported on the PCH.
C8 DN44
CSI_D_DP_3/CSI_C_CLK_P CNV_WR_D0P DG42 CNV_WR_D1N CNV_WR_D0P 40 0 = 38.4 MHz (default)
G11 CNV_WR_D1N DG44 CNV_WR_D1P CNV_WR_D1N 40 1 = 24 MHz
mm J11 CSI_H_CLK_N
mm CNV_WR_D1P DK44 CNV_WR_CLKN CNV_WR_D1P 40
mm Notes:
mm
c.o
co co co co o co o
F6 CSI_H_CLK_P CNV_WR_CLKN DJ44 CNV_WR_CLKP CNV_WR_CLKN 40 1. The internal pull-down is disabled after RSMRST# de-asserts.
.s s.s.CNV_WT_RCOMP s.s.c s.s.c
CNV_WR_CLKP 40 2. This signal is in the primary well.

CNVi
G6 CSI_H_DN_0 CNV_WR_CLKP

c s G10 CSI_H_DP_0
c
CNV_WT_RCOMP RC1005 1
c c
c c c c
DT45 2 150_0402_1%
i i i i i i i i
at at at at
F10 CSI_H_DN_1
at G8 CSI_H_DP_1
a t DL29 CNVI_BRI_RSP
at CNVI_RGI_DT 40 at
em em em em
J8 CSI_H_DN_2/CSI_G_DN_0 GPP_F1/CNV_BRI_RSP/UART0_RXD CNVI_RGI_DT_R RC1006 1CNVI_BRI_RSP 40

em em GPP_F0/CNV_BRI_DT/UART0_RTS_N m em
DP31 2 1/20W_22_5%_0201
K6 CSI_H_DP_2/CSI_G_DP_0
e
GPP_F2/CNV_RGI_DT/UART0_TXD DL31 CNVI_BRI_DT_R RC1007 1 2 1/20W_22_5%_0201 +1.8VALW_PCH
h h L6 CSI_H_DN_3/CSI_G_CLK_N h
h CNVI_RGI_RSP
h h
CNVI_BRI_DT 40
h h ch
Sc Sc c c40 Sc
DN29

Sc Sc c RC1009 1 Sc
CSI_H_DP_3/CSI_G_CLK_P GPP_F3/CNV_RGI_RSP/UART0_CTS_N CNVI_RGI_RSP

kS kS
CNVI_RGI_DT_R
S S
2 100K_0402_5%

okok CSI_RCOMP k k k o okk k

RC1008 1 2 100_0402_1% CSI2_COMP B4 DJ29 BOARD_ID12

o o oo GPP_F4/CNV_RF_RESET_N DP29 o 1 o 2 1/20W_75K_5%_0201

RC1011 1 2 4.7K_0402_5% o o
bo bo o
@

bb o DP38 b
o GPP_F6/CNV_PA_BLANKING WP_PRESENT RC1010o o o
eb
DT34 DL27
b
GPP_D4/IMGCLKOUT0 GPP_F19/A4WP_PRESENT
b eb eb
te e e e ete e
DK29
t t t
DK36
o DN38
GPP_H20/IMGCLKOUT1 GPP_F5/MODEM_CLKREQ
ot o t t ot t
o NNo
DL36 GPP_H21/IMGCLKOUT2
GPP_H22/IMGCLKOUT3
NN o NNo
GPP_F2 /CNV_RGI_DT /UART0_TXD:
M.2 CNVI MODES, Rising edge of RSMRST# NNo
GPP_H23/IMGCLKOUT4
A weak external pull-up is required.
0 = Integrated CNVi enabled.
1 = Integrated CNVi disabled.
Note:
ICELAKE-U_BGA1526 9 of 19 When a RF companion chip is connected to the PCH CNVi interface,
the device internal pulldown resistor will pull the strap low to
mm mm mm mm
C +3VS @ C
enable CNVi interface.
10K_0201_5% 2 c.o
.s
@ 1 RC1012
co
WLAN_CLKREQ#
c.o
.s co c.o
.s co c.o
.s co
cics s s s
it SSD_CLKREQ#
icic icic icic
at at at at
10K_0201_5% 2 1 RC1013

aGPU_CLKREQ# at at at
mm mm mm mm
10K_0201_5% 2 1 RC1014
e e e e e e e e
ch ch chch ch
ch ch
ch chc
o kS kS
UC1J

o kS kS o kS
kS o kSkS o kSkS
o o o o o
bo o CJ3 bo o bobo bo o
eb
o o
eb b bID eb
CLK_PCIE_WLAN# CF5
te ete ete e
BOARD
te
40 CLK_PCIE_WLAN#

ot ot ot ot t
CLK_PCIE_WLAN CJ5 CLKOUT_PCIE_N0 CLKOUT_PCIE_N5 CF3

ot
40 CLK_PCIE_WLAN CLKOUT_PCIE_P0 CLKOUT_PCIE_P5 DP40
o o o NNo
WLAN_CLKREQ# DK33
NN CL2 NN NN
40 WLAN_CLKREQ# GPP_D5/SRCCLKREQ0_N GPP_H11/SRCCLKREQ5_N +1.8VALW_PCH
CLK_PCIE_SSD#
37 CLK_PCIE_SSD# CLK_PCIE_SSD CLKOUT_PCIE_N1 RTC_X1
CL1 DL48
37 CLK_PCIE_SSD SSD_CLKREQ# CLKOUT_PCIE_P1 RTCX1 RTC_X2
DN34 DL49
37 SSD_CLKREQ# GPP_D6/SRCCLKREQ1_N RTCX2
CLK_PCIE_GPU# CL3 DT47 RTC_RST#
20 CLK_PCIE_GPU# CLK_PCIE_GPU CLKOUT_PCIE_N2 RTCRST_N SRTC_RST#

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%
CL5 DK46
20 CLK_PCIE_GPU CLKOUT_PCIE_P2 SRTCRST_N

1
GPU_CLKREQ#

RC833

RC832

RC831

RC830

RC829

RC828

RC827

RC826

RC825

RC824

RC823

RC822

RC821
DP34
mm 20 GPU_CLKREQ# GPP_D7/SRCCLKREQ2_N
mm mm mm

1
DF49
co o c.o c.o co o
SUSCLK
o SUSCLK
GPD8/SUSCLK 40
co
s.s.c cXTAL_PCH_38P4M_IN s.s.c
CK3

s.s .s
CLKOUT_PCIE_N3

c
CK4
c c s c
i ic itic DU8 XTAL_PCH_38P4M_OUT i ic i ic
CLKOUT_PCIE_P3

17@

15@

NTS@

@
DP36 DW8 @ @

at
at at at
at at
at

2
GPP_D8/SRCCLKREQ3_N XTAL_IN
aXTAL_OUT

2
CJ2

e mm CJ1 CLKOUT_PCIE_N4
em m e mm BOARD_ID0 e mm
e DN40 CLKOUT_PCIE_P4 e XCLK_BIASREF
e BOARD_ID1
e
ch
GPP_H10/SRCCLKREQ4_N h
ch ch ch
DU6 RC1016 1 2 1/20W_60.4_1%_0201

ch c ch ch ch
XCLK_BIASREF BOARD_ID2
c
kS kS
S S S S kSkS kSkS
BOARD_ID3

o o k k 10 of 19

o k k BOARD_ID4
o o
o o o BOARD_ID5
o o
bo o oo oo oo oo
ICELAKE-U_BGA1526
b b eb b
BOARD_ID6

eb b @ b eb e eb
1K_0402_5% 2 @ 1 RC1015 SUSCLK

te e e e e
BOARD_ID7

ot ot t t t ot t ot t
B BOARD_ID8 B
o
NNo NNo NNo NNo
BOARD_ID9
BOARD_ID10
BOARD_ID11
BOARD_ID12

1
100K_0201_5%
RC846

100K_0201_5%
RC845

100K_0201_5%
RC844

100K_0201_5%
RC843

100K_0201_5%
RC842

100K_0201_5%
RC841

100K_0201_5%
RC840

100K_0201_5%
RC839

100K_0201_5%
RC838

100K_0201_5%
RC837

100K_0201_5%
RC836

100K_0201_5%
RC835

100K_0201_5%
RC834
1

1
2m m mm mm mm
co o co o co o co o
XTAL_PCH_38P4M_IN XTAL_PCH_38P4M_IN_R

1415@

1417@

TS@

@
RC1017 1 0_0402_5%

s.s.c s.s.c s.s.c s.s.c

2
@
@ @ @ @ @ @ @ @

2
i c i c ici c i ci c i ci c
ata4t 4 LC1000 3 3 atat atat at at
h em e m
h eme m
h eme m
h em e m
h
Sc ch 1 2
Sc ch Sc ch Sc c14"h 01(R839,R825)
00(R839,R838)
ScSc
ok kS ok kS ok kS ok kS 15" k
1 2

o EXC24CH500U_4P
o o
BOARD_ID5..4
o 17" 10(R826,R838)
oo k
o
b bo o o o o o
b bo bobo
EMC_NS@

eb eb
Sumsang 0000

te eb eb e e
BOARD_ID6/7/8/9 Hynix 0001
e e te
ot ot t ot t t
o ot ot
XTAL_PCH_38P4M_OUT RC1021 1 2 0_0402_5% XTAL_PCH_38P4M_OUT_R M icron 0010

NNo RTC_X1
NNo NN NN o
RTC_X2
XTAL_PCH_38P4M_IN_R 1
RC10231 2 200K_0402_1% XTAL_PCH_38P4M_OUT_R VCCRTC CC1000
RC1022 1 2 10M_0402_5% 1U_6.3V_K_X5R_0201
YC1001 YC1000 RC1018 1 2 20K_0402_1% 2 RTC_RST# RC1019 1 2 0_0402_5% @
EC_RTC_RST# 44
1 2
m m mm SRTC_RST#m
m mm
c.o c.o c.o co o
4
3 RC1020 1 2 20K_0402_1%

co c1o co
NC1 OSC2
.s .s .s s.s.c
32.768KHZ 9PF 202934-PG14 1
1
c s 2 1
c s c s CC1001
c
i
OSC1
i c NC2
i i c i i c
1U_6.3V_K_X5R_0201
i i c
at t at at at at 2 at at
CC1002 CC1003
a
A A
1 1
CC1004 CC1005 10P_0402_50V8J 10P_0402_50V8J

em e2m emem em em em em
38.4MHZ_10PF_7R38400001 2 2

h h
10P_0402_50V8J 10P_0402_50V8J
h h h h h h ch
ScSc ScSc Sc Sc ScSc Sc
2

ok ok ok ok kS
o o ok o o ok o o ok o o ok o o
o o k
bb eb eb eb eb
te e eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 10 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
UC1K

PM_SLP_SUS# DM49 CY42 PBTN_OUT#_R

44 PM_SLP_SUS# PM_SLP_S5# DF45 SLP_SUS_N GPD3/PWRBTN_N DE46 AC_PRESENT_R PBTN_OUT#_R 44
PM_SLP_S4# GPD10/SLP_S5_N GPD1/ACPRESENT AC_PRESENT_R 44
mm mm om mm
DC48 DH48 BATLOW# 1

om
44 PM_SLP_S4# GPD5/SLP_S4_N GPD0/BATLOW_N

co o
PM_SLP_S3#

co o GPD6/SLP_A_N co o
DF47 TP1102 @
CPU_C10_GATE#.c.c
44 PM_SLP_S3# GPD4/SLP_S3_N

s.s.c s.s.c s.s.c

PM_SLP_A# DH47 CL39
s s 1 TP1101 @
PM_SLP_S0# CL45 GPP_B11/PMCALERT DU40

ici c
44 PM_SLP_S0#
i c c GPP_B12/SLP_S0_N GPP_H18/CPU_C10_GATE_N DG40
i c c
SX_EXIT_HOLDOFF#
i c c
atat 40 PM_SLP_WLAN#
at ti
PM_SLP_WLAN#
aPM_SLP_LAN#
DE49
DN48 GPD9/SPL_WLAN_N
GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO
DL45 at at
i
at
at
i
em m em m PCH_RSMRST#_R DG49 SLP_LAN_N mm em m
WAKE_N PCIE_WAKE# 40

h e h e h eDE47
e PCH_LAN_WAKE#
h e h
Sc ch S1c ch Sc chDF48 40 c c
h
ScSc
SYS_RESET# DK19 RSMRST_N GPD_2/LAN_WAKE_N PCH_CNVI_EN# RC1100 1 2 0_0402_5% @
S
kS kS kS 2 0_0201_5% @ VCCST_OVERRIDEk kS
CNVI_EN#
D
2 0_0201_5% @ PLT_RST#_R CM49 SYS_RESET_N GPD11/LANPHYPC/DSWLDO_MON D

ok ok ok k
RC1101

o
26,37,40,44 PLT_RST#
o
GPP_B13/PLTRST_N
o
CE4 VCCST_OVERRIDE_R RC1102 1
o o VCCST_OVERRIDE 46
oo k
o o o o bo
VCCST_OVERRIDE VCCST_PWRGD_R
o b boRC1105 1 b bo b bo bo
CF2 RC1103 1 2 60.4_0402_1%
b
VCCST_PWRGD EC_VCCST_PWRGD 44
b
PCH_DPWROK_R DR48 CE3 VCCSTPWRGOOD_TCSS RC1104 1 2 0_0201_5% @

te e e e e e e e ete
2 0_0201_5% @ PCH_PWROK_R DN47 DSW_PWROK VCCSTPWRGOOD_TCSS CF1 CPU_PROCPWRGD
t t t ot
1

ot o ot o ot t
44 PCH_PWROK
o
SYS_PWROK_R PCH_PWROK PROCPWRGD
o o
RC1106 1 2 0_0201_5% @ DP19 TP1100 @
44 SYS_PWROK SYS_PWROK
NN INPUT3VSEL DN49 NN GPD7
DC47
NN NN
INTRUDER# DR47 INPUT3VSEL
INTRUDER_N
11 of 19

ICELAKE-U_BGA1526

mm mm @
mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat DSW_PWROK and RSMRST# are always separate power good signals atat +3VALW at at atat
h emem h emem h em em h emem
h h h h ch

2
ScSc Sc Sc
c
Sc
S100K_0201_5% ScSc kS Sc
PCH_DPWROK RC1107 1 2 0_0402_5% @ PCH_DPWROK_R RC1135 EC_VCCST_PWRGD

ok ok ok ok
44 PCH_DPWROK

o o ok RC1108 1
o o ok
2 10K_0402_5%
o o ok @ o o ok o o
o o k
bb eb eb eb eb
eb eb eb eb

1
te

3
e
o1t ot ot t ot t
D

ot ot 2 0_0402_5% @ PCH_RSMRST#_R ot
5 QC1101B

NNo NNo
EC_RSMRST#
N NN
RC1109 G
44 EC_RSMRST#
N 2N7002KDWH_SOT363-6

6
D
RC1110 1 2 10K_0402_5% PM_SLP_S3# 2 S @

4
G

S QC1101A

1
2N7002KDWH_SOT363-6
@
C
mm mm mm mm C

c.o
co c.o
co c.o
co c.o
co
+3VALW_PCH

s .s RC1111 2 1 4.7K_0402_5% s .s s .s s .s
icic icic icic icic
@ INPUT3VSEL +VCCST_CPU

at
at at
at at at at
at
RC1112 2 1 100K_0402_5% EC_VCCST_PWRGD RC1113 1 2 1K_0402_5%

e mm e mm e mm e mm
e e Glitch Free Requirements:
e e
chch chch
hSLP_S0#
h h
+3VS h ch
CAD NOTE: Pull-up resistor is required if a device is monitoring

kS
INPUT3VSEL: 3V SELECT STRAP
kS
before RSMRST# de-assertion
Sc Sc Sc c
kS
c
o o kS LOW-> 3.3V +/-5%
HIGH->3.0V +/-5% o o kS 75K for 1.8V Signaling Mode ok k
100K for 3.3V Signaling Mode
o
SYS_RESET# RC1114 1 2 k
o o kS
10K_0201_5%
o o kS
bo o bo
bo eb
o o
eb
o o
eb
o o
eb eb eb eb
+3VALW_PCH

te ot
ete ot t ot t ot t
ot NN o NNo RC1115 1
PM_SLP_S0# 2 100K_0201_5%
NNo NNo
+3VALW_PCH

PCIE_WAKE# RC1116 1 2 10K_0201_5%

VCCRTC
PCH_LAN_WAKE# RC1117 1 2 10K_0402_5%
Glitch Free Requirements:
mm RC1118 12 1M_0402_5% mm mm mm
co o co o co o co o
@ INTRUDER# Cap or pull-down resistor is required PBTN_OUT#_R

s.s.c s.s.c s.s.c BATLOW# s.s.c

RC1119 1 @ 2 100K_0201_5%
Option 1:Cap Implementation
c
i ic RC1121 1 c
i ic 330 nF for 3.3v Ramp Rate from 5-50ms c
i ic RC1120 1 2 100K_0201_5%
c
i ic
at
at at
at at
at at
at
2 10K_0402_5%
33 nF for 3.3V Ramp Rate Less than 5ms AC_PRESENT_R RC1122 1 2 100K_0402_5%

e mm @
e mm e mm e mm
e e Option 2:Pull-down Resistor Implementation
e CPU_C10_GATE#
e
ch ch ch ch ch
CC11002 1 0.1U_6.3V_K_X5R_0201 RC1123 1 @ 2 1/20W_20K_5%_0201

ch ch ch ch
100K for 3.3V Signaling Mode
c
kS kS kS kS kS
75K for 1.8V Signaling Mode

o o kS o o kS o o kS o o kS o o kS
bo bo bo oo oo
SPI Voltage Configuration:
o bo
1 o
eb b
PM_SLP_SUS#

eb eb1 2 0.033UC_10VC_KC_X5RC_0201 b 2 10K_0201_5% e eb

The VCCSPI voltage (3.3V or 1.8V) is selected via a hard strap RC1126 2 100K_0201_5%

te on the INTRUDER#.
te erising
ot
eCC1101
ot
e
ot t
ot t ot ot 1
B PCH_PWROK B

of RTCRST#. Designers should strap thiso

@ RC1124 1

N o
This strap sets the SPI interface signaling voltage at the edge
N SYS_PWROK N NNo
NSPI device as follows.
pin to
interface operational voltage for their target
match the expected
N RC1128 1
PM_SLP_S3# 2 100K_0201_5%
NRC1125 2 10K_0201_5%
0 = SPI interface operation voltage is 3.3V VCCST_OVERRIDE RC1127 1 2 100K_0402_5%
(ground through a 10kohm resistor) @ CC1102 1 2 0.033UC_10VC_KC_X5RC_0201
1 = SPI interface operation voltage is 1.8V
(pulled up with 1 Mohm to VCCRTC)
PM_SLP_S4# RC1129 1 2 100K_0201_5%
mm mm mm mm
co o co o co o co o
@ CC1103 1 2 0.033UC_10VC_KC_X5RC_0201

c s.s.c CC1107 c s.s.c c s.s.c c s.s.c

i i c i i c i i c i i c
at at at at
PCH_RSMRST#_R PM_SLP_A#

atPCH_DPWROK_R CC1109 at at at
2 1 1000P_0201_50V7-K EMC_NS@ @ RC1130 1 2 100K_0201_5%

em m em m em m em m
2 1 1000P_0201_50V7-K EMC_NS@ @ CC1104 1 2 0.033UC_10VC_KC_X5RC_0201

h h e h e h e h e h
ch ch ch
SYS_RESET# 2 1 1000P_0201_50V7-K EMC_NS@

Sc Sc Sc Sc Sc
CC1444

Sc Sc
PM_SLP_WLAN# @ RC1131 1 2 100K_0201_5%

ook k FOR EMC

ok o kS @ CC1105
ok
1
o kS
2 0.033UC_10VC_KC_X5RC_0201
oko kS k
oo k
bo o
eb
o o bb o o
eb
o o bobo
te eb eb eRC1132
e 1 eb ete
ot ot t ot@ tCC1106 1 2 0.033UC_10VC_KC_X5RC_0201 ot t ot
PM_SLP_LAN# @ 2 100K_0201_5%

NNo NNo NNo NN o

PM_SLP_S5# @ RC1133 1 2 100K_0201_5%

@ CC1108 1 2 0.033UC_10VC_KC_X5RC_0201

mm mm mm mm
co o co o co o co o
PLT_RST# RC1134 1 2 100K_0201_5%

c s.s.c c s.s.c c s.s.c c s.s.c

i ic i i c i i c i i c
atat atat at at at at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 11 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot +VCCIN UC1L ot
o +VCCIN oto oto oto
A19
NN CJ35 NN NN NN
AC12 VCCIN_1 VCCIN_52 CK10 +1.2V UC1M +1.2V
V13 VCCIN_2 VCCIN_53 J32
W12 VCCIN_3 VCCIN_54 CL34 AA37 BP39
Y13 VCCIN_4 VCCIN_55 CL35 +VCCST_CPU AG36 VDDQ_1 VDDQ_31 BR37
K29 VCCIN_5 VCCIN_56 CN34 AJ36 VDDQ_2 VDDQ_32 BT38
VCCIN_6 VCCIN_57 VR_SVID_DAT VDDQ_3 VDDQ_33
mm mm mm mm
K31 CN35 RC1201 1 2 100_0402_1% AL36 AC35
VCCIN_7 VCCIN_58 VDDQ_4 VDDQ_34

co o c.o co o co o
B19 CP33 AL49 BU37
VCCIN_8 VCCIN_59
o VDDQ_5 VDDQ_35

s.s.c c s.s.c s.s.c

VR_SVID_ALRT#
.s
B23 CR34 2 56_0402_5% RC1202 1 AN36 BU49
s
B27 VCCIN_9 VCCIN_60 A29 AP37 VDDQ_6 VDDQ_36 CA39
ici c B29 VCCIN_10 VCCIN_61
i
CR35 c i
1
c 2 1/16W_45.3_1%_0402 VR_SVID_CLK
i ci c AR36 VDDQ_7 VDDQ_37
i ci c
CB49

at at
RC1203 @

at at at
at atat
BN10 VCCIN_11 VCCIN_62 CT33 AR37 VDDQ_8 VDDQ_38 L38
BP11 VCCIN_12 VCCIN_63 CT34 AT36 VDDQ_9 VDDQ_39 L49
CAD NOTE:
em m em m em m em m
BP9 VCCIN_13 VCCIN_64 CT35 AT49 VDDQ_10 VDDQ_40 N36
Alert signal must be routed between Clk and Data signals
h e VCCIN_14 VCCIN_65
h e h e VDDQ_11 VDDQ_41
h e h
ch ch ch ch
BR10 CU33
to minimize Cross-Talk. AA49 T49

Sc Sc Sc Sc ScSc
BT11 VCCIN_15 VCCIN_66 D19 AV36 VDDQ_12 VDDQ_42 AC37

kS kS kS kS
D
A21 VCCIN_16 VCCIN_67 D21 AW37 VDDQ_13 VDDQ_43 AD35 D

ok ok ok ok k k
VCCIN_17 VCCIN_68 VDDQ_14 VDDQ_44
oo
BT9 D23 AY36 AD36
o o o o o o o o
bo
VCCIN_18 VCCIN_69 VDDQ_15 VDDQ_45

b bo o o b bo bo
BU10 D24 BA37 AE36

eb eb
VCCIN_19 VCCIN_70 VDDQ_16 VDDQ_46

eb eb
BV36 D27 BA49 AF49

te e te e ete
VCCIN_20 VCCIN_71 VDDQ_17 VDDQ_47

ot t ot t ot
BV9 AA12 BB36

ot ot
oC33
VCCIN_21 VCCIN_72 VDDQ_18

NNo NNo o
BW10 D29 BD36
VCCIN_22 VCCIN_73 VDDQ_19 RSVD_77
BW36
BW9 VCCIN_23
VCCIN_24
VCCIN_74
VCCIN_75
F19
F21
BE37
BF36 VDDQ_20
VDDQ_21
N N A33
RSVD_2 B33
NN
BY10 F23 BF37
C19 VCCIN_25 VCCIN_76 F24 AB36 VDDQ_22 RSVD_3
C23 VCCIN_26 VCCIN_77 F27 BF49 VDDQ_23 BG9
A23 VCCIN_27 VCCIN_78 F29 BG36 VDDQ_24 VCC1P8A_1 BJ9
C27 VCCIN_28 VCCIN_79 G1 BJ36 VDDQ_25 VCC1P8A_2 BM9
C29 VCCIN_29 VCCIN_80 G19 BL37 VDDQ_26 VCC1P8A_3 BW1 0.7A
mm CA36 VCCIN_30 VCCIN_81 G23
mm mm BM49 VDDQ_27 VCC1P8A_4
mm BW2

co o co o co o co o
VCCIN_31 VCCIN_82 VDDQ_28 +VCC1P8A VCC1P8A_5
CA9 AB1 BN37

s.s.c s.s.c s.s.c s.s.c

CB10 VCCIN_32 VCCIN_83 G27 BP38 VDDQ_29
R35
c c c c
VCCIN_33 VCCIN_84 VDDQ_30
VCCSTG_OUT_3 V34
c c c c
CC11 G29
i i i i i i i i
at at at at
VCCIN_34 VCCIN_85 VCCSTG_OUT_4 T34

at at at BY1 at
CC36 H19 +VCCST_CPU 0.605A CB1
CC9 VCCIN_35 VCCIN_86 H23 VCCST VCCSTG_OUT_5 U35

em em
+VCCSTG_CPUm 0.119A +VCCSTG_OUT_Rm
VCCIN_36 VCCIN_87 VCCSTG_OUT_6 AB34

em em e em e em
CD10 H27
CE11 VCCIN_37 VCCIN_88 H29 VCCSTG VCCSTG_OUT_7 W35
h h VCCIN_38 VCCIN_89
h h h h RSVD_74 AA35
h h ch
Sc Sc Sc Sc
A24 J18

Sc Sc c Sc Sc
VCCIN_39 VCCIN_90 RSVD_75 Y34
S kS
CE34 J20

okok okok okok okok k

CE35 VCCIN_40 VCCIN_91 J22 INTERNAL RAIL.F33 RSVD_76

o
CF10 VCCIN_41 VCCIN_92
o
J23
o
+VCCSTG_OUT
G33 VCCSTG_OUT_1
o o o o
bb o VCCIN_42
o
VCCIN_93
o VCCSTG_OUT_2
o o
eb bb bb eb
CF33 AB13 CD2 0.09A
eb eb
VCCIN_43 VCCIN_94 VCCPLL_1 +VCC1.05_OUT_SFR

te e ete ete
CG11 J26 INTERNAL RAIL. E5

ot ot t ot ot ot t
VCCIN_44 VCCIN_95 +VCCSTG_OUT_LGC VCCSTG_OUT_LGC
CG34 J28 CG38

NNo o o NNo
CG35 VCCIN_45 VCCIN_96 K17 VCCPLL_OC_1 CG41
CH10
J30
VCCIN_46
VCCIN_47
VCCIN_97
VCCIN_98
+VCCIN K19
K21
NN NNCG49
VCCPLL_OC_2 CG42
VCCPLL_OC_3
VCCIN_48 VCCIN_99 +VCCSFR_OC 0.16A
VCCPLL_OC_4
CJ11 K23
VCCIN_49 VCCIN_100

1
A27 K24 AD7 INTERNAL RAIL.
+VCCIO_OUT
CJ34 VCCIN_50 VCCIN_101 K27 RC1204 VCCIO_OUT
VCCIN_51 VCCIN_102 M1 1/20W_100_1%_0201
VCCIN_103 U1 ICELAKE-U_BGA1526
VR_SVID_ALRT# VCCIN_104
m mm mm mm
H1 @ 13 of 19

m
C C
56 VR_SVID_ALRT#

c.o VCCIN_SENSE o
c.o c.o

2
VIDALERT VR_SVID_CLK

cH3oVIDSOUT c.c5656o co co
H2 F17
56 VR_SVID_CLK
.s .s .s .s
VIDSCK VCCIN_SENSE G17
VR_SVID_DAT
56
s
VR_SVID_DAT VSSIN_SENSE
s
VSSIN_SENSE
s s
icic icic icic icic
at
at at at at
at at
at
ICELAKE-U_BGA1526

1
@
mm mm mm mm
RC1205 12 of 19

e e e e
1/20W_100_1%_0201
e e e e
chch chch ch
ch ch
ch chc
kSkS kSkS kS
kS kSkS kSkS
2

o o o o o o o o o o
bo o bobo bobo bo
bo eb
o o
te eb ete ete e
te eb
ot ot o oto ot
o ot t
NNo
+VCCST_CPU
NN NN NN

1U_6.3V_M_X5R_0201
1U_6.3V_M_X5R_0201

CC1213
1 VCCST:

CC1212
1 1x1uF 0402 Close SOC
+1.8VALW_PCH +VCC1P8A +VCCSTG_OUT_LGC +VCCSTG_TERM
1x0402 (holder）
2
0.7A
m mm mm 2 mm
om
RC1208 1 2 0_5%_0603 1 2 0_5%_0603
c.o co o co o co o
@ RC1206 @ @

.
ss c s.s.c s.s.c s.s.c
22UC_6.3VC_MC_X5RC_0603

c
i ic c
i ic c
i ic c
i ic
10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

at at at at
1 1 1

at at at at
CC1204

CC1205

CC1206

VCC1P8A
1x10uF 0402 close toBGA

e mm 1x0603(hold)
e mm e mm e mm
e 2 2 2 W>1.8mm
e e e
chch @
ch
ch chch ch ch chc
kS kS kS kS kSkS kS kS kSkS
@

o o o o o o o o o o
bo o
eb
oo
eb
oo
eb
oo boo
eb eb eb eb e eb
+VCCSTG_CPU

te ot t ot t ot ot t
ot ot VCCSTG:
B B

NNo NNo NNo

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1 N N
1 1x1uF 0402 Close SOC

CC1214

CC1215
1x0402 (holder）
+1.2V +VCCSFR_OC If VCCST is enabled by SLP_S4#, 2 2
no power gate is required for @
VCCPLL_OC and it can
0.16A
mm mm mm mm
be merged with VDDQ directly.
RC1207 1
0_0402_5% @ 2

c.o co1 co o co o co o
.s s.s.c s.s.c s.s.c
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

s
VCCPLL_OC:
i ci c 1
ici c
1x1uF 0402 Close SOC
i ci c i ci c
at at at at
CC1216

CC1217

at at at at
1x0402 (holder）
m
ee m em m em m em m
e e e
2 2

chch Sc
h
ch Sc
h
ch Sc
h
ch Sc
h
@

k S S kS kS kS Sc
oo k oko oko oko
k
oo k
bo o
eb
o o
eb
o o
eb
o o bobo
te eb eb eb eb ete
ot ot t ot t ot t ot
NNo NNo NNo NN o

+VCCSTG_OUT_R
+VCCSTG_OUT

RC1210 1 2 0_5%_0603
m mm mm mm
@
1m
co o co o co o co o
1U_6.3V_M_X5R_0201

s.s.c s.s.c s.s.c s.s.c

CC1211

icic i ci c i c i c i ci c
at
at atat at at at at
A 2 A
@
mm em em em
h e e h em h em h em
Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 12 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
+1.8VALW +1.8VALW_PCH

PJ1301
1 2
1 2
mm mm mm mm
co o co o co o co o
+VCCIN_AUX JUMP_43X39

s.s.c s.s.c +VCCPRIM_3P3 s.s.c s.s.c

UC1N
@
ici c i c c
iDF23 i ci c i ci c
atat at at DG26 at
at at
at
AH1
AW10 VCCIN_AUX_1 VCCPRIM_3P3_2

em em em
+VCCPDSW_3P3 m
e m AY11 VCCIN_AUX_2
AY9 VCCIN_AUX_3 e m
VCCPRIM_3P3_3
VCCPRIM_3P3_4
DG28
e m +3VALW_PCH
e em
h h h h h
Sc ch c ch Sc ch S@c c4mAh
ScSc
BA10 VCCIN_AUX_4 +VCCPRIM_1P8
BB9 VCCIN_AUX_5 S
kS kS kS kS
D D
RC1302 1 2 0_0402_5%

ok ok ok ok k k
CH1 VCCIN_AUX_6
oo

1U_6.3V_M_X5R_0201
DF15
o o o o
VCCDSW_3P3:
o o
CK11 VCCIN_AUX_7
o o bo
VCCPRIM_1P8_2 DF17

b bo bo o b bo bo
1 1x0402(holder）DE31
bVCCIN_AUX_9 eb
VCCIN_AUX_8 VCCPRIM_1P8_3

eb

CC1301
CL10 DF18

te e e eVCCIN_AUX_10 e e ete
VCCPRIM_1P8_4 DF20

ot t ot t ot
CM11

ot ot o ot
VCCPRIM_1P8_5 DG17

NNoCN10 o
CN1
AJ1 VCCIN_AUX_11 VCCPRIM_1P8_6 DG18
N NN NN
2
VCCIN_AUX_12
CP11 VCCIN_AUX_13
VCCPRIM_1P8_7 DG20
VCCPRIM_1P8_8 DF34
N @

CR10 VCCIN_AUX_14 VCCPRIM_1P8_9

CT11 VCCIN_AUX_15
CU10 VCCIN_AUX_16
CV1 VCCIN_AUX_17 +3VALW_PCH +VCCPRIM_3P3
CV11 VCCIN_AUX_18 202mA
mm CW10
om
VCCIN_AUX_19
m DW37
mm RC1303 1 2 0_0402_5% @
mm
co o co o c.o
INTERNAL RAIL.

DW15 c co co
VCCIN_AUX_20 VCCLDOSTD_0P85 +VCCLDOSTD_OUT_0P85
CY11

s.s.c s.s.c
VCCPRIM_3P3:
VCCA_CLKLDO_1P8 s. .s
s.INTERNAL RAIL.
VCCIN_AUX_21
s

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
DC1 0.165A +VCCA_CLKLDO_1P8 1x0402(holder）DG26
1 1
c c c c
VCCIN_AUX_22
c c c c

CC1302

CC1303
AL1
i i i i i i i i
at at at at
VCCIN_AUX_23 1x0402(holder）DF23
at at DD34 INTERNAL RAIL. at at
P13 DW32 +VCCDPHY_1P24
VCCDPHY_1P24
R12 VCCIN_AUX_24

em em em @ em
VCCIN_AUX_25

em em em e@m
T13 2 2
VCCDSW_1P05 VCCIN_AUX_26 +VCCDSW_1P05
U12
h h h h VCCIN_AUX_27
h h h h ch
Sc cc cc Sc
DC11 BY2

Sc Sc Sc
VCCIN_AUX_28
VCC1P05_1 CB2

kS S kS kS kS
+VCCIN_AUX DE12

okok k okok k
DF12 VCCIN_AUX_29
VCC1P05_2 CC1 FET TO VCCST_CPU & VCCSTG_CPU

o o o VCC1P05_3
AM1 VCCIN_AUX_30 +VCC1.05_OUT_FET
o TO o
o o
o bobo +VCC1.05_OUT_SFR o o o o o o
VCCIN_AUX_31
bb b eb eb
AN1 CD1
b eb eb
SHORT CPU SIDE VCCPLL.
VCCPLL_2 VCCIN_AUX_32
te e ee
1

e te
AT11

ot ot ot t ot t ot t
RC1304 AT9 VCCIN_AUX_33
DG31 INTERNAL RAIL.
100_0402_1%
NN o VCCPRIM_1P05_1
AU10
AV9
VCCIN_AUX_34
VCCIN_AUX_35
DG29 NNo NNo
+3VALW_PCH +V3.3A_1.8A_PCH_SPI NNo
VCCPRIM_1P05_2 VCCIN_AUX_36 VCCPRIM_1P05 is internal supply rail.
2

VCCIN_AUX_VCCSENSE BF9 DF29 Do not connect to external supply 3mA SPI

55 VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE VCCIN_AUX_VCCSENSE VCCPRIM_1P05_3 Merge the pins together.
BD9 RC1305 1 2 0_0402_5% @
55 VCCIN_AUX_VSSSENSE VCCIN_AUX_VSSSENSE DF31 +VCC1.05_OUT_PCH
VCCPRIM_1P05_4
1

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
RC1306 DG33 VCCRTC 1 1
VCCRTC
mm omm mm mm

CC1304

CC1305
C 100_0402_1% 1.05V 0.2A DJ15 C
+V1.05A_BYPASS

c.o c.o c.o

VCC_V1P05EXT_1P05
o .c.co co co
DE31 +VCCPDSW_3P3
.s c .s .s
1.05V / 0.76V 0.2A CY34 VCCDSW_3P3
s VCCPGPPR s s s s
+VNN_BYPASS
2

VCC_VNNEXT_1P05 DF26 2 2
cic iciCL38 icic icic
VID[1] VID[0] VCCIN_AUX
it c VCCIN_AUX_VID0
+VCCPGPPR_3P3_1P8
t at at at
DC33

at CJ38 at at
+VCCPRIM_3P3 0 0 0
VCCPRIM_3P3_1
aa GPP_B0/CORE_VID0 VCCIN_AUX_VID1 VCCIN_AUX_VID0 55
0 1 1.1 @ @

em mm m mm
DD35 1 0 1.65

em m
+VCCPRIM_1P8 VCCIN_AUX_VID1 55
e e e
VCCPRIM_1P8_1 GPP_B1/CORE_VID1 CN38 GPPC_B2_VRALERT_N
e e e
1 1 1.8
h h ch ch ch
GPP_B2/VRALERT_N
cc h DB34
h ch ch
Sc
+V3.3A_1.8A_PCH_SPI

Sc c
VCCSPI
S kS kS kS
ok kS ok ok o kS o kS o kS
oo o o o
ICELAKE-U_BGA1526

bo
@o
b eb
o bo bo bo
bo eb
o o
eb eb
14 of 19

e
t te e te ete
o ot t ot ot ot t
NNo NN o NN o NNo
+1.8VALW_PCH
+VCCPRIM_1P8
+3VALW_PCH PJ1308 1.3A
1 2
1 2
mm mm mm mm

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
co o co o co o c.o
JUMP_43X39

s.s.c s.s.c DC1301 s.s.c s.s co

RC1312 VCCPRIM_1P8:
@ 1 1 1

CC1308

CC1309

CC1310
20K_0201_5% 1x0402(holder）DG20
c
i ic c
titic c
i ic c
i ic
at
at H_PROCHOT# a a at
at at
a2 t

2
2 1 GPPC_B2_VRALERT_N 2 2

e mm 6,44,55
e mm e mm @e
m m @
e e e e
ch ch ch ch ch
2 1 @

ch ch RB521CM-30T2R_VMN2M-2
ch ch c
o kS kS o kSkS o kSkS o kSkS o kSkS
o o o o o
bo oo oo oo oo
RC1314 1 @ 2 0_0402_5%
o
te eb eb eb eb eb
b
e eb b
e eb
ot ot t ot t ot t ot t
B B

NNo NNo NNo NNo

+1.8VALW_PCH +VCCPGPPR_3P3_1P8

5mA
RC1307 1 2 0_0402_5% @
VCCPGPPR:Audio Power:

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
1 1

CC1306

CC1307
mm mm mm mm
co o co o co o co o
2 2

s.s.c s.s.c s.s.c s.s.c

@ @

i ci c i ci c i ci c i ci c
at
at at at atat atat
h em e m
h em e m
h eme m
h em e m
h
Sc ch Sc c h
ScSc
h
S c ch ScSc
ok kS ok kS k k S k
VCCRTC +VCCPRIM_1P8
k k k
+VCC1.05_OUT_SFR +VCCDSW_1P05 +VCCDPHY_1P24 +VCCLDOSTD_OUT_0P85 +V1.05A_BYPASS +VNN_BYPASS +VCCA_CLKLDO_1P8

o o o o oo oo oo
o o bo bo b2 o o @ bobo
0.165A
b b b b b
te ee e e te
RC1310 1 0_5%_0603 VCCA_CLKLDO_1P8:
e te te te
ot ot t ot t
1

1
1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

100K_0201_5%

1K_0402_5%

By Default: 47uF 0603 is stuffed

o o
1 1 1 1 1 1 1

NNo o o o
with a 0 Ohm resistor; Inductor is
CC1316

CC1317

CC1218

CC1219

CC1312

CC1313
4.7U_0402_6.3V6M

CC1311
2.2U_0402_6.3V6M

RC1309

RC1311

LC1301
NN N N
placeholder; 100mOhm Resistor is
NN

0_0402_5%
1 2 stuffed only when Inductor is

RC1313
0.6UH_HBLE041B-R60MSA_7.65A_20% stuffed.
2 2 2 2 2 2 2 @ @ Place the component near to package
2

@ @ pin
@ DW15 right after signal breakout.

2
It is recommended to have GND
shield around the VCC trace

47U_6.3V_M_X5R_0805_H1.25

1U_6.3V_M_X5R_0201
1 1 routing, and minimum of 4nH of loop

CC1314

CC1315
mm mm mm mm inductance from BGA to LC filter

co o co o co o co o
c s.s.c c s.s.c c s.s.c 2 2
c s.s.c
i ic
t t VCCPLL: i i c i i c i i c
aDG33 atat at at atat
VCCRTC: VCCDSW_1P05: VCCDSW_1P05: VCCLDOSTD_0P85 For volume segment platform this rail is disabled. @
a
A A
Keep the pin floating (do not short this pin to
mm
1x0.1uF 0402 1x1uF 0402 SOC 1x1uF 0402 DD34 1x4.7uF 0402
em
1x2.2uF 0402
m em em
em em
ground).

h e0402
1x1uF
e 1x0402 (holder） edge w/i3 mm
h
edge
ew/i 3 mm
h h
c c h
Sc
h
Sc
h
Sc
h ch
k SS Sc Sc Sc kS Sc
o ok ok ok ok ok okok o o k
bo o
eb
o o
eb
o o
eb
o o
eb
o o
te eb eb eb eb eb
o t ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 13 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN

mm mm mm mm
co o co o co o co o
s.s.c s.s.c s.s.c s.s.c
+1.2V

i ci c i c i c i ci c i ci c
at
at at
at at
at atat
h eme m 1
h eme m
h em
e m
h em
e m
h
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

h 1 1 1
ch ch ch
ScSc CC1414 Sc Sc Sc ScSc

CC1405

CC1415

CC1406
VDDQ:
kS kS kS
D D

k
oo k ok
6x1uF 0402 Back ,Outer row
ok ok k
oo k
o 2x10uF 0402 back Outer row
o o
bo o o o bo
2 2 2 2

bo eb
o
eb
o
eb
o bo
3x0402 (holder）back Outer row
te e eb eb eb ete
ot t ot t ot t ot
2x22uF 0603 (SODIMM need)
ot NNo
1x0603(holder)
NNo NNo NN o

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i
t 1t ic i
t 1t i c i i c i i c
1 aa 1 aa atat atat
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 1 1 1 1

emem em em emem emem

CC1402

CC1401

CC1413

CC1418

CC1419

CC1404

CC1421

CC1422

CC1403

CC1420

CC1416

CC1417

CC1423
h h h h h h h h ch
ScSc kS
cc ScSc ScSc kS Sc
2 2 2 2 2 2 2 2 2 2 2 2 2
S
o okok @ @ @ @ @ @ @
o o
@
ok @ @ @ @ @
o okok o okok o o o k
bb o bb o o o o
te e t e e eb eb eb eb ebeb
ot o t ot t ot t ot t
NNo NNo NNo NNo

m mm mm mm
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

m1
C C
1 1 1 1 1 1

c.o
co c.o
co c.o
co c.o
co
CC1432

CC1434

CC1409

CC1424

CC1411

CC1407

CC1425

s .s s .s s .s s .s
icic2 2 2 2 2 2
icic
2
icic icic
atat at
at at
at at
at
m m mm mm mm
hehe ch
e e
ch
e e
ch
e e
ch
ScSc ch ch ch c
k
oo k o kSkS o kS
kS o kSkS o kSkS
o o o o
bo o bobo bobo bo
bo eb
o o
te eb ete ete ete eb
o t oto oto oto ot t
NN NN NN NNo
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1 1 1 1 1 1 1 1 1 1
CC1426

CC1428

CC1429

CC1430

CC1410

CC1408

CC1433

CC1412

CC1431

CC1427

2
mm 2 2 2 2 2 2
mm 2 2 2
mm mm
co o co o co o co o
@
c [email protected] @@ @ @
c s.s.c@ @ @ @
c s.s.c c s.s.c
i ic i ic i ic i ic
at
at at
at at
at at
at
e mm e mm e mm e mm
e e e e
chch chch chch ch
ch chc
o kS kS o kSkS o kSkS o kSkS o kSkS
o o o o o
bo o
eb
oo
eb
oo
eb
oo boo
te eb eb eb eb e eb
ot ot t ot t ot t ot t
B B

NNo NNo NNo NNo

+1.8VALW_PCH
+3VALW_PCH
+VCCIN +VCCIN_AUX
mm mm mm mm
co o 1 oo
c co o co o
s.s.c s.s.c s.s.c s.s.c
1 1
CC1441 EMC_NS@
12P_50V_F_COG_0402

CC1442 EMC_NS@
12P_50V_F_COG_0402

CC1443 EMC_NS@
12P_50V_F_COG_0402

i c c
i1 ic c
i 2 i ci c i ci c
at t at at
0.1U_6.3V_K_X5R_0201

at t at at
1 1 1 1
aa
CC1435 EMC_NS@
100P_0402_50V8J

CC1436 EMC_NS@
12P_50V_F_COG_0402

CC1437

CC1438 EMC_NS@
100P_0402_50V8J

CC1439 EMC_NS@
12P_50V_F_COG_0402

2 2

h eme m
h em e m
h eme m
h eme m
h
h 2 2 2 2 2
ch ch ch
ScSc Sc Sc Sc ScSc
k k ok kS ok kS ok kS k k
EMC_NS@

oo o o o oo
bo o
eb
o o
eb
o o
eb
o o bobo
te eb eb eb eb ete
ot ot t ot t ot t ot
EMC CAPS refer CRB NNo EMC CAPS refer CRB NNo NNo NN o

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at at at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 14 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat UC1O at
at UC1P at
at atat
h eme m
h eme m
h em
e m
h eme m
h
h h ch c ch
A11 AF45 BT3 CR37

ScSc
c c Sc ScSc
A46 VSS_1 VSS_75 AF47 BT39 VSS_149 VSS_223 CR45
SS kS
kS kS
D
BA45 VSS_2 VSS_76 AG1 BT41 VSS_150 VSS_224 CR49 D

k
oo k BA47 VSS_3 VSS_77 AG11
k
oo k BT42 VSS_151 VSS_225 CT37
ok UC1Q
oF11 k
oo k
o o
bo o o o bo
VSS_4 VSS_78 VSS_152 VSS_226
o o o boF31 bo
BB11 AG3 BT43 CT39 DJ33
BB3 VSS_5
b eb bVSS_363
VSS_79 AG38 VSS_153 VSS_227 VSS_297 VSS_362

eb b eb
BT7 CT42 DJ36

te e e te eVSS_364 ete
BB7 VSS_6 VSS_80 AG39 VSS_154 VSS_228 DJ42 VSS_298
t ot t ot
BU45 CT9 F45

ot o ot ot VSS_365
oVSS_300
BC37 VSS_7 VSS_81 AG41 VSS_155 VSS_229 DK3 VSS_299
NNo o
BU47 CU45 F47
BD3 VSS_8 VSS_82 A31 BV1 VSS_156 VSS_230
BD38 VSS_9
VSS_10
VSS_83
VSS_84
AG42 NN BV11 VSS_157 VSS_231
CU47
CU49 N N
DK4
DK49 VSS_301
F8
VSS_366 G21 NN
BD39 AG43 BV2 VSS_158 VSS_232 CV3 DK6 VSS_302 VSS_367 G24
BD41 VSS_11 VSS_85 AG5 BV3 VSS_159 VSS_233 CV34 DK8 VSS_303 VSS_368 G3
A48 VSS_12 VSS_86 AG9 BV7 VSS_160 VSS_234 CV35 DL10 VSS_304 VSS_369 G31
BD42 VSS_13 VSS_87 AH2 BW3 VSS_161 VSS_235 CV5 DL13 VSS_305 VSS_370 G36
BD43 VSS_14 VSS_88 AH37 BW37 VSS_162 VSS_236 CV9 DL44 VSS_306 VSS_371 G49
BD45 VSS_15 VSS_89 AH45 BW5 VSS_163 VSS_237 CY41 DL47 VSS_307 VSS_372 G5
mm
BD49 VSS_16 VSS_90 AH49
mm BW6 VSS_164 VSS_238 CY45
mm DM47 VSS_308 VSS_373
mm
H17

co o co o co o co o
BD5 VSS_17 VSS_91 AJ2 BW7 VSS_165 VSS_239 CY49 DN15 VSS_309 VSS_374 H21

s.s.c s.s.c s.s.c s.s.c

BD6 VSS_18 VSS_92 AJ3 BY37 VSS_166 VSS_240 CY9 DN19 VSS_310 VSS_375 H24
c c c c
VSS_19 VSS_93 VSS_167 VSS_241 VSS_311 VSS_376
c c c c
BD7 A34 BY45 D13 DN24 H31
i i i i i i i i
at at at at
VSS_20 VSS_94 VSS_168 VSS_242 VSS_312 VSS_377

at at at at
BE1 AK37 BY49 D17 DN31 H33
BE2 VSS_21 VSS_95 AL2 C11 VSS_169 VSS_243 D31 DN36 VSS_313 VSS_378 H36

em em em em
VSS_22 VSS_96 VSS_170 VSS_244 VSS_314 VSS_379

em em em em
BF3 AL45 C13 D44 DN42 H45
A49 VSS_23 VSS_97 AL47 C14 VSS_171 VSS_245 D49 DP45 VSS_315 VSS_380 H49
h h VSS_24 VSS_98
h h VSS_172 VSS_246
h h h
VSS_316
h VSS_381
ch
Sc Sc Sc Sc
BF45 AL6 C17 DA10 DR49 J10

Sc Sc Sc Sc Sc
VSS_25 VSS_99 VSS_173 VSS_247 VSS_317 VSS_382

kS
BF47 AM2 C21 DA33 DT1 J13

okok okok okok okok k

BF7 VSS_26 VSS_100 AM37 C24 VSS_174 VSS_248 DA9 DT10 VSS_318 VSS_383 J16

o
BG3 VSS_27 VSS_101 AN2
o
C31 VSS_175 VSS_249 DB32
o
DT15
o
VSS_319 VSS_384 J36
o o o
bb o VSS_28 VSS_102
o VSS_176 VSS_250
o oVSS_320 VSS_385
o
eb eb eb eb
BG41 AN38 C34 DB35 DT20 J6

eb eb eb eb
VSS_29 VSS_103 VSS_177 VSS_251 VSS_321 VSS_386
te e
BG7 AN39 C39 DB38 DT27 K11

ot ot t ot t ot t ot t
BH37 VSS_30 VSS_104 A36 C48 VSS_178 VSS_252 DB45 DT3 VSS_322 VSS_387 K33

NNo NNo NNo NNo

BJ1 VSS_31 VSS_105 AN41 C49 VSS_179 VSS_253 DB47 DT32 VSS_323 VSS_388 K8
BJ2 VSS_32 VSS_106 AN42 C6 VSS_180 VSS_254 DB49 DT37 VSS_324 VSS_389 L36
BJ3 VSS_33 VSS_107 AN43 CA3 VSS_181 VSS_255 DC3 DT42 VSS_325 VSS_390 L39
AA45 VSS_34 VSS_108 AN45 CA38 VSS_182 VSS_256 DC49 DT49 VSS_326 VSS_391 L41
BJ41 VSS_35 VSS_109 AN49 CA41 VSS_183 VSS_257 DC5 DT6 VSS_327 VSS_392 L42
BJ43 VSS_36 VSS_110 AN6 CA42 VSS_184 VSS_258 DC6 DT7 VSS_328 VSS_393 L43
BJ45 VSS_37 VSS_111 AR1 CA43 VSS_185 VSS_259 DD37 DT8 VSS_329 VSS_394 L45
BJ49 VSS_38 VSS_112 AR11 CA7 VSS_186 VSS_260 DD42 DU1 VSS_330 VSS_395 L47
VSS_39 VSS_113 VSS_187 VSS_261 VSS_331 VSS_396
C
mm
BJ7 AR2
mm CB37 DE10
mm DU10
mm
M10 C

c.o c.o c.o c.o

VSS_40 VSS_114 VSS_188 VSS_262 VSS_332 VSS_397

co co co co
BM11 AR3 CB45 DE13 DU15 M3
.s .s .s .s
BM3 VSS_41 VSS_115 A39 CB47 VSS_189 VSS_263 DE17 DU2 VSS_333 VSS_398 M36
s BM45 VSS_42 VSS_116 AR7 s CC3 VSS_190 VSS_264 DE18 s DU20 VSS_334
s
VSS_399 M5
icic VSS_43 VSS_117
icic VSS_191 VSS_265
icic VSS_335
icic
VSS_400

at at at at
BM47 AR9 CC7 DE20 DU27 N45

at at at at
BM5 VSS_44 VSS_118 AT3 CE37 VSS_192 VSS_266 DE22 DU32 VSS_336 VSS_401 N49
VSS_45 VSS_119 VSS_193 VSS_267 VSS_337 VSS_402
mm mm mm mm
AA47 AT45 CE45 DE23 DU37 P11
e e e e
VSS_46 VSS_120 VSS_194 VSS_268 VSS_338 VSS_403
e e e e
BM6 AT47 CE49 DE26 DU48 P41

ch ch ch ch ch
VSS_47 VSS_121 VSS_195 VSS_269 VSS_339 VSS_404

ch ch ch ch
BM7 AT5 CE9 DE28 DU49 P8
BP1 VSS_48 VSS_122 AT6 CG37 VSS_196 VSS_270 DE29 DU7 VSS_340 VSS_405 R3
c
kSkS kSkS kS
kS kSkS kSkS
BP2 VSS_49 VSS_123 AT7 CG39 VSS_197 VSS_271 DE33 DV2 VSS_341 VSS_406 R37
o
VSS_50 VSS_124
o
VSS_198 VSS_272
o
VSS_342 VSS_407
o
BP3 AU37
o
CG43 DE45
o
DV44
o o
T11
o o
bo bo bo bo o
VSS_51 VSS_125 VSS_199 VSS_273 VSS_343 VSS_408
o BP43 AV11
bo
CG45 DE6
bo
DV48
bo
T36
o
eb eb eb
BP7 VSS_52 VSS_126 A42 CG47 VSS_200 VSS_274 DF13 DV8 VSS_344 VSS_409 T41
te ot
ete ot
ete ot
ete ot t
VSS_53 VSS_127 VSS_201 VSS_275 VSS_345 VSS_410

ot
BR45 AV3 CG9 DF22 DW1 T43
VSS_54 VSS_128 VSS_202 VSS_276 VSS_346 VSS_411
BR49
AB11 VSS_55
VSS_56
VSS_129
VSS_130
AV38
AV39
NN o CH3
CH5 VSS_203
VSS_204
VSS_277
VSS_278
DF28
NN
DF33 o NN o
DW10
DW2 VSS_347
VSS_348
VSS_412
VSS_413
T45
T47
NNo
AB3 AV41 CJ37 DF35 DW20 U3
AB38 VSS_57 VSS_131 AV42 CJ42 VSS_205 VSS_279 DF39 DW27 VSS_349 VSS_414 U37
AB39 VSS_58 VSS_132 AV43 CJ9 VSS_206 VSS_280 DG10 DW44 VSS_350 VSS_415 U5
AB41 VSS_59 VSS_133 AV45 CK45 VSS_207 VSS_281 DG12 DW46 VSS_351 VSS_416 V11
A17 VSS_60 VSS_134 AV49 CK49 VSS_208 VSS_282 DG13 DW48 VSS_352 VSS_417 V36
AB42 VSS_61 VSS_135 AV7 CK9 VSS_209 VSS_283 DG15 DW49 VSS_353 VSS_418 V45
AB43 VSS_62 VSS_136 AY3 CL37 VSS_210 VSS_284 DG22 DW7 VSS_354 VSS_419 V49
AB5 mm
VSS_63 VSS_137 A44 mm
CL42 VSS_211 VSS_285 DG23 mm E11 VSS_355 VSS_420 V9 mm
co o co o co o co o
VSS_64 VSS_138 VSS_212 VSS_286 VSS_356 VSS_421

s.s.c s.s.c s.s.c s.s.c

AB6 AY7 CL49 DG47 E34 W37
AC45 VSS_65 VSS_139 B17 CM45 VSS_213 VSS_287 DG6 E36 VSS_357 VSS_422 Y36
c
i ic AC49 VSS_66 VSS_140 B2
c
i ic CM47 VSS_214 VSS_288 DH1
c
i ic E39 VSS_358 VSS_423 Y38
c
i ic
at
at at
at at
at at
at
AD10 VSS_67 VSS_141 B21 CM9 VSS_215 VSS_289 DH3 E42 VSS_359 VSS_424 Y43
AD11 VSS_68 VSS_142 B24 CN3 VSS_216 VSS_290 DH45 E6 VSS_360 VSS_425 Y9

e mm AD34 VSS_69 VSS_143 B3

e mm CN37 VSS_217 VSS_291 DH5
e mm VSS_361 VSS_426
e mm DE15
e VSS_70 VSS_144
e VSS_218 VSS_292
e VSS_427
e
ch ch ch ch ch
AD37 B31 CN39 DJ19

ch ch ch ch
VSS_71 VSS_145 VSS_219 VSS_293
c
A3 B48 CN5 DJ21 ICELAKE-U_BGA1526

kS kS kS kS kS
VSS_72 VSS_146 VSS_220 VSS_294

kS kS kS kS kS
AE6 BA1 CP9 DJ27 @
AF37 VSS_73 VSS_147 BA2 CR32 VSS_221 VSS_295 DJ31
o o VSS_74 VSS_148
o o VSS_222 VSS_296
o o
17 of 19
o o o o
bo o
eb
oo
eb
oo
eb
oo boo
eb eb eb eb e eb
16 of 19

te
15 of 19

ot t ot t ot t ot t
ICELAKE-U_BGA1526 ICELAKE-U_BGA1526

ot
B B
@ @

NNo NNo NNo NNo

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat atat atat atat
h em
e m
h eme m
h eme m
h eme m
h
Sc ch Sc ch Sc ch Sc ch ScSc
ok
o kS oko kS oko kS oko kS k
oo k
o
b bo o o o o o o bo
ebeb eb eb eb eb bo
te e
ot t ot t ot t ot
ete
ot NNo NNo NNo NN o

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at at at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 15 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
PROCESSOR CFG STRAPS
+VCCIO_OUT
mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
RC1606 1 2 1K_0201_5%
i i c i i c i i c i i c
at at at
2 t
at at RSVD_TP_35 DA11 at at
UC1R
N34
CFG0 RC1601 1 @
a1K_0201_5%
em m em m em m em m
AK10 RSVD_TP_27 CL32

h e BT36 RSVD_TP_28
h e RSVD_TP_36 CN32
h e h e h
Sc ch c ch Sc ch Sc Sc
h
ScSc
AH10 RSVD_7 RSVD_TP_37 CY35
S
kS S kS
D
BC10 RSVD_TP_29 RSVD_32 DB37 D

ok ok k RSVD_TP_31 ok ok k k k
RSVD_TP_30 RSVD_33
oo
CH33 DF37
o o oCJ32 o o
Stall reset sequence after PCU
bo o o bo
RSVD_34

b bo bo AM10 b b o Test_Point_12MIL
eb
o lock until de-asserted bo
eb
BF11 IST_TP_0 1 TP1601
PLL
te e e e IST_TRIG_0 te e ete
RSVD_12 IST_TP_0 BD11 IST_TP_1
t ot t ot
1

ot o t o t 1 TP1603 Test_Point_12MIL
TP1602 Test_Point_12MIL
RSVD_TP_32 IST_TP_1 BE10

NNo NNo 1 TP1604 Test_Point_12MIL NNo o

BH10
J34 RSVD_TP_33 IST_TRIG_0 BF10
NN
IST_TRIG_1
1:Normal(Default)
Y11
RSVD_TP_34 IST_TRIG_1

L34
CW33
RSVD_9 PCH_IST_TP_0 CY32
PCH_IST_TP_0
PCH_IST_TP_1
1 TP1605 Test_Point_12MIL
1 TP1607 Test_Point_12MIL
CFG0 *
RSVD_10 PCH_IST_TP_1 0:Stall
AJ11 CY37
CG32 RSVD_17 RSVD_27 CV37
RSVD_21 RSVD_28
mm om mm mm
co o
CK33
c om co o co o
+VCCIO_OUT

s.s.c s.s .c G34 s.s.c s.s.c

BP41 RSVD_22
c AL11 RSVD_20
c c c
RSVD_35
c c c c
H34
i i i i i i i i
at at at at
BG11 RSVD_23 RSVD_46 DJ34

at at at at
CFG1 RC1607 1 2 1K_0201_5%
AN11 RSVD_24 RSVD_48 DK31

mm M13 RSVD_16
mm em em
RSVD_49 DK15

em em
CFG8 RC1608 1 2 1K_0201_5%

he e he e
Test_Point_12MIL TP1608 1 TP_M34 M34 RSVD_18 RSVD_50 CP3
h h ch
ch ch h h
RSVD_19 RSVD_51 CP5

Sc Sc Sc cc
1 2 1K_0201_5%

Sc Sc
CFG9 RC1609
RSVD_52 AN9
CFG10 SRC1610
k k S k k S
ok k kS 1 kS
ok k
RSVD_53 AN7 2 1K_0201_5%

o o o o o oDU42 RSVD_54 AF10

o o o o RC1611 1 o o o
b o b o RSVD_36 AE11
o o o
eb b eb
CFG12 2 1K_0201_5%
b b DW42 RSVD_42 RSVD_37 H5
eb b eb
te
t e
oo t e t e D33 RSVD_43 RSVD_38 D1
ot t ot
ete CFG13 RC1612 1 2 1K_0201_5%
ot t
o NN
L13 RSVD_44
K13 RSVD_45
RSVD_39 DJ40
RSVD_40 DK40
NNo NN o NNo
RSVD_47 RSVD_41

ICELAKE-U_BGA1526
18 of 19
@
C
mm mm mm mm C

c.o
.s co c.o
.s co c.o
.s co c.o
.s co
s s s s
icic icic icic icic
at
at at
at at
at at at
e mm e mm e mm mm
e e e RC1602e
1 e 2 1K_0402_5%
chch ch h ch
ch ch ch ch
CFG4
c c
o kSkS o kSkS
UC1S

o kS
kS o kS kS o kSkS
o CFG0o AG6 o o o
bo o oo bobo
o o o o
A47

eb e1 b
eb eb eb eb eb
CFG1 AE7 CFG_0 RSVD_TP_1 B47

te Test_Point_12MIL TP1611 t t
AG7 CFG_1
ot
ete ot t ot t
RSVD_TP_2

o t o AD9 CFG_2
NNo o NNo Embedded Display Port Presence StrapNNo
C1
AE9 CFG_3
NN
CFG4
RSVD_57 E1
AB9 CFG_4 RSVD_58
Test_Point_12MIL CFG_5
TP1613 1 AJ6 CT32
AB7 CFG_6 RSVD_TP_10 CV32
CFG8 V10 CFG_7
CFG_8
RSVD_TP_11 1:Disable
CFG9 AJ5 G15
CFG10 Y10 CFG_9 RSVD_79 F15 CFG4
0:Enable(Default)
mm
AJ7
AB10
om
CFG_10

m
CFG_11
BW11
RSVD_80
mm mm *
co o co o co o
CFG12

co C16
CFG_12
RSVD_TP_5
c
s.s.c s.s.c s.s.c
AL7 CA11

s.s.VSS_428
CFG13
CFG_13
RSVD_TP_6
AL9

t c
itic t c
itic VSS_429 A16
AJ9 CFG_14
c
i ic c
i ic
at
at atat
CFG_15
aa CFG16 V6 aa
mm Test_Point_12MIL TP1615 1
CFG_17 m
e em
V7 CFG_16 C2
mm mm
he e e e e e
RSVD_55 A4
Y6 h h
c h c chch ch
ch ch
RSVD_56

S c CFG18
S Y7 c c
kS kS kS
CFG_18
kk S k kAD6 S CFG_19
DP5
RSVD_65 DR5
kS kS kS
oo o oo o o o o o o o
RSVD_66
oo oo oo
RC1603 2 1 1/20W_49.9_1%_0201

b o b o CFG_RCOMP

eb b eb eb eb eb
b
e eb
D14

te te
RSVD_59
1e
1 T9 E16

ot t ot t ot t
Test_Point_12MIL TP1617

ot ot11
B
T7 BPM_N_0 RSVD_60 B

Test_Point_12MIL o
Test_Point_12MIL TP1618

NNo NNo NNo

T10 BPM_N_1
NN
TP1619 DV6
Test_Point_12MIL TP1620 T6 BPM_N_2 RSVD_TP_13 DW6
BPM_N_3 RSVD_TP_14
BJ11 DP2
BL10 RSVD_62 RSVD_TP_24 DP1
RSVD_63 RSVD_TP_25
Test_Point_12MIL TP1621 1 AV1 DW4
RSVD_TP_17 RSVD_TP_15 DV4
mm mm mm mm
AT2 RSVD_TP_16

co o coTP_3 o CM33 co o co o
AT1 RSVD_TP_18

s.s.c s.s.c s.s.c s.s.c

AU1 RSVD_TP_20
DB10 CFG16 RC1604 1 2 51_0402_5%
TP_4 RSVD_TP_19
c c c c
AU2
i i c i c
i RSVD_TP_12 R1
RSVD_TP_21
i i c i i c
atat
t t atat atat
CFG18 RC1605 1 2 51_0402_5%
AV2
RSVD_TP_22 aa
em m em m em m em m
DW3
RSVD_TP_7 DV3
h e DP3
h he h e h e h
ch ch ch
DT2 RSVD_67 RSVD_TP_8

Sc c c Sc Sc ScSc
RSVD_68
S
DH49

ok kS ok
S
ok kS ok kS k
RSVD_TP_9
k k
AR10

o o o o AP10 RSVD_69 DL8

o o o o oo
b bo b bo o o bobo
BP36 RSVD_71 RSVD_TP_23

eb eb eb eb
BM36 RSVD_70
te e e
DW47
e t e te
ot t ot t ot
RSVD_72 TP_1 DV47

ot o t
NNo NNo NNo o
J15 TP_2 DU47
K15 VSS_430
VSS_431
VSS_432
P10
NN
TP1622 1 C5 RSVD_TP_26
Test_Point_12MIL D4 SKTOCC_N
A5 RSVD_78
RSVD_64
19 of 19

mm mm mm mm
co o co o co o co o
ICELAKE-U_BGA1526

s.s.c s.s.c s.s.c s.s.c

@

icic i ci c i c i c i ci c
atat atat at at at at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date

NN 2018/08/20 S740-ICL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 16 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1

e te te te te
ot DDR4 Memory Down oto oto oto +0.6VS
oto
+1.2V

NN NN DDRB_BG1_R NN DDP@
2 0_0201_5% DDRB_BG1
NN

1
RD1701 1 DDRB_BG1 5 2
RD1702 CD1701

1
0_0402_5% .01U_0402_16V7-K
RD1765 @ M D@
0_0201_5% 1

2
SDP@

2
DDRB_CLK0#
RD1704 1 M D@ 2 1/20W_39_5%_0201
UD1701 UD1702 DDRB_CLK0 RD1705 1 M D@ 2 1/20W_39_5%_0201

mm mm mm mm
co o co o co o co o
DDRB_M A0 P3 G2 DDRB_DQ11 DDRB_M A0 P3 G2 DDRB_DQ61
5 DDRB_M A0 DDRB_M A1 A0 DQL0 DDRB_DQ8 DDRB_M A1 A0 DQL0 DDRB_DQ60

s.s.c s.s.c s.s.c s.s.c

P7 F7 P7 F7
5 DDRB_M A1 DDRB_M A2 R3 A1 DQL1 H3 DDRB_DQ14 DDRB_M A2 R3 A1 DQL1 H3 DDRB_DQ59
5 DDRB_M A2 DDRB_M A3 A2 DQL2 DDRB_DQ15 DDRB_M A3 A2 DQL2 DDRB_DQ57

c c c c
N7 H7 N7 H7 +0.6VS

i c i c i c i c
5 DDRB_M A3 DDRB_M A4 DDRB_DQ9 DDRB_M A4 DDRB_DQ62

i i i i
N3 A3 DQL3 H2 N3 A3 DQL3 H2

at at at at
Byte 1 Byte 7
at at at at
5 DDRB_M A4 DDRB_M A5 P8 A4 DQL4 H8 DDRB_DQ10 DDRB_M A5 P8 A4 DQL4 H8 DDRB_DQ58 UD1_DDRB_UZQ 1 SDP@ 2 0_0402_5%
RD1706
5 DDRB_M A5 DDRB_M A6 P2 A5 DQL5 J3 DDRB_DQ12 DDRB_M A6 P2 A5 DQL5 J3 DDRB_DQ63 DDRB_M A0
RD1713 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_M A6 DDRB_M A7 A6 DQL6 DDRB_DQ13 DDRB_M A7 A6 DQL6 DDRB_DQ56 DDRB_M A1

em em em em
D R8 J7 R8 J7 RD1709 1 DDP@ 2 240_0402_1% RD1714 1 M D@ 2 1/20W_39_5%_0201 D

m m m m
5 DDRB_M A7 DDRB_M A8 R2 A7 DQL7 A3 DDRB_DQ4 DDRB_M A8 R2 A7 DQL7 A3 DDRB_DQ45 DDRB_M A2 RD1716 1 M D@ 2 1/20W_39_5%_0201

e e e e
5 DDRB_M A8 DDRB_M A9 R7 A8 DQU0 B8 DDRB_DQ6 DDRB_M A9 R7 A8 DQU0 B8 DDRB_DQ42 DDRB_M A3
RD1717 1 M D@ 2 1/20W_39_5%_0201

h h h h h
ch ch h5 ch
5 DDRB_M A9 DDRB_M A10 M3 A9 DQU1 C3 DDRB_DQ1 DDRB_M A10 M3 A9 DQU1 C3 DDRB_DQ47 UD2_DDRB_UZQ 1 SDP@ 2 0_0402_5%
RD1711

Sc Sc Sc c Sc ScSc
5 DDRB_M A10 DDRB_M A11 T2 A10/AP DQU2 C7 DDRB_DQ3 DDRB_M A11 T2 A10/AP DQU2 C7 DDRB_DQ41 DDRB_M A4 RD1719 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_M A11 DDRB_M A12 A11 DQU3 Byte 0
DDRB_DQ0 DDRB_M A12 A11 DQU3 Byte DDRB_DQ46 DDRB_M A5

kS kS kS kS
M7 C2 M7 C2 RD1712 1 DDP@ 2 240_0402_1% RD1720 1 M D@ 2 1/20W_39_5%_0201

ok ok ok ok k
5 DDRB_M A12 DDRB_M A13 A12/BC_N DQU4 DDRB_DQ7 DDRB_M A13 A12/BC_N DQU4 DDRB_DQ40 DDRB_M A6

k
T8 C8 T8 C8 RD1722 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_M A13 DDRB_DQ2 DDRB_DQ43 DDRB_M A7

oo
A13 DQU5 D3 A13 DQU5 D3 1 2 1/20W_39_5%_0201

o o o o
DDRB_M A14_WE# DDRB_DQ5 DDRB_M A14_WE# DDRB_DQ44 UD3_DDRB_UZQ DDRB_M A8 RD1723 M D@
DQU6 DQU6

o o o o bo
L2 D7 L2 D7 RD1715 1 SDP@ 2 0_0402_5% RD1725 1 M D@ 2 1/20W_39_5%_0201

b bo o o o bo
5 DDRB_M A14_WE# DDRB_M A15_CAS# M8 WE_N/A14 DQU7 DDRB_M A15_CAS# M8 WE_N/A14 DQU7

eb eb eb eb eb eb
5 DDRB_M A15_CAS# DDRB_M A16_RAS# L8 CAS_N/A15 +1.2V DDRB_M A16_RAS# L8 CAS_N/A15 +1.2V 1 DDP@ 2 240_0402_1% DDRB_M A9 1 2 1/20W_39_5%_0201

te e
RD1718 RD1726 M D@

e te
5 DDRB_M A16_RAS# RAS_N/A16 RAS_N/A16 DDRB_M A10

ot t ot t ot t ot
D1 D1 RD1727 1 M D@ 2 1/20W_39_5%_0201

ot
DDRB_CLK0# K8 VDD1 J1 DDRB_CLK0# K8 VDD1 J1 DDRB_M A11 1 2 1/20W_39_5%_0201
RD1728 M D@

NNo NNo NNo o

5 DDRB_CLK0# DDRB_CLK0 K7 CK_C VDD2 L1 DDRB_CLK0 K7 CK_C VDD2 L1 UD4_DDRB_UZQ 1 SDP@ 2 0_0402_5% DDRB_M A12 1 2 1/20W_39_5%_0201
RD1721 RD1729 M D@

NN
5 DDRB_CLK0 CK_T VDD3 R1 CK_T VDD3 R1
DDRB_CKE0 K2 VDD4 B3 DDRB_CKE0 K2 VDD4 B3 1 DDP@ 2 240_0402_1%
5 DDRB_CKE0 RD1724
CKE VDD5 G7 CKE VDD5 G7 DDRB_M A13 RD1730 1 M D@ 2 1/20W_39_5%_0201
DDRB_DQS#1 F3 VDD6 B9 DDRB_DQS#7 F3 VDD6 B9 DDRB_M A14_WE# 1 2 1/20W_39_5%_0201
DDRB_DQS1 G3 DQSL_C VDD7 J9 DDRB_DQ[0..63] DDRB_DQS7 G3 DQSL_C VDD7 J9 DDRB_M A15_CAS# RD1731 1 M D@
2 1/20W_39_5%_0201
RD1734 M D@
DDRB_DQS#0 A7 DQSL_T VDD8 L9 DDRB_DQ[0..63] 5 DDRB_DQS#5 A7 DQSL_T VDD8 L9 DDRB_M A16_RAS# RD1737 1 M D@ 2 1/20W_39_5%_0201
+1.2V DDRB_DQS0 B7 DQSU_C VDD9 T9 DDRB_DQS#[0..7] +1.2V DDRB_DQS5 B7 DQSU_C VDD9 T9
DQSU_T VDD10 DDRB_DQS#[0..7] 5 DQSU_T VDD10
2 0_0402_5%@ DDRB_DM 1 DDRB_DQS[0..7] 2 0_0402_5%@ DDRB_DM 2 +1.2V DDRB_BG0
RD17321 E2 A1 RD1733 1 E2 A1 RD1738 1 M D@ 2 1/20W_39_5%_0201
RD17351 2 0_0402_5%@ DDRB_DM 0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_DQS[0..7] 5
RD1736 1 2 0_0402_5%@ DDRB_DM 3 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_BG1_R
RD1739 1 DDP@ 2 1/20W_39_5%_0201
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1

mm mm mm mm
DDRB_BS0# N2 VDDQ3 F2 DDRB_BS0# N2 VDDQ3 F2 DDRB_BS0#
5 DDRB_BS0# RD1740 1 M D@ 2 1/20W_39_5%_0201

co o co o co o co o
DDRB_BS1# N8 BA0 VDDQ4 J2 DDRB_BS1# N8 BA0 VDDQ4 J2 DDRB_BS1# RD1741 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_BS1# 1

1
BA1 VDDQ5 BA1 VDDQ5

s.s.c s.s.c s.s.c s.s.c

F8 F8 CD1702
DDRB_ACT # L3 VDDQ6 J8 DDRB_ACT # L3 VDDQ6 J8 DDRB_ACT #
5 DDRB_ACT # 0.1U_6.3V_K_X5R_0201 RD1743 RD1742 1 M D@ 2 1/20W_39_5%_0201
DDRB_CS0# L7 ACT_N VDDQ7 A9 DDRB_CS0# L7 ACT_N VDDQ7 A9 DDRB_PAR RD1744 1 2 1/20W_39_5%_0201

c c c c
1.8K_0402_1% M D@

c c c c
@

i i i i
5 DDRB_CS0# DDRB_ALERT # CS_N VDDQ8 DDRB_ALERT # CS_N VDDQ8 2

i i i i
P9 D9 P9 D9 M D@

at at at at
5 DDRB_ALERT # ALERT_N VDDQ9 ALERT_N VDDQ9 DDRB_CKE0

at at at at
G9 +2.5V_DDR G9 +2.5V_DDR RD1710 1 M D@ 2 1/20W_39_5%_0201

2
DDRB_BG0 M2 VDDQ10 DDRB_BG0 M2 VDDQ10
5 DDRB_BG0 BG0 B1 BG0 B1 DDRB_CS0#
RD1707 1 M D@ 2 1/20W_39_5%_0201

emem emem emem emem

DDRB_ODT 0 K3 VPP1 R9 DDRB_ODT 0 K3 VPP1 R9 1 RD1748 2 M D@ +VREF_CA_M D
5 DDRB_ODT 0 ODT VPP2 ODT VPP2 5 DDR_SB_VREFCA DDRB_ODT 0

CD1703
1U_6.3V_M_X5R_0201

CD1704
1U_6.3V_M_X5R_0201
2.7_0402_1% RD1708 1 M D@ 2 1/20W_39_5%_0201

h h h h ch
DDRB_PAR +VREF_CA_M D DDRB_PAR +VREF_CA_M D

h h h h

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
T3 M1 1 1 T3 M1 1

Sc Sc Sc Sc
5 DDRB_PAR

1
PAR VREFCA PAR VREFCA

Sc Sc Sc Sc Sc

CD1707

CD1709
T EN_UD1 T EN_UD2 1

kS
1 1

.047U_0402_16V7K

0.1U_6.3V_K_X5R_0201

.047U_0402_16V7K

0.1U_6.3V_K_X5R_0201
RD1745 1 M D@ 2 10K_0402_5% N9 E1 RD1747 1 M D@ 2 10K_0402_5% N9 E1 1 1 CD1711 CD1712

CD1710
TEN VSS1 TEN VSS1 RD1749

ok ok ok ok

CD1705 MD@

CD1706

CD1708
K1 K1 0.1U_6.3V_K_X5R_0201

ok ok ok
0.022U_16V_K_X7R_0402

ok k
CPU_DRAM RST # VSS2 1 1 CPU_DRAM RST # VSS2 1.8K_0402_1%
2 2 2

MD@

MD@
P1 N1 P1 N1 M D@
2 @
o
5,18 CPU_DRAM RST # RESET_N VSS3 T1 RESET_N VSS3 T1 M D@

o o o o o
2 2

o o o o o

2
1
F1 VSS4 B2 F1 VSS4 B2 2 2

bb eb eb eb eb
RD1752

eb eb eb eb
VSSQ1 VSS5 2 2 VSSQ1 VSS5

MD@
H1 G8 H1 G8

te
VSSQ2 VSS6 VSSQ2 VSS6 24.9_0402_1%

e
+1.2V

MD@
A2 K9 @ A2 K9 @ @

ot ot t ot t ot t ot t
C
D2 VSSQ3 VSS8 D2 VSSQ3 VSS8 M D@ C
VSSQ4 1 DDP@ 2 VSSQ4 1 DDP@ 2 DDRB_ALERT #

NNo NNo NNo NNo

E3 T7 E3 T7 RD1746 1 M D@ 2 49.9_0402_1%

2
A8 VSSQ5 VSS7 RD1750 0_0402_5% A8 VSSQ5 VSS7 RD1751 0_0402_5%
D8 VSSQ6 D8 VSSQ6
E8 VSSQ7 M9 DDRB_BG1_R E8 VSSQ7 M9 DDRB_BG1_R
C9 VSSQ8 VSS9 C9 VSSQ8 VSS9
H9 VSSQ9 E9 UD1_DDRB_UZQ H9 VSSQ9 E9 UD2_DDRB_UZQ
VSSQ10 VSS10 VSSQ10 VSS10 VDDQ:
F9 F9 16x1uF 4 per DRAM
ZQ ZQ
5x10uF distribute evenly across dram
1

1
+1.2V
RD1753 RD1754
240_0402_1% 240_0402_1%
K4AAG165WA-BCWE_FBGA96 K4AAG165WA-BCWE_FBGA96
M D@ M D@ First DRAM 1x10uF 4x1uF 2nd DRAM 1x10uF 4x1uF
mm mm mm mm
@ @
2

2
c.o
.s co c.o
.s co c.o
.s co .s c.o
co

CD1729
4.3U_0402_4V6-M

CD1723
1U_6.3V_M_X5R_0201

CD1724
1U_6.3V_M_X5R_0201

CD1719
1U_6.3V_M_X5R_0201

CD1713
1U_6.3V_M_X5R_0201

CD1732
10U 6.3V M X5R 0402

CD1731
4.3U_0402_4V6-M

CD1715
1U_6.3V_M_X5R_0201

CD1716
1U_6.3V_M_X5R_0201

CD1717
1U_6.3V_M_X5R_0201

CD1728
1U_6.3V_M_X5R_0201

CD1733
10U 6.3V M X5R 0402

CD1742
22P_0402_50V8-J
s s s s 1 1 1 1 1 1 1 1 1 1 1

icic icic icic icic

3
at
at at
at at
at at at

4
2 2 2 2 2 2 2 2 2 2 2@

MD_3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD@

MD_3T@

MD_N3T@

MD_N3T@

MD@
mm mm mm mm
UD1703

e e e e
UD1704

e DDRB_M A0 DDRB_DQ36
e e e
ch hh ch ch ch
P3 G2

ch ch ch
DDRB_M A1 DDRB_DQ38 DDRB_M A0 DDRB_DQ18

Sc c
P7 A0 DQL0 F7 P3 G2
DDRB_M A2 A1 DQL1 DDRB_DQ34 DDRB_M A1 A0 DQL0 DDRB_DQ17
c
kS kS kS kS
R3 H3 P7 F7

kS Byte 4 k kS kS Byte 2 kS kS
DDRB_M A3 N7 A2 DQL2 H7 DDRB_DQ35 DDRB_M A2 R3 A1 DQL1 H3 DDRB_DQ23
DDRB_M A4 A3 DQL3 DDRB_DQ32 DDRB_M A3 A2 DQL2 DDRB_DQ21 UD1701 UD1704
N3 H2 N7 H7

o o o o o o o o o o
DDRB_M A5 P8 A4 DQL4 H8 DDRB_DQ39 DDRB_M A4 N3 A3 DQL3 H2 DDRB_DQ19

bo bo bo o o
DDRB_M A6 DDRB_DQ33 DDRB_M A5 DDRB_DQ16

o bo bo o o
P2 A5 DQL5 J3 P8 A4 DQL4 H8 3rd DRAM 1x10uF 4x1uF 4th DRAM 2x10uF 4x1uF

eb eb
DDRB_M A7 A6 DQL6 DDRB_DQ37 DDRB_M A6 A5 DQL5 DDRB_DQ20

eb eb eb
R8 J7 P2 J3
DDRB_M A8 DDRB_DQ49 DDRB_M A7 DDRB_DQ22

te e e
R2 A7 DQL7 A3 R8 A6 DQL6 J7

ot te ot te ot t ot t
DDRB_M A9 A8 DQU0 DDRB_DQ51 DDRB_M A8 A7 DQL7 DDRB_DQ26

ot
R7 B8 R2 A3
DDRB_M A10 A9 DQU1 DDRB_DQ50 DDRB_M A9 A8 DQU0 DDRB_DQ30

CD1721
1U_6.3V_M_X5R_0201

CD1725
1U_6.3V_M_X5R_0201

CD1722
1U_6.3V_M_X5R_0201

CD1718
1U_6.3V_M_X5R_0201

CD1734
10U 6.3V M X5R 0402

CD1730
4.3U_0402_4V6-M

1U_6.3V_M_X5R_0201

CD1727
1U_6.3V_M_X5R_0201

CD1726
1U_6.3V_M_X5R_0201

CD1714
1U_6.3V_M_X5R_0201

CD1735
10U 6.3V M X5R 0402

CD1736
10U 6.3V M X5R 0402

CD1741
22P_0402_50V8-J
o o NNo NNo
M3 C3 R7 B8
DDRB_M A11 A10/AP DQU2 DDRB_DQ55 DDRB_M A10 A9 DQU1 DDRB_DQ31

CD1720 @
T2 C7 M3 C3

NN Byte 6
NN
DDRB_M A12 A11 DQU3 DDRB_DQ52 DDRB_M A11 A10/AP DQU2 DDRB_DQ29 1 1 1 1 1 1 1 1 1 1 1 1

3
M7 C2 T2 C7
DDRB_M A13 T8 A12/BC_N DQU4 C8 DDRB_DQ54 DDRB_M A12 M7 A11 DQU3 Byte 3
C2 DDRB_DQ28
A13 DQU5 D3 DDRB_DQ48 DDRB_M A13 T8 A12/BC_N DQU4 C8 DDRB_DQ24

4
DDRB_M A14_WE# DQU6 DDRB_DQ53 A13 DQU5 DDRB_DQ27 2 2 2 2 2@ 2 2 2 2 2 2 2

MD_N3T@

MD_N3T@

MD_3T@

MD_N3T@

MD_N3T@

MD@

MD@
L2 D7 D3
DDRB_M A15_CAS# M8 WE_N/A14 DQU7 DDRB_M A14_WE# L2 DQU6 D7 DDRB_DQ25
@
DDRB_M A16_RAS# L8 CAS_N/A15 +1.2V DDRB_M A15_CAS# M8 WE_N/A14 DQU7
RAS_N/A16 D1 DDRB_M A16_RAS# L8 CAS_N/A15 +1.2V
DDRB_CLK0# K8 VDD1 J1 RAS_N/A16 D1
B DDRB_CLK0 K7 CK_C VDD2 L1 DDRB_CLK0# K8 VDD1 J1 B
CK_T VDD3 R1 DDRB_CLK0 K7 CK_C VDD2 L1
DDRB_CKE0 VDD4 CK_T VDD3 UD1703 UD1702

mm mm mm mm
K2 B3 R1
CKE VDD5 G7 DDRB_CKE0 K2 VDD4 B3

co o co o co o co o
DDRB_DQS#4 F3 VDD6 B9 CKE VDD5 G7

s.s.c s.s.c s.s.c s.s.c

DDRB_DQS4 G3 DQSL_C VDD7 J9 DDRB_DQS#2 F3 VDD6 B9
DDRB_DQS#6 A7 DQSL_T VDD8 L9 DDRB_DQS2 G3 DQSL_C VDD7 J9

c c c c
+1.2V DDRB_DQS6 DQSU_C VDD9 DDRB_DQS#3 DQSL_T VDD8

i ic i ic i ic i ic
B7 T9 A7 L9
DQSU_T VDD10 +1.2V DDRB_DQS3 DQSU_C VDD9

at at at at
B7 T9

at at at at
RD1755 1 2 0_0402_5%@ DDRB_DM 4 E2 A1 DQSU_T VDD10
RD1756 1 2 0_0402_5%@ DDRB_DM 5 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD1757 1 2 0_0402_5%@ DDRB_DM 6 E2 A1
2 0_0402_5%@ DDRB_DM 7
mm mm mm mm
NF/LDM_N/LDBI_N VDDQ2 G1 RD1758 1 E7 NF/UDM_N/UDBI_N VDDQ1 C1
DDRB_BS0# VDDQ3 NF/LDM_N/LDBI_N VDDQ2

e e e e
N2 F2 G1

e e e e
DDRB_BS1# BA0 VDDQ4 DDRB_BS0# VDDQ3

ch ch ch ch ch
N8 J2 N2 F2

ch ch ch ch
BA1 VDDQ5 F8 DDRB_BS1# N8 BA0 VDDQ4 J2

c
DDRB_ACT # L3 VDDQ6 J8 BA1 VDDQ5 F8

kS kS kS kS kS
+2.5V_DDR

kS kS kS kS kS
DDRB_CS0# L7 ACT_N VDDQ7 A9 DDRB_ACT # L3 VDDQ6 J8
DDRB_ALERT # P9 CS_N VDDQ8 D9 DDRB_CS0# L7 ACT_N VDDQ7 A9

o o o o o
ALERT_N VDDQ9 DDRB_ALERT # CS_N VDDQ8

o o o o o
G9 +2.5V_DDR P9 D9 VPP:

bo oo oo oo oo
DDRB_BG0 VDDQ10 ALERT_N VDDQ9 +2.5V_DDR

o
M2 G9
8x1uF

CD1737
10U 6.3V M X5R 0402

CD1738
10U 6.3V M X5R 0402

CD1739
10U 6.3V M X5R 0402

CD1740
10U 6.3V M X5R 0402
BG0 DDRB_BG0 VDDQ10

eb eb eb b

CD1745
22P_0402_50V8-J

CD1746
22P_0402_50V8-J
B1 M2

eb eb eb eb e eb
DDRB_ODT 0 VPP1 BG0 3x10uF

te
K3 R9 B1 1 1 1 1 1 1
ODT VPP2 DDRB_ODT 0 VPP1

ot t ot t ot t ot t
K3 R9

ot
DDRB_PAR +VREF_CA_M D ODT VPP2
CD1747
1U_6.3V_M_X5R_0201

CD1749
1U_6.3V_M_X5R_0201

T3 M1

NNo NNo NNo NNo

PAR VREFCA DDRB_PAR +VREF_CA_M D

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1 1 T3 M1

MD@

MD@

MD@

MD@
T EN_UD3 PAR VREFCA 2 2 2 2 2@ 2@
.047U_0402_16V7K

0.1U_6.3V_K_X5R_0201

CD1751 MD@

CD1752
RD1759 1 M D@ 2 10K_0402_5% N9 E1 1 1
TEN VSS1 2 10K_0402_5% T EN_UD4
CD1748 MD@

CD1750

K1 1 1 RD1760 1 M D@ N9 E1
CPU_DRAM RST # VSS2 TEN VSS1

CD1753 MD@
.047U_0402_16V7K

CD1754
0.1U_6.3V_K_X5R_0201
P1 N1 K1 1 1
RESET_N VSS3 T1 2 2 CPU_DRAM RST # P1 VSS2 N1
VSS4 RESET_N VSS3 2 2
MD@

MD@

F1 B2 T1
H1 VSSQ1 VSS5 G8 2 2 F1 VSS4 B2 @
A2 VSSQ2 VSS6 K9 @ H1 VSSQ1 VSS5 G8 2 2
D2 VSSQ3 VSS8 A2 VSSQ2 VSS6 K9 @
E3 VSSQ4 T7 1 DDP@ 2 D2 VSSQ3 VSS8
A8 VSSQ5 VSS7 RD1761 0_0402_5% E3 VSSQ4 T7 1 DDP@ 2
D8 VSSQ6 A8 VSSQ5 VSS7 RD1762 0_0402_5% +0.6VS

mm mm mmVTT: mm
E8 VSSQ7 M9 DDRB_BG1_R D8 VSSQ6

co o co o co o 8x1uF co o
C9 VSSQ8 VSS9 E8 VSSQ7 M9 DDRB_BG1_R
VSSQ9 UD3_DDRB_UZQ VSSQ8 VSS9

s.s.c s.s.c s.s.c s.s.c

H9 E9 C9
VSSQ10 VSS10 VSSQ9 UD4_DDRB_UZQ

CD1743

CD1744

CD1755
1U_6.3V_M_X5R_0201

CD1756
1U_6.3V_M_X5R_0201

CD1757
1U_6.3V_M_X5R_0201

CD1758
1U_6.3V_M_X5R_0201

CD1759
1U_6.3V_M_X5R_0201

CD1760
1U_6.3V_M_X5R_0201

CD1761
1U_6.3V_M_X5R_0201

CD1762
1U_6.3V_M_X5R_0201

CD1764
10U 6.3V M X5R 0402

CD1763
10U 6.3V M X5R 0402

CD1765
22P_0402_50V8-J

CD1766
22P_0402_50V8-J
F9 H9 E9

4.3U_0402_4V6-M

4.3U_0402_4V6-M
ZQ VSSQ10 VSS10 2x10uF
c c c c
F9

c c c c
1 1 1 1 1 1 1 1 1 1 1 1

i i i i
1

3
ZQ

i i i i
atat atat atat at at
1

RD1763
240_0402_1% RD1764

4
K4AAG165WA-BCWE_FBGA96 2 2 2 2 2 2 2 2 2 2 2 2

MD_3T@

MD_3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD@
em em em em
M D@ 240_0402_1%

m m m m
A K4AAG165WA-BCWE_FBGA96 A
@ M D@ @ @ @

e e e e
2

h h h h h
ch ch
2

h h
Sc Sc ScSc Sc Sc ScSc
ok
o kS oko kS k
oo k k
oo k k
oo k
o
b bo o o bo bo bo
ebeb bo bo bo
te e
ot t ot
e
te ot
e
te tete
ot NNo NN o NN o LC Future Center Secret Data
NN
o o Security Clas s ification Title

DDR4 Memory Down Issued Date 2017/06/24 Deciphered Date 2018/06/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Docum ent Num ber Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday , December 06, 2019 Sheet 17 of 60
5 4 3 2 1

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat atat atat
h emem h emem h emem h emem
Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o okok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot t ot t
NNo NNo NNo NNo

omm omm omm omm

 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot DDR4 SO-DIMM oto oto oto oto
NN NN NN +1.2V
NN

1
+1.2V +1.2V
JDDR1B
RD1801
+1.2V JDDR1A +1.2V 240_0402_1%

o1 m mm mm mm
@
m
co o
DDRA_MA3

coA1o
DDRA_MA2

co o
131 132
DDRA_DQ61 .c.c
o

2
A3 A2

s.s.c s.s.cVDD_9 s.s.c

2 DDRA_MA1 133 134 DDRA_EVENT#

s s 35 DQ5
VSS_1 VSS_2 4 DDRA_DQ60 135 EVENT_n 136
i c i c DQ4 6
i c i c DDRA_CLK0
i ci c 137 VDD_10 138
i c
5 ic
DDRA_CLK1

atat at at at at at at5
DDRA_DQ62 VSS_3 VSS_4 DDRA_DQ58 5 DDRA_CLK0 DDRA_CLK0# CK0_t CK1_t DDRA_CLK1# DDRA_CLK1
7 8 139 140
9 DQ1 DQ0 10 DDRA_DQ[0..63] 5 DDRA_CLK0# CK0_c 141 CK1_c 142 DDRA_CLK1#

em mDDRA_DQS#7 em m em m em m
DDRA_DQ[0..63] 5
11 VSS_5 VSS_6 12 DDRA_PAR VDD_11 143 VDD_12 DDRA_MA0
144

h h e DDRA_DQS7 13 DQS0_C DM0_n/DBIO_n/NC 14

h h e
DDRA_DQS#[0..7] 5 DDRA_PAR
h e
h DDRA_BS1#
Parity A0
h e h
c c c Sc ch Sc
DDRA_DQS#[0..7] 5
c c c Sc
15 DQS0_t VSS_7 16 DDRA_DQ57
SS DDRA_DQ59kS S S S kS
D DDRA_DQ56 17 VSS_8 DQ6 18 DDRA_DQS[0..7] 145 146 DDRA_MA10 D

k k 19 DQ7 VSS_9 20
k DDRA_DQS[0..7] 5 5
kkDDRA_BS1#
147 BA1 A10/AP 148
ok k k
oooo oo oo
o5 o o oo
DDRA_MA[0..13]
o o bo
DDRA_DQ63 VSS_10 DQ2 DDRA_CS0# 149 VDD_13 VDD_14 150 DDRA_BS0#
o b bo bo
21 22
DDRA_BS0# 5
b b b
DDRA_MA[0..13] 5 DDRA_CS0#
23 DQ3 VSS_11 24 151 CS0_n BA0 152
b b b
DDRA_DQ53 DDRA_MA14_WE# DDRA_MA16_RAS#

te
26e e VDD_16 156te e e
5 DDRA_MA14_WE#
e 28 te e te
VSS_12 DQ12 DDRA_MA16_RAS# 5
DDRA_DQ51 153 WE_n/A14 RAS_n/A16 154
VSS_13 t t ot
25

ot o o ot CAS_n/A15 o t DDRA_MA15_CAS#
27 DQ13 DDRA_DQ55 DDRA_ODT0 155 VDD_15
DDRA_DQ54 29 VSS_14
N
DQ8 o NN
5 DDRA_ODT0 DDRA_CS1# 157 ODT0
N 158o DDRA_MA13 DDRA_MA15_CAS# 5
NN o
N 32 A13N
30
5 DDRA_CS1#
31 DQ9 VSS_15 DDRA_DQS#6 159 CS1_n 160
33 VSS_16 DQS1_c 34 DDRA_DQS6 DDRA_ODT1 161 VDD_17 VDD_18 162
DM1_n/DBl1_n/NC DQS1_t 5 DDRA_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMM
35 36 163 164
DDRA_DQ50 37 VSS_17 VSS_18 38 DDRA_DQ49 165 VDD_19 VREFCA 166 DDRA_SA2
DQ15 DQ14 C1/CS3_n/NC SA2

0.1U_6.3V_K_X5R_0201

2.2U_0402_6.3V6M
39 40 167 168
DDRA_DQ48 VSS_19 VSS_20 DDRA_DQ52 DDRA_DQ25 VSS_53 VSS_54 DDRA_DQ28

CD1801

CD1802
41 42 169 170 1 1
43 DQ10 DQ11 44 171 DQ37 DQ36 172
mm DDRA_DQ35 45 VSS_21 VSS_22 46
mm DDRA_DQ37
mm DDRA_DQ24 173 VSS_55 VSS_56 174
mmDDRA_DQ26

co o co o co co co o
47 DQ21 DQ20 48 175 DQ33 DQ32 176

s.s.c s.s.c DDRA_DQS3 s.

s. s.s.c
DDRA_DQ39 49 VSS_23 VSS_24 DDRA_DQ38
50 DDRA_DQS#3 177 VSS_57 VSS_58 178 2 2

c c c c
DQ17 DQ16 DQS4_c DM4_n/DBl4_n/NC
c c c c
51 52 179 180
i
t t i i i i i i i
at at at
VSS_25 VSS_26 DQS4_t VSS_59

at at at
DDRA_DQS#4 53 54 181 182 DDRA_DQ31 @
aDDRA_DQS4
a 55 DQS2_c DM2_n/DBl2_n/NC 56 DDRA_DQ29 183 VSS_60 DQ39 184

em em em em
DQS2_t VSS_27 DQ38 VSS_61

emDDRA_DQ33 em em em
57 DDRA_DQ32
58 185 DDRA_DQ30 186
59 VSS_28 DQ22 60 DDRA_DQ27 187 VSS_62 DQ35 188

c h h DQ23 VSS_29 DDRA_DQ34

h h h h DQ34 VSS_63 DDRA_DQ22
h h ch
Sc Sc Sc
61 62 189 190
c VSS_30 DQ18
Sc Sc
VSS_64 DQ45
Sc Sc
kS kS
DDRA_DQ36 DDRA_DQ19

kS
63 64 191 192

ok ok okok ok ok k
65 DQ19 VSS_31 DDRA_DQ40
66 193 DQ44 VSS_65 DDRA_DQ23 194

oooo
o o
DDRA_DQ44 67 VSS_32 DQ28 68 DDRA_DQ21 195 VSS_66 DQ41 196

b
DQ29 VSS_33
o o
DDRA_DQ42
o o DQ40 VSS_67
o o
DDRA_DQS#2
o o
eb bb eb eb
69 70 197 198
b VSS_34 DQ24
b VSS_68 DQS5_c
eb eb
te e
DDRA_DQ41 DDRA_DQS2
e eDDRA_DQS#5 e
71 72 199 200
t ot t DDRA_DQS5 t t ot t DDRA_DQ17 ot t
73 DQ25 VSS_35 74 201 DM5_n/DBl5_n/NC DQS5_t 202
o o
NNo DDRA_DQ43 NNo NNo DDRA_DQ16 NNo
+1.2V 75 VSS_36 DQS3_c 76 DDRA_DQ18 203 VSS_69 VSS_70 204
77 DM3_n/DBl3_n/NC DQS3_t 78 205 DQ46 DQ47 206
DDRA_DQ46 79 VSS_37 VSS_38 80 DDRA_DQ20 207 VSS_71 VSS_72 208
81 DQ30 DQ31 82 209 DQ42 DQ43 210
DDRA_DQ47 83 VSS_39 VSS_40 84 DDRA_DQ45 DDRA_DQ6 211 VSS_73 VSS_74 212 DDRA_DQ5
DQ26 DQ27 DQ52 DQ53
1

85 86 213 214
RD1802 87 VSS_41 VSS_42 88 DDRA_DQ3 215 VSS_75 VSS_76 216 DDRA_DQ7
RD1803 89 CB5/NC CB4/NC 90 217 DQ49 DQ48 218
240_0402_1% 240_0402_1% VSS_43 VSS_44 VSS_77 VSS_78

om mm
DDRA_DQS#0
91 92
mm 219 220
mm
om
C C

c.o c.o c.o

CB1/NC CB0/NC DDRA_DQS0 DQS6_c DM6_n/DBl6_n/NC

co co co
93 94 221 222
DDRA_DQS8 .c.c
2

.s .s .s
DDRA_DQS#8 95 VSS_45 VSS_46 96 223 DQS6_t VSS_79 224 DDRA_DQ4

cics s 97 DQS8_c DM8_n/DBI8_n/NC 98 s DDRA_DQ2

s 225 VSS_80 DQ54 226 s
t it DQS8_t VSS_47
icic icic DQ55 VSS_81
icic DDRA_DQ0

at at at
99 100 227 228

at at at
VSS_48 CB6/NC VSS_82 DQ50
aa 101 102 DDRA_DQ1 229 230
CB2/NC VSS_49 DQ51 VSS_83 DDRA_DQ8

em mm mm mm
103 104 231 232

em e e e
VSS_50 CB7/NC DDRA_DQ9 VSS_84 DQ60
e e e
105 106 233 234
h ch ch hh ch
CB3/NC VSS_51 DQ61 VSS_85
h ch ch DDRA_DQ12
107 CPU_DRAMRST#
108 235 DDRA_DQ10 236

Sc c Sc c c
DDRA_CKE0 VSS_52 RESET_n DDRA_CKE1 CPU_DRAMRST# 5,17 VSS_86 DQ57

0.1U_6.3V_K_X5R_0201
109 110 237 238

kS kS kS DDRA_ACT# 5 kS kS kS kSkS
5 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 5 DQ56 VSS_87 DDRA_DQS#1
kDDRA_BG1 DDRA_DQS1 k

CD1803
111 112 1 239 240
o
VDD_1 VDD_2
o o
VSS_88 DQS7_c
o o
DDRA_BG1 DDRA_ACT#
o o o o o
113 114 241 242

bo bo bo o o
5 BG1 ACT_n DM7_n/DBl7_n/NC DQS7_t
o o bo o o
DDRA_BG0 115 DDRA_ALERT#
116 243 244
b bDDRA_MA11 ebeb eb eb
5 DDRA_BG0 BG0 ALERT_n DDRA_ALERT# 5 DDRA_DQ14 VSS_89 VSS_90 DDRA_DQ13
117 118 245 246
e
t te ete DDRA_MA7 ete
ot ot ot t DDRA_DQ11 ot t
DDRA_MA12 119 VDD_3 VDD_4 120 2@ 247 DQ62 DQ63 248
A12 A11 VSS_91 VSS_92
o o o NNo SMB_DATA_S3 NNo
DDRA_MA9 121 122 DDRA_DQ15 249 250
NN NN
123 A9 A7 124 251 DQ58 DQ59 252
DDRA_MA8 125 VDD_5 VDD_6 DDRA_MA5
126 SMB_CLK_S3 253 VSS_93 VSS_94 254
DDRA_MA6 A8 A5 DDRA_MA4 7 SMB_CLK_S3 +VDD_SPD SCL SDA DDRA_SA0 SMB_DATA_S3 7
127 128 255 256
129 A6 A4 130 257 VDDSPD SA0 258

2.2U_0402_6.3V6M
VDD_7 VDD_8 VPP_1 VTT DDRA_SA1 +0.6VS

0.1U_6.3V_K_X5R_0201
1 1 259 260
VPP_2 SA1

CD1804

CD1805
+3VS RD1804 1 @ 2 0_5%_0603 261 262
GND_1 GND_2
m m
ARGOS_D4AR0-26001-1P40
mm mm mm 2 2

co o ME@ co o co o ME@ co o
ARGOS_D4AR0-26001-1P40

c s.s.c c s.s.c c s.s.c c s.s.c

i ic i ic titic VDDSPD: i ic
at
at at
at RD1805 1 @ 2 0_5%_0603a
a
+VPP at
at
mm mm mm mm
+2.5V_DDR
+1.2V
e e e e e e
1x2.2uF
e e
0.1U_6.3V_K_X5R_0201

chch chch chch ch

ch ch
1x0.1uF
c
kS kS kSkS kS kS kSkS kSkS
1
CD1806

o o o o o o o o o o
1

bo o
eb
oo
eb
oo
eb
oo boo
eb eb eb eb e eb
RD1806

te
2

ot t ot t ot t ot t
1K_0402_1%

ot
B B

NNo +VREF_CA_DIMM NNo NNo NNo

+2.5V_DDR
2

RD1807 1 2 2_0402_5% +1.2V 2nd DRAM 1x10uF 4x1uF

5 DDR_SA_VREFCA
VPP:

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
0.1U_6.3V_K_X5R_0201

1 1x1uF
1

CD1812

CD1811

CD1814

CD1813
CD1815 1 1x10uF

0.1U_6.3V_K_X5R_0201
CD1816

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201
0.022U_16V_K_X7R_0402 RD1808 VDDQ: 1 1 1 1

CD1836
CD1818

CD1819

CD1820

CD1822

CD1823

CD1824

CD1817

CD1821

CD1833

CD1834

CD1835

CD1837
33P_0402_50V8J

CD1838
33P_0402_50V8J
1K_0402_1% 8x1uF
mm 2
1 m 1
m 1 1 1 mm
1 1 1 1 1 1 1 1 1 mm
co o co o c.o co2 @o
8x10uF
co
1

s.s.c s.s.c .s s.s.c

2

RD1809 2 2@ 2

c 24.9_0402_1%
c c s c
i i c i i c i 2c
i i i c
at at at at
2@ 2@ 2 2 2 2@ 2 2 2 2 2 2 2

at at at at
@
@ @ @ @ @ @
2

em
e m
he
m m eem m em m
h
ch he h
ch
h
ch
e h
Sc ScSc Sc Sc ScSc
ok
o kS +3VS k
oo k oko kS oko kS k
oo k
o
b bo bo o o bo
bo o o bo
+3VS +3VS

te e e te eb
eb eb
eb ete
ot ot ot
ot 1 ot t ot
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
o NNo o
1

CD1825

CD1826

CD1828

CD1829

CD1830

CD1832

CD1831

CD1827
RD1810
0_0402_5%
RD1811
0_0402_5%
NN RD1812
0_0402_5%
1 1 N
1 N1 1 1 1
+0.6VS
NN
@ @ @
VTT:
2

2@ 2 2 2 2 2 2 2

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
DDRA_SA0 DDRA_SA1 DDRA_SA2 2x1uF

CD1809

CD1810

CD1807

CD1808
@ @
1x10uF
1 1 1 1
mm mm mm o2 m
om
1

co o co o co o 2 .c.c
s.s.c 0_0402_5% s.s.c s.s.c
RD1814 RD1813 RD1815

@cs s
2 2 @
c c c
0_0402_5% 0_0402_5%
i ic i i c i i c @
i i c
at t atat at at at
at
@ @ @
a
A A
2

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok SPD Address = A0 o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
o t ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

NN 2016/08/20 DDR4 SO-DIMM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 18 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
N16x GPIO

GPIO
I/O
mm
ACTIVE Function Description
mm Performance Mode P0 TDP
m and EDP-Continuous current (GDDR5) mm
m
c.o
co co o co o co o
c s .s
GPIO0
OUT - GPU Core VDD PWM control signal
c s.s.c c s.s.c c s.s.c
i i c i i c i c
t ti Min i
t ti c
at at
FBVDDQ Other
at OUT at GPUa a
FBVDD (GPU+Mem) (1.05V)
a a
em em em mm
GPIO1 N/A FB Enable for GC6 2.0 Mem Core Clk NVVDD (1.35V) (1.35V) (6) (3.3V)
em e m e m (W) e
(W)e (mA) (W)
chch GPIO2
h
ch
h h h h h
Products (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA)
S S
OUT N/A
Sc kS
c c SS c c ScSc
kS S
D D

ok
o k oko oo
kN16S-GMR TBD 4.2 k
oo
k 800 TBD 60 TBD k
oo k
oo oo
16 1.6 849 TBD 19 TBD 2 TBD
o
b bo o o bobo
GPIO3 OUT N/A
te e eb eb e b
e b b
2 te e 4.2 b ete
ot ot t t
o t o t ot
N16S-GTR 18 1.7 967 26.5 800 60

NNo NNo NNo o

GPIO4 OUT N/A
NN
GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7
OUT m
N/Am mm mm mm
c.o
co co o co o co o
c
.s
sI/O c s.s.c c s.s.c c s.s.c
i c
GPIO8
i
- System side PCIe reset Monitor
i i c i i c i i c
at at I/O at at at at atat
mm em em em
em em em
GPIO9 N/A 2.2K Pull-up
e
h he h h h
c c Sc
h
Sc
h
Sc
h ch
kS
kS
GPIO10 OUT FBVREF_ALTV for GDDR5
Sc Sc Sc kS Sc
oo okok okok okok o k
b oo o o o o N16x Multi-level Straps o o o o o
eb bb eb eb
GPIO11 OUT -
b eb eb eb
te e
ot ot
ete ot t ot t
ot GPIO12 IN
NNDetect
AC Power otInput (10K pull High)
NN o NNo NNo
Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
C
mN/Am mm mm mm C

c.o
co c.o
co
oDEVID_SEL
co c.o o
GPIO15 IN ROM_SO +3VGS PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
.s .s c.Reserved(keep
.s .s c
s
cic s s s
icic cic cic
STRAP0 +3VGS pull-up and pull-down footprint and stuff 50Kohm pull-up)
t it i i
at t t
GPIO16 N/A
aa at STRAP1 t
a a+3VGS a at
hemem
GPIO17 IN N/A e mm
e STRAP2em
em +3VGS em e m
h chch
h h h h ch
Reserved(keep pull-up and pull-down footprint and not stuff by default)
ScSc kS
cc
SSTRAP3 Sc Sc kS
c
+3VGS
k
oo k GPIO18 IN N/A
o o kS ok
S
okSTRAP4 +3VGS ok ok o o kS
bobo bobo eb
o o
eb
o o
eb
o o
e e eb eb eb
GPIO19 IN N/A
t te ot te ot t ot t ot t
o GPIO20 N/A NN o NNo NNo NNo
GPIO21 OUT GPU PCIe self-reset control

OVERT OUT Active Low Thermal Catastrophic Over Temperature

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i ic i ic i ic
at
at at
at at
at at
at
e mm e mm e mm e mm
e e e e
chch chch chch ch
ch chc
o kS kS o kSkS o kSkS o kSkS o kSkS
o o o o o
bo o
eb
oo
eb
oo
eb
oo boo
te eb eb eb eb e eb
ot ot t ot t ot t ot t
B B

NNo NNo NNo NNo

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat atat atat atat
h em
e m
h eme m
h eme m
h eme m
h
Sc ch Sc ch Sc ch Sc ch ScSc
ok
o kS oko kS oko kS oko kS k
oo k
o
b bo o o o o o o bo
ebeb eb eb eb eb bo
te e
ot t ot t ot t ot
ete
ot NNo NNo NNo NN o

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at atat
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

NN 2016/08/20 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 19 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN

+3.3V_1.8V_AON +3V_1.8VGS +3.3V_1.8V_AON

mm mm mm mm
c.o o
cRV2003 co o co o co o
s.s10K_0402_5% s.s.c s.s.c s.s.c

2
RV2001
t i c
RV2002
i c i ci c i ci c i ci c
t at
at at
at at at
0_0402_5%
@
aa @ 0_0402_5%
OPT@
+1.0VGS

mm em m em m em m
he
UV1A ? COMMON INS35853665

1
e
hCV2003 h e h e h e h
ch ch c ch
1/14 PCI_EXPRESS
c c Sc Sc ScSc
1 Under Near GPU and PS
SS kS
kS kS kS
D D

ok ok ok k
0.1U_6.3V_K_X5R_0201
k k
2o o oo

CV2008
10U 6.3V M X5R 0402

CV2009 OPTN17@
10U 6.3V M X5R 0402
@
o o o

OPTN17@
o o o o bo

CV2004 OPT@
1U_6.3V_M_X5R_0201

CV2005 OPTN17@
4.7U_0402_6.3V6M

CV2006 OPT@
4.7U_0402_6.3V6M

CV2007 OPTN17@
4.7U_0402_6.3V6M
b bo o o PEX_DVDD_1 AA22 o bo
2

22U_0603_6.3V6-M
2

eb eb eb
eb eb eb

2
PEX_DVDD
te e
1 1 1 1
e PLT_RST_VGA#
te
ot t ot t ot ot
AC7 AB23

ot ot
26 PLT_RST_VGA# PEX_DVDD_2 AC24 1 N16:+1.05VGS(recommend)

NNo NNo o
OPT@ QV2001
PEX_DVDD_3 AD25 +1.0VGS(Used)
N NN
CLK_REQ_GPU# PEX_RST_N 1 1

OPTN17@
2 N
10 GPU_CLKREQ# 1 3 AC6
PEX_CLKREQ_N PEX_DVDD_4 AE26 2 2 2 N17:+1.0VGS

CV2010
CLK_PCIE_GPU AE8 PEX_DVDD_5 AE27 2
10 CLK_PCIE_GPU CLK_PCIE_GPU# PEX_REFCLK PEX_DVDD_6
LSI1012XT1G_SC-89-3 AD8
10 CLK_PCIE_GPU# PEX_REFCLK_N
RV2004 1 @ 2 0_0402_5% PCIE_CRX_GTX_P5 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P5 PEX_HVDD +3V_1.8VGS
OPT@ CV2001 1 AC9
PCIE_CRX_GTX_N5 OPT@ CV2011 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N5 AB9 PEX_TX0
PEX_TX0_N
2000mA

2
mm
oRV2005 mm
PCIE_CTX_C_GRX_P5 AG6
mm Under GPU Near GPU GPU and PS
mm OPTN17@

co o co o
1 0_0805_5% o
o
c10K_0402_5%
PCIE_CTX_C_GRX_N5 AG7 PEX_RX0 AA10 (below 150mils) PEX_HVDD
c.co
2

s.s.c @ s.s.c s.s.c s.s+1.0VGS

PEX_RX0_N PEX_HVDD_1 AA12
RV2006
c c c c
PCIE_CRX_GTX_P6 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P6 PEX_HVDD_2
c c c c

CV2014 OPT@
1U_6.3V_M_X5R_0201

CV2015 OPTN17@
1U_6.3V_M_X5R_0201

CV2016
1U_6.3V_M_X5R_0201

CV2017
1U_6.3V_M_X5R_0201

CV2018 OPT@
4.7U_0402_6.3V6M

CV2019 OPTN17@
4.7U_0402_6.3V6M

CV2020 OPT@
10U 6.3V M X5R 0402

CV2021 OPTN17@
10U 6.3V M X5R 0402

CV2022 OPT@
22U_0603_6.3V6-M

CV2023 OPT_RF@
33P_0402_50V8J
CV2012 1 AB10 AA13
i i i i
OPT@
i i i i
at at at 2 at 1 t
PEX_TX1 PEX_HVDD_3
t atPCIE_CTX_C_GRX_P6 AF7 at
PCIE_CRX_GTX_N6 OPT@ CV2013 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N6
AC10 AA16 OPTN16@
1 1 1 1 1 1 1 2 2 1 1
a a 0_0805_5%
PEX_TX1_N PEX_HVDD_4 AA18
mm em mm mm
PEX_HVDD_5

em
AA19

hehe
e
he 2 ee
PCIE_CTX_C_GRX_N6 PEX_RX1 PEX_HVDD_6 RV2007
AE7 AA20

c1h ch ch h h ch
PEX_RX1_N 2 2 2 2 PEX_HVDD_7 2 2 1 1 2
c Sc
AA21
c Sc
PEX_HVDD_8
Sc
PEX_HVDD
Sc
kS OPT@ S
kS kS
PCIE_CRX_GTX_P7 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P7
kS S
OPT@ CV2002 AD11 @ @ AB22
k
o ok k okok k
PCIE_CRX_GTX_N7 CV2024 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N7 AC11 PEX_TX2 PEX_HVDD_9 AC23 N16:+1.05VGS(recommend)
oooo
o o o o
PEX_TX2_N PEX_HVDD_10 AD24 +1.0VGS(Used)
bo bo
o o o o o o
PCIE_CTX_C_GRX_P7 PEX_HVDD_11
b eb b eb
AE9 AE25 N17:+1.8VGS
b PEX_RX2
eb
PEX_HVDD_12
b eb
te e e
PCIE_CTX_C_GRX_N7
e e e
AF9 AF26
t ot t t ot t
ot t t
PEX_RX2_N PEX_HVDD_13 AF27 For RF
o o oo
NNo NNo
PCIE_CRX_GTX_P8 OPT@ CV2025 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P8 AC12 PEX_HVDD_14
NNPCIE_CRX_GTX_N8 OPT@ CV2026 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N8 AB12 PEX_TX3
PEX_TX3_N N N
Change by Bourne 20170412
PCIE_CTX_C_GRX_P8 AG9
PCIE_CTX_C_GRX_N8 AG10 PEX_RX3
PEX_RX3_N
AB13
AC13 PEX_TX4
PEX_TX4_N
C
mm mm mm +3.3V_1.8V_AON mm C

c.o
co c.o
co AE10 c.o
co c.oco
9 PCIE_CRX_GTX_N[5..8] AF10
.s .s .s .s
PEX_RX4
s s PEX_RX4_N
s s
icic cic
it icic icic
9 PCIE_CRX_GTX_P[5..8]

at t at at
AD14 OPTN16@

at at at
PEX_TX5 PEX_PLL_HVDD
aa AC14 AA8 PEX_PLL_HVDD RV2008 1 2 0_0402_5%
9 PCIE_CTX_C_GRX_N[5..8] PEX_TX5_N PEX_PLL_HVDD_1 AA9 N16:+3.3V_AON
mm em mm m
em m
+3V_1.8VGS
e e e
PEX_PLL_HVDD_2
e e e
AE12

0.1U_6.3V_K_X5R_0201
N17:+1.8VGS
ch h ch ch ch
9 PCIE_CTX_C_GRX_P[5..8] PEX_RX5

ch h ch ch
AF12 OPTN17@
cc
1
PEX_RX5_N
c

CV2027
RV2009 1 2 0_0402_5%

OPT@
kSkS k S S kS kS kS kS kSkS
AC15
o o oo k AB15 PEX_TX6
o o o o o o
bo bo bo bo o
PEX_TX6_N Change by Bourne 20170412
o o bo bo o
2

eb eb eb eb
AG12
te t e
ot
ete ot
e te ot t
PEX_RX6

ot t
AG13
oo PEX_RX6_N
o o
NN AB16
AC16 NN
PEX_TX7 NN NNo
PEX_TX7_N PEX_DVDD/Q Decouling
Under GPU
AF13
AE13 PEX_RX7 (below 150mils)
PEX_RX7_N
AD17 MLCC N16 N17 location
AC17 PEX_TX8
mm mm PEX_TX8_N
mm mm 1.0uF 1 1
co o co o AE15 co o co o
s.s.c s.s.c s.s.c s.s.c
AF15 PEX_RX8 Under
4.7uF 0 1
c
i ic c
i ic
PEX_RX8_N
c
i ic c
i icNear
at
at atat at
at 1 at 2t
AC18
AB18 PEX_TX9
4.7uF a
mm em mm mm
em
PEX_TX9_N
e e e e e e
ch ch ch ch ch
AG15

ch ch ch h
PEX_RX9 10uF 0 2 Midway
Sc c
AG16

kS S kS kS kS
PEX_RX9_N

PEX LANES 15 - 4 ARE DEFEATURED

o o kS o k
o k S AB19
PEX_TX10
o o kS o o k22uF 0 1
o o kS
bo bo oo oo oo
AC19
o bo
PEX_TX10_N

te eb e e AF16
ebeb eb eb
b
e eb
ot ot t otot ot t ot t
B
AE16 PEX_RX10 B

NNo NNo NNo

PEX_RX10_N PEX_HVDD/Q Decouling
AD20 N
PEX_TX11N
AC20
PEX_TX11_N
AE18
MLCC N16 N17 location
AF18 PEX_RX11
PEX_RX11_N 1.0uF 1 4 Under
AC21
mm mm mm mm Near
PEX_TX12
AB21 4.7uF 1 2
co o co o AG18 co o c.oco
PEX_TX12_N

c s.s.c c s.s.c AG19 PEX_RX12

c s.s.c c
.s
sMidway 10uF 1 2
i i c i i c i i c i c
1 ti
PEX_RX12_N

atat atat AD23

PEX_TX13 atat 22uF 1 at a
em m em m em m em m
AE23
PEX_TX13_N
h e h e h e h e h
ch h ch ch
AF19

Sc c c Sc Sc ScSc
PEX_RX13
SS
AE19

ok kS k ok kS ok kS k
PEX_RX13_N

o oo k AF24
o o oo k
o
b bo bo o o bo
bo o o bo
AE24 PEX_TX14

eb eb eb eb
PEX_TX14_N

te e te e
ot t ot t ot
ete
ot o t
AE21

NNo NNo NNo o

AF21 PEX_RX14

AG24
PEX_RX14_N PEX_PLL_HVDD/Q Decouling NN
AG25 PEX_TX15
PEX_TX15_N
MLCC N16 N17 location
AG21
AG22 PEX_RX15
PEX_RX15_N 0.1uF 1 1 Near
mm mm m 2m mm
co o co o co o co o
AF25
OPT@ 1 PEX_TERMP
RV2010 2.49K_0402_1%
PEX_TERMP

c s.s.c c s.s.c c s.s.c c s.s.c

i ic i i c N17S-G1-A1_GB2C-64-595 @
i i c i i c
atat atat at at at at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb eb eb eb eb eb eb
ot ot t ot t ot
ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

N N 2016/08/20 GPU_PCIE Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 20 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN

UV1B ? COMMON INS35854731

2/14 FBA
FBA_D0 E18
mm FBA_D1 F18
mm
FBA_D0
mm mm
co o co o co o co o
FBA_D2 E16 FBA_D1

s.s.c s.s.c s.s.c s.s.c

27,28 FBA_D[0..63] FBA_D3 FBA_D2
F17
c
FBA_D3
c c c
FBA_D4
c c c c
D20
27,28
i i
FBA_CMD[31..0]
i i i i i i
at at at at
FBA_D5 FBA_D4

at at at at
D21
FBA_D6 F20 FBA_D5
27,28 FBA_EDC[7..0]
mm em em em
FBA_D7 FBA_D6
m m m
E21
27,28 e e e e e
FBA_D8 E15 FBA_D7
h h h h h
ch ch ch ch
FBA_DBI[7..0] FBA_D9 FBA_D8

Sc Sc Sc Sc Sc
D15

Sc
FBA_D10 F15 FBA_D9

kS kS kS kS
D D

ok ok ok ok k
FBA_D10
k
FBA_D11 F13

o o o o
FBA_D12 C13 FBA_D11
o o o o oo
b bo o o o bobo
FBA_D13 FBA_D12

eb eb eb
B13

eb eb eb
FBA_D13
te e
FBA_D14 E13
e te
ot ot t ot t ot t ot
FBA_D15 D13 FBA_D14

NNo NNo NNo o

FBA_D16 B15 FBA_D15
FBA_D17
FBA_D18
C16
A13
FBA_D16
FBA_D17 NN
FBA_D19 A15 FBA_D18
FBA_D20 B18 FBA_D19
FBA_D21 A18 FBA_D20
FBA_D22 A19 FBA_D21
FBA_D23 C19 FBA_D22
FBA_D24 FBA_D23
mm mm mm mm
B24 +1.35VGS

co o co o co o co o
FBA_D25 C23 FBA_D24

s.s.c s.s.c s.s.c s.s.c

FBA_D26 A25 FBA_D25
FBA_D27 A24 FBA_D26

i cic FBA_D28
i ci c
FBA_D27
i ci c i ci c
at at at at
A21

at at at at
FBA_D29 B21 FBA_D28

1
FBA_D30 C20 FBA_D29

emem emem emem emem

FBA_D31 FBA_D30 RV2101 RV2102
C21
h h h h ch
FBA_D32 FBA_D31 10K_0402_1% 10K_0402_1%
h h h h
R22

ScSc ScSc ScSc ScSc Sc

FBA_D33 FBA_D32 FBA_CMD0 OPT@ OPT@
R24 C27

kS
FBA_D34 FBA_D33
FBA_CMD0 FBA_CMD1

ok ok ok ok
T22 C26

2
ok ok ok ok k
FBA_D34
FBA_CMD1
o
FBA_D35 R23 E24 FBA_CMD2

o o o o
FBA_D36 N25 FBA_D35
FBA_CMD2 F24 FBA_CMD3
o o
FBA_CMD14
o o o o o
bb b b
FBA_D36
FBA_CMD3
eb b eb eb
eb eb
FBA_D37 N26 D27 FBA_CMD4

te e e e FBA_CMD6 t te
FBA_D37
FBA_CMD4
t ot t ot t
FBA_D38 FBA_CMD5 FBA_CMD30

ot t
N23 D26
oo oo
FBA_D39 FBA_D38
FBA_CMD5

NNo NNo
N24 F25
NN N
FBA_D40 FBA_D39
FBA_CMD6 FBA_CMD7
N
V23 F26
FBA_D41 V22 FBA_D40
FBA_CMD7 F23 FBA_CMD8
FBA_D42 T23 FBA_D41
FBA_CMD8 G22 FBA_CMD9 FBA_CMD13
FBA_D43 U22 FBA_D42 FBA_CMD9 G23 FBA_CMD10
FBA_D44 Y24 FBA_D43 FBA_CMD10 G24 FBA_CMD11 FBA_CMD29
FBA_D45 AA24 FBA_D44 FBA_CMD11 F27 FBA_CMD12
FBA_D46 Y22 FBA_D45 FBA_CMD12 G25 FBA_CMD13
FBA_D47 AA23 FBA_D46 FBA_CMD13 G27 FBA_CMD14

1
C
mm FBA_D48 AD27 mm
FBA_D47 FBA_CMD14 G26 FBA_CMD15
mm mm C

c.o
co c.o
co c.o
co c.o
co
FBA_D49 FBA_D48 FBA_CMD15 FBA_CMD16 RV2103 RV2104
AB25 M24

s .s FBA_D50 AD26
s .s
FBA_D49 FBA_CMD16 M23 FBA_CMD17
s .s 10K_0402_1%
s .s 10K_0402_1%

icic icic icic icic

FBA_D51 FBA_D50 FBA_CMD17 FBA_CMD18 OPT@ OPT@
AC25 K24

at at at at
FBA_D51 FBA_CMD18

at at at at
FBA_D52 AA27 K23 FBA_CMD19

2
FBA_D53 AA26 FBA_D52 FBA_CMD19 M27 FBA_CMD20

e mm FBA_D54
e mmW26 FBA_D53 FBA_CMD20 M26 FBA_CMD21
e mm e mm
e FBA_D55
e Y25 FBA_D54 FBA_CMD21 M25 FBA_CMD22
e e
chch chch ch
ch ch
ch ch
FBA_D56 FBA_D55 FBA_CMD22 FBA_CMD23
c
R26 K26

kS kS kS kS kS
FBA_D57 FBA_D56 FBA_CMD23 FBA_CMD24

kS kS kS kS kS
T25 K22
FBA_D58 N27 FBA_D57 FBA_CMD24 J23 FBA_CMD25
o o o o
FBA_D59 FBA_D58 FBA_CMD25 FBA_CMD26
o o o o o o
bo bo bo bo o
R27 J25
o bo
FBA_D60 FBA_D59 FBA_CMD26
bo
FBA_CMD27
bo o
eb
V26 J24

te eb e e e eb
FBA_D61 FBA_D60 FBA_CMD27 FBA_CMD28

te te te
V27 K27

ot ot ot ot ot t
FBA_D62 W27 FBA_D61 FBA_CMD28 K25 FBA_CMD29

NN o FBA_D63 W25 FBA_D62

FBA_D63
FBA_CMD29
FBA_CMD30
J27
J26 NN o
FBA_CMD30
FBA_CMD31
+1.35VGS
NN o NNo
FBA_CMD31 B19
FBA_DBI0 D19 FBA_CMD32 F22 RV2105 2 @ 1 60.4_0402_1%
FBA_DBI1 D14 FBA_DQM0 FBA_CMD34 J22 RV2106 2 @ 1 60.4_0402_1%
FBA_DBI2 C17 FBA_DQM1 FBA_CMD35
FBA_DBI3 C22 FBA_DQM2
FBA_DBI4 P24 FBA_DQM3

mm mm mm mm
FBA_DBI5 W24 FBA_DQM4

co o co o co o co o
FBA_DBI6 AA25 FBA_DQM5

s.s.c s.s.c s.s.c s.s.c

FBA_DBI7 U25 FBA_DQM6
FBA_DQM7
c
i ic c
i ic c
i ic c
i ic
at
at at
at at
at at
at
FBA_EDC0 E19
FBA_EDC1 C15 FBA_DQS_WP0

e mm mm
FBA_EDC3 B22 FBA_DQS_WP2 e e
FBA_EDC2 B16 FBA_DQS_WP1 FBA_CLK0
e mm e mm
e e e
D24

ch hh 27 h h
ch ch
FBA_CLK0 27

ch ch
FBA_CLK0 D25 FBA_CLK0#

Sc Sc 28c c c
FBA_EDC4 R25 FBA_DQS_WP3 FBA_CLK0_N FBA_CLK1 FBA_CLK0#

kS kS kS kS
N22

kS k28S kS kS
FBA_EDC5 W23 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1
FBA_EDC6 AB26k
FBA_CLK1#
k
M22
o FBA_EDC7 o o o o
FBA_DQS_WP5 FBA_CLK1_N FBA_CLK1#
o T26o o o o
bo o oo oo oo oo
FBA_DQS_WP6
b eb eb b
eb e eb F19 eb eb e eb
FBA_DQS_WP7

te ot t ot ot t ot t
ot ot
B B

NNo NNo NNo

D18 FBA_WCLK01

N
FBA_WCLK01 27
C14 FBA_DQS_RN0 FBA_WCK01
N
C18 FBA_WCLK01#
FBA_WCLK01# 27
A16 FBA_DQS_RN1 FBA_WCK01_N D17 FBA_WCLK23
FBA_DQS_RN2 FBA_WCK23 FBA_WCLK23# FBA_WCLK23 27
A22 D16
FBA_DQS_RN3 FBA_WCK23_N FBA_WCLK45 FBA_WCLK23# 27
P25 T24
W22 FBA_DQS_RN4 FBA_WCK45 U24 FBA_WCLK45# FBA_WCLK45 28
FBA_DQS_RN5 FBA_WCK45_N FBA_WCLK67 FBA_WCLK45# 28 PEX_HVDD
AB27 V24
FBA_DQS_RN6 FBA_WCK67 FBA_WCLK67# FBA_WCLK67 28
T27 V25 +FB_PLLAVDD Place close to BGA
FBA_DQS_RN7 FBA_WCK67_N FBA_WCLK67# 28 200mA
mm mm mm om
co o coco co o
Near GPU
N16:+1.05VGS(recommend) .c.c
PEX_HVDD om
s.s.c s.s.FB_PLL_AVDD_1 s s.c
Under .GPU
LV2101

+1.0VGS(Used) cs s
F16 2 1
i ci c ici c i
t tic c i i c
at at at

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
at at at
SBK160808T-300Y-N

1a a
P22 +FB_PLLAVDD N17:+1.8VGS

CV2101 OPT@

CV2102 OPT@

CV2103 OPTN17@

CV2104 OPTN17@

CV2105 OPT@
22U_0603_6.3V6-M
FB_PLL_AVDD_2 OPT@

em m em m em m mm
H22 Place close to ball 1 1 1 1
e e FB_REFPLL_AVDD
e 30ohms (ESR=0.01) 0603eBead e
h h h h h
Sc ch Sc ch Sc ch 2 Sc ch ScSc
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

kS kS kS kS
CV2106 OPT@

CV2107 OPTN17@

CV2108 OPTN17@

ok ok o1 k ok k
2 2 2 2

o o o o oo k
o o o o bo
1 1

b bo eb
o
eb
o
eb
o bo
te e eb eb 2 eb ete
ot ot t o2 t t 2 ot t ot
NNo NNo NNo NN o
D23
FB_VREF

N17S-G1-A1_GB2C-64-595 @

N17S Add 2x0.1u

mm mm m
FB_PLL/Q Decouling
m mm
co o co o co o co o
c s.s.c c s.s.c .c
MLCC cs.sN16 N17 c s.s.c location
i ic i i c titic i i c
atat atat a a atat
A A

em em m0.1uF em
2 4
em em em em
Under
h h h h he h ch
ScSc ScSc Sc ch 22uF Near
ScSc
h
Sc
kS
1 1
S
o okok o okok o ok k okok o o k
bb o
eb
o bo o
eb
o o
eb
o o
te e eb e eb eb eb
ot ot t t
oo t ot ot ot t
NNo NNo
Security Classification LC Future Center Secret Data Title
NN Issued Date 2015/08/20 Deciphered Date
NN 2016/08/20 GPU_MEM Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 21 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
+VGA_CORE
+VGA_CORE
Under GPU 12x4.7uF 5x1uF
+VGA_CORE CV2201 CV2202 CV2203 CV2204 CV2205 CV2206 CV2207 CV2208 CV2209 CV2210 CV2211 CV2212 CV2213 CV2214 CV2215 CV2216 CV2217 CV2218
mm mm mm mm
co o co o co o co co 1
UV1C ? COMMON INS37185662
UV1G ? COMMON INS35856873

s.s.c s.s.c s1.s.c 1 1 s.

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
s.1

33P_0402_50V8J
11/14 NVVDD

OPTN17@
6/14 XVDD
K10
c c 1 1 1 1 1 1 1
c 1 1 1 1 1 1
c

OPTNS@

OPTN17@

OPTNS@

OPTNS@

OPTN17@
i i c K12 VDD_001
i
t ti c i i c i i c

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
at t XVDD_36 N4 at at 2 at at2

OPT@

OPT_RF@
VDD_002
K16 VDD_003a a
K14
G2 XVDD_1 a
G1
m
eG3 m
N5
mm
K18 VDD_004
eVDD_005
2 2 2 2 2
em
2
m2 2 2 2 2 2 2
em m
2 2 2
e e e e
XVDD_2 XVDD_37 N7

c h hG5 XVDD_4
XVDD_3 XVDD_38 P3
c hL15h
L13
c h h c h h h
Sc
G4
c c c c Sc
VDD_006
XVDD_39 P4

kSkS kSkS M12 kS kS

SS
D
M10 VDD_007 D
G6 XVDD_5
k k
XVDD_40 P6
VDD_008
k k
oooo oooo oooo
oo oo
G7 XVDD_6 XVDD_41 R1

bo bo
M16 VDD_009

bo bo
H3 XVDD_7 XVDD_42 R2
b b H4 XVDD_8 XVDD_43 R3 b b M18 VDD_010
b b
te e ee te te e te ete
VDD_011

ot t ot ot
N11

ot
H6 XVDD_9 XVDD_44 R4
N13 VDD_012
oGPU
NNo NNo CV2222 CV2223 o o
J1 XVDD_10 XVDD_45 R5
Near 4x4.7uF 11x10uF 4x22uF
N15 VDD_013
J2
J3
XVDD_11
XVDD_12
XVDD_46
XVDD_47
R6
R7
N17 VDD_014
CV2219CV2220 CV2221 CV2224 CV2225 CV2226 CV2227 CV2228 CV2229 CV2230
NN
CV2231 CV2232 CV2233 CV2234 CV2235 CV2236 CV2237 CV2238 CV2239 CV2240
NN
XVDD_13 XVDD_48 P14 VDD_015
J4 T1 VDD_016
XVDD_14 XVDD_49 R11
J5 T2 VDD_017

22U_0603_6.3V6-M

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

XVDD_15 XVDD_50 R13

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

33P_0402_50V8J
J6 T3 VDD_018

OPTN17_NS@

OPTN17_NS@

OPTN17_NS@
XVDD_16 XVDD_51 R15

OPTN17_NS@

OPTN17@

OPTN17@

RF_NS@
J7 T4 VDD_019

OPTNS@

OPTNS@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTNS@

OPTN17@

OPTNS@

OPTNS@
XVDD_17 XVDD_52 R17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2

OPT@

OPT@

OPT@
K1 T5 VDD_020
XVDD_18 XVDD_53 T10
mm mm mm mm
K2 T6 VDD_021
T12

co o co o 2 co 2o 2 co o1
K3 XVDD_19 XVDD_54 T7
T16 VDD_022

s.s.c s.s.c s.s.c s.s.c

K4 XVDD_20 XVDD_55 U3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
T18 VDD_023
K5 XVDD_21 XVDD_56 U4
c c c c
VDD_024
c c c c
U13
i i i i
XVDD_22 XVDD_57
i i i i
at at at t at
K6 U6 VDD_025

at at at
XVDD_23 XVDD_58 U15
K7 V1
CV88 Use virtual Symbol for diff value a
V10 VDD_026
L3 XVDD_24 +VGA_CORE XVDD_59 V2

em em em em
VDD_027

em m m em
XVDD_25 XVDD_60 V12
L4 V3
e e V14 VDD_028
h h h h ch
XVDD_26 XVDD_61
h h h h
M1 V4 VDD_029

Sc Sc Sc cc
V16

Sc Sc Sc Sc
M2RV2201 1XVDD_27
@ 2 0_0402_5% XVDD_62 V5 VDD_030
XVDD_28 XVDD_63 V18
SDecouling
S kS
ok ok ok ok
M3RV2202 1 2 0_0402_5% V6

ok ok ok ok k
@ VDD_031 NVVDD/Q
XVDD_29 XVDD_64

o
M4
XVDD_30
o
XVDD_65
V7
o o o o o
o o o o o
M5 W1
bb eb
XVDD_31 XVDD_66
bb b eb
eb b eb
M7 W2

te e ee
NVVDD_VCC_SENSE
MLCC N16 N17 location
e te
XVDD_32 XVDD_67 F2

ot ot t ot ot t ot t
N1 W3
VDD_SENSE F1 NVVDD_VSS_SENSE NVVDD_VCC_SENSE 58
XVDD_33 XVDD_68

NNo NNo NNo NNo

N2 W4
GND_SENSE NVVDD_VSS_SENSE 58
N3 XVDD_34 XVDD_69
XVDD_35 4.7uF 10 12
trace width: 16mils Under
differential voltage sensing.
differential signal routing. 1.0uF 4 5

N17S-G1-A1_GB2C-64-595
N17S-G1-A1_GB2C-64-595 47uF 1 0
C
mm mm mm mm C

@
c.o c.o c.o c.o
@

s .s co s .s co s .s co s .s co 10uF 0 11
icic icic icic cic
it Near
at
at at
at at
at 22uF 1 at
a4
e mm e mm e mm e mm
e e e e
ch ch chch ch
ch ch
ch ch
4.7uF 5 4
c
o kSkS o kSkS o kS
kS o kS
330uF kS 1 2 o kSkS
o o o o o
bo o +1.35VGS bobo bobo bo o
eb
o o
te eb ete ete e eb eb
ot oto oto ot t ot t
UV1D
12/14 FBVDDQ
? COMMON INS35857178
NN NN NNo NNo
B26 +1.35VGS
C25 FBVDDQ_01
E23 FBVDDQ_02 +VGA_CORE
FBVDDQ_03 1x10uF 3x22uF
E26
F14 FBVDDQ_04 Under GPU(below 150mils) 8x10uF 2x10uF Near GPU UV1F ? COMMON INS35856561
F21 mm
FBVDDQ_05
m m mm mm
co o co o co o co o
CV2247 CV2241 CV2242
CV2250 CV2243 CV2244 CV2248 CV2245 CV2249 CV2251 CV2252 CV2253 CV2254 CV2246 7/14 VDDS
FBVDDQ_06

s.s.c s.s.c s.s.c s.s.c

G13
FBVDDQ_07
0.1U_6.3V_K_X5R_0201

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U 6.3V M X5R 0402

G14
c
i ic
FBVDDQ_08
c c 1
1 iti 1
c
2 i ic c
i ic
10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

OPTN17_NS@
G15 L11

at at at at

OPTN17@
at at at
FBVDDQ_09 1 1 1 VDDS_1
OPTN17@

OPTN17@

OPTN17@
G16 L17
a
1 2 1 1 1 1 1
OPTNS@

OPTN17@

OPTN17@

OPTN17@

OPT@

OPT@
FBVDDQ_10 VDDS_2
OPTNS@

OPT@

G18 M14
mm mm m mm
OPT@

m1
G19 FBVDDQ_11 P10 VDDS_3
e e FBVDDQ_12
e e e 2e e e VDDS_4

ch hh ch ch ch
G20 P12

ch ch ch
2 2

Sc
FBVDDQ_13 2 1 2 2 2 2 2 2 2 2 VDDS_5

Sc c
G21 P16

kS kS kS kS
FBVDDQ_14 VDDS_6

kS kS kS kS
L22 P18

o
L24 FBVDDQ_19
oo k k o o
T14 VDDS_7
o
o FBVDDQ_20
o o VDDS_8
o
bo bo oo oo oo
L26 U11
o FBVDDQ_21
o VDDS_9

eb eb eb eb eb eb
b
e eb
M21 U17

te evirtual
N21 FBVDDQ_22 VDDS_10
CV32 CV686t
ot Uset
ot t ot t ot t
B FBVDDQ_23 B
oo
R21

NNo NNo NNo

FBVDDQ_24 Symbol for diff value
NN
T21
V21 FBVDDQ_25
W21 FBVDDQ_26
H24 FBVDDQ_27 FBVDD/Q Decouling
H26 FBVDDQ_15
J21 FBVDDQ_16 F4 1 TV2201 @
K21 FBVDDQ_17 MLCC N16 N17 location VDDS_SENSE F3 FB_CLAMP RV2203 1 OPTN16@2 10K_0402_5%
FBVDDQ_18 GNDS_SENSE

mm mm mm
0.1uF 2 0 mm
co o co o co o co o
N17S-G1-A1_GB2C-64-595

s.s.c s.s.c s.s.c s.s.c

@
i ci c ici c 1.0uF 2 8 i ci c i ci c
atat atat at tUnder atat
0 ma
em m em m em em m
4.7uF 2
h e h e h e h e h
Sc ch Sc ch 0Sc ch2 Sc ch ScSc
kS kS kS kS
10uF
ook
o o ok
o ook
o ooko
k
oo k
b bo eb
o 10uFb o 1 1
eb
o bobo
te e eb e eb eb ete
ot t ot ot t ot
Near
ot NNo ot
NN22uF 1 3 NNo NN o
+1.35VGS

m m1 OPT@ 2 40.2_0402_1% CALIBRATION PIN mm

GDDR5 mm mm
co o c.o co o co o
D22 RV2204

co
FB_CAL_PD_VDDQ

c s.s.cC24 RV2205 1 OPT@ 2 40.2_0402_1% FB_CAL_x_PD_VDDQicis

.s
c s.s.c c s.s.c
i i c c
40.2Ohm i i c i i c
at at atat 40.2Ohm at at atat
A
FB_CAL_PU_GND A

em em FB_CAL_TERM_GND emem
FB_CAL_x_PU_GND
emem em em
B25 RV2206 1 OPT@ 2 60.4_0402_1%
h h h h h h h h ch
ScSc ScSc Sc Sc ScSc Sc
Place near balls
kS
FB_CAL_xTERM_GND 60.4Ohm
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title
N17S-G1-A1_GB2C-64-595 Issued Date 2015/08/20 Deciphered Date
NN 2016/08/20 GPU_+VGA_CORE,FBVDDQ
@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 22 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN
N16 3V3_MAIN(N17 VDD_18) Decouling NN Discharge NN
+3V_1.8VGS
+5VALW +1.35VGS
Under GPU Near GPU MLCC N16 N17 location
@
UV1E ? COMMON INS35858730 +VDD18 RV2301 1 2 0_0402_5%

1
14/14 VDD18
0.1uF 2 2

CV2301
0.1U_6.3V_K_X5R_0201

CV2302
0.1U_6.3V_K_X5R_0201

CV2303
1U_6.3V_M_X5R_0201

CV2304
4.7U_0402_6.3V6M
1m mm mm mm Under RV2302
m1 RV2303

co o c.o c.o co o
G8

co 1.0uF co
VDD18_1 1 1 47K_0402_5% 470_0603_5%

s.s.c .s .s s.s.c
G9
s s
VDD18_2 G10 1 1 OPTNS@ OPTNS@
ic i c 1V8_AON_1 G12
i ci c i ci c i c i c
at at at at

3 2
Near
at at at at
2 1V8_AON_2
2 2 2

OPT@

OPT@

OPT@

OPT@
D
4.7uF 1 1
em em em em
FBVDDQ_PWR_EN#
m m m m
5 QV2301B

h e h e h e G
h e h
ch ch ch h
LBSS138DW1T1G_SOT363-6

6
Sc Sc Sc Sc Sc
D
c Sc
S

4
FBVDDQ_PWR_EN 2

kS kS +3.3V_1.8V_AON kS kS
D OPTNS@ D

ok ok ok ok k
QV2301A

o o o
G
o
S LBSS138DW1T1G_SOT363-6 oo k
o
b bo o o o o o o bobo

1
N16 3V3_AON(N17 1V8_AON) Decouling
Near GPUeb b eb eb
OPTNS@

te e Under GPU
e eb eb ete
ot ot t RV2304 1 @ 2 0_0402_5% ot ot ot t ot
VDD_AON

NNo MLCC N N N17 location

N16 NNo NN o

CV2305
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201
CV2306 OPTN17@

CV2307 OPT@

CV2308 OPT@
4.7U_0402_6.3V6M
N17S-G1-A1_GB2C-64-595 1 1 1 1 0.1uF 1 2 Under +5VALW +3.3V_1.8V_AON
@

2
OPT@
1.0uF 1 1

1
2 2 2 2 RV2305
mm mm Near
mm 47K_0402_5%
RV2306
mm
co o c.o
co 4.7uF co o co o
470_0603_5%
OPTNS@
s.s.c .s s.s.c s.s.c
1 1 OPTNS@
c c s c c

1
i c i c i c i c

3 2
i i i i
at at at at atat PXS_PWREN# 5
D
at at
em em em em
QV2302B

em em em e m
G
2N7002KDWH_SOT363-6
h h h h ch

6
h h h D
h
Sc cc cc S c OPTNS@
Sc PXE_VDD & 1V8_AON c +3V_1.8VGS Sc
PXS_PWREN 2 QV2302A

kS S kS S kS S kS

4
okok k k OPTNS@ o ok k
G
2N7002KDWH_SOT363-6

o o ooo o o o o
o bobo
o o o o
S
bb bPXS_PWR_EN_R eb eb

1
b eb eb
te e e
PXS_PWREN
e te te
RV2307 1 @ 2 0_0402_5%

ot ot ot t ot t

1
ot
8 PXS_PWREN PXS_PWR_EN_R 57 1
o
NN RV2309 NN o NNo
RV2308
470_0603_5%
CV2309
10U 6.3V M X5R 0402
NNo
1
OPTNS@ GC6@
2
100K_0402_5%

2
@

1
2

D
2 OPTNS@
G
C
mm mm mm mm QV2303 C

c.o
.s co DV2301 @ +3VS
.s c.o co c.o
.s co c.o
.s co
S L2N7002KWT1G_SOT323-3

3
+3.3V_1.8V_AON
s s s s
icic
DGPU_PWROK
icic icic icic
at at at at
1 2

at at at at
2

mm mm mm mm
1 2

e e RB521CM-30T2R_VMN2M-2 RV2310
10K_0402_5% e e
RV2311
e e e e
chch ch ch ch
ch ch ch ch
10K_0402_5%
RV2316 建虚拟料号,N16=470 c
kS kS kS kS kS
@ OPT@ ohm,N17=5.11 ohm
kS kS RV2313 kS kS kS
1

o o
DV2302
o o o o +5VALW
o o +1.0VGS
o o
bo o bo bo
oo o o o o
PXS_PWREN 2
57b b
eb ebeb eb eb
RV2312 1 PXE_VDD_EN 2 1 PXE_VDD_EN_R RV109 change to 470ohm 0805 for N16 GPU
te e te ete
PXE_VDD_EN_R

ot ot ot t ot t
1.8VGS_PWR_EN

ot
1 2 3
30K_0402_5%

NN o OPT@
NN o NNo NNo
1

0_0402_5% LBAT54AWT1G_SOT323-3 2

1
@ OPT@ RV2314

1
CV2310 OPT@
10K_0402_5% D2301 RV2317
0.22U_0402_10V6K RV2315 RV2316 470_0805_5%
@ 1
1 2 OPT@ 47K_0402_5% 5.11_0805_1%
2

OPT@ OPTN17@ @

2
1 2

2
mm mm RB521CM-30T2R_VMN2M-2
mm mm
co o co o co o co o
+1.8VG_AON TO +1.8VGS
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i ic i ic i ic

1
at
at at
at at
at at at

D
e mm e mm e mm +1.0VGS_PWR_EN# 2
e mm
QV2304
e e e G
e
ch ch ch ch ch
AO3402_SOT-23-3

ch ch ch chOPTN17@ c
kS
+3VS S
kS k kS kSkS kS kS kSkS

S
o o o o o o o o o o

3
1
D

bo o
eb
oo
eb
oo bo o boo
1

PXE_VDD_EN_R

eb eb eb eb e eb
2 QV2305

te ot t ot t OPT@ tSe
ot t
RV2318 G LBSS139WT1G_SC70-3

ot o t
B B
82K_0402_1%

NNo NNo NNo NNo

1
@ D
@ 2 QV2306
DV2303
2

PXS_PWREN G LBSS139WT1G_SC70-3
RV2321 1 @ 2 0_0402_5% 2
NVVDD_EN OPTN16@ S
1

3
1.8VGS_PWR_EN NVVDD_EN 58
RV2323 1 @ 2 0_0402_5% 3
26,57 1.8VGS_PWR_EN
RV2324 1 @ 2 0_0402_5% LBAT54AWT1G_SOT323-3
1

+3V_1.8VGS

mm mm RV2325
mm mm
co o co o co o co o
RV2326 1 @ 2 0_0402_5% 100K_0402_1%

s.s.c s.s.c s.s.c s.s.c

@

i ci c ici c i ci c i ci c
2

atat atat atat atat

em m em m em m em m
+5VALW +VGA_CORE

h e h e h e h e h
Sc ch Sc ch Sc ch Sc ch ScSc
ok kS ok kS ok kS ok kS k

1
o o o
RV2327
o oo k
o
b bo o o o o o o OPTNS@ bobo
47K_0402_5% RV2328

ebeb eb eb eb eb
OPTNS@ 10_0603_5%

te e
ot t ot t ot t ot
ete
ot NNo NNo NNo o

3 2
NVVDD_EN# 5
D
QV2309B NN
DV2304 G LBSS138DW1T1G_SOT363-6

6
FB_GC6_EN_R RV2329 1 @ 2 0_0402_5% GC6_EN 2 D OPTNS@
8,26 FB_GC6_EN_R S

4
1 FBVDDQ_PWR_EN FBVDDQ_PWR_EN 57 NVVDD_EN 2 QV2309A
DGPU_PWROK OPT@
RV2330 1 2 10K_0402_5% 3 G
8,58 DGPU_PWROK LBSS138DW1T1G_SOT363-6
S

1
1

mm mm mm mm
BAV70W-7-F_SOT323-3 OPTNS@

co o co o co o co o
RV2333
GC6@

s.s.c s.s.c s.s.c s.s.c

CV2313 OPT@
0.1U_6.3V_K_X5R_0201

200K_0402_5%
GC6@
c c c c
1
i ic i i c i i c i i c
atat atat at at atat
2

A A

emem emem emem em em

2

h h h h h h h h ch
ScSc ScSc kS
cc
S kS
cc
S kS Sc
o okok o okok o o o k
o o o k
o o o k
bb o o o o o
te e eb eb ebeb eb eb eb
eb
ot ot t ot t ot ot ot
ot
NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

NN 2016/08/20 GPU_AON/MAIN PWR/SEQUENCE
NN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 23 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat at
at at
at atat
em m em m em m em m
UV1H ? COMMON INS35859464

h e h e h e h e h
Sc ch Sc ch c ch Sc ch Sc
13/14 GND

kS kS kSkS kS Sc
D D
A2 K11

ok ok ok k k
AB17 GND_001 GND_057 K13
GND_058 K15 o oo
o o o o o o o o
bo
AB20 GND_005
b bo eb
o bK17 bo eb
o bo
GND_006 GND_059

eb eb
AB24

te e e teL12 ete
AC2 GND_007 GND_060

ot t ot ot t ot
L10

ot
AC22 GND_008 GND_061

NNo AC26 GND_009 o NNo o

GND_062
AC5 GND_010NN GND_063 L16 NN
L14

AC8 GND_011 GND_064 L18

AD12 GND_012 GND_065 L5
AD13 GND_013 GND_069 M11
A26 GND_014 GND_070 M13
AD15 GND_002 GND_071 M15
AD16 GND_015 GND_072 M17
mm mm AD18 GND_016 GND_073 N10
mm mm
co o co o co o co o
AD19 GND_017 GND_074 N12

s.s.c s.s.c s.s.c s.s.c

AD21 GND_018 GND_075 N14
c c c c
GND_019 GND_076
c c c c
AD22 N16
i i i i i i i i
at at at at
GND_020 GND_077

at at at at
AE11 N18
AE14 GND_021 GND_078 P11

em em em em
GND_022 GND_079

em em em em
AE17 P13
AE20 GND_023 GND_080 P15
h h h h GND_024 GND_081
h h h h ch
Sc Sc Sc Sc
AB11 P17

Sc Sc Sc Sc Sc
GND_003 GND_082

kS
AF1 P23

okok okok okok okok k

AF11 GND_025 GND_084 P26

o o
AF14 GND_026 GND_085
o
R10
o o o o
bb o o GND_027
o
GND_087
o o
eb eb eb eb
AF17 R12

eb eb eb eb
GND_028 GND_088
te e
AF20 R14

ot ot t ot t ot t ot t
AF23 GND_029 GND_089 R16

NNo NNo NNo NNo

AF5 GND_030 GND_090 R18
AF8 GND_031 GND_091 T11
AG2 GND_032 GND_092 T13
AG26 GND_033 GND_093 T15
AB14 GND_034 GND_094 T17
B1 GND_004 GND_095 U10
B11 GND_035 GND_096 U12
B14 GND_036 GND_097 U14
GND_037 GND_098
C
mm mm B17 U16
mm mm C

c.o c.o c.o c.o

GND_038 GND_099

co co co co
B20 U18
.s .s .s .s
B23 GND_039 GND_100 U23
s s B27 GND_040 GND_102 U26 s s
icic icic GND_041 GND_103
icic icic
at at at at
B5 V11

at at at at
B8 GND_042 GND_105 V13
GND_043 GND_106
mm mm mm mm
E11 V15
e e e e
GND_044 GND_107
e e e e
E14 V17

ch ch ch ch ch
GND_045 GND_108

ch ch ch ch
E17 Y2
E2 GND_046 GND_109 Y23
c
kSkS kSkS kS
kS kSkS kSkS
E20 GND_047 GND_110 Y26
o o
GND_048 GND_111
o o
E22
o o
Y5
o o o o
bo bo bo bo o
GND_049 GND_112
o bo
E25
bo
AA7
bo o
eb eb eb
E5 GND_050 GND_F AB7
te ot
ete ot
ete ot
ete ot t
GND_051 GND_H

ot
E8
GND_052

NN o NN o NN o NNo

H2 P2
mm mmH5 GND_053 GND_083 P5
mm mm
co o co o L2 GND_066 co o co o
GND_056 GND_086 U2

s.s.c s.s.c s.s.c s.s.c

GND_101 U5

c
i ic c
i ic
GND_104
c
i ic c
i ic
at
at at
at at
at at
at
e mm e mm e mm e mm
e e e e
chch chch
H23 L23
chch ch
ch chc
kS kS kS kS kS
H25 GND_054 GND_067 L25

o o kS o o kS GND_055 GND_068
o o kS o o kS o o kS
bo o
eb
oo
eb
oo
eb
oo boo
eb eb eb eb e eb
N17S-G1-A1_GB2C-64-595

te ot t ot t ot t ot t
@

ot
B B

NNo NNo NNo NNo

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat atat atat atat
h em
e m
h eme m
h eme m
h eme m
h
Sc ch Sc ch Sc ch Sc ch ScSc
ok
o kS oko kS oko kS oko kS k
oo k
o
b bo o o o o o o bo
ebeb eb eb eb eb bo
te e
ot t ot t ot t ot
ete
ot NNo NNo NNo NN o

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at atat
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb e
te
bb eb eb
ot ot t ot t ot ot t
Title
NNo NNo o2016/08/20 NNo
Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered DateNN GPU_GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 24 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
PEX_PLLVDD/Q Decouling

MLCC N16 N17 location UV1J ? COMMON INS35860124

4/14 IFPAB

1.0uF
1 mm
NA mm Under
mm om m
coNA co o co o
DVI HDMI DP

o c co
s1.s.c s.s.c s.s.c
SL/DL

c
1uF
c c c s.s AC4.
i i c i i c i i c i i c
at at at at
Near IFPA_L3_N

at 1 at at at
AC3
TXC/TXC
IFPA_L3
4.7uF NA
em m em m em m em m IFPA_L2_N Y3
AA6
e e e e
IFPAB_RSET
h h INS35860218h h h
TXD0/0

Sc ch Sc ch Sc ch Sc
h
Sc
UV1I ? COMMON Y4

Sc Sc
IFPA_L2

kS kS kS
D +1.0VGS 5/14 NC D

o ok
o
OPTN16@

o ok
o o ok o
k
oo k AA2 k
oo k
bo bo
TXD1/1

b bo b bo o bo bo
Under GPU Near GPU +PEX_PLLVDD +PEX_PLLVDD IFPA_L1_N AA3

eb
RV2501 2 1 0_0402_5% AA14 W7

eb
AA15 NC_1 IFPAB_PLLVDD IFPA_L1
te e te e
ot ot
e te ot
ete

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

4.7U_0402_6.3V6M
ot ot ot
AB6 NC_2
o o o

CV2501 OPTN16@

CV2502 OPTN16@

CV2503 OPTN16@
PEX_SVDD_3V3 AB8 NC_3 AA1
NN AD10 NC_4 N NN NN
TXD2/2
1 1 1
AD7 NC_5 N IFPA_L0_N AB1
IFPA_L0
PEX_PLLVDD 1 @ 2 PEX_TSTCLK_OUT AE22 NC_6
N16:+1.0VGS(recommend) RV2502 200_0402_1% AE3 NC_7 AA5
2 2 2 NC_8 IFPA_AUX_SDA_N
N17:NC AE4 AA4
+3.3V_1.8V_AON AF2 NC_9 IFPA_AUX_SCL
PEX_TSTCLK_OUT# AF22 NC_10
NC_11
mm mm mm mm
AF3 AB4

co o co o co o c.o
NC_12 IFPB_L3_N

1
co
+3.3V_1.8V_AON Differential signal AF4 AB5
TXC

s.s.c s.s.c s.s.c

NC_13 IFPB_L3
s.s
RV2503 AG3
10K_0402_5% D10 NC_14

i ci c i ci c i ci c NC_15
i c i c
at at at at
@ E10 W6 AB2

at at at at
TXD0/3
F10 NC_16 IFP_IOVDD_1 IFPB_L2_N AB3

2
F5 NC_17 Y6 IFPB_L2

em em RV2504 2 OPTN16@1 0_0402_5% PEX_SVDD_3V3 emem emem emem IFPB_L1_N AD2

MULTI_STRAP_REF0_GND F6 NC_18 IFP_IOVDD_2

h h h h ch
NC_19
h h h h
W5 TXD1/4

ScSc Sc c ScSc ScSc Sc

NC_20 AD3

kS
4.7U_0402_6.3V6M

kS 4.7U_0402_6.3V6M
IFPB_L1

1
ok ok ok ok
OPTN16@

OPTN16@

ok o ok ok o o k
1 1 RV2505

bbo o o o 40.2K_0402_1%
o o o o
AD1
TXD2/5
o o
eb eb eb eb
IFPB_L0_N AE1

eb eb eb eb
OPTN16@

te e PEX_SVDD_3V3 IFPB_L0

ot ot t ot t ot t ot t
N17S-G1-A1_GB2C-64-595
CV2504

CV2505

2
N16:+3.3V_AON(recommend) 2 2

NNo NNo NNo NNo

@
N17:NC AD5
IFPB_AUX_SDA_N AD4
Change by Bourne 20170412 IFPB_AUX_SCL
Change by Bourne 20170412 Near GPU
IFPAB (DEFEATURED 0N GM108)

PEX_SVDD/Q Decouling
C
mm mm mm N17S-G1-A1_GB2C-64-595 mm C

c.o o location c.o

co
o o c.o
co
UV1K ? COMMON INS35860067

.s c .s c.c
.s .s

@
MLCC s N16 N17 s s
10/14 MISC2

s
icic icic icic icic
atat 2
4.7uF NA Near at
at at
at at
at
e mm e mm e mm e mm
e e e e
D12 1

ch ch ch h h 29 ch
ROM_CS_N TV2501 @

ch ch Sc
h B12 ROM_SI
cROM_SI
c 29 c
kSkS kSkS kS kS kS kSkS
ROM_SI A12 ROM_SO

o o o o o o
STRAP0 k
D1 ROM_SO C12 ROM_SCLK
o o
ROM_SO
o o
bo bo o o o
29 STRAP0 ROM_SCLK 29
D2 STRAP0 ROM_SCLK
o o oSTRAP1
b b STRAP3 E3 STRAP2 bb o o
eb eb eb eb
29 STRAP1 STRAP1
STRAP2 E4
te e e e STRAP4 D3 STRAP3 e e
29 STRAP2
t t
oo t 29 t
STRAP4 o o
STRAP3
t o t t ot t
o NN
29
29 NN
STRAP5
STRAP5 C1 STRAP4
STRAP5 NNo NNo
D11 RV2506 2 @ 1 10K_0402_5%
BUFRST_N

mm XS_PLLVDD/Q Decouling mm mm mm
co o co o co o co o
c s.s.c MLCC s.s.c
N16 N17 location
c c s.s.c c s.s.c
i ic titic i ic i ic
PEX_HVDDat at 0.1uF 1 ma 1 a Under at at at
at
e m m
N16:+1.05VGS(recommend)
e m e mm e mm
e e e e
ch h 22uFch hh ch ch
+1.0VGS(Used)
ch c ch
1 0 Near
PEX_HVDD c c c
N17:+1.8VGS
kS kS 1 LV2501 2 OPT@ kSkS XS_PLLVDD kSkS kS kS kSkS
N17S-G1-A1_GB2C-64-595

o o o o o

@
o o o o o
bo o bo oo oo oo
2 0_0402_5% Under GPU
bo
LV2502 1 @

te eb ete eb eb ebeb
b
e eb
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

ot ot t ot ot t
SBK160808T-300Y-N UV1L ? COMMON INS35860348

ot ot
CV2509
22U_0603_6.3V6-M

B B
CV2508
4.7U_0402_6.3V6M

CV2507 OPT@

CV2506

NNo NNo XS_PLLVDD NNo

1 1 9/14 XTAL_PLL
30ohms (ESR=0.05) Bead SP_PLLVDD & VID_PLLVDD/Q Decouling
1 1
L6 N N
SP_PLLVDD M6 XS_PLLVDD +3.3V_1.8V_AON
2 2 MLCC N16 N17 location GPCPLL_AVDD F11 SP_PLLVDD
OPT@

2 2 VID_PLLVDD GPCPLL_AVDD
OPT@

@ N6
VID_PLLVDD

2
0.1uF 2 2 Under 150mA RV2507
10K_0402_5%
mm 10uF 1 0 mm mm @
mm
c.o co Under GPU(below 150mils) 47uF
Near
c.o
co 10K_0402_5% 2 OPT@ 1 RV2508 c.ocoXTAL_OUTBUFF C10 XTALOUT co o
.s .s .s s.s.c

1
XTALSSIN A10

c s 1 0
c s XTAL_SSIN
c s c
c c c c
Change by Bourne 20170412
i i LV2503 1 @ 2 0_0402_5% i i i i i i
at at at at at at atat
SP_PLLVDD

1
XTAL_IN C11 B10 XTAL_OUT
XTAL_IN XTAL_OUT

em m em m em m em m
RV2509

e e e e
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

N17S-G1-A1_GB2C-64-595 10K_0402_5%
h h h h h
ch ch VID_PLLVDD ch ch
CV2510 OPT@

CV2511 OPT@

Sc Sc Sc Sc Sc
OPTN17@ OPT@

@ Sc
1 1
RV2510 1 2 0_0402_5%

kS kS kS kS

2
ook
o o ok o o ok o ooko
k
oo k
b bo o o o bobo
2 2 RV2511 1 OPT@ 2 10M_0402_5% XTAL_OUT

te e eb
eb eb eb eb eb ete
ot ot t ot t ot ot ot
NNo NNo o

2
N
R2501
N
51_0402_1%
NN
YV2501
OPT@

1
OPTN17@ XTAL_IN 1 4
LV2504 1 2 0_0402_5% GPCPLL_AVDD OSC1 GND2
2 3 XTAL_OUT_R
GND1 OSC2
0.1U_6.3V_K_X5R_0201

mm mm mm 1 mm
12P_0402_50V8-J

12P_0402_50V8-J
1
OPT@

co o co o co o co o
CV2512 OPTN17@

OPT@
GPCPLL_AVDD/Q Decouling 1

s.s.c s.s.c s.s.c s.s.c

27MHZ_10PF_7V27000050
OPT@
icic i ci c 2
i c i c i ci c
atat
N16 N17t location
a at at at atat
CV2513

CV2514
A MLCC 2 2 A

h emem 0.1uF he
m1
NA em Under
h emem h em em
Sc
h
Sc
h
Sc
h
Sc
h ch
Sc S c NA Sc Sc kS Sc
okok
k
o ok ok ok
4.7uF 1
o
Near ok ok o o k
bb o bo o 22uF
eb
o o
eb
o o
eb
o o
eb eb eb eb
NA 1
te e t e
ot t ot ot t
ot o
NNo
t
NNo
Security Classification LC Future Center Secret Data
N ot Title
NNo
Issued Date 2015/08/20 Deciphered Date N 2016/08/20 GPU_STRAP/DP/HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 25 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN
UV1M ? COMMON INS35861009
8/14 MISC1
+3.3V_1.8V_AON +3.3V_1.8V_AON

GPU Address 0x9E

mm mm mm mm
co o c.o o co o co o
s.s.c cD9 s.s.c s.s.c

3
4
s .s VGA_SMB_CLK
Internal Thermal Sensor RPV4
c c
I2CS_SCL
i c i c
D8 VGA_SMB_DATA
i c c i c c

2
i i i i
at at at
2.2K_0404_4P2R_5%

at
I2CS_SDA

at at I2CC_SDA at at
OVERT# A6 QV2601A
AE2 OVERT A9 I2CC_SCL OPT@

G1
PJT7838_SOT363-6

em em em D1 em
TS_VREF I2CC_SCL B9 I2CC_SDA
m m m 6 OPT@
m

2
1
VGA_SMB_CLK 1

h e h e h e S1
h e EC_SMB_CK0 39,44
h

0.1U_6.3V_K_X5R_0201
Sc ch c ch c ch c ch ScSc

CV2601
S S S
1 E12

kS S S S
D D

ok ok ok ok k
THERMDN

ok ok okQV2601B k
C9 I2CB_SCL

o o F12 I2CB_SCL C8 I2CB_SDA

oo
bo bo bo bo

5
b bo bo bo bo bo
THERMDP I2CB_SDA
2

te e e e e

G2
e t e t e t e te
ot o t o t o t ot
@ PJT7838_SOT363-6
VGA_SMB_DATA

NNo NNo NNo o

4 3 OPT@
S2 D2 EC_SMB_DA0 39,44
NN
C6 NVVDD_PWM_VID
GPIO0 B2 FB_GC6_EN NVVDD_PWM_VID 58 PU AT EC SIDE, +3VS AND 4.7K
GPIO1 D6 GPU_EVENT#_R
GPIO2 C7 NVVDDS_PWM 1
GPIO3 1.8VGS_PWR_EN_R TV2601
PLT_RST_VGA# @ F9
RV2605 1 2 56_0402_5% GPIO4
mm m mm mm
A3
CV2602 o m
c.o co o co o
1 PSI_VGA GPIO5

.c co co
A4
PSI_VGA 58

s.s.c s.s.c
GPIO6
s @ s.
220P_0201_25V7-K
s .s MEM_VDD_CTL GPIO7
B6
E9
i c i c i ci c VGA_ALERT# GPIO8
i ci c i c i c
at at at at
F8

at
2

at at at
2

GPIO10_FBVREF_ALTV GPIO9 C5 +3.3V_1.8V_AON +3VALW +3VS

GPIO10_FBVREF_ALTV 27 GPIO10 E7

eme3 m 1 emem em em em em
VGA_AC_DET_R 2 1 GPIO11 D7
VGA_AC_DET 44

2
OVERT# RV2606
h h h h ch
DV2601 OPT@ GPIO12
h h h h
WRST# 44 B4
cc Sc Sc Sc
Sc Sc cRV2609 Sc
RB751V-40_SOD323-2 GPIO13 10K_0402_5%
B3

kS S1 S kS
GPIO14 GC6N17@

2
ok ok k
C3
o k CV2603
ok
SYS_PEX_RST_MON#_GPU
ok
GPIO15
SYS_PEX_RST_MON#
10K_0402_5% o o
k o k
oo @ 2
RV2607 1 2 0_0402_5% D5
o
QV2602 RV2608 10K_0402_5%

bo o o @ oo o
0.01U_0201_10V6K GPIO16 FB_GC6_EN_R
o o o
OPTN16@ D4 GC6N17@

1
eb bb eb eb
LSI1012XT1G_SC-89-3 GPIO17 FB_GC6_EN_R 8,23

eb eb eb eb
C2

te e te
@ GPIO18

ot ot t ot ot t ot
ot
F7

1
GPIO19

NNo o NNo
E6

3
VGA_CRT_DATA NN N
GPU_PEX_RST_HOLD#_GPU GPIO20
GPU_PEX_RST_HOLD# QV2603B
N
RV2610 1 2 0_0402_5% C4
GPIO21

D2
OPTN16@ A7
VGA_CRT_CLK GPIO22 5 PJT7838_SOT363-6
B7 G2
GPIO23
GC6N17@

S2
6
N17S-G1-A1_GB2C-64-595
QV2603A

4
@

D1
FB_GC6_EN 2
mm mm mm
PJT7838_SOT363-6
C G1
mm C

c.o
co c.oco c.o
co c.o
co
@

.s .s .s .s
MEM_VDD_CTL SYS_PEX_RST_MON#

S1
RV2611 1 2 0_0402_5%

2
s s s s
icic icic icic icic
RV2612 GC6N17@

at at at at

1
at at at at
10K_0402_5%
GC6@

e mm mm mm mm
e ? ee e e e e

1
chch
hh ch h c1h h ch
UV1N COMMON INS35861249

kS ScSc kS Sc kS
c
kS
c
3/14 JTAG +3.3V_1.8V_AON GC6N16@

kS k kS kS
RV2613 2 0_0402_5%
o o oo k o o k
2.2K_0404_4P2R_5%
o o o o
bo o bo o bo bo 1@
o o o o
1 AE5 VGA_CRT_DATA 2 3

eb eb eb eb eb eb
TV2602
1 AE6 JTAG_TCK VGA_CRT_CLK 4
te eJTAG_TDI e te
TV2603
t ot ot t ot t
ot AD6 tJTAG_TDO
1 AF6
oo
TV2604
o NNo NNo
1 RPV1

N NN I2CB_SCL
TV2605
AG4 JTAG_TMS
TESTMODE N AD9 JTAG_TRST_N
10K_0402_5% 2 OPT@ 1 RV2614 2.2K_0404_4P2R_5%
10K_0402_5% 2 OPT@ 1 RV2615 2 3
NVJTAG_SEL I2CB_SDA 1 4 +3.3V_1.8V_AON +3.3V_1.8V_AON
@ RPV2

0.1U_6.3V_K_X5R_0201
2.2K_0404_4P2R_5% 1

CV2604
2
I2CC_SCL 2 3
mm mm I2CC_SDA 1 4 mm RV2616
mm
co o co o c.o
co co o
10K_0402_5% 2

s.s.c s.s.c .s s.s.c

@
GC6@
s
RPV3 @
c
i ic c
i ic c
2 10K_0402_5% ti ic c
i ic

1
at
at at
at at at at

2
MEM_VDD_CTL RV2617 1
a +3.3V_1.8V_AON
@

e mm e mm e mm e m 1m
e e e GPU_EVENT#_R
e GPU_EVENT#

ch ch hh ch ch
N17S-G1-A1_GB2C-64-595 3

ch ch RV2618 c ch GC6@
GPU_EVENT# 8
c 1 1K_0402_1% c
@

kS kS kS kS
SS S S kSkS
1.8VGS_PWR_EN_R 2 OPT@
kRV2619
k 1 OPT@ 2 10K_0402_5% ok
o o o ok LSI1012XT1G_SC-89-3 o
QV2604
o o o o
bo oo oo bo oo
OVERT#
o bo RV2621 1 @ 2 0_0402_5%
te eb eb eb e te
b b
VGA_ALERT# RV26201 OPT@ 2 10K_0402_5%
e e
b
e eb
ot ot t otVGA_AC_DET_R ot t ot t
B B

NNo NNo NNo NNo

RV26221 OPT@ 2 100K_0402_5%

PSI_VGA RV26231 @ 2 10K_0402_5%

GPU_PEX_RST_HOLD# RV26241 OPT@ 2 10K_0402_5% +3VS
+3VS

2
RV2625
mm mm mm mm 10K_0402_5%

co o co o co o co o
OPT@

2
s.s.c s.s.c s.s.c s.s.c
RV2626
10K_0402_5%

i ci c ici c i ci c OPT@
i c i c 1.8VGS_PWR_EN

1
at at at at
+3VS

at at at at
1.8VGS_PWR_EN 23,57

em m em m em m mm

1
he
2

3
h h e h e h e h5e h
Sc Sc ch Sc ch Sc Sc
RV2627 QV2605B

Sc ScOPT@ G2 Sc

D2
0_0402_5%

kS kS
PJT7838_SOT363-6
k
oo k @
ok
+3.3V_1.8V_AON
ok k
oo k k
oo k
o o
0.1U_6.3V_K_X5R_0201

bo o o bo bo

S2
bo o o bo QV2605A bo
+3.3V_1.8V_AON
+1.8VGARST 1

CV2605 OPT@

1
b b eb eb

6
te e
otRV2628
e te ot t ot
e te2 G1 ot
e
te

4
ot
2

D1
NNo NNo o o
RV2629 1.8VGS_PWR_EN_R
PJT7838_SOT363-6
NN NN
2

2 10K_0402_5%
10K_0402_5% OPT@ OPT@

S1
OPTN16@ DV2602
1
5

UV2603 GPU_PEX_RST_HOLD# 2

1
PLT_RST# 1 1
P

11,37,40,44 PLT_RST# PLT_RST_VGA# 20

1

B 4 SYS_PEX_RST_MON# 3
2 Y
8 PXS_RST# A
G

m mm mm mm
LBAT54AWT1G_SOT323-3
m
1

co o co o co o co o
MC74VHC1G09DFT2G_SC70-5 OPTN16@
3

s.s.c s.s.c s.s.c s.s.c

OPT@ OPTNS@
RV2630
1

1.8VGS_PWR_EN_R RV2632 1 2 0_0402_5% 1.8VGS_PWR_EN

icic
100K_0402_5%
RV2633
RV2631 1 2
i c c
0_0402_5%
i i c i c i ci c
atat at at at at at at
OPT@
A 100K_0402_5% OPTN17@ A
2

OPT@

emem em em emem em em
2

h h h h h h h h ch
ScSc ScSc Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o ok ok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

NN 2016/08/20 GPU_GPIO/JTAG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 26 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
Lower 32 bits NN NN NN NN

MF=0 No Mirror
21,28 FBA_D[0..63]
mm mm mm mm
co o co o co o co o
s.s.c s.s.c s.s.c s.s.c
+1.35VGS
21,28 FBA_CMD[31..0]

ici c i c i c
UM2701
i ci c i c i c
atat at
at at
at at at
21,28 FBA_EDC[7..0]
MF=0 MF=1 MF=1 MF=0 Close to VRAM

em m em m FBA_EDC0 FBA_D0m
e em em m
21,28 FBA_DBI[7..0]

h e h e A4
h
CV2703 CV2704
h e
CV2705 CV2701 CV2702 CV2706 CV2707
h
ch ch ch c ch
DQ24 DQ0 A2 FBA_D1

Sc Sc
DQ1 B4 c FBA_D2
Sc
C2

Sc

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
C13 EDC0 EDC3 DQ25
DQ2 S S
FBA_EDC1

kS kS B2 S FBA_D3 1 S
D D

ok ok kk kk k
R13 EDC1 EDC2 DQ26
k
FBA_EDC2 1 1 1 1 1 1

OPT_NS@
BYTE0
oDQ3 oo oo

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
o o R2 EDC2
o oo 2
FBA_EDC3 EDC1 DQ27 FBA_D4

OPT@
E4
o
b bo o o o oDQ5 F4 bobo
EDC3 EDC0 DQ28 DQ4 FBA_D5
b b b
E2
b DQ29
b b
te ee ee ee e
FBA_D6
e 2 2 2 2 2 2
te
ot ot t otot DQ31 ot t ot
FBA_DBI0 D2 DQ30 DQ6 F2 FBA_D7

NNo NNo o
FBA_DBI1 D13 DBI0# DBI3# DQ7 A11 FBA_D8

DBI1# NN NN
FBA_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D9
FBA_CLK0 OPT@ FBA_DBI3 P2 DBI2# DQ17 DQ9 B11 FBA_D10
RV2702 1 2 40.2_0402_1% DBI3# DBI0# DQ18 DQ10 FBA_D11
21 FBA_CLK0 B13 BYTE1
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_D12
FBA_CLK0# RV2701 1 OPT@ 2 40.2_0402_1%
21 FBA_CLK0# FBA_CLK0# J11 CK DQ20 DQ12 E13 FBA_D13
FBA_CMD14 J3 CK# DQ21 DQ13 F11 FBA_D14 CV2709 CV2710 CV2711 CV2712 CV2713 CV2714 CV2715
1 CKE# DQ22 DQ14 F13 FBA_D15

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
CV2708 DQ23 DQ15 FBA_D16
mm OPT@ mm BA2/A4 mm mm

1U_6.3V_M_X5R_0201
0.01U_0201_10V6K
U11

co o 2 K10o
co o co o
FBA_CMD2 DQ8 DQ16 FBA_D17 1 1 1 1 1 1 1
o
H11 U13
FBA_CMD3 .c

OPT_NS@

OPT@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
s.s.c .cBA1/A5 BYTE2s.s.c s.s.2 c
FBA_CMD4 BA0/A2 DQ9 DQ17 FBA_D18

OPT_NS@
T11

c c ss K11 BA3/A3
c
DQ10 DQ18 T13 FBA_D19
c
i ic i i
FBA_CMD1
c H10 BA2/A4 BA0/A2
i i c DQ11 DQ19 FBA_D20
i 2 c
i
at at at at
N11

at t at
2 2 2 2

at
BA3/A3 BA1/A5 DQ12 DQ20 2
N13 FBA_D21
a DQ13 DQ21 M11 FBA_D22

emem em em FBA_CMD11 em m mm
FBA_CMD6 DQ14 DQ22 FBA_D23
K4
e
M13
e
h h h ch he ch
H5 A8/A7 A10/A0 DQ15 DQ23 FBA_D24
h h h
U4

ScSc Sc Sc ScSc Sc Sc
FBA_CMD10 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D25

kS kS
FBA_CMD7 K5 A10/A0 A8/A7 DQ1 DQ25 FBA_D26

ok ok ok
T4

ok ok ok k k
J5 A11/A6 A9/A1 DQ2 DQ26
o o
FBA_CMD9 T2 FBA_D27

o o o o o
bo o
A12/RFU/NC DQ3 DQ27 FBA_D28 Around VRAM
o o o bo o
BYTE3 N4
bb bb bb DQ4 DQ28
ebeb
A5 N2 FBA_D29

te e ete
U5 VPP/NC1 ete e eCV2716
DQ5 DQ29

ot ot t ot t
FBA_D30

ot t
M4
o
VPP/NC2 DQ6 DQ30 FBA_D31

NN o NN o +1.35VGS
DQ7 DQ31
M2
NNo
CV2717 CV2718 CV2719 CV2720 CV2721 CV2722
NNo

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
RV27031 OPT@ 2 1K_1%_0201 J1
FBA_SEN0 MF RV27041 OPT@ 2 1K_1%_0201 J10 1 1
SEN 1 1 1 1 1

OPT@

OPT@

OPT@

OPT@

OPT@
RV2705 1 2 121_0402_1% OPT@ J13 B1
ZQ VDDQ1

OPT_NS@

OPT_NS@
D1
VDDQ2 F1
FBA_CMD8 VDDQ3 2 2
J4 M1 2 2 2 2 2
FBA_CMD12 G3 ABI# VDDQ4 P1
C
mm mm CAS#
RAS#
FBA_CMD0 G12 mm VDDQ5 T1 mm C

c.o
co c.o o c.o
co c.o
co
CS# WE#
FBA_CMD15 L3 VDDQ6 G2

s .s s .s cCAS# RAS#
FBA_CMD5 L12
s .s VDDQ7 L2
s .s
icic icic icic icic
WE# CS# VDDQ8 B3

at at at at
VDDQ9

at at at at
D3
VDDQ10 F3

e mm mmFBA_WCLK01# D5
mm VDDQ11 H3
mm
e FBA_WCLK01e e e e e e
21 FBA_WCLK01# FBA_WCLK01 D4 WCK01# WCK23# VDDQ12 K3
ch ch ch h ch
ch ch
ch ch
21 WCK01 WCK23 VDDQ13

Sc c
M3

kS kS kS kS kS
FBA_WCLK23# VDDQ14

kS kS kS kS
P5 P3
21 FBA_WCLK23#
k P4 WCK23#
FBA_WCLK23 WCK01# VDDQ15 T3
o o o o
21 FBA_WCLK23 WCK23 WCK01
o o VDDQ16
o o o o
bo bo bo bo o
E5
o bo FBA_VREFC bo
VDDQ17
bo o
eb
N5

te eb e e e eb
VDDQ18
te te te
A10 E10

ot ot ot ot ot t
U10 VREFD1 VDDQ19 N10
+1.35VGS
NN o FBA_VREFC J14 VREFD2
VREFC NN o VDDQ20
VDDQ21
B12
D12 NN o NNo
CV2723 1 VDDQ22 F12
820P_0402_25V7 VDDQ23 H12
VDDQ24
1

FBA_CMD13 J2 K12
RV2706 OPT@ 2 RESET# VDDQ25 +1.35VGS
M12
549_0402_1% VDDQ26 P12
OPT@ VDDQ27 T12
CV2724 CV2725 CV2726 CV2727 CV2728
mm mm mm mm
VDDQ28 G13

co o oVSS1 co o co o
1 2

VDDQ29
o
FBA_VREFC H1 L13
cK1
s.s.c s.sG5.cVSS2 s.s.c s.s.c
VDDQ30 B14

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

4.3U_0402_4V6-M
VDDQ31
c c c c
B5 D14
i ic itic L5 VSS4 i ic i ic

OPT_3T@
RV2707 VSS3 VDDQ32

at t at at
1 1 1 1

OPT_N3T@

OPT_N3T@

OPT_N3T@

OPT_N3T@
F14

at at at

3
aa
1.33K_0402_1% VDDQ33 M14
OPT@
T5 VSS5 VDDQ34
mm mm mm 2 m
P14
e m
he e e
2

B10 VSS6 VDDQ35

e e e e
T14

4
2 2 2

ch ch h chch ch
ch ch
D10 VSS7 VDDQ36
c
Sc c
G10 VSS8

kS kS kS L10 VSS9
kS A1 S
kSkS kSkS
o oo ok o k o o
P10 VSS10 VSSQ1
o o o o
C1

bo o o oo oo oo
T10 VSS11 VSSQ2 E1
b eb eb b
eb eb eb VSSQ4 eb e eb
H14 VSS12 VSSQ3 N1

te ot
e K14 VSS13
ot t ot t ot t
ot t
B R1 B

NNo NNo NNo NNo

VSS14 VSSQ5 U1
VSSQ6 H2
+1.35VGS G1 VSSQ7 K2
VDD1 L1 VSSQ8 A3
VDD2 VSSQ9 +1.35VGS
G4 C3
FBA_VREFC L4 VDD3 VSSQ10 E3
RV2708 C5 VDD4 VSSQ11 N3 CV2732 CV2733 CV2729 CV2730
VDD5 VSSQ12 CV2731
R5 R3

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

4.3U_0402_4V6-M
931_0402_1% VDD6 VSSQ13
C10 U3
mm mm mm mm

OPT_3T@
2 1 VDD7 VSSQ14 1 1 1 1
c.o co o co o co o

OPT_N3T@

OPT_N3T@

OPT_N3T@

OPT_N3T@
R10 C4

co OPT@

3
VDD8 VSSQ15
.s s.s.c s.s.c s.s.c
D11 R4
s G11 VDD9 VSSQ16 F5
i c i c ici c L11 VDD10
i ci c
VSSQ17 M5
i ci c

4
at at at at
2 2 2 2

at at at at
P11 VDD11 VSSQ18 F10
1

D QV2701
G14 VDD12 VSSQ19 M10

em m em m em m em m
2 VDD13 VSSQ20
26 GPIO10_FBVREF_ALTV LBSS139WT1G_SC70-3 L14 C11

h e G
h e VDD14
h e VSSQ21 R11
h e h
Sc ch Sc ch Sc ch Sc ch Sc
OPT@ VSSQ22

Sc
1

S A12
3

RV2709

kS kS kS kS
VSSQ23 C12

ok ok ok ok k k
VSSQ24
oo
100K_0402_5% E12

o o o o o o VSSQ25
o o
bo
N12
b bo o o o bo
OPT@

eb eb eb
VSSQ26

eb eb eb
R12

te e
2

VSSQ27
e te
ot t ot t ot t ot
170-BALL U12

ot
VSSQ28 H13

NNo NNo NNo o

VSSQ29
NN
SGRAM GDDR5 K13
VSSQ30 A14
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36

mm mm
@ H5GQ1H24AFR-T2L_BGA170
mm mm
co o c.o
co co o co o
c s.s.c c s .s
c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at atat
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

NN 2016/08/20 GPU_GDDR5_Rank0_[31:0]
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 27 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
upper 32 bits NN NN NN NN

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c MF=0 No Mirror c s.s.c c s.s.c
i c i c i c i c
21,27 FBA_D[0..63]

FBA_CMD[31..0] t t
i i i i
21,27
aa at
at at at atat
em m em m mm em m
UM2801
21,27
h e
FBA_EDC[7..0]
h e h e
MF=0e h e h
h
c cFBA_DBI[7..0] ch ch A4 ch
Sc Sc Sc ScSc
MF=0 MF=1 MF=1

S21,27
kS kS kS kS
D D

ok ok ok ok k k
FBA_D32

o o o o
FBA_EDC4 C2
o o
DQ24 DQ0 A2 FBA_D33
o o oo
b bo b bo o o bobo
FBA_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34
b b eb eb
R13 EDC1 EDC2 DQ26 DQ2 B2
te e e e
FBA_EDC6 FBA_D35
e t e t e BYTE4
te
ot o ot t ot t ot
FBA_EDC7 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D36
o oEDC0
NNo o
EDC3 DQ28 DQ4 E2 FBA_D37
NN FBA_DBI4 D2
N N DQ29
DQ30
DQ5 F4
DQ6 F2
FBA_D38
FBA_D39
NN
FBA_DBI5 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D40
FBA_DBI6 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D41
FBA_DBI7 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D42
DBI3# DBI0# DQ18 DQ10 B13 FBA_D43
FBA_CLK1 DQ19 DQ11 FBA_D44
BYTE5 +1.35VGS
J12 E11
FBA_CLK1# CK DQ20 DQ12 FBA_D45 Close to VRAM
mm mm mm mm
J11 E13

co co o co o co
FBA_CMD30 CK# DQ21 DQ13 FBA_D46

c2 o o
J3 F11
OPT@

s.s.c FBA_CMD18 s.s.c s.s.c

CKE# DQ22 DQ14
s1 .OPT@
FBA_CLK1 RV2801 1 FBA_D47

s. 2 40.2_0402_1%
40.2_0402_1% F13 CV2802 CV2807 CV2808 CV2803 CV2804 CV2805 CV2806
21 FBA_CLK1 DQ23 DQ15 FBA_D48
U11
i c i c
FBA_CLK1# RV2802
i ci c i c c
DQ8
i
DQ16 FBA_D49
i c i c
at at at a1t
H11 U13
t at at t

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
21 FBA_CLK1# FBA_CMD20 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D50

10U 6.3V M X5R 0402

K10 T11
a 1 FBA_CMD19 K11 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D51 1 1 1 1 a 1 1

OPT_NS@

OPT_NS@
T13
mm mm em mm
em

OPT@

OPT@

OPT_NS@

OPT_NS@

OPT_NS@
CV2801 FBA_CMD17 H10 BA2/A4 BA0/A2 DQ11 DQ19 FBA_D52

he e he e 2
N11

he e
0.01U_0201_10V6K BYTE6
h h ch
BA3/A3 BA1/A5 DQ12 DQ20 FBA_D53
h h 2 ch2
N13
c c c c Sc c c
Sc
OPT@ DQ13 DQ21 M11 FBA_D54

kS SS SS kS
2 2 2 2 2

kS S
FBA_CMD22 DQ14 DQ22 FBA_D55

ok k ok
K4 M13

ok o ok ok k
H5 A8/A7 A10/A0 DQ15 DQ23

oo o
FBA_CMD27 FBA_D56

oo
U4
o o
FBA_CMD26 H4 A9/A1
A8/A7 o o
A11/A6 DQ0 DQ24 U2 FBA_D57
o o o o o
b b b b K5 A10/A0
bb DQ1 DQ25
eb eb
eb eb
FBA_CMD23 T4 FBA_D58

te e e e J5 A11/A6 e e
A9/A1 DQ2 DQ26
t t ot t ot t
FBA_CMD25 FBA_D59

ot t t
T2
oo oo
A12/RFU/NC DQ3 DQ27 FBA_D60

NNo CV2814 CV2809 NNo

BYTE7 N4
NN U5 N
DQ4 DQ28 FBA_D61
N
A5 N2 CV2810 CV2811 CV2812 CV2813 CV2815
VPP/NC1 DQ5 DQ29 M4 FBA_D62
VPP/NC2 DQ6 DQ30 FBA_D63

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
M2
DQ7 DQ31

OPT_NS@
+1.35VGS
1 1 1 1 1 1 1

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
RV28031 OPT@ 2 1K_1%_0201 J1

OPT@
RV28041 OPT@ 2 1K_1%_0201 FBA_SEN1 J10 MF
RV2805 1 2 121_0402_1% OPT@ J13 SEN B1
ZQ VDDQ1 D1 2 2 2 2 2 2 2
C
mm m m mm VDDQ2 F1 mm C

c.o
co c.o
co c.o
co c.o
co
FBA_CMD24 J4 VDDQ3 M1

s .s s .s FBA_CMD28 G3 ABI#
s .s VDDQ4 P1
s .s
icic cic icic icic
FBA_CMD16 RAS# CAS# VDDQ5
it
G12 T1

at t at at
CS# WE# VDDQ6

at at at
FBA_CMD31 L3 G2
aa FBA_CMD21 L12 CAS# RAS# VDDQ7 L2
mm em mm m
em m
WE# CS# VDDQ8 B3
e e e e VDDQ9 D3 e
Around
e
VRAM
chch
h h ch
ch ch ch ch
VDDQ10

ScSc 21 c
F3

kS kS kS kS
FBA_WCLK45# VDDQ11

kS kS kS kS
D5 H3 CV2816 CV2817 CV2818 CV2819 CV2820 CV2821 CV2822

ok
FBA_WCLK45#

ok
FBA_WCLK45 D4 WCK01# WCK23# VDDQ12 K3
o o
21 FBA_WCLK45 WCK01 WCK23
o o VDDQ13
o o o o

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
bo o bo o o
M3
o bb o FBA_WCLK67#
o VDDQ14
bb o o
eb
P5 P3 1 1 1 1 1 1 1

eb eb eb

OPT@

OPT@

OPT@

OPT@
21 FBA_WCLK67#
te e te e
FBA_WCLK67 P4 WCK23# WCK01# VDDQ15
e e
T3
t ot ot t
ot t t t

OPT_NS@

OPT_NS@

OPT_NS@
21 FBA_WCLK67 WCK23 WCK01 VDDQ16
oo o
E5

NN FBA_VREFC
A10 NN
o VDDQ17
VDDQ18
N5
E10 NN o 2 2 2 2 2 2 2
NNo
U10 VREFD1 VDDQ19 N10
FBA_VREFC J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12
1 VDDQ22
CV2823 F12
820P_0402_25V7 VDDQ23 H12
FBA_CMD29 J2 VDDQ24 K12
OPT@
mm mm mm mm
2 RESET# VDDQ25 M12

co o co o co o co o
VDDQ26 P12

s.s.c s.s.c s.s.c s.s.c

VDDQ27 T12
VDDQ28
c c c c
G13
i ic i ic i ic VDDQ29
i ic
at at at at
H1 L13

at at at at
K1 VSS1 VDDQ30 B14
VSS2 VDDQ31
mm mm mm mm
B5 D14
e e e e
VSS3 VDDQ32
e e e e
G5 F14

chch chch chch ch ch ch

L5 VSS4 VDDQ33 M14 +1.35VGS
VSS5 VDDQ34
c
kS kS kS kS kS
T5 P14

kS kS kS kS kS
B10 VSS6 VDDQ35 T14
o o o CV2824o CV2825 o
VSS7 VDDQ36
o o o o o
D10

bo oo oo bo oo
CV2828
o o
G10 VSS8 CV2826 CV2827

eb eb eb eb b eb
b
e eb
L10 VSS9 A1
te ot t VSS11 t te
ot
e
ot t
VSS10 VSSQ1 C1

ot t

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
B P10 B
oo
NNo NNo NNo
VSSQ2 E1

4.3U_0402_4V6-M
T10
N
VSS12
N
VSSQ3 N1

OPT_3T@
H14
VSS13 VSSQ4 R1

OPT_N3T@

OPT_N3T@

OPT_NS@

OPT_N3T@
K14 1 1 1 1

3
VSS14 VSSQ5 U1
VSSQ6 H2
+1.35VGS G1 VSSQ7 K2

4
VDD1 VSSQ8 2 2 2 2
L1 A3
G4 VDD2 VSSQ9 C3
L4 VDD3 VSSQ10 E3
mm mm VDD4
mm VSSQ11
mm
co o co o co o co o
C5 N3
VDD5 VSSQ12

s.s.c s.s.c s.s.c s.s.c

R5 R3
C10 VDD6 VSSQ13 U3
i ci c ici c R10 VDD7
i ci c
VSSQ14 C4
i ci c
atat atat atat at at
D11 VDD8 VSSQ15 R4
G11 VDD9 VSSQ16 F5

em m em m em m em m
L11 VDD10 VSSQ17 M5

h e h e P11 VDD11
h e VSSQ18 F10 +1.35VGS
h e h
Sc ch Sc ch Sc ch Sc ch Sc
VDD12 VSSQ19

Sc
G14 M10

kS kS kS kSCV2831 CV2832
L14 VDD13 VSSQ20 C11

ok ok ok CV2829 k k k
VDD14 VSSQ21
oo oo
R11

o o o o o o VSSQ22
o
CV2830 CV2833

bo
A12
b bo eb
o
eb
o b bo bo
VSSQ23

eb eb
C12

te e e
VSSQ24
e e te
ot t ot t ot
E12

ot ot o t

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

4.3U_0402_4V6-M
VSSQ25 N12

NNo NNo o

OPT_NS@
VSSQ26
NN NN
1 1 1 1

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
R12

3
170-BALL VSSQ27 U12
VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13

4
VSSQ30 2 2 2 2
A14
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
mm mm mm mm
VSSQ34 R14

co o co o co o co o
VSSQ35 U14

s.s.c s.s.c s.s.c s.s.c

VSSQ36

icic i ci c
@
i c i
H5GQ1H24AFR-T2L_BGA170
c i ci c
atat atat at at atat
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

NN 2016/08/20 GPU_GDDR5_Rank0_[64:32]
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 28 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN

+3.3V_1.8V_AON
X76
mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c GPU
c s.s.c
FB Memory (GDDR5) RAMCFG[4:0] STRAP2
c s.s.c
STRAP1 STRAP0
i i c i i c i
t ti c i i c
at
at at
at atat

2
RV2901 RV2902 RV2903 aK4G80325FB-HC28
a
em em em em
Samsung 8Gb 0(0x0000) L L L
e m 100K_0402_5% 100K_0402_5% 100K_0402_5%
e m e m e m
h h h h h h
ch h L c chH
@ @ @
c c Sc c c ScSc
8Gb Micron 8Gb MT51J256M32HF-70:A 1(0x0001) L
S S kS kS
kS kS kS

1
D D

k
oo k ok k k
oo L oo H oo
STRAP0
25 STRAP0
o ooHynix 8Gb
bo o o o o
b bo bobo
STRAP1 H5GC8H24MJR-R0C 2(0x0010) L
25 STRAP1

eb ebeb
b b
STRAP2

te e e e
25 STRAP2

ot ot t ot te ot te ot te
NNo NN o NN o NN o

2
RV2904 RV2905 RV2906
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @

mm mm mm mm
1

1
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at
at atat
h emem h emem h em em h emem
Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o okok o okok o o o k
bb o o o o o
te e
+3.3V_1.8V_AON
eb eb ete
bb
te
bb
te ebeb
ot ot t ot STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL
oPCIE_CFG VGA_DEVICE
ot t
NNo NNo NNo NNo
L L L 0 0 0 0
2

2
RV2907 RV2908 RV2909
100K_0402_5% 100K_0402_5% 100K_0402_5% 1: SMB_ALT_ADDR ENABLE
@ @ @
C
mm mm 0: SMB_ALT_ADDR DISABLE mm mm C

c.o c.o c.o c.o

1

s .s co s .s co s .s co s .s co
tit cic icic
1: DEVID_SEL REBRAND
icic icic
at at at
STRAP3

at at at
25 STRAP3
25 STRAP4 aSTRAP4
a 0: DEVID_SEL ORIGNAL
mm mm mm mm
25 STRAP5 STRAP5

e e e e e e e e
ch hh 1: PCIE_CFG LOW POWERh h
ch Sc Sc ch
ch ch
kSkS Sc Sc kSkS kSkS
c
2

RV2912 k k
ok ok
0: PCIE_CFG HIGH POWER
o o
RV2910 RV2911
o o o o o o
bo o bo@ o
o o bo
bo
o o
100K_0402_5% 100K_0402_5% 100K_0402_5%
b b b b ENABLE eb eb
@ @
e
t te e te e
1: VGA_DEVICE
te ete
ot ot0: VGA_DEVICE ot ot t
1

o NN o NNo
DISABLE
NN o NNo

Strap5 is NC pin on N16

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i ic i ic i ic
at
at at
at at
at at
at
e mm e mm e mm e mm
e e e e
chch chch chch ch
DEVID_SEL ch chc
o kS kS o kSkS o kSkS o kSkS o kSkS
o o o 0 o (Default) o
bo o
eb
oo
eb
oo
eb
oo boo
te eb eb eb eb 1 e eb
ot ot t ot t ot t ot t
B B

NNo NNo NNo NNo

+3V_1.8VGS +3.3V_1.8V_AON PCIE_CFG
ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE 0 (Default)
2
2

mm mm mm mm
RV2914
RV2913

co o co o co o SOR0/1/2/3 DISABLE co o
0_0402_5%
0_0402_5% 1 0000
s.s.c s.s.c s.s.c s.s.c
OPTN17@ N17S-G1 H H M
OPTN16@

c c c c c c c c
1

i i i i i i i i
1

atat
t
aa t N16S-GTR atat SMBUS_ALT_ADDR at at
eme m
he
mm
e eme m em e m
2

h h h h
Sc ch c h
Sc ch Sc
h
Sc
0 0x9E (Default)
RV2915 RV2916 RV2917
c Sc Sc
kS kS kS kS
100K_0402_5% 100K_0402_5% 100K_0402_5%

ok oo ok o1 k k k
oo k
@ @ @

o o oo o o o o 0x9C (Multi-GPU usage)

o o o bobo
1

b b b b eb eb
te e ee eb eb ete
ot ot t ot t ot t ot
NNo NNo NNo o
ROM_SI VGA_DEVICE
25
25
ROM_SI
ROM_SO
ROM_SO
ROM_SCLK
NN
25 ROM_SCLK 0 3D Device (Class Code 302h)
2

RV2918 RV2919 RV2920 1 VGA Device (Default)

100K_0402_5% 100K_0402_5% 100K_0402_5%
mm @ @ @
mm mm mm
co o co o co o co o
s.s.c s.s.c s.s.c s.s.c
1

icic i ci c i c i c i ci c
atat atat at at at at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

NN 2016/08/20 GPU_MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 29 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN

+5VS
+3VS J1
mm mm mm mm
co o co o co o co o
+3VL 1
1

s.s.c s.s.c s.s.c s.s.c

2
BEEP 3 2

ici c i c i c i ci c i ci c 4 3

atat at
at at t NOVO# atat
RA3001 1 2 1K_0402_5% CA3001 1 2 0.1U_6.3V_K_X5R_0201 5 4

NOVO#a
R3001 1 2 200_0402_1% NOVO_BTN# 6 5

em m em m em m em m
44 EC_MUTE# 6
7

h e DA3001
h e h e 44 EC_MUTE#
h e 7
h
44 h ch h ch
8
cc Sc c c Sc ScSc
3 USB20_N8 9 8
S S
EC_BEEP
kS
kS kS kS
D 9 USB20_N8 USB20_P8 9 D
10

okok ok ok k k
9 USB20_P8 10

oo oo
1 RA3002 1 2 1K_0402_5% CA3002 1 2 0.1U_6.3V_K_X5R_0201 BEEP 11
o oo o
bo o o bo
11

bo b bo o bo
12
b eb
33 DMIC_CLK 12
2
b eb
13

te e e e
8 PCH_BEEP 33 DMIC_DATA
e e te te
13
t ot ot t ot
14

ot o t RA3003
14

2
NNo 10K_0402_5% o NNo o
BAT54CW_SOT323-3 15
6 HDA_BITCLK_AUDIO 15
@
NN 6 HDA_SDOUT_AUDIO
6 HDA_SDIN0
16
17 16
17
NN
@ 18
6 HDA_SYNC_AUDIO 18
RA3004 1 2 0_0402_5% @ DVDD_IO 19

1
20 19
+1.8VS 20
21
22 GND1
GND2
mm mm mm mm
HIGHS_FC5AF201-1151H

co o co o co o co o
ME@

c s.s.c c s.s.c c s.s.c c s.s.c

i i c i i c i i c i i c
at at atat atat atat
emem emem emem emem
CPU HDA BUS power 1.8VALW
h h h h h h h h ch
ScSc kS
cc ScSc S cc
kS Sc
+5VS
S S
o okok o o ok
DVDD_IO
o okok +3VS
+3VLo
ok o1k
J2
o o o k
b o +1.8VALW
b o o o o
eb b eb
1mA
b b eb b 2 1
eb
te e ee
ot t DVDD_IO ot t
BEEP te e
ot t
ot o ot
3 2

NNo NNo NNo

RA3006 1 2 0_5%_0603 @ 4 3
+3VALW
NNOVO_BTN#
N 5 4
6 5
6

2
EC_MUTE# 7
@ RA3007 8 7
RA3005 1 2 0.01_0603_1% 0_0402_5% USB20_N8 9 8
@ USB20_P8 10 9
11 10

1
11
mm mm mm
DMIC_CLK
C 12
mm C

c.o c.o c.o c.o

DMIC_DATA 12

co co co co
13
.s .s .s .s
14 13
s s s HDA_BITCLK_AUDIO 15 s 14
icic icic icic HDA_SDOUT_AUDIO
icic 15

at at at at
16

at at at at
HDA_BITCLK_AUDIO HDA_SDIN0 17 16
HDA_SYNC_AUDIO 17
mm mm mm mm
18
e e e e
18
e e e e
DVDD_IO
19

ch ch hh ch ch
19

ch ch h 25 20

Sc
1

Sc
+1.8VS
cGND1 21 20
c
kS kS kS kS
CA3003 ON/OFF

kS kS kS GND2 kS
44,45 ON/OFF PWR_LED1# 21
k
33P_0402_50V8J 2622
o o
EMC_NS@
o o o o k 44 PWR_LED1# PWR_LED2#
o o
23 22
o o
bo bo bo o o
44 PWR_LED2# 23
o bo bo o o
2 24

eb eb
+3VALW

eb eb eb
24

te ot
e te ot
ete ot t ot t
ot
HIGHSTAR_FC5AF241-2931H

NN o NN o NNo
ME@
NNo

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i ic i ic i ic
at
at at
at at
at at
at
e mm e mm e mm e mm
e e e e
chch chch chch
+5VS
ch h ch
kS kS kSkS kSkS k S Sc kSkS
c
1 k
+3VS J3
o o o o o o o o o o
bo oo oo oo 2 2 oo
+3VL
o 1

te eb eb eb eb eb eb eb 3 b
e eb
ot t ot t ot ot t
BEEP

ot ot
B
4 3 B

NNo NNo NNo

5 4
NNOVO_BTN#
N 6 5
EC_MUTE# 7 6
8 7
USB20_N8 9 8
USB20_P8 10 9
11 10
DMIC_CLK 12 11

mm mm mm mm
DMIC_DATA 13 12

co o co o co o co o
14 13

s.s.c s.s.c s.s.c s.s.c

HDA_BITCLK_AUDIO 15 14
HDA_SDOUT_AUDIO 15
c c c c
16
i i c i i c i i c i i c 16

at at at at
HDA_SDIN0

at at at at
17
HDA_SYNC_AUDIO 18 17
18

em m em m em m em m
DVDD_IO 19
19
h e h e h e +1.8VS
h e 20
h
ch ch c ch ch
21 20

Sc Sc Sc Sc
ON/OFF

Sc
PWR_LED1# 21
S
22

ok kS ok kS ok
S
ok kS k
PWR_LED2# 22

ok k
23

o o o o o 24 23
oo
bo o bo
+3VALW

b bo o bo o bo
25 24

ebeb eb eb
25

te e e
26
e e te
ot t t ot t ot
+1.8VS 26

ot o t
27

NNo NNo NNo o

28 27
NN
+3VS 28
32 29
31 30 29 GND2
+5VS 30 GND1

HIGHS_FC5AF301-2931H
ME@

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at atat
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date

NN 2016/08/20 CODEC_RTS5199
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Sheet
Friday, December 06, 2019 30 of 60

omm omm omm omm

5 4 3 2 1
 bb bb bb bb bb
te e e e e
5 4 3 2 1
e te te te te
ot oto oto oto oto
NN NN NN NN

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat at
at at
at atat
h em
e m
h eme m
h em
e m
h em
e m
h
Sc ch Sc ch Sc ch Sc ch ScSc
kS kS kS kS
D D

o ok
o o oko o oko o oko
k
oo k
b bo eb
o
eb
o
eb
o bobo
te e eb eb eb ete
ot ot t ot t ot t ot
NNo NNo NNo NN o

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat atat atat
h emem h emem h emem h emem
Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o okok o okok o o o k
bb o o o o o
te e eb eb eb eb eb eb ebeb
ot ot t ot t ot t ot t
NNo NNo NNo NNo

C
mm mm mm mm C

c.o
.s co c.o
.s co c.o
.s co c.o
.s co
s s s s
icic icic icic icic
at
at at
at at
at at
at
e mm e mm e mm e mm
e e e e
chch chch ch
ch ch
ch chc
o kSkS o kSkS o kS
kS o kSkS o kSkS
o o o o o
bo o bobo bobo bo
bo eb
o o
te eb ete ete ete eb
ot oto oto oto ot t
NN NN NN NNo

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i ic i ic i ic
at
at at
at at
at at
at
e mm e mm e mm e mm
e e e e
chch chch chch ch
ch chc
o kS kS o kSkS o kSkS o kSkS o kSkS
o o o o o
bo o
eb
oo
eb
oo
eb
oo boo
te eb eb eb eb e eb
ot ot t ot t ot t ot t
B B

NNo NNo NNo NNo

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i i c i i c i i c i i c
atat atat atat atat
h em
e m
h eme m
h eme m
h eme m
h
Sc ch Sc ch Sc ch Sc ch ScSc
ok
o kS oko kS oko kS oko kS k
oo k
o
b bo o o o o o o bo
ebeb eb eb eb eb bo
te e
ot t ot t ot t ot
ete
ot NNo NNo NNo NN o

mm mm mm mm
co o co o co o co o
c s.s.c c s.s.c c s.s.c c s.s.c
i ic i i c i i c i i c
atat atat at at at at
A A

h emem h emem h emem h em em

Sc
h
Sc
h
Sc
h
Sc
h ch
Sc Sc Sc Sc kS Sc
o okok o okok o ok ok o okok o o o k
bb o o o o o
te e eb eb ebeb eb eb eb eb
ot ot t ot t ot ot ot t
NNo NNo NNo
Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date

NN 2014/07/01
Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019Sheet 31 of 60

omm omm omm omm

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

TPM
Issued Date 2012/07/01 Deciphered Date 2014/07/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 32 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS
LCD POWER CIRCUIT CMOS Camera
+3VS +3VS_EDP
FI3301 W=40mils
CG3301 +LCDVDD_CON
1
W=60mils 1 2
UG3301

0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

10U 6.3V M X5R 0402

0.047U_0402_16V7K
5 1 1 1A_32V_ERBRD1R00X

CI3301
D 2 IN OUT D

CI3302

CI3303
1 2

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201

33P_0402_50V8J
2
GND
PCH_ENVDD 1 1 1 2

CG3302

CG3303

CG3304
4 3
4 PCH_ENVDD EN OCB 2 1
SY6288C20AAC_SOT23-5 @ @
2 2 2
@ @ CPU_EDP_TX0+ CG3305 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX0+
4 CPU_EDP_TX0+
CPU_EDP_TX0- CG3306 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX0-
4 CPU_EDP_TX0-
EMI request
For RF CPU_EDP_TX1+ EDP_TX1+
CG3307 1 2 0.1U_6.3V_K_X5R_0201
V9B+ +LEDVDD 4 CPU_EDP_TX1+
FG3301 CPU_EDP_TX1- CG3308 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX1-
4 CPU_EDP_TX1-
1 2

0.47U_25V_K_X5R_0603

2200P_25V_K_X7R_0402
3A_32V_ERBRD3R00X
CG3309 CPU_EDP_AUX# EDP_AUX#

CG3310
1 1 CG3311 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_EDP_AUX#
CPU_EDP_AUX CG3312 1 2 0.1U_6.3V_K_X5R_0201 EDP_AUX JEDP1
4 CPU_EDP_AUX 1
2 2 +LEDVDD 1
2
3 2
4 3
5 4
EDP_TX0+ 6 5
EDP_TX0- 7 6
8 7
EMI Request 8
Camera 1 2 0_0402_5% @
EDP_TX1+
EDP_TX1-
9
10 9
RI3301
11 10
EDP_AUX 12 11
LI3301 EDP_AUX# 13 12
+3VS USB20_N5 1 2 USB20_N5_R 14 13
9 USB20_N5 1 2 15 14
DISPOFF#
C INVT_PWM 16 15 C
16
2

USB20_P5 4 3 USB20_P5_R CPU_EDP_HPD 17

9 USB20_P5 4 3 4 CPU_EDP_HPD 17
RG3302 +LCDVDD_CON
18
PCH_ENBKL RG3303 1 @ 2 0_0402_5% 4.7K_0402_5% EXC24CH900U_4P 19 18
4,44 PCH_ENBKL 19
@ @ 20
21 20
1

RI3302 1 2 0_0402_5% @ DMIC_CLK 22 21

@ 30 DMIC_CLK DMIC_DATA 22
BKOFF# RG3304 1 2 0_0402_5% DISPOFF# 23
44 BKOFF# 30 DMIC_DATA 24 23
+3VS_EDP 24
25
26 25
27 26
+3VS USB20_P5_R 28 27
USB20_N5_R 29 28
30 29
EMI request 30
2

31
RG3305 32 G1
1K_0402_5% DMIC_DATA DMIC_CLK DISPOFF# INVT_PWM G2
@ DRAPH_FC5AF301-3181H
1 1 1 1 ME@
@
1

RG3306 1 2 0_0402_5% INVT_PWM

4 PCH_EDP_PWM
CG3410 CG3313 CG3314 CG3315
1

100P_0402_50V8J 100P_0402_50V8J 470P_0402_50V7K 470P_0402_50V7K

2 @ 2 @ 2 @ 2 @
RG3307
100K_0402_5%
2

B B

Touch Screen

+5VS +5VS_TS

RG3310 1 @ 2 0_0402_5%
RG3309 1 2 0_0402_5% @ USB20_P6_CONN
+5VS_TS +3VS
1
CG3316
USB20_N6_CONN 0.1u_0201_10V6K
AZ5725-01F.R7GR_DFN1006P2X2

TS@
AZ5423-01F.R7GR_DFN1006P2E2

AZ5423-01F.R7GR_DFN1006P2E2
1

LG3301 RG3308 1 2 0_0402_5% @ 2 +5VS_TS

USB20_P6 USB20_P6_CONN
EMC_NS@

4 3
1

9 USB20_P6 4 3 JTS1
DG3301

EMC_NS@

DG3302

EMC_NS@

DG3303

1
USB20_N6 1 2 USB20_N6_CONN RG3311 1 2 0_0402_5% @ TS_RS 2 1
9 USB20_N6 1 2 44 EC_TS_ON 3 2
USB20_N6_CONN 3
2

EXC24CH900U_4P 4
EMC_NS@ USB20_P6_CONN 5 4
2

6 5
6 7
RG3312 1 2 0_0402_5% @ GND1 8
GND2
HIGHS_WS83061-S0171-HF
ME@
For EMI For ESD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 eDP/CAMERA.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 33 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS

2
G
CPU_HDMI_TXP2 CG3401 1 2 0.1U_6.3V_K_X5R_0201 HDMI_TX2_DP_C
4 CPU_HDMI_TXP2 CPU_HDMI_TXN2 HDMI_TX2_DN_C
CG3402 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_TXN2
CPU_HDMI_TXP1 CG3403 1 2 0.1U_6.3V_K_X5R_0201 HDMI_TX1_DP_C PCH_HDMI_DDC_DATA 1 6 DDPB_DATA_U

S
4 CPU_HDMI_TXP1 CPU_HDMI_TXN1 HDMI_TX1_DN_C 4 PCH_HDMI_DDC_DATA

D
CG3404 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_TXN1 QG3401A
2N7002KDWH_SOT363-6
CPU_HDMI_TXP0 CG3405 1 2 0.1U_6.3V_K_X5R_0201 HDMI_TX0_DP_C
4 CPU_HDMI_TXP0 CPU_HDMI_TXN0 HDMI_TX0_DN_C
CG3406 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_TXN0

5
G
D CPU_HDMI_CLKP HDMI_CLK_DP_C D
CG3407 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_CLKP CPU_HDMI_CLKN HDMI_CLK_DN_C
CG3408 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_CLKN
PCH_HDMI_DDC_CLK 4 3 DDPB_CLK_U

S
4 PCH_HDMI_DDC_CLK

D
QG3401B
2N7002KDWH_SOT363-6

+3VS
Need to change about 470Ohm 5%-575412 Page115 Rev0.8 RG3425 2 @ 1 0_0402_5%
HDMI_TX0_DP_C RG3401 1 2 470_0402_5%
+1.8VALW
HDMI_TX0_DN_C RG3402 1 2 470_0402_5%
HDMI_TX1_DP_C RG3403 1 2 470_0402_5% RG3405 1 2 0_0402_5% @
HDMI_TX1_DN_C RG3404 1 2 470_0402_5%

2
HDMI_TX2_DP_C RG3406 1 2 470_0402_5% RG3408
1M_0402_5%

2
HDMI_TX2_DN_C RG3407 1 2 470_0402_5%
QG3403

1
HDMI_CLK_DP_C RG3409 1 2 470_0402_5%
CPU_HDMI_HPD 3 1 HDMI_DET
HDMI_CLK_DN_C 4 CPU_HDMI_HPD
RG3410 1 2 470_0402_5%

2
LSI1012XT1G_SC-89-3
1

D RG3411
+3VS
2 20K_0402_5%
QG3404 Maybe 2N7002 is ok?
G
L2N7002KWT1G_SOT323-3

1
S
3

1 2
C RG3412 C
100K_0402_5%
@

@ HDMI_TX0_DP_CON
RG3413 1 2 0_0402_5%

F1 use 1.1A
1

LG3401
HDMI_TX0_DP_C 4 3 RG3414
4 3 +5VS_HDMI_F +5VS_HDMI
DG3401 +5VS
270_0402_1%
EMC_HDMI_R@ HDMI_CLK_DP_CON 1 1 10 9 HDMI_CLK_DP_CON
HDMI_TX0_DN_C 1 2 FG3401
2

1 2 HDMI_CLK_DN_CON 2 2 8 HDMI_CLK_DN_CON 1 3 1 2
9

S
EXC24CH900U_4P
EMC_HDMI@ HDMI_TX0_DP_CON 4 4 7 7 HDMI_TX0_DP_CON 1.1A_8V_1206L110THYR

G
2
RG3415 1 @ 2 0_0402_5% HDMI_TX0_DN_CON HDMI_TX0_DN_CON 5 5 6 HDMI_TX0_DN_CON QG3402
6 1
LP2301ALT1G_SOT23-3 CG3409
3 3 0.1U_6.3V_K_X5R_0201
46 SUSP
8 2

AZ1045-04F_DFN2510P10E-10-9
RG3416 1 2 0_0402_5% @ HDMI_TX1_DP_CON EMC_NS@

LG3402
2

HDMI_TX1_DP_C 4 3 DG3402
4 3 RG3417 HDMI_TX1_DN_CON 1 1 10 9 HDMI_TX1_DN_CON
270_0402_1%
HDMI_TX1_DN_C 1 2 EMC_HDMI_R@ HDMI_TX1_DP_CON 2 2 8 HDMI_TX1_DP_CON
B 1 2 9 B
+5VS_HDMI
1

EXC24CH900U_4P HDMI_TX2_DN_CON HDMI_TX2_DN_CON

4 4 7 7
EMC_HDMI@
HDMI_TX2_DP_CON 5 5 6 HDMI_TX2_DP_CON
RG3418 1 2 0_0402_5% @ HDMI_TX1_DN_CON 6

2
1
3 3 RPG1
2.2K_0404_4P2R_5%
8 +5VS_HDMI
HDMI_TX2_DP_CON JHDMI1
RG3419 1 2 0_0402_5% @

3
4
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ 18 15 DDPB_CLK_U
LG3403 +5V_Power SCL 16 DDPB_DATA_U
SDA
2

HDMI_TX2_DP_C 4 3
4 3 RG3420 HDMI_TX0_DP_CON 7
HDMI_TX0_DN_CON 9 TMDS_Data0+ 13
270_0402_1%
HDMI_TX2_DN_C 1 2 EMC_HDMI_R@ DG3403 HDMI_TX1_DP_CON 4 TMDS_Data0- CEC 17
1 2 HDMI_DET 1 1 HDMI_DET HDMI_TX1_DN_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
10 9 6 19
1

EXC24CH900U_4P HDMI_TX2_DP_CON 1 TMDS_Data1- Hot_Plug_Detect

EMC_HDMI@ DDPB_CLK_U 2 2 8 DDPB_CLK_U HDMI_TX2_DN_CON 3 TMDS_Data2+
9
TMDS_Data2-
RG3421 1 2 0_0402_5% @ HDMI_TX2_DN_CON DDPB_DATA_U 4 4 7 DDPB_DATA_U 8 14
7
5 TMDS_Data0_Shield Utility
+5VS_HDMI 5 5 6 +5VS_HDMI 2 TMDS_Data1_Shield
6
TMDS_Data2_Shield
3 3 20
11 GND1 21
8 HDMI_CLK_DP_CON 10 TMDS_Clock_Shield GND2 22
HDMI_CLK_DN_CON 12 TMDS_Clock+ GND3 23
RG3422 1 2 0_0402_5% @ HDMI_CLK_DP_CON TMDS_Clock- GND4
AZ1045-04F_DFN2510P10E-10-9
LG3404 EMC_NS@
2

HDMI_CLK_DP_C 4 3
4 3 ALLTO_C128AF-K1935-L
RG3423 For EMC
270_0402_1% ME@
HDMI_CLK_DN_C 1 2 EMC_HDMI_R@
1 2
1

A EXC24CH900U_4P A
EMC_HDMI@

RG3424 1 2 0_0402_5% @ HDMI_CLK_DN_CON

For EMC

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 34 of 60
5 4 3 2 1
 A B C D E F G H

1 1

2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 35 of 60
A B C D E F G H
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HALL Sensor

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 36 of 60
5 4 3 2 1
 5 4 3 2 1

M.2 SSD
+3VS +3VS_SSD

PJ3701
+3VS_SSD 1 2 Min 3A
JSSD1 1 2

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201
JUMP_43X39

CF3705

CF3706

CF3707

CF3708
1 2
3 GND_1 3.3V_1 4
@ 1 1 1 1
GND_2 3.3V_2

10U 6.3V M X5R 0402

CF3703
0.1U_6.3V_K_X5R_0201
5 6 1 1
9 PCIE_PRX_DTX_N13 PERN3 N/C_2

CF3701
7 8
9 PCIE_PRX_DTX_P13 PERP3 N/C_3 2 2 2 2
9 10
0.22U_0402_10V6K 1 2 CF3702 PCIE_PTX_C_DRX_N13 11 GND_3 DAS/DSS# 12 @ @ @ @
9 PCIE_PTX_DRX_N13 PCIE_PTX_C_DRX_P13 PETN3 3.3V_3 2 2@
0.22U_0402_10V6K 1 2 CF3704 13 14
D 9 PCIE_PTX_DRX_P13 PETP3 3.3V_4 D
15 16
17 GND_4 3.3V_5 18
9 PCIE_PRX_DTX_N14 PERN2 3.3V_6
19 20
9 PCIE_PRX_DTX_P14 PERP2 N/C_4
21 22
0.22U_0402_10V6K 1 2 CF3709 PCIE_PTX_C_DRX_N14 23 GND_5 N/C_5 24
9 PCIE_PTX_DRX_N14 PCIE_PTX_C_DRX_P14 PETN2 N/C_6
9 PCIE_PTX_DRX_P14 0.22U_0402_10V6K 1 2 CF3710 25 26
PETP2 N/C_7

1
27 28
29 GND_6 N/C_8 30 RF3702
9 PCIE_PRX_DTX_N15 PERN1 N/C_9 10K_0402_5%
31 32
9 PCIE_PRX_DTX_P15 PERP1 N/C_10 +3VS_SSD
33 34 @
0.22U_0402_10V6K 1 2 CF3711 PCIE_PTX_C_DRX_N15 35 GND_7 N/C_11 36
9 PCIE_PTX_DRX_N15

2
0.22U_0402_10V6K 1 2 CF3712 PCIE_PTX_C_DRX_P15 37 PETN1 N/C_12 38 PCH_SATA_DEVSLP
9 PCIE_PTX_DRX_P15 PETP1 DEVSLP PCH_SATA_DEVSLP 9

1
39 40
41 GND_8 N/C_13 42 +3VS_SSD RF3704
9 PCIE_PRX_DTX_P16 PERN0/SATA-B+ N/C_14 SSD_PCIE_DET#
43 44 100K_0402_5%
9 PCIE_PRX_DTX_N16 45 PERP0/SATA-B- N/C_15 46 SSD_PCIE_DET# 9
@
GND_9 N/C_16

1
0.22U_0402_10V6K 1 2 CF3713 PCIE_PTX_C_DRX_N16 47 48
9 PCIE_PTX_DRX_N16

2
PETN0/SATA-A- N/C_17

3
0.22U_0402_10V6K 1 2 CF3714 PCIE_PTX_C_DRX_P16 49 50 PLT_RST# RF3705 D
9 PCIE_PTX_DRX_P16 PETP0/SATA-A+ PERST# SSD_CLKREQ_Q# PLT_RST# 11,26,40,44
51 52 RF3703 1 2 0_0402_5% @ SSD_CLKREQ# 10 100K_0402_5% 5 QF3701B
53 GND_10 CLKREQ# 54 @ G
10 CLK_PCIE_SSD# REFCLKN PEWAKE#

6
55 56 D 2N7002KDWH_SOT363-6
10 CLK_PCIE_SSD

2
57 REFCLKP N/C_18 58 SSD_DET 2 S

4
GND_11 N/C_19 G @
59 NC NC 60
61 NC NC 62 QF3701A S

1
63 NC NC 64 +3VS_SSD 2N7002KDWH_SOT363-6
65 NC NC 66 @
67 68
SSD_DET 69 N/C_1 SUSCLK 70
71 PEDET 3.3V_7 72
GND_12 3.3V_8

CF3715
10U 6.3V M X5R 0402

CF3716
0.1U_6.3V_K_X5R_0201
73 74
SSD_DET# 75 GND_13 3.3V_9 1 1 SSD_DET RF3707 1 2 0_0402_5% @ SSD_PCIE_DET#
GND_14
SATA-->GND 77 76
PCIE-->NC PEG1 PEG2 2 2@

ARGOS_NASM0-S6701-TS40
C ME@ +3VS_SSD C

RF3706 2 @ 1 100K_0402_5% PCH_SATA_DEVSLP

SATA

SATA_PTX_DRX_P0 RF3709 1 2 0_0201_5% SATA_NRE@ SATA_PTX_DRX_P0_R CF3735 1 2 0.01U_6.3V_K_X7R_0201 SATA_NRE@ SATA_PTX_DRX_P0_CON

9 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 RF3710 1 SATA_PTX_DRX_N0_R SATA_PTX_DRX_N0_CON
2 0_0201_5% SATA_NRE@ CF3736 1 2 0.01U_6.3V_K_X7R_0201 SATA_NRE@
9 SATA_PTX_DRX_N0
+5VS +5VS_HDD
SATA_PRX_DTX_P0 RF3712 1 2 0_0201_5% SATA_NRE@ SATA_PRX_DTX_P0_R CF3738 1 2 0.01U_6.3V_K_X7R_0201 SATA_NRE@ SATA_PRX_DTX_P0_CON
9 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 RF3711 1 SATA_PRX_DTX_N0_R SATA_PRX_DTX_N0_CON
2 0_0201_5% SATA_NRE@ CF3737 1 2 0.01U_6.3V_K_X7R_0201 SATA_NRE@ PJ3708
9 SATA_PRX_DTX_N0 1 2
1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
JUMP_43X39
@

CF3717

CF3718

CF3719
10U 6.3V M X5R 0402

CF3720
10U 6.3V M X5R 0402

CF3721
0.1U_6.3V_K_X5R_0201

CF3722 RF_NS@
33P_0402_50V8J

CF3723 RF_NS@
33P_0402_50V8J
1 1 1 1 1 1 1

2@ 2@ 2@ 2 2 2 2
SATA Redriver +3VS +3VS

B B
2

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
CF3732 @

CF3733 SATA_RE@

RF3713
1/20W_4.7K_5%_0201 1 1
SATA_RE@
1

@ UF1
0.1U_6.3V_K_X5R_0201 2 1 CF3734 7 10 2 2
EN VDD1 20
SATA_PTX_DRX_P0 CF3728 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PTX_DRX_P0_C 1 VDD2
SATA_PTX_DRX_N0 CF3729 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PTX_DRX_N0_C 2 A_INP 6 REXT
A_INN REXT 16 DEW
SATA_PRX_DTX_P0 CF3731 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PRX_DTX_P0_C 5 DEW
SATA_PRX_DTX_N0 CF3730 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PRX_DTX_N0_C 4 B_OUTP 9 A_DE
B_OUTN A_DE 8 B_DE
A_EQ1 17 B_DE
A_EQ2 18 A_EQ1 15 SATA_PTX_DRX_P0_RE CF3725 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PTX_DRX_P0_CON
B_EQ1 19 A_EQ2 A_OUTP 14 SATA_PTX_DRX_N0_RE CF3724 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PTX_DRX_N0_CON
B_EQ2 13 B_EQ1 A_OUTN
B_EQ2 11 SATA_PRX_DTX_P0_RE CF3727 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PRX_DTX_P0_CON
3 B_INP 12 SATA_PRX_DTX_N0_RE CF3726 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PRX_DTX_N0_CON
21 GND1 B_INN
EPAD
PS8527CTQFN20GTR2A2_TQFN20_4X4
SATA_RE@
+5VS_HDD

JHDD1
1
2 1
+3VS 3 2
4 3
SATA_PRX_DTX_P0_CON 5 4
SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3715 A_EQ1 @ 1/20W_4.7K_5%_0201 2 1 RF3723 SATA_PRX_DTX_N0_CON 6 5
7 6
SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3716 A_EQ2 @ 1/20W_4.7K_5%_0201 2 1 RF3724 SATA_PTX_DRX_N0_CON 8 7 12
SATA_PTX_DRX_P0_CON 9 8 GND2
SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3717 B_EQ1 @ 1/20W_4.7K_5%_0201 2 1 RF3725 10 9 11
A
10 GND1 A
SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3718 B_EQ2 @ 1/20W_4.7K_5%_0201 2 1 RF3726
HIGHS_FC5AF101-2931H
SATA_RE@ 4.99K_0402_1% 2 1 RF3719 REXT @ 1/20W_4.7K_5%_0201 2 1 RF3727 ME@

SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3720 DEW @ 1/20W_4.7K_5%_0201 2 1 RF3728

SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3721 A_DE SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3729

SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3722 B_DE SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3730

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF_SSD_1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 37 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 SATA HDD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 38 of 60
5 4 3 2 1
 5 4 3 2 1

SMSC thermal sensor

+3VS

RS3901 1 2 10K_0402_5% SEN_THERM_N Near CPU core Near GPU&VRAM

RS3902 1 2 10K_0402_5% @ SEN_ALERT_N
REMOTE2+ REMOTE1+
D D
1

1
CS3902 C 1 C
+3VS 2 QS3902 CS3901 2 QS3901
100P_0402_50V8J
B MMBT3904WH_SOT323-3 100P_0402_50V8J B MMBT3904WH_SOT323-3
2 E E

3
2
1
CS3903 REMOTE2- REMOTE1-
0.1U_6.3V_K_X5R_0201

2 US3901 +3VALW +3VALW

1 10 EC_SMB_CK0
1 VCC SCL EC_SMB_CK0 26,44

1
CS3904
2200P_0402_50V7K REMOTE1+ 2 9 EC_SMB_DA0 RS3904 RS3903
DP1 SDA EC_SMB_DA0 26,44
13.7K_0402_1% 13.7K_0402_1%
2 REMOTE1- 3 8 SEN_ALERT_N @
DN1 ALERT#

2
REMOTE2+ 4 7 SEN_THERM_N NTC_V2 NTC_V1
DP2 THERM# NTC_V2 44 NTC_V1 44
1

1
CS3905 REMOTE2- 5 6
2200P_0402_50V7K DN2 GND RS3907 RS3906
100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC
2 F75303M_MSOP10 @

2
REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"

C C

FAN Conn

+5VS
+5VS_FAN1 +5VS_FAN1
JFAN1

44 EC_FAN_PWM
1
RS3909 1 2 0_0402_5% @ 1
2
44 EC_FAN_SPEED 2
3
4 3
B 1 1 4 B
CS3907
CS3906 5
0.1U_6.3V_K_X5R_0201 GND1
10U 6.3V M X5R 0402 6
@ GND2
2 @ 2

HIGHS_WS33040-S0351-HF
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Thermal sensor/FAN CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 39 of 60
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
+3V_WLAN
+3VALW_PCH

+3VALW RN4001 1 2 0_5%_0603 @

+3VALW
UN4001

1
RN4002 5 1 RN4003 1 @ 2 0.01_0603_1%
1
75K_0402_5% IN OUT 1

0.01U_0402_25V7K

100U_1206_6.3V6M
@ 2
GND
1

1
WLAN_PWR_EN

CN4001

CN4002
4 3
EN OCB
SY6288C20AAC_SOT23-5

2
1
D @ 2@

1
2 @
11 CNVI_EN#
G QN4001

1
RN4004
RN4005 S 200K_0402_5%

3
75K_0402_5% @ @

2
@ L2N7002KWT1G_SOT323-3
2

+3V_WLAN
RN4006 1 @ 2 0_0402_5%
11 PM_SLP_WLAN#

CN4003
0.1U_6.3V_K_X5R_0201

CN4004
0.01U_0402_25V7K

CN4005
10U 6.3V M X5R 0402
RN4007 1 @ 2 0_0402_5%
44,46 SUSP#
RN4008 1 1 1
200K_0402_5%
@
@ @ @
2

NC if use SUSP# 2 2 2

JWLAN1
1 2
USB20_P10 3 GND1 3.3VAUX1 4
+3V_WLAN 9 USB20_P10 USB20_N10 USB_D+ 3.3VAUX2
5 6
9 USB20_N10 7 USB_D- LED1# 8
CNV_WR_D1N 9 GND2 PCM_CLK/I2S_SCK 10 CNVI_RF_RESET#_R RN4010 1 2 0_0402_5% @
10 CNV_WR_D1N CNV_WR_D1P SDIO_CLK PCM_SYNC/I2S_WS CNVI_RF_RESET# 6
11 12
PCH_WLAN_OFF# 10 CNV_WR_D1P SDIO_CMD PCM_IN/I2S_SD_IN CNVI_MODEM_CLKREQ_R
RN4011 1 2 10K_0402_5% @ 13 14 RN4012 1 2 0_0402_5% @
PCH_BT_OFF# CNV_WR_D0N SDIO_DATA0 PCM_OUT/I2S_SD_OUT CNVI_MODEM_CLKREQ 6
RN4009 1 2 10K_0402_5% @ 15 16
10 CNV_WR_D0N CNV_WR_D0P 17 SDIO_DATA1 LED#2 18
2 2
10 CNV_WR_D0P SDIO_DATA2 GND11
19 20
+1.8VALW CNV_WR_CLKN 21 SDIO_DATA3 UART_WAKE# 22 CNVI_BRI_RSP_R RN4013 1 2 22_0402_5% CNVI@
10 CNV_WR_CLKN CNV_WR_CLKP 23 SDIO_WAKE# UART_RXD CNVI_BRI_RSP 10
CNVI_BRI_DT 10 CNV_WR_CLKP SDIO_RESET#
RN4014 1 2 20K_0402_5% @

RN4015 1 2 20K_0402_5% @ CNVI_RGI_DT

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32 CNVI_RGI_DT
PCIE_PTX_C_DRX_P9 GND3 UART_TXD CNVI_RGI_RSP_R CNVI_RGI_DT 10
35 34 RN4016 1 2 22_0402_5% CNVI@
9 PCIE_PTX_C_DRX_P9 PCIE_PTX_C_DRX_N9 PETP0 UART_CTS CNVI_BRI_DT CNVI_RGI_RSP 10
37 36
9 PCIE_PTX_C_DRX_N9 PETN0 UART_RTS EC_TX_RSVD EC_TX CNVI_BRI_DT 10
39 38 RN4017 1 2 0_0402_5% @
PCIE_PRX_DTX_P9 41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD RN4018 1 2 0_0402_5% @ EC_RX
9 PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 PERP0 VENDOR_DEFINED2
PCIE 43 42
9 PCIE_PRX_DTX_N9 PERN0 VENDOR_DEFINED3
45 44
CLK_PCIE_WLAN 47 GND5 COEX3 46
+3V_WLAN 10 CLK_PCIE_WLAN CLK_PCIE_WLAN# REFCLKP0 COEX2
49 48
+3VS 10 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
51 50 RN4019 1 2 0_0402_5% @
WLAN_CLKREQ_Q# GND6 SUSCLK WLAN_PERST# SUSCLK 10
53 52
CLKREQ0# PERST0#
2

PCIE_WAKE#_WLAN 55 54 BT_OFF# RN4020 1 2 0_0402_5% @

PEWAKE0# W_DISABLE2# PCH_BT_OFF# 9
2

RN4021 57 56 WLAN_OFF# RN4022 1 2 0_0402_5% @

G

GND7 W_DISABLE1# PCH_WLAN_OFF# 8

QN4002 10K_0402_5%

@ CNV_WT_D1N 59 58 WLAN_SMB_DATA RN4023 1 2 0_0402_5% @

10 CNV_WT_D1N EC_RX 44
1

3 1 WLAN_CLKREQ_Q# CNV_WT_D1P 61 RSRVD/PETP1 I2C_DATA 60 WLAN_SMB_CLK RN4024 1 2 0_0402_5% @

10 WLAN_CLKREQ# 10 CNV_WT_D1P RSRVD/PETN1 I2C_CLK EC_TX 44
S

63 62
GND8 ALERT#

1
L2N7002KWT1G_SOT323-3 CNV_WT_D0N 65 64 1
10 CNV_WT_D0N CNV_WT_D0P RSRVD/PERP1 RSRVD T4001
67 66 RN4026
10 CNV_WT_D0P RERVD/PERN1 UIM_SWP/PERST1#
RN4025 1 2 0_0402_5% @ 69 68 100K_0402_5%
CNV_WT_CLKN 71 GND9 UIM_POWER_SNK/CLKREQ1# 70
10 CNV_WT_CLKN CNV_WT_CLKP 73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72
10 CNV_WT_CLKP

2
75 RSRVD/REFCLKN1 3.3VAUX3 74
GND10 3.3VAUX4
3 3
77 76
GND15 GND14
+3V_WLAN
ARGOS_NASE0-S6701-TS40
+3V_WLAN
PCIE_WAKE#_WLAN_R(GPP_H2) ME@

0.01U_0402_25V7K

0.1U_6.3V_K_X5R_0201

10U 6.3V M X5R 0402

strap pin at PCH side, default internal 20K PD 1 1 1
1

CN4006

CN4007

CN4008
R3506 request by CNVi check list
RN4027
200K is to make sure GPP_H2 strap low at RSMRST# 200K_0402_5%
GPP_H2 internal PD disabled after RSMRST# CNVI@ 2 2 2
@
2

RN4028 1 @ 2 0_0402_5% PCIE_WAKE#_WLAN

11 PCIE_WAKE#

RN4029 1 2 0_0402_5% @
6 PCIE_WAKE#_WLAN_R

RN4030 1 2 0_0402_5% @ WLAN_PERST#

11,26,37,44 PLT_RST#

RN4031 2 @ 1 0_0402_5%
8 PCH_WLAN_PERST#

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2017/12/13 NGFF_WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 40 of 60
A B C D E
 5 4 3 2 1

USB3.0 Port1 +USB_VCCA

+5VALW
UI4101
5 1
IN OUT
1
CI4101 2
1U_10V_M_X5R_0201 GND
4 3 USB_OC1#
2 ENB OCB USB_OC1# 4 +USB_VCCA +USB_VCCA
SY6288D20AAC_SOT23-5
JUSB2

41,44 USB_ON# USB30_TX_R_P2

Low Active 2A 9
StdA_SSTX+

100U_1206_6.3V6M

1U_0402_10V6K
1
USB30_TX_R_N2 VBUS

CI4103
1 8
D USB20_P1_R StdA_SSTX- D

CI4102
3
D+

2
7
USB20_N1_R 2 GND_DRAIN 10
2 @ USB30_RX_R_P2 6 D- GND_2 11

1
RI4101 1 @ 2 0_0402_5% 4 StdA_SSRX+ GND_3 12
USB30_RX_R_N2 5 GND_1 GND_4 13
StdA_SSRX- GND_5
LI4101
USB20_N1 4 3 USB20_N1_R
9 USB20_N1 4 3 ALLTO_C19043-10905-L
ME@
USB20_P1 1 2 USB20_P1_R
9 USB20_P1 1 2
EXC24CH900U_4P
EMC@

RI4104 1 @ 2 0_0402_5%

RI4105 1 2 0_0402_5% @

LI4102 +USB_VCCA USB20_P1_R

USB30_TX_P2 CI4104 1 2 0.1U_6.3V_K_X5R_0201 USB30_TX_C_P2 1 2 USB30_TX_R_P2 DI4102
9 USB30_TX_P2 1 2 USB20_N1_R
USB30_RX_R_N2 10 1 USB30_RX_R_N2
NC1 Line-1

1
USB30_TX_N2 CI4105 1 2 0.1U_6.3V_K_X5R_0201 USB30_TX_C_N2 4 3 USB30_TX_R_N2
9 USB30_TX_N2 USB30_RX_R_P2 9 2 USB30_RX_R_P2

AZ5725-01F.R7GR_DFN1006P2X2
4 3

2
AZ5515-02FPR7GR_DFN1006P3X
NC2 Line-2

1
DI4101
EXC24CH900U_4P USB30_TX_R_N2 USB30_TX_R_N2
7 4
EMC_NS@ NC3 Line-3

EMC@

DI4105
EMC_NS@ USB30_TX_R_P2 USB30_TX_R_P2
6 5
NC4 Line-4

2
RI4106 1 2 0_0402_5% @
3
GND1

2
8

3
C GND2 C

RI4107 1 2 0_0402_5% @ AZ1143-04F-R7G_DFN2510P10E10

EMC@

LI4103
USB30_RX_P2 1 2 USB30_RX_R_P2
9 USB30_RX_P2 1 2
EMC
USB30_RX_N2 4 3 USB30_RX_R_N2
9 USB30_RX_N2 4 3
EXC24CH900U_4P
EMC_NS@

RI4108 1 2 0_0402_5% @

+5VALW +USB_VCCB
USB3.0 Port2 5
UI4301
1
IN OUT
1 +USB_VCCB
CI4303 2 +USB_VCCB
1U_10V_M_X5R_0201 GND
4 3 USB_OC0#
2 ENB OCB USB_OC0# 9 JUSB1

100U_1206_6.3V6M
SY6288D20AAC_SOT23-5
USB30_TX_R_P1 9
1

1U_0402_10V6K
41,44 USB_ON# StdA_SSTX+

2
CI4301
1

CI4302
USB30_TX_R_N1 8 VBUS
Low Active 2A USB20_P2_R 3 StdA_SSTX-

1
2 7 D+
USB20_N2_R 2 GND_DRAIN 10
B @ USB30_RX_R_P1 6 D- GND_2 11 B
4 StdA_SSRX+ GND_3 12
USB30_RX_R_N1 5 GND_1 GND_4 13
RI4301 1 @ 2 0_0402_5% StdA_SSRX- GND_5

ALLTO_C19043-10905-L
LI4301
USB20_N2 4 3 USB20_N2_R ME@
9 USB20_N2 4 3

USB20_P2 1 2 USB20_P2_R
9 USB20_P2 1 2
EXC24CH900U_4P
EMC@

RI4302 1 @ 2 0_0402_5%

DI4301
+USB_VCCB USB30_RX_R_N1 10 1 USB30_RX_R_N1 USB20_P2_R
NC1 Line-1
AZ5725-01F.R7GR_DFN1006P2X2

RI4303 1 2 0_0402_5% @ USB30_RX_R_P1 9 2 USB30_RX_R_P1 USB20_N2_R

NC2 Line-2
1

USB30_TX_R_N1 USB30_TX_R_N1

AZ5515-02FPR7GR_DFN1006P3X
7 4
NC3 Line-3

2
LI4302
1

USB30_TX_P1 USB30_TX_C_P1 USB30_TX_R_P1 USB30_TX_R_P1 USB30_TX_R_P1

EMC_NS@

DI4302

CI4304 1 2 0.1U_6.3V_K_X5R_0201 1 2 6 5
9 USB30_TX_P1 1 2 NC4 Line-4

EMC@

DI4509
3
USB30_TX_N1 CI4305 1 2 0.1U_6.3V_K_X5R_0201 USB30_TX_C_N1 4 3 USB30_TX_R_N1 GND1
9 USB30_TX_N1 4 3
2

8
EXC24CH900U_4P GND2
2

EMC_NS@ AZ1143-04F-R7G_DFN2510P10E10

3
EMC@
RI4304 1 2 0_0402_5% @

A RI4305 1 2 0_0402_5% @ A
EMC
LI4303
USB30_RX_P1 1 2 USB30_RX_R_P1
9 USB30_RX_P1 1 2

USB30_RX_N1 4 3 USB30_RX_R_N1
9 USB30_RX_N1 4 3
EXC24CH900U_4P
EMC_NS@ Title
Security Classification LC Future Center Secret Data
RI4306 1 2 0_0402_5% @ Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 PORT_LEFT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 41 of 60
5 4 3 2 1
 A B C D E

USB2.0 PORT x1
+USB2_VCCA

+USB2_VCCA JUSB3
1
+5VALW +USB2_VCCA USB20_N9_R 2 VBUS
1
UI4302 USB20_P9_R 3 D- 1
D+

100U_1206_6.3V6M
5 1 4 5
IN OUT GND GND1

470P_0402_50V7K
1 1 6
GND2

CI4307

CI4308
CI4306 2 1 7
1U_10V_M_X5R_0201 GND GND3 8
4 3 USB_OC2# GND4
2 ENB OCB USB_OC2# 4 2 ALLTO_C107G1-10803-L
SY6288D20AAC_SOT23-5 2 ME@
@
USB_ON#
41,44 USB_ON# Low Active 2A

+5VALW

RI4307 2 @ 1 100K_0201_5% USB_ON#

USB20_N9_R

+USB2_VCCA USB20_P9_R

2
RI4308 1 @ 2 0_0402_5%

1
1
LI4304
USB20_P9 4 3 USB20_P9_R DI4306
9 USB20_P9 4 3 DI4305 AZC199-02S.R7G_SOT23-3
USB20_N9 USB20_N9_R

2
1 2 EMC@
9 USB20_N9 1 2

2
EXC24CH900U_4P AZ5725-01F.R7GR_DFN1006P2X2
EMC@ EMC_NS@

1
2 2
RI4309 1 @ 2 0_0402_5%

EMC

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 Port_Right & USB2.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 42 of 60
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 43 of 60
5 4 3 2 1
 5 4 3 2 1

+3VL_EC +3VL_EC +3VL_EC_R

+3VL VCC_LPC_ESPI
RE4402 1 2 0_5%_0603@ +1.8VALW

0.1U_6.3V_K_X5R_0201

1000P_50V_K_X7R_0201
1 1 +3VL +3VALW VCC_FSPI
RE4403 1 2 0_5%_0603 @ RE4404 1 2 0_0402_5% @ +3VS

CE4407

CE4408

0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1 RE4405 1 2 0_0402_5% @
2 2 EC_FAN_SPEED

CE4409
1 1 1 1 1 1 RE4409 1 2 100K_0402_5%

0.1U_6.3V_K_X5R_0201
RE4406 1 @ 2 0_0402_5%
CPU_VR_READY

CE4401

CE4402

CE4403

CE4404

CE4405

CE4406
1 RE4410 1 2 10K_0402_5%
2

CE4410
RE4407 1 2 0_5%_0603@
2 2 2 2 2 2 RPE1
EC_SMB_DA0 1 4
2 EC_SMB_CK0 2 3
GPU/Thermal sensor
2.2K_0404_4P2R_5%
EC_AGND

+3VL_EC
D D

EC_SMB_DA3 RPE2
1 4
EC_SMB_CK3 2 3
PMIC
2.2K_0404_4P2R_5%

VCC_LPC_ESPI VCC_FSPI +3VL_EC RPE3

EC_SMB_CK1 1 4
+3VL_EC_R EC_SMB_DA1 2 3
Battery/Charger
2.2K_0404_4P2R_5%

UE4401
LID_SW#

114
121

106

127
RE4421 1 2 100K_0201_5%

11
26
50
92

74
IT8227E-CX_LQFP128_16X16
1 EC_ESPI_IO0
2 0_0201_5%@ 10 87 EC_SMB_CK0
RE4415

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VFSPI

VSTBY(PLL)
7 ESPI_IO0 1 EC_ESPI_IO1
2 0_0201_5%@ 9 EIO0/LAD0/GPM0(3) SMCLK0/GPF2 88 EC_SMB_DA0 EC_SMB_CK0 26,39
RE4416 GPU/Thermal sensor
7 ESPI_IO1 1 EC_ESPI_IO2
2 0_0201_5%@ 8 EIO1/LAD1/GPM1(3) SMDAT0/GPF3 115 EC_SMB_CK1 EC_SMB_DA0 26,39 EC_USB_ON#
7 ESPI_IO2 RE4417 SM BUS EC_SMB_CK1 52,53 RE4424 2 1 100K_0201_5%
RE4418 1 EC_ESPI_IO3
2 0_0201_5%@ 7 EIO2/LAD2/GPM2(3) SMCLK1/GPC1 116 EC_SMB_DA1
7 ESPI_IO3 EC_ESPI_RST# 22 EIO3/LAD3/GPM3(3) SMDAT1/GPC2 117 PECI_EC 2 1 43_5%_0201 EC_SMB_DA1 52,53 Battery/Charger
RE4438 H_PECI 6
ON/OFF RE4426 1 2 100K_0402_5%
EC_ESPI_CLK ERST#/LPCRST#/GPD2 PECI/SMCLK2/GPF6(3)
RE4419 1 2 0_0201_5%@ 13 118
7 ESPI_CLK EC_ESPI_CS# ESCK/LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3)
7 ESPI_CS# RE4420 1 2 0_0201_5%@ 6 NOVO# RE4428 2 1 100K_0402_5%
ECS#/LFRAME#/GPM5(3)
EC_ON_3VALW_R
RE4429 2 1 100K_0402_5%
EC_RTCRST#_ON 126
5 GA20/GPB5(3) 85 1 IT12
PLT_RST# 15 ALERT#/SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0 86 PBTN_OUT#
11,26,37,40,44 PLT_RST# LPC RE4436 1 2 0_0201_5%@
PBTN_OUT#_R 11
EC_SCI# 23 PLTRST#/ECSMI#/GPD4(3) PS2DAT0/TMB1/GPF1 89 3VALW_PCH_EN
6 EC_SCI# 14 ECSCI#/GPD3 PS/2 PS2CLK2/GPF4 90 EC_ON_1.8V 3VALW_PCH_EN 46
WRST#
4 WRST# PS2DAT2/GPF5 EC_ON_1.8V 55
KBRST#/GPB6(3)
IT8227E-CX PWM0/GPA0
24 PWR_LED#
PWR_LED1# PWR_LED# 45

33 BKOFF#
BKOFF#
LID_SW#
113
123 CRX0/GPC0
LQFP128 PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
25
28
29
30
BATT_LOW_LED#
BATT_CHG_LED#
EC_FAN_PWM
PWR_LED1#
BATT_LOW_LED#
BATT_CHG_LED#
30
45
45
45 LID_SW# CTX0/TMA0/GPB2(3) CIR SMCLK5/PWM4/GPA4 31 PWR_LED2# EC_FAN_PWM 39
SMDAT5/PWM5/GPA5 PWR_LED2# 30

H_PROCHOT#_EC 80
PWM
RE4586 1 @ 2 0_0201_5% 119 DAC4/DCD0#/GPJ4(3) 47 EC_FAN_SPEED
55 VDDQ_PGOOD FP_PWR_EN_R DSR0#/GPG6 TACH0A/GPD6(3) PM_SLP_S4#_R EC_FAN_SPEED 39
C
45 FP_PWR_EN RE4585 1 2 0_0201_5%@ 33 48 RE4422 1 2 0_0201_5% @
PM_SLP_S4# 11 C
RE4430 1 @ 2 0_0402_5% GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) GPG1:Def:GPO-L
11,26,37,44 PLT_RST# EC_ON_3VALW_R
54 EC_ON RE4437 1 2 0_0201_5%@ 81 120
RESETN 45
RE4432 1 2 0_0402_5% @ EC_ESPI_RST# DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) 124 SUSP#
7 ESPI_RST# EC_TX 17 TMRI1/GPC6(3) SUSP# 40,46
40 EC_TX EC_RX 16 TXD/SOUT0/LPCPD#/GPE6
40 EC_RX RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3)
ADP_I 71 107 EC_VR_ON
+3VL_EC
53 ADP_I SYS_PWROK 72 ADC5/DCD1#/GPI5(3) GPE4 18 PM_SLP_S3#_R EC_VR_ON 56
UART port RE4444 1 2 0_0201_5% @
11 SYS_PWROK 73 ADC6/DSR1#/GPI6(3) WAKE UP RI1#/GPD0(3) 21 EC_USB_ON# PM_SLP_S3# 11
PSYS RE4443 1 2 0_0201_5% @
53,56 PSYS PCH_DPWROK_EC ADC7/CTS1#/GPI7(3) RI2#/GPD1 USB_ON# 41
RE4431 2 1 1K_0201_5% 35
11 PCH_DPWROK EC_VCCST_EN RTS1#/GPE5
1

34
46 EC_VCCST_EN CPU_VR_READY PWM7/RIG1#/GPA7
1

RE4433 122 112 when mirror, GPG2 pull high

56 CPU_VR_READY EC_SMB_DA3 95 DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 110 ON/OFF
DE4401 100K_0402_5% 55 EC_SMB_DA3 EC_SMB_CK3 CTX1/SOUT1/GPH2/SMDAT3/ID2 PWRSW/GPB3 ON/OFF 30,45 when no mirror, GPG2 pull low +3VL_EC
RB521CS-30GT2RA_VMN2-2 94 111
PMIC
2

55 EC_SMB_CK3 CRX1/SIN1/SMCLK3/GPH1/ID1 GPB4 109

@ NOVO# GPG2 RE4434 1 2 100K_0402_5%
2

1 2 EC_SPI_CLK 105 GPB1 108 ACIN# NOVO# 30

7 SPI_CLK RE4445 49.9_1%_0201
WRST# RE4446 1 2 0_0201_5%@ EC_SPI_CS0# 101 FSCK GPB0 RE4435 1 @ 2 100K_0402_5%
26 WRST# 7 SPI_CS# EC_SPI_SI FSCE#
1U_6.3V_M_X5R_0201

RE4447 1 2 0_0201_5%@ 102

1 7 SPI_SI EC_SPI_SO FMOSI EXTERNAL SERIAL FLASH NTC_V1
CE4412

WRST# MIN 10us RE4449 1 2 0_0201_5%@ 103 66

7 SPI_SO FMISO ADC0/GPI0(3) 67 PM_SLP_S0#_R NTC_V1 39
RE4425 1 2 0_0201_5% @
PM_SLP_S0# 11
KSO16 56 ADC1/GPI1(3) 68 NTC_V2
2 57 KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) 69 PM_SLP_SUS#_R NTC_V2 39
KSO17 RE4427 1 2 0_0201_5% @
PM_SLP_SUS# 11
EC_BEEP 32 KSO17/SMISO/GPC5(3) ADC3/GPI3(3) 70
30 EC_BEEP PWM6/SSCK/GPA6 ADC4/GPI4(3) GPIO_SCL 11
GPG2 100 A/D D/A
PCH_ENBKL EC_ENBKL SSCE0#/GPG2
GPG0:Def:GPO-H 4,33 PCH_ENBKL RE4423 1 2 0_0402_5% @ 125 SPI ENABLE
SSCE1#/GPG0 76 EC_VCCST_PWRGD
KSO0 36 TACH2A/GPJ0 77 EC_MUTE# EC_VCCST_PWRGD 11
KSO1 37 KSO0/PD0 TACH2B/GPJ1 78 EC_TP_ON EC_MUTE# 30
KSO2 38 KSO1/PD1 DAC2/TACH0B/GPJ2(3) 79 ME_FLASH EC_TP_ON 45
KSO3 39 KSO2/PD2 DAC3/TACH1B/GPJ3(3) ME_FLASH 6
40 KSO3/PD3 EC_VCCST_EN
KSO4 RE4440 1 @ 2 100K_0402_5%
KSO5 41 KSO4/PD4
KSO6 42 KSO5/PD5 SUSP# RE4441 1 2 100K_0402_5%
KSO7 43 KSO6/PD6
KSO8 44 KSO7/PD7 BKOFF# RE4442 1 2 10K_0402_5%
KSI[0..7] KSO9 45 KSO8/ACK#
45 KSI[0..7] KSO10 46 KSO9/BUSY
KSO[0..17] 51 KSO10/PE 2 BATT_TEMP EC_ON_1.8V
KSO11 RE4580 1 2 100K_0201_5%
45 KSO[0..17] 52 KSO11/ERR# GPJ7 128 AC_PRESENT BATT_TEMP 52,53
KSO12 CLOCK RE4450 1 2 0_0201_5%@
AC_PRESENT_R 11
53 KSO12/SLCT GPJ6 EC_VPP_PWREN
KSO13 RE4581 1 2 100K_0201_5%
KSO14 54 KSO13
KSO15 55 KSO14 84 EC_VPP_PWREN EC_VR_ON RE4582 1 2 100K_0201_5%
KSO15 KBMX EGCLK/GPE3 83 EC_VPP_PWREN 55
EGCS#/GPE2 82 VGA_AC_DET_EC GPIO_AL0 45 EC_USM
B RE4448 1 2 0_0201_5%@ RE4583 1 2 100K_0201_5% B
KSI0 58 EGAD/GPE1 VGA_AC_DET 26
KSI1 59 KSI0/STB# 3VALW_PCH_EN RE4584 1 2 100K_0201_5%
KSI2 60 KSI1/AFD# 19 NUM_LED#
61 KSI2/INIT# SMCLK4/L80HLAT/BAO/GPE0 20 EC_TS_ON NUM_LED# 45 GPIO_AL0
KSI3 RE4587 2 1 1/20W_49.9K_1%_0201
KSI4 62 KSI3/SLIN# SMDAT4/L80LLAT/GPE7 EC_TS_ON 33
63 KSI4 GPIO 3 EC_USM PWR_LED1#
KSI5 EC_USM 54 RE4588 1 2 100K_0201_5% @
KSI6 64 KSI5 GPH7 99 PCH_PWROK
KSI6 ID6/GPH6 EC_SMI_R PCH_PWROK 11 PWR_LED2#
KSI7 65 98 RE4579 1 2 0_0201_5% @ RE4589 1 2 100K_0201_5% @
KSI7 ID5/GPH5 97 EC_SMI 6
ID4/GPH4 CAPS_LED# DELINK 45
96
VCORE

ID3/GPH3 93 EC_RSMRST#_EC CAPS_LED# 45

RE4452 1 2 1K_0201_5%
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5

CLKRUN#/ID0/GPH0 EC_RSMRST# 11
1
27
49
91
104

75

12

SA0000A8N00

CE4411 Emergency Power Loss Early De-assertion of DSW_PWROK control circuit

VCOREVCC 2 1
ALW_PWRGD EC_RSMRST#
54 +3VALW_PG RE4453 1 @ 2 0_0402_5% DE4402 1 2
EC_AGND 0.1U_6.3V_K_X5R_0201
RB521CS-30GT2RA_VMN2-2

1 2 0_0402_5% @ PCH_DPWROK
54,55 +5VALW_PG RE4454 DE4403 1 2

RB521CS-30GT2RA_VMN2-2

CPU_VR_READY
CE4413 1 2 EMC_NS@ 0.1U_6.3V_K_X5R_0201
VDDQ_PGOOD
CE4414 1 2 EMC_NS@ 0.01U_6.3V_K_X7R_0201
PM_SLP_S4# CE4415 1 2 EMC_NS@ 1000P_0201_50V7-K
+3VL
EC_RTC_RST# 10 PM_SLP_S3#
RE4455 1 2 0_0402_5% @ H_PROCHOT# 6,13,55 CE4416 1 2 EMC_NS@ 1000P_0201_50V7-K
53,56 VR_HOT#
1

Power side install NOVO# CE4417 1 2 0.1U_6.3V_K_X5R_0201

1

RE4456 1 QE4401
100K_0402_5% RE4457 CE4418 SSM3K15AMFV_2-1L1B PECI_EC CE4419 1 2 EMC_NS@ 47P_0201_25V8-J
EC_RTCRST#_ON 2
100_0402_5% 47P_0201_25V8-J
EMC_NS@ BATT_TEMP CE4420 1 2 EMC_NS@ 100P_0201_25V8J
2

ACIN# RE4458 1 2 0_0402_5% @ 2

1 2

RE4459 ACIN# CE4421 1 2 EMC_NS@ 100P_0201_25V8J

1

A 10K_0402_5% A
QE4402 ON/OFF CE4422 1 2 EMC_NS@ 1U_6.3V_M_X5R_0201
2

2 H_PROCHOT#_EC 2 PLT_RST#
CE4423 1 2 EMC_NS@ 220P_0201_25V7-K
ACIN 53
QE4403
SSM3K15AMFV_2-1L1B SSM3K15AMFV_2-1L1B
3

@ For ESD

Security Classification LC Future Center Secret Data Title

Issued Date 2017/09/01 Deciphered Date 2017/09/01 EC ITE8586LQFP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Docum ent Num ber Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cus tom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Monday, December 30, 2019 Sheet 44 of 60
5 4 3 2 1
 5 4 3 2 1

K/B Connector PWR_CAPS_LED

RI4501 1 2 0_0402_5% @ 32
JKB1
33
+3VALW CAPS_LED# RI4502
CAPS_LED#_R 32 GND1
1 2 200_0402_1% 31 34
44 CAPS_LED# 31 GND2
KSO15 30
KSO10 29 30
KSO11 28 29
KSI[0..7] KSO14 27 28
KSI[0..7] 44 27
KSO13 26
KSO[0..17] KSO12 25 26
KSO[0..17] 44 24 25
KSO3
KSO6 23 24
KSO8 22 23
KSO7 21 22
KSO4 20 21
ON/OFF RI4503 1 2 0_0402_5% @ ON/OFFBTN# KSO2 19 20
30,44 ON/OFF 19
KSI0 18
KSO1 17 18
D
J4501 J4502 KSO5 16 17 D
1 16

2
CI4501 KSI3 15
0.1U_6.3V_K_X5R_0201 SHORT PADS SHORT PADS KSI2 14 15
@ @ @ KSO0 13 14

1
2 KSI5 12 13
KSI4 11 12
KSO9 10 11
KSI6
KSI7
9
8
10
9
TP/B Connector
KSI1 7 8
KSO16 6 7 JTP1 JTP2
KSO17 5 6 RI4507 1 2 0_0402_5% @ EC_TP_ON_R 1 EC_TP_ON_R 1
NUM_LED#_R 5 44 EC_TP_ON TP_INT# 1 TP_INT# 1
RI4504 1 1517@ 2 200_0402_1% 4 RI4508 1 2 0_0402_5% @ 2 2
44 NUM_LED# PWR_LED# 4 8 PCH_TP_INT# 2 2
RI4505 1 S145@ 2 200_0402_1% 3 3 3
ON/OFFBTN# RI4627 1 S145@ 2 0_0201_5% 2 3 PCH_I2C1_SDA_TP 4 3 4 3
2 8 PCH_I2C1_SDA_TP PCH_I2C1_SCL_TP 4 4
RI4628 1 S145@ 2 0_0201_5% 1 5 5
1 8 PCH_I2C1_SCL_TP 5 PCH_I2C1_SDA_TP 5
1 1 TP_PWR
6 6
HIGHS_FC8AR321-3160-1H 6 PCH_I2C1_SCL_TP 7 6
CI4507 7
KSO15 RI4623 1 S350@ 2 0_0201_5% KSO15_R ME@ CI4506 100P_0402_50V8J 7 TP_PWR 8
KSI1 RI4624 1 S350@ 2 0_0201_5% KSI1_R 100P_0402_50V8J EMC_NS@ 8 GND1 8
EMC_NS@ 2 2 GND2 9
HIGHS_FC5AF061-2931H 10 GND1
ME@ GND2
HIGHS_FC5AF081-2931H
ME@
CAPS_LED#_R NUM_LED#_R PWR_LED# ON/OFFBTN# PWR_CAPS_LED

+3VS TP_PWR PCH_I2C1_SCL_TP

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
PCH_I2C1_SDA_TP

AZ5123-01F.R7GR_DFN1006P2X2
1
RI4506 1 2 0_0402_5% @
1

3
100P_0402_50V8J

EMC@

DI4504

100P_0402_50V8J
2

1
EMC@

EMC_NS@

1517@

EMC_15_NS@
100P_0201_25V8J

EMC_NS@

EMC_NS@

CI4505
2 2 DI4505
1

1
DI4501

CI4503

CI4504

DI4503

1
DI4502

CI4502 EMC_NS@
1 0.1U_6.3V_K_X5R_0201
1 1
2 2
2

C C
2

AZC199-02S.R7G_SOT23-3

1
For EMC

+3VS_FP
44 BATT_LOW_LED#
BATT_LOW_LED# LED1 1 2 RI4509 1 2 470_0402_5% +3VALW Finger Print Connector

1
L-C192JFCT-LCFC_SUPER_AMBER
1

RI4622
330_0402_1%
1

D4501
AZ5123-01F.R7GR_DFN1006P2X2

1 2
EMC_NS@ +3VL +3VS_FP
+3VL QI4501
2

LP2301ALT1G_SOT23-3
FP@
2

1
FP_PWR_EN# 2 QI4502
1
3 1 CI4508

D
RI3803
1/20W_200K_5%_0201 1 0.1u_0201_10V6K SSM3K15AMFV_2-1L1B

3
BATT_CHG_LED# LED2 1 2 RI4510 1 2 470_0402_5% FP@ CI4510 FP@ FP@
44 BATT_CHG_LED# +3VALW 1 2
0.047U_0402_25V_X7R_0402 CI4511

G
2

2
L-C192WDT-LCFC_WHITE FP@ 0.1u_0201_10V6K
1

RI4525 1 2 0_0201_5% @ 2 @
2 +3VS_FP
1

1
0_0201_5% 1 @ 2 RI4619 FP_PWR_EN
D4502 GPIO_AL0
RI4621 RI4521 2 @ 1 1/20W_4.7K_5%_0201
AZ5725-01F.R7GR_DFN1006P2X2
100K_0201_5%
EMC_NS@ 2 1 1/20W_4.7K_5%_0201 GPIO_SCL
FP@ 1 RI4522 @
2

CI4509

2
FP_PWR_EN# 0.1u_0201_10V6K RI4523 2 @ 1 1/20W_4.7K_5%_0201 FPR_RESET
2

B B
@

1
QI3802 2

FPR_RESET RI4524 1 @ 2 1/20W_4.7K_5%_0201

44 FP_PWR_EN
2
PWR_LED# LED3 1 2 RI4511 1 2 470_0402_5% DELINK_R RI4618 1 @ 2 100K_0201_5%
44 PWR_LED# +3VALW

1
SSM3K15AMFV_2-1L1B

3
L-C192WDT-LCFC_WHITE RI3806 FP@
1

100K_0201_5%
FP@
1

2
D4503
AZ5725-01F.R7GR_DFN1006P2X2 +3VS_FP JFP1
EMC_NS@ 10
GND2
2

9
GND1
2

RI4513 1 2 0_0402_5% @ 8
USB20_N7_CONN 7 8
LI4501 USB20_P7_CONN 6 7
USB20_N7 1 2 USB20_N7_CONN RI4620 1 @ 2 0_0201_5% 5 6
9 USB20_N7 1 2 8 FPR_DELINK DELINK_R 5
44 DELINK RI4515 1 2 0_0201_5% @ 4
DELINK GPIO_AL0 RI4516 1 2 GPIO_AL0_R 3 4
0_0201_5% @
USB20_P7 USB20_P7_CONN 44 GPIO_AL0 FPR_RESET 3
4 3 RESETN RI4517 1 @ 2 0_0201_5% 2
9 USB20_P7 4 3 44 RESETN 2
1
HALL Sensor EXC24CH900U_4P
EMC_NS@
44
8 FPR_RESET
GPIO_SCL
GPIO_SCL RI4518 1 2 0_0201_5% @ GPIO_SCL_R 1
HIGHS_FC5AF081-2931H
ME@
RI4514 1 2 0_0402_5% @
+3VL
US4501 USB20_N7_CONN +3VS_FP
@
+VCC_LID

AZ5515-02FPR7GR_DFN1006P3X

AZ5725-01F.R7GR_DFN1006P2X2
RS4501 1 2 0_0402_5% 2 DI4508
VCC DELINK_R 10 1 DELINK_R USB20_P7_CONN
2 NC1 Line-1
CS4501 3 RS4502 1 @ 2 0_0402_5% LID_SW# GPIO_AL0_R 9 2 GPIO_AL0_R
OUTPUT LID_SW# 44 NC2 Line-2

1
.01U_0402_16V7-K
1 FPR_RESET FPR_RESET

EMC_FP@

EMC_NS@
@ 1 2 7 4

1
GND NC3 Line-3

DI4506

DI4507
A CS4502 A
AH9247-W-7_SC59-3 100P_0402_50V8J GPIO_SCL_R 6 5 GPIO_SCL_R
EMC_NS@ NC4 Line-4
1 3
GND1

2
8

2
GND2
AZ1143-04F-R7G_DFN2510P10E10
EMC_FP@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 KB/TP_CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Tuesday, December 10, 2019 Sheet 45 of 60
5 4 3 2 1
 A B C D E

+3VALW to PCH
+3VALW

PJ4602
1
1 2
2
+3VALW_PCH
Load Switch +3VS, C173 --> 2.74ms
CX4601
1 JUMP_43X39 +5VALW To +5VS +5VS, C176 --> 2.03ms
@
1U_6.3V_M_X5R_0201
@ UX4608
+3VALW To +3VS VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm
2 1 14 +5VS
IN1_1 OUT1_2 +5VALW
Need Short
2 13 1
1 IN1_2 OUT1_1 CX4607 G2898KD1U_TDFN14P_2X3 J12 @
1
3 12 CX4622 1 2 1800P_25V_K_X7R_0201 0.1U_6.3V_K_X5R_0201 1 14 +5VS_LS 1 2
44 3VALW_PCH_EN EN1 CT1 IN1_1 OUT1_2 1 2
@ 2 13
VBIAS 4 11 2 IN1_2 OUT1_1 JUMP_43X79
@ 1 1
VBIAS GND

0.01U_0402_25V7K
C4624
1 C177 C3916 5VSON 3 12 C176 1 2 1 1
5 10 CX4623 1 2 1000P_50V_K_X7R_0201 1U_0402_6.3V6K .01U_0402_16V7-K EN1 CT1 1000P_0201_50V7-K C174 C3917
EN2 CT2 EMC@ 4 11 0.1u_0201_10V6K 0.01U_0201_10V6K
+5VALW VBIAS GND

1
@ 6 9 @ 2 2 @ EMC@
2 RX4633 7 IN2_1 OUT2_2 8 +3VALW 3VSON 5 10 C173 1 2 2 2
IN2_2 OUT2_1 EN2 CT2 +3VS
0_0201_5% 2200P_0402_25V7-K
@ 15 6 9 J11 @
Thermal Pad 7 IN2_1 OUT2_2 8 +3VS_LS 1 2
1

2
TPS22976DPUR_WSON_2X3 C178 IN2_2 OUT2_1 1 2
@ 1U_0402_6.3V6K 15 JUMP_43X79

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
@ Thermal Pad
Need Short

C175

C4625

C4626
2 U13 1 1 1

+3VALW RX4632 1 2 0_0201_5% VBIAS

@
2 2@ 2@

+1.8VALW to +1.8VS
+1.8VALW +1.8VS

RX4601 1 @ 2 1/2W_0.01_+-1%_0603_50PPM/C +5VL

@
QX4601 SUSP# R64 1 2 0_0402_5% 3VSON
0.6A 40,44,46 SUSP#

1
S

3 1 LP2301ALT1G_SOT23-3
RX4630
0.1U_6.3V_K_X5R_0201

2 100K_0402_5% 2
CX4602

RX4603
10K_0402_5%

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
G
2
2

CX4603

CX4604

CX4605

1 1 1 1 @

2
SUSP R27 1 2 0_0402_5% 5VSON
SUSP 34
1 1
2 2 2 2

1
@

D C180 C179
1

@ @ 2 1U_0402_6.3V6K 1U_0402_6.3V6K
40,44,46 SUSP# 2 2
@ G QX4606
SUSP RX4604 1 2 0_0402_5% L2N7002KWT1G_SOT323-3
S

3
1

1 CX4609
RX4606
0.1U_6.3V_K_X5R_0201
470K_0402_5%
@
2
2

+VCCST_CPU +VCCSTG_CPU

VCCST&VCCSTG RX4614 1 2 0_0402_5% @

+3VALW +3VALW +3VALW VccSTG and VccST are

merged and gated by
SLP_S4#
2

3 1 3
RX4619 RX4618 CX4619
100K_0201_5% 100K_0201_5% 0.1U_6.3V_K_X5R_0201

UX4605 2
1

3V3_VCCST_OVERRIDE 1 5
INB VCC
2
INA
6

3 4 PM_SLP_VCCST_OVRD RX4622 1 2 0_0201_5% @

GND OUT Y
PM_SLP_VCCST_OVRD_R
D1

D2

2 5 MC74VHC1G32DFT1G_SOT353-5
11 VCCST_OVERRIDE G1 G2
1

+VCC1.05_OUT_FET
RX4625 +3VALW
S1

S2

OR Gate 200K_0402_5%
QX4602A QX4602B @ 1
1

PJT7838_SOT363-6 PJT7838_SOT363-6 1 CX4618

2

CX4620 +3VALW 10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201 +VCCST_CPU_LS +VCCST_CPU
2
2
EC_VCCST_EN +VCCST_EN 1
RX4621 1 2 0_0402_5% @ UX4606 UX4604
44 EC_VCCST_EN 1 5 2 4
CX4617 RX4620 1 2 0_0402_5% @
INB VCC 1U_6.3V_M_X5R_0201 VIN VOUT
+3VALW 2 2 5 3
INA VBIAS NC If VCCST is enabled by SLP_S4#, no power
3 4 VCCST_EN_R RX4624 1 2 0_0201_5% @ VCCST_EN 6 1 gate is required for VCCPLL_OC and it can
GND OUT Y ON GND be merged with VDDQ directly.
1 If VCCST is enabled by SLP_S3#, a power
CX4621 MC74VHC1G32DFT1G_SOT353-5 EM5201BJ-45_SOT23-6
gate is required for VCCPLL_OC.
UX4607 0.1U_6.3V_K_X5R_0201 OR Gate
1 5
55 VCCIN_AUX_VID0 INB VCC 2 PM_SLP_VCCST_OVRD RX4623 1 @ 2 0_0201_5%
2
55 VCCIN_AUX_VID1 INA

1
3 4 VCCIN_AUX_VALID RX4628 1 2 0_0201_5% @ VCCIN_AUX_VCCST_R
GND OUT Y RX4627
1

MC74VHC1G32DFT1G_SOT353-5 200K_0402_5%
OR Gate

2
4 RX4629 4
200K_0402_5%
@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20

DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Tuesday, December 10, 2019 Sheet 46 of 60
A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3

V
PU301 PU904 +3V_PCH

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5

V
PBTN_OUT#

EC_ON PM_SLP_S3# PCH 15

PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4 PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V PU801

V
PU501
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)

V
+1.5VS_VGA

V
PU901 VR_ON Q31
V

PU601

V
+CPU_CORE
+5VS

B B

V
Q32 +1.05VSP_VGA

V
+3VS PU702

V
SUSP#,SUSP 9 VGA

V
PU602
+1.5VS +3VS_VGA

V
Q27

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Power sequence block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 47 of 60
5 4 3 2 1
 5 4 3 2 1

GPU
CPU RV2317 OPTN17@ RV2317 OPTN16@

UC1 1035G4@ UC1 1035G1@ UC1 1005G1@ UC1 1065G7@

D D
MP PN
MP PN MP PN MP PN 5.11_0805_1% 470_0805_5%
SD00001NQ00 SD00247008J

Intel i5-1035G4 1.1G/4C Intel i5-1035G1 1G/4C/6M Intel i3-1005G1 1.2G/2C/4M Intel i7-1065G7 1.3G/4C/8M
SA0000A4T20 SA0000A8W30 SA0000A9V10 SA0000A4U10

VRAM
DRAM_Samsung DRAM_Hynix DRAM_Micron

ZZZ1 SAM_DRAM@ ZZZ1 Hyn_DRAM@ ZZZ1 Mic_DRAM@

D4G SAM HYNIX D4G D4G MIC

X7648112001 X7648112002 X7648112003

SO_DIMM only

C C

PCB_MB HDMI Royalty

ZZZ
ZZZ ZZZ2 HDMI@

NM-D031 NM-D031 HDMI PN

DAZ1K000100 RO00000040J
DAZ1JZ00100
15@
14@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Tuesday, December 10, 2019 Sheet 48 of 60
5 4 3 2 1
 5 4 3 2 1

PCB Fedical Mark PAD

FD4901 FD4902 FD4903 FD4904 FD4905 FD4906

1
D
MD Shielding D

SH4901 SH4902 SH4903 SH4904 SH4905 SH4906

CPU Thermal Hole
H4902 H4904 H4906 H4907
HOLEA HOLEA HOLEA HOLEA
1

1
1

1
PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2

SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

GPU Thermal Hole

C
H4903 H4905 C
HOLEA HOLEA
1

PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2
SODIMM Shielding

SH4911
SH4907 SH4908 SH4909 SH4910

H4908 H4909 H4910 H4911

HOLEA HOLEA HOLEA HOLEA

1
1

1
B B
PAD_C7P0D4P0 PAD_C7P0D4P0 PAD_O2P5X3P0D2P5X3P0N PAD_O2P5X3P0D2P5X3P0N

H4912 H4913 H4914 H4901 SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

HOLEA HOLEA HOLEA HOLEA
1

PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C10P0D8P0

H4915 H4916 H4917

HOLEA HOLEA HOLEA
1

A A
PAD_C7P0D2P4 PAD_CT7P0B10P0D4P0 PAD_CT7P0B10P0D4P0

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 49 of 60
5 4 3 2 1
 5 4 3 2 1

V20B+
+5VS
Richtek
+5VALW/8A
LV5083AGQUF
Adaptor 65W
D D

Converter +3VS

FOR SYSTEM VCCIN_AUX/14A

+3VALW/ 6A
EN PGOOD

+1.8VALW/4A

TI Richtek +1.35V/8A Silergy +2.5V/1A

BQ24780SRUYR LV5095B LV5116A

Battery Charger Switch Mode SYS PMIC
EN
C C

Switch Mode FOR VRAM +1.2V/8A

PGOOD

UPI +0.6VS/1A

SMBus UP1666QQKF +VGA_CORE/30A

EN Switch Mode
PGOOD
FOR GPU VDDC

Battery Richtek
polymer RT3612EB VCCIN/39A

3S1P/2S2P Switch Mode

EN FOR CPU Core
PGOOD
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 50 of 60
5 4 3 2 1
 5 4 3 2 1

PJ5101 @ PJ5102 @
JUMP_43X79 JUMP_43X79
1 2 1 2
1 2 1 2 VIN
3.25A HCB2012KF-121T50_0805
JDCIN1 PF5101 PL5101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 EMC@
3 7A_24VDC_F1206HI7000V024TM
GND2 4

470P_0201_50V7-K

1000P_0201_50V7-K
GND3 5 @ HCB2012KF-121T50_0805

1000P_0201_50V7-K

470P_0201_50V7-K
GND4

EMC@

EMC@
6 PL5102

PC5101

PC5102
GND5

2
EMC@

EMC@
D 7 1 2 D

PC5103

PC5104
GND6
EMC_NS@
HIGHS_PJSS0026-8B01H

1
ME@

change symbol to DC021508142 by amy 0704

+3VL

2
PR5101
@ 0_0402_5%

VCCRTC 1
1

PR5102
C C
45.3K_0402_1%
@ RTC_VCC
2

1
JRTC1
3 2 PR5103 1 1
2 1
PD5101 1K_0603_5% 3 2
GND1
2

BAT54CW_SOT323-3 4
PC5105 GND2
1U_0402_6.3V6K
1

HIGHS_WS33020-S0351-HF
@ ME@
change symbol to SP021510283 by amy 0620

RTC_VCC 20MIL
+3VL 20MIL
VCCRTC 20MIL

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-DCIN / RTC charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 51 of 60
5 4 3 2 1
 5 4 3 2 1

SUYIN_125022HB008M202ZL VBAT EMC@

D
JBATT1 10A HCB2012KF-121T50_0805
BATT+
D

1 PL5201
1 2 1 2
9 2 3 EC_SMCA PR5201 1 2100_0402_1%
10 GND1
GND2
3
4
4 EC_SMDA 1 2
EC_SMB_CK1
EC_SMB_DA1
44,53
44,53
1 2 2S1P polymer battery
5 PR5202 100_0402_1%
5 6 PL5202 voltage level: +5.5V ~
6
7
7 HCB2012KF-121T50_0805 8.8 V

3
8 EMC@
8

1
PC5201 PC5202
ME@ 1000P_0201_50V7-K 0.01U_0201_25V6-K
EMC@ EMC@

2
VBAT
JBATT2
PD5201
1 AZC199-02S.R7G_SOT23-3
1 2 EMC_NS@

1
2 3 EC_SMCA
9 3 4 EC_SMDA
10 GND1 4 5
GND2 5 6
6 7
7 8
8 PR5203
1 2
+3VALW
100K_0402_1%
HIGHSTAR_WS33081-S120S-1H
C C
ME@ PR5204
1 2
BATT_TEMP 44,53
10K_0402_5%

1
1

PD5202
AZ5215-01F_DFN1006P2E2
EMC_NS@
2
2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 52 of 60
5 4 3 2 1
 5 4 3 2 1

VIN
PQ100 PQ101
AONS32314_DFN8-5 AONR32340C_DFN8-5
N2
N1
PR100
1 1 0.01_1206_1%
2 2 S1 5 V9B+
5 3 3 S2 D 1 4
S3

G
2 3
D D

470P_0201_50V7-K

220P_0402_50V7K

470P_0402_50V7K

680P_0402_50V7K

4700P_0402_50V7-K

6800P_0402_25V7-K
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.022U_0402_25V7K

0.01U_0201_25V6-K
4

EMC_NS@

EMC_NS@
PC100
2 2

1
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
PC102

PC103

PC104

PC105

PC106

PC107

PC108

PC109
1

PC101
PR101

2
4.7_0603_5% 1 1

5
0.1U_0201_25V6-K

2
PQ102
PC110
AON6324_DFN8-5
1 2
@
BQ24780_BATDRV 1 2 BQ24780_BATDRV_R 4

2
09/09 NC MEC part
PC111 PC112 PR102
0.1U_0201_25V6-K 0.1U_0201_25V6-K 0_0402_5%

3
2
1
2
PR103
499K_0402_1% PC113
0.01U_0201_25V6-K

1
VIN BATT+

2
BAT54CW_SOT323-3
PD100
2

3
V9B+

4.02K_0603_1%
VIN

1
1

1
4.02K_0603_1%

10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K
EMC_NS@
ACN
ACP
PR105

PR106

1
10_1206_5%

PC114

PC115

PC116
2
1

PR104
BQ24780_VDD
2

2
2

5
C PR107 0.47U_25V_K_X5R_0603 PU100 C
7.15K_0402_1% 44.2K_0402_1%

ACP

ACN
PC117
1 2 PC118

1
PR108 2 1 780_VCC 28 24 1 2

2
VCC REGN PQ103
1 2 ACDET 6 2.2U_10V_K_X5R_0603 4
PC119 ACDET PR109 PC120 AON7380_DFN8-5
0.01U_0402_25V7K 25 BST_CHG 1 2 2 1
BTST PR110
2.2_0603_5% 0.047U_0603_16V7K PL100 0.01_1206_1% 6A

3
2
1
DH_CHG
3
CMSRC HIDRV
26 2.2UH_PCMB063T-2R2MS_8A_20% BATT+
@ 1 2 CHG 1 4

5
PR111 2 1 20K_0402_1% 4
ACDRV

1
@ 2 3
PR112 2 1100K_0402_1% 27 LX_CHG PR113

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
BQ24780_VDD PHASE
@ 2.2_0805_5%

1
PR114 1 2 0_0402_5% ACIN_R 5 PQ104

PC122

PC121

PC123

PC124
44 ACIN ACOK EMC_NS@
@ 4

2
PR115 1 2 0_0402_5% EC_SMB_DA1_R 11 AON7380_DFN8-5

2
44,52 EC_SMB_DA1 SDA 23 DL_CHG

470P_0201_25V7K
LODRV

1
@

2
PR116 1 2 0_0402_5% EC_SMB_CK1_R 12 22 PC126

PC125

3
2
1
44,52 EC_SMB_CK1 SCL GND 1000P_0402_50V7K

2
@ BQ24780SRUYR_QFN28_4X4 EMC_NS@

1
PR117 1 2 0_0402_5% ADP_I_R 7 29 @

0.1U_0201_25V6-K

0.1U_0201_25V6-K
44 ADP_I IADP PAD

2
8 18 BQ24780_BATDRV

PC127

PC128
IDCHG
IDCHG BATDRV
9 PR118 10_0603_5%

1
44,56 PSYS PMON 17 2 1
BATSRC
20K_0402_1%
100P_0201_25V8J

100P_0201_25V8J

100P_0201_25V8J
2

PR121 @ 20 SRP_R 2 1 SRP

0.1U_0201_25V6-K
SRP
2

1 2 0_0402_5% 10 10_0603_5%
PR119

PC131

44,56 VR_HOT# PR120

PC129

PROCHOT#

2
PC130

PC132
1

13
1

CMPIN
@
1

1
14

BATPRES#
TB_STAT#
CMPOUT 19 SRN_R 2 1 SRN
B
ILIM 21 SRN PR122 10_0603_5% B
ILIM
2

16

15
PR123
0_0402_5% @
09/19 PR331 change from 147K to 133K
PR124 PR125
1

1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
30K_0402_1%
133K_0402_1%
0.01U_0201_25V6-K

1
2

PC133

PR126
100K_0402_1%
1

ACDECT setting 17.2V

Charge current limit HW=7A
DC discharge limit =26A
Discharge current limit HW=9A during Turbo boost

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 53 of 1
5 4 3 2 1
 5 4 3 2 1

+3VALW
D D

1
PR5924
100K_0201_5%
@
PJ401
PU1101

2
2 1 +3VALW_VIN 2 7 +3VALW_PG
V9B+ +3VALW_BST +3VALW_PG 44

0.1U_0402_25V6
2 1 IN1 PG

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
3 1 1 2PC1115

EMC_NS@
1 1 IN2 BS

1
4

PC1101
JUMP_43X79 IN3
.1U_0603_25V7K

PC1102

PC1103
@ 5

2
2 2 6 LX1 15 PL1101
PJ402
14 GND1 LX2 16 +3VALW_LX 1 2 +3VALW_P 1 2
GND2 LX3 1 2 +3VALW

1
17
PR1103 GND3 PR1102 2.2UH_PCMB063T-2R2MS_8A_20% JUMP_43X118

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
100K_0402_5% 2.2_0805_5%
1 2 PR1109 1
@ 2 0_0402_5% +3VALW_EN PR1106 9 11 +3VALW_P @
44 EC_ON +3VALW_VIN 1 2 8 EN1 OUT EMC_NS@ 1 1 1 1 1 1

PC1105

PC1106

PC1107

PC1108

PC1120

PC1121
1 2
10 +3VALW_FBEN2

@
@ 2 0_0402_5% +5VALW_EN
PR1105 1

0.1U_0402_25V6
10K_0201_1% FF

1
12 PC1114 2 2 2 2 2 2
100mA

PC1116
TEST

1
13 1000P_0402_50V7K
+3VLP

2
LDO
PR1104 PR1107 EMC_NS@
3VALW:

2
1/16W_82K_1%_0402 1/20W_1M_1%_0201 1
SY8386BRHC_QFN16_2P5X2P5
PC1112 TDC=6A
2

2
1
2 4.7U_0603_6.3V6K 1 2 1 2
@ @
OCP=8A
PQ9710
PC1111 PR1108
OVP=120%
2
1000P_0402_25V7-K 1K_0402_1% Fsw=600KHz
44 EC_USM SSM3K15AMFV_2-1L1B
3

+3VLP +3VL
PJ9919
C C
1 2
1 2
JUMP_43X39
@

+5VLP +5VL
PJ9717
1 2
1 2
JUMP_43X39
@ +3VALW

1
PR1605
100K_0402_5%

V9B+

2
@ PU1601
PJ405
2 1 +5V_VIN 2 7 +5VALW_PG
+5VALW_PG 44,55
0.1U_0402_25V6

2 1 IN1 PG
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

3 1 +5VBS 1 2
EMC_NS@

1 1 IN2 BS +5VALW
1

4 PC1605
PC1601

JUMP_43X79 IN3 0.1U_0603_25V7K PJ406

PC1602

PC1603

SY8388CRHC_QFN16_2P5X2P5
5 +5VLX PL1601 1 2 1.5UH_PCMB063T-1R5MS_10A_20% +5VALW_P 1 2 8A
2

LX1 1 2

1
2 2 15
LX2 16 PR1608 JUMP_43X118

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
6 LX3 2.2_0805_5%
14 GND1 @
17 GND2 EMC_NS@ 1 1 1 1 1 1

PC1610

PC1611

PC1612

PC1613

PC1615

PC1614
1 2
GND3 11 +5VALW_P
OUT
10 PC1608 2 2 2 2 2 2
+5VALW_EN 9 FF 1000P_0402_50V7K
5VALW:

2
+5V_VIN 1 2 8 EN1 12
EN2 LDO +5VLP EMC_NS@
PR1603
TDC=8A
0.1U_0402_10V7K

4.7U_0603_6.3V6M
13 +5VVCC 100mA
PC1604

10K_0402_1% VCC
1

1 1 OCP=12A
1

1M_0402_5%

PC1606
PC1607 @ @
OVP=120%
PR1604

B @ 4.7U_0603_6.3V6K B
1M_0402_5%
2

PR1602

2 2
Fsw=600KHz
2

PC1609
2

+5VFB 1 2 1 2
PR1609
1000P_25V_K_X7R_0402 1K_0402_1%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Docum ent Num ber Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cus tom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ADA
Date: Friday, December 06, 2019 Sheet 54 of 44
5 4 3 2 1
 5 4 3 2 1

@
P_LV5116A_EN
PR9800 1 2 0_0402_5%
44,54 +5VALW_PG
@
VTT_EN
5 CPU_DRAMPG_CNTL PR9801 1 2 0_0402_5%

@
+1.8VALW_EN
PR9802 1 2 0_0402_5%
44 EC_ON_1.8V V9B+
@
VDDQ_VPP_EN
PR9803 1 2 0_0402_5%
44 EC_VPP_PWREN

2
D
+5VL D
PR9804
2.2_0603_5%

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 P_LV5116A_VCC_30 P_LV5116A_VSY S_10

1
2

2
PC9800

PC9801

PC9802

PC9803
2
PR9806 1
+5VALW 2.2_0603_5% PC9805

1
1U_0402_10V6K PC9804
@ @ @ @ 1 0.1U_25V_K_X7R_0402 +3VALW
2 PJ9807 @
2 1 2 1
2 2 1 1A

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR9808
2.2_0603_5% PC9806 JUMP_43X39
1U_0402_10V6K
1 PU9800
1 1
6

PC9807

PC9808
36 VSYS @
VCC
P_LV5116A_PVCC_30 4 27 P_+1.8VALW_VIN_S 2 2 +1.8VALW
PVCC V1P8A_IN
P_VDDQ_UG_30 1
PR9810 @ VDDQ_HG 25 P_+1.8VALW_LX_S 1 2 +1.8VALW_P 1 2 4A
1 2P_VDDQ_BST_R_30 1 2 P_VDDQ_BST_30 40 V1P8A_PH1 1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
VDDQ_BOOT

1
26 PL9800 PJ9803
PC9892 0_0603_5% V1P8A_PH2 2 1 PR9812 1UH_PCMB053T-1R0MS_7A_20% JUMP_43X79
P_VDDQ_LX_30 2 29 +1.8VALW_P +3VALW
0.1U_25V_K_X5R_0402 JUMP_43X39 4.7_0603_5%
VDDQ_PH V1P8A_SNS PC9816 PJ9808 @ 1 1 1 1
@
P_VDDQ_LX_SENS_10 P_VDDQ_VPP_IN 1A EMC_NS@
39 9 10U 6.3V M X5R 0402 2 1

1 2
VDDQ_SWSNS VPP_IN 2 1
P_VDDQ_LG_30 3 8 P_VDDQ_VPP +VDDQ_OUT

PC9809

PC9812

PC9810

PC9811
VDDQ_LG VPP PC9814 2 2 2 2
@
13 P_VTT_IN_30 1A 2 1 1200P_50V_K_X7R_0402

2
P_VDDQ_SENS_10 12 VT T _IN 2 1
2 1 VDDQ_SNS 14 P_VDDQ_VTT EMC_NS@
PJ9809
PC9893 @ VT T 2 1 JUMP_43X39 @ +0.6VS
0.1U_25V_K_X7R_0402 15
P_VCCIN_AUX_EN_10 23 VT T _SNS PC9894
AUX_DRVEN
P_LV5116A_DDR_ID_10
10U 6.3V M X5R 0402
P_VDDQ_VTT 1
1 2
2 1A
28

10U 6.3V M X5R 0402

P_VCCIN_AUX_PWM_10 21 DDR_ID 1 PJ9805
AUX_PWM 20 P_LV5116A_AUX_CS_10
PR9816 1 2 300K_0402_1%

PC9817
JUMP_43X39
AUX_CS
5 P_LV5116A_VDDQ_CS_10
PR9817 1 2 1/16W_240K_1%_0402 +3VALW +3VALW
@
P_VCCIN_AUX_LXSENS_10 22 VDDQ_CS 2
@
P_VCCIN_AUX_VCCSENSE_10 AUX_SWSNS
PR9818 1 2 0_0402_5% +VCCIN_AUX OCP=41A
13 VCCIN_AUX_VCCSENSE P_VCCIN_AUX_VCCSENSE_10 19 P_LV5116A_V1P8A_CTRL_10

2
24 +2.5V_DDR
AUX_SNS V1P8A_CT RL
2
PC9818
1000P_0402_50V7K 30 P_LV5116A_AUX_SET_10 +VDDQ OCP=13A PR9828 PR9829
C @
1
P_VCCIN_AUX_VSSSENSE_10
@ AUX_SET 100K_0402_5% 100K_0402_5%
P_VDDQ_VPP 1 2 1A C
PR9819 1 2 0_0402_5% PR9820 1 2 0_0402_5% P_LV5116A_PROCHOT# 7 1 2
13 VCCIN_AUX_VSSSENSE 6,13,44 H_PROCHOT# VCCIN_AUX_VID0

22UC_6.3VC_MC_X5RC_0603
PROCHOT # 16 PJ9802
P_VCCIN_AUX_PG_1011 AUX_VID0 VCCIN_AUX_VID0 13,46
PR9821 1 2 100K_0402_5% JUMP_43X39
+3VALW PG_ARAIL VCCIN_AUX_VID1
17
PR9823 1 2 100K_0402_5% VDDQ_PGOOD 10 AUX_VID1 VCCIN_AUX_VID1 13,46 @

10U 6.3V M X5R 0402

+3VALW PG_DDR P_LV5116A_CLK_5

2
33 PR9824 1 2 0_0402_5%

PC9813
44 VDDQ_PGOOD @ EC_SMB_CK3 44 1 1
SCL

PC9815
34 P_LV5116A_DAT_5
PR9825 1 @ 2 0_0402_5% PR9833 PR9834
P_LV5116A_EN SDA EC_SMB_DA3 44
38 10K_0402_5% 10K_0402_5%
@ PM IC_EN @ @ 2 2

1
0_0402_5% 1 2 PR9827 P_LV5116A_DIGITAL_CTL_10 37 @
DIGIT AL_CT RL P_VCCIN_AUX_VSSSENSE_10
10K_0402_5% 1 2 PR9826 18
+5VL +1.8VALW_EN 35 AUX_RGND +5VALW +5VALW +5VALW
SLP_SUS#
VDDQ_VPP_EN 32 41
DIGITAL_CTRL Control Mode

100K_0402_5%

100K_0402_5%
SLP_S4# GND

2
AUX_VID1 AUX_VID0 Vout_AUX

10K_0402_5%
VTT_EN 31

PR9830

PR9831

PR9832
DDR_VT T _CT RL
High HW Control
0 0 0V

1
P_LV5116A_DDR_ID_10
Low SW Control LV5116AGQW_WQFN40_5X5 @
P_LV5116A_V1P8A_CTRL_10
@
P_LV5116A_AUX_SET_10 0 1 1.1V

2
P_VCCIN_AUX_VIN_S V9B+ 1 0 1.65V

0_0402_5%

10K_0402_5%

10K_0402_5%
PR9835

PR9836

PR9837
AUX_SET VCCIN_AUX Internal RAMP
PJ9806
1 1 1.8V
1 2 3A High RAMP1

1
1 2 @ @
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_0201_25V6-K

P_VCCIN_AUX_BST_R_30 JUMP_43X79
Low RAMP2 DDR_ID Type VPP VDDQ VTT/VDDQTX
EMC@

@
P_VCCIN_AUX_BST_30

PC9820

PC9821

PC9822

+5VALW 1 1
1

PR9839 @
5

1 2 1 2 Floating RAMP3 Low DDR4 2.5V 1.2V VDDQ/2(VTT)

PQ9800
2

PC9819 0_0603_5% AON6380_DFN8-5 2 2

--
2

0.22U_25V_K_X5R_0402 Floating LPDDR4 1.8V 1.1V

PR9840
P_VCCIN_AUX_UG_30
4
2.2_0603_5% DIGITAL_CTRL V1P8A_CTRL V1P8A Sequence V9B+
PU9801
4
1 High LPDDR4X 1.8V 1.1V 0.6V(VDDQTX)
+VCCIN_AUX
2200P_0402_50V7K

P_VCCIN_AUX_VCC_30 BOOT
1

8
@

High Low V1P8A follow PMIC_EN

PC9824

VCC 3 P_VCCIN_AUX_UG_30
1.5A
3
2
1

P_VCCIN_AUX_PWM_10 5 UGAT E 2 PJ9810

1U_0402_10V6K

PWM 2 P_VCCIN_AUX_LX_S 1 2 P_VDDQ_VIN_S 1 2

High High V1P8A follow SLP_SUS#

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402
P_VCCIN_AUX_EN_10
1

1 PHASE 1 2
PC9823

PL9801
P_VCCIN_AUX_LG_30

330U_D2_2.5VY_R9M
EN 7

5
0.22UH_CMMS063T-R22MS2R107_26A_20% 1
6 LGAT E JUMP_43X79
Low Low V1P8A follow PMIC_EN PQ9801

PC9828

PC9827
1 1 1

D
2

GND1
1

B 9 + @ B

EMC_NS@
PC9825

PC9826
AONR32340C_DFN8-5
GND2
2

PR9842 PJ9800
5

RT9610CGQW_WDFN8_2X2
PQ9802
2.2_0805_5% JUMPER
2
Low High V1P8A follow I2C P_VDDQ_UG_30 4 2 2 2
EMC_NS@ @
1

G
AON6324_DFN8-5
2

S3
S2
S1
place close to VCCIN_ALX LMOS drain +VDDQ_OUT +1.2V
1

4
8A

3
2
1
PC9829
PL9802
1000P_0201_50V7-K PJ9804
2

P_VCCIN_AUX_LXSENS_10 P_VDDQ_LX_30 1 2 1 2
Rdson=2.8mohm@Vth=4.5V EMC_NS@ 1 2
PQ9803
3
2
1

0.47UH_PCMB053T-R47MS_13A_20% JUMP_43X118

5
AON7380_DFN8-5
@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
2

2
PJ9801 1 1 1 1 1 1

PC9830

PC9831

PC9832

PC9833

PC9834

PC9835
+VCCIN_AUX VCCIN_AUX Vout CAP Config Vboot=1.8V Loadline=6mΩ 4.7_0603_5% JUMPER
PR9844 @
P_VDDQ_LG_30

1
4
AC+DC Ripple=(-10%~+5%)*VOUT EMC_NS@ 2 2 2 2 2 2
#1:Pure MLCC 22U/0603*20pcs

1
TDC=14A Iccmax=32A place close to VDDQ LMOS drain
Rdson=10.5mohm@Vth=4.5V

1
#2:POSCAP+MLCC 330U/9mohm*1pcs+22U/0603*7pcs CURRENT LIMIT=45A @ @

3
2
1
PC9851
1200P_50V_K_X7R_0402
Max Overshoot:2.13v/500us

2
EMC_NS@
OVP=(1.2~1.3)*Vref P_VDDQ_LX_SENS_10 P_VDDQ_SENS_10
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

UVP=(0.45~0.55)*Vref
1

1
PC9836

PC9837

PC9838

PC9839

PC9840

PC9841

PC9842

PC9843

PC9844

PC9845

PC9846

PC9847

PC9848

PC9849

PC9850

Fsw=600Khz
2

@ @ @ @ @ @ @
22U_0603_6.3V6-M

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
PC9863

PC9858

PC9864

PC9866

PC9871

PC9853

PC9854

PC9855

PC9856
PC9859

PC9860

PC9861

PC9862
2

A A
@
@ @ @ @
@ @ @ @ @ @ @ @

1 1 1 1 1 1 1 1 1 1 1
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
PC9872

PC9875

PC9877

PC9880

PC9881

PC9882

PC9883

PC9884

PC9885

PC9886

PC9887

2 2 2 2 2 2 2 2 2 2 2 Title
Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR PMIC-LV5116
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
@ @ @ @ @ DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 55 of 2
5 4 3 2 1
 5 4 3 2 1

+5VALW +5VALW
+3VS

4.7_0603_5%
2

2.2_0603_5%
PR3400

PR3401
1

1
D @ D

1K_0402_1%
4.7U_0402_6.3V6M

2.2U_0402_6.3V6M

PR3403
PR3402

2
54.9_0402_1% @

PC3400

PC3401
PU3400

2
RT3612EBGQW-02_WQFN32_4X4 V9B+
P_VCCIN_PVCC_20 29
PVCC VR_HOT
2
VR_HOT# 44,53 CPU_VIN
+VCCST_CPU +VCCST_CPU 8A
PL9902
P_VCCIN_VCC_20 10 24 1 2
VCC VR_RDY CPU_VR_READY 44
HCB2012KF-121T50_0805

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

33U_D2_25VM_R40M
0.1U_0201_25V6-K
1
PR3405 @ 1

1K_0402_1%
P_VCCIN_BST1_R_30
0_0402_5%

PR3404
1 1 1
1U_0402_6.3V6K

1/16W_45.3_1%_0402

VR_PSY S PL9901

1
1 @ 2 9 +

PC3403

PC3404

PC3405

PC3448
44,53 PSY S PSYS P_VCCIN_BST1_301
1

1 2 25 2 1 2 1 2
PC3402

PC3485
2 PR3409 1

2 PR3410 1

PR3448 BOOT 1 PC3406 HCB2012KF-121T50_0805

100_0402_1%

110_0402_1%

2
0_0402_5% PR3406 0.22U_0603_25V7K 2 2 2 2
PR3407

+VCCIN
2

@ @ @ 2.2_0603_5% EMC@
P_VCCIN_EN_10 P_VCCIN_UG1_30
PR3411 1 2 23 26 1 4 PQ3400 @
44 EC_VR_ON VRON UGAT E1
0_0402_5% AON6380_DFN8-5 @
20A Vboot=1.8V Loadline= 2mohm

2200P_0402_50V7K
2

2 1

@
PC3407
0.22UH_CMMS063T-R22MS2R107_26A_20%
PC9895 @
P_VCCIN_PH1_S Ripple=30mV(0A~1A)

330U_D2_2.5VY_R9M
@ 0.1U_25V_K_X7R_0402 27 2 2 1 1

5 3
2
1
VR_SVID_DAT_R PHASE1
PR3408 1 2 0_0402_5% 4
12 VR_SVID_DAT VDIO Ripple=30mV(1A~5A)

PC3418
PL3400 +
PR3412
Ripple=15mV(5A~TDC)

AON6324_DFN8-5

AON6324_DFN8-5
P_VCCIN_LG1_30

2
@ 28 2.2_0805_5% PJ3402 PJ3403
VR_SVID_ALRT#_R LGAT E1 2
PR3413 1 2 0_0402_5% 3 EMC_NS@ JUMPER JUMPER
12 VR_SVID_ALRT# ALERT PR3415
TDC=39A Iccmax=70A

PQ3401

PQ3402
@ @

1
4 P_VCCIN_LG1_30 4
0_0402_5% PR3416 1
@ @ 4.22K_0402_1%
OCP=112A
VR_SVID_CLK_R
PR3414 1 2 0_0402_5% 5 1 2 1 2 PC3408
12 VR_SVID_CLK VCLK
1200P_50V_K_X7R_0402
Max Overshoot:200mv/500us
P_VCCIN_ISEN1P_10 2 EMC_NS@
CPU_VIN 20 PR3417 1 21/16W_1.15K_1%_0402
OVP=VID+400mV

3
2
1

3
2
1
ISEN1P
1 2 @
1 2 P_VCCIN_VIN_10 22 PC3409 0.1U_0402_25V7-K
P_VCCIN_ISEN1P_R_10
CPU_VIN UVP=VID-150mV
VIN 19 P_VCCIN_ISEN1N_10 1 2 P_VCCIN_ISEN1N_R_10
2.2_0402_1%
Fsw=600 Khz

0.1U_0402_25V7-K
ISEN1N

1
PR3418 PR3419

PC3411
680_0402_1% PC3410
0.1U_0402_25V7-K

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
2

0.1U_0201_25V6-K
2 1 1 1
P_VCCIN_BST2_R_30

1
RT3612EB_VREF

PC3412

PC3413

PC3414

PC3453
5
1 2 1 2 12 1 P_VCCIN_BST2_301 2 1 2PC3416 PQ3403
VREF06 BOOT 2

2
PR3421 AON6380_DFN8-5 2 2 2
0.47U_0402_25V-K PR3420 2.2_0603_5% 0.22U_0603_25V7K EMC@
C RT3612EB_VREF PC3415 3.9_0402_1% C
P_VCCIN_IMON_NTC_10 32 P_VCCIN_UG2_30
1 4 @ +VCCIN
UGAT E2

2200P_0402_50V7K
@
13.7K_0402_1% 0.22UH_CMMS063T-R22MS2R107_26A_20%

PC3445
RT3612EB_VREF 1 2 1 2 P_VCCIN_IMON_R_10 1 P_VCCIN_IMON_10
PR3423 2 11
PR3422 @ IM ON 31 P_VCCIN_PH2_S 2 2 1 20A

5 3
2
1
14K_0402_1% PH3400 PHASE2

330U_D2_2.5VY_R9M
5

1
@ 100K_0402_1%_NCP15WF104F03RC PL3401 1
1 2 PR3425

AON6324_DFN8-5

AON6324_DFN8-5
24.9K_0402_1% 1/16W_86.6K_1%_0402

P_VCCIN_LG2_30

2
PR3424 30 2.2_0805_5% PJ3400 PJ3401 +

PC3417
LGAT E2
1

22.1K_0402_1% EMC_NS@ JUMPER JUMPER

PQ3404

PQ3405
1.33K_0402_1%

34K_0402_1%
PR3426

PR3427

PR3428

@ P_VCCIN_SET1_10 P_VCCIN_LG2_30 4 @ @

1
8 PR3429 PR3430 4 1 2
@ SET 1 0_0402_5% 4.22K_0402_1%
1 @ 2 1 2 PC3419
2

P_VCCIN_ISEN2P_10 1200P_50V_K_X7R_0402
17 PR3431 1 21/16W_1.15K_1%_0402 2 EMC_NS@

3
2
1

3
2
1
ISEN2P
P_VCCIN_SET2_10 @
1/16W_1.18K_1%_0402

7 1 2 PC3420
SET 2 P_VCCIN_ISEN2P_R_10
1

0.1U_0402_25V7-K
18 P_VCCIN_ISEN2N_10 1 2 P_VCCIN_ISEN2N_R_10
PR3432

1/16W_28.7K_1%_0402

ISEN2N
1

2
PR3434

@ @ PR3433 PC3421
680_0402_1% 0.1U_0402_25V7-K
2

1
1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
P_VCCIN_SET3_10 6 14
PR3436
2

SET 3 VSEN
1

1
180P_25V_J_NPO_0402
150_0402_1%
PR3437

PC3426

PC3427

PC3428

PC3429

PC3430

PC3431

PC3432

PC3433

PC3434

PC3435

PC3436

PC3437

PC3438

PC3439

PC3440

PC3441

PC3442

PC3443
PC3422
1

PC3423 1 2 100P_0402_50V8J 1 2
1/16W_29.4_1%_0402

2
RT3612EB_VREF 15 P_VCCIN_COMP_10
PR3438

@ 110K_0402_1% COM P 1 2 1 2
VCCIN_SENSE 12
2

2P_VCCIN_TSEN_R_10 P_VCCIN_TSEN_10
1

1 2 PR3442 1 21 PR3439 PR3440

1/16W_374_1%_0402

T SEN
PR3443

PR3441 1/16W_28K_1%_0402 1/16W_8.45K_1%_0402 @ @ @ @ @ @ @ @ @ @

P_VCCIN_FB_10
2

2
19.6K_0402_1% 16 @
1 2 1 2
PH3401 FB @ PR3444 PC3425 @ PC3424
2 1 16.9K_0402_1% 470P_0402_50V7K 1000P_0402_50V7K
2

1
100K_0402_1%_NCP15WF104F03RC 33 13
GND RGND VSSIN_SENSE 12
Place close to MOSFET 34+8；
1

PR3445
14K_0402_1%

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
PC3447

PC3452

PC3458

PC3460

PC3461

PC3462

PC3463
2

PC3444

PC3446

PC3449

PC3450

PC3451

PC3455

PC3457
1

2
PR3449
1/16W_237_1%_0402 @
B @ @ @ @ @ @ @ B
@ @ @ @ @ @
2

1 1 1 1 1 1 1 1 1 1 1

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
PC3464

PC3465

PC3466

PC3467

PC3468

PC3469

PC3473

PC3476

PC3477

PC3478

PC3479
2 2 2 2 2 2 2 2 2 2 2

@ @ @ @ @ @ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 56 of 3
5 4 3 2 1
 A B C D

V9B+
PJ9902 @
1.5A 2 1 PC9902

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
2 1 PR9900 0.1U_0603_25V7-M
+1.35V_BST 1 2+1.35V_BST_R 1 2
JUMP_43X79 1 1

PC9900

PC9901
OPT@ 10_0603_5% OPT@
PD9900
OPT@ +1.35VGS
2 2

18
PU9900

5
1 2 PL9900
PJ9901
0.68UH_PCMB063T-R68MS_16A_20%
8A

VBOOT
AGND
LRB751V-40T1G_SOD323-2 +1.35V_VIN 12 3 +1.35V_LX 1 2 +1.35V_P 2 1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
VIN4 SW_1 2 1
OPT_NS@ OPT@ OPT@
+1.35V_EN
OPT@ JUMP_43X118
1 23 FBVDDQ_PWR_EN 1 2 16 4 1 1 1 1 1 1 1
EN4 SW_2

PC9905

PC9906

PC9907

PC9908

PC9909

PC9910
PR9901 @

1
100K_0402_5% 1 2 PC9903 OPT@ PC9904 OPTNS@
15 +1.35V_FB 1 2
OPT@ 0.022U_0402_25V7K
FB
PR9902
25 2.2_0603_5% 2 2 2 2 2 2

1
NC_3 0.1U_0402_25V6 EMC_OPTNS@

OPTNS@

OPTNS@
23

OPT@

OPT@

OPT@

OPT@
PR9903

2
22 NC_2

+1.35V_SN
1K_0402_1%
NC_1
OPT@

1
6

2
PGND_1
+5VALW

1
7 PR9904
2 1 PC9911 24 PGND_2 PC9912 +1.35V_FB_1 42.2K_0402_1%
VCC_SW 8
1U_0402_6.3V6K 1000P_0402_50V7K OPT@

2
PGND_3
OPT@ EMC_OPTNS@ PC9913
PR9905 0_0402_5% 9 560P_0402_50V7-K
1.8VGS_PWR_EN 1 2 MAIN_PWR_EN 19 PGND_4
OPT@
Vout=1.35V±5%

2
23,26 1.8VGS_PWR_EN +3.3V_1.8V_AON EN2 10
@
PGND_5 Vset=1.36V±2%

2
PC9914 1 2 PC9915 21 11 +1.35V_FB
0.1U_0402_25V6 1U_0402_6.3V6K VIN2 PGND_6 OCP>12A
0.5A

1
PJ9907
OPT_NS@ OPT_NS@ +3V_1.8VGS
Vref=0.6V

1
20 +3V_1.8VGS_R 2 1
VOUT2 @ 2 1 0.5A PR9907
PXS_PWR_EN_R 28 1 2 31.6K_0402_1%
OVP=(1.25~1.35)*Vref
23 PXS_PWR_EN_R EN3 JUMP_43X39
PC9917 OPT@
UVP=(0.7~0.8)*Vref

2
+3.3V_1.8V_AON_IN PJ9906
PC9916 1U_0402_6.3V6K OPT@ +3.3V_1.8V_AON
2 0.1U_0402_25V6 1 26 +3.3V_1.8V_AON_R 2 1
OPT_NS@
VIN3_1 VOUT3_1 @ 2 1 Fsw=700Khz
2 27 1A
1A LSW1 RDS=36~50mohm,Io=0.5A
1

VIN3_2 VOUT3_2 JUMP_43X39

1
29 PC9918
PC9919 VIN3_3
1U_0402_6.3V6K
LSW2 RDS=18~25mohm,Io=1A

PGOOD
TH_ALT
1U_0402_6.3V6K OPT@ LSW3 RDS=5~7mohm,Io=3.5A

2
VCC
OPT_NS@

14

17

13
+1.35V_VCC
2

1
2 2

PR9908 PR9909
100K_0402_1% 100K_0402_1%
OPT_NS@ OPT_NS@

2
1
PC9920
1U_0402_6.3V6K

2
OPT@

+3.3V_1.8V_AON_IN
+3VS
PR9910
2 1
0_0402_5%
+1.8VALW OPTN16@
PR9911
2 1
0_0402_5%
OPTN17@

3
+3VALW 3

+3VALW

2
PC9921 PR9912 +1.0VGS
1U_0402_6.3V6K 100K_0402_5%
+1.8VALW

2
OPT@ PJ9905
1A

1
PU9901 +1.0V_P 2 1
1A

1/20W_100K_1%_02011/20W_24.9K_1%_0201
PJ9908 6 7 @ 2 1
2 1 +1.0VGS_VIN 5 VCNTL POK
Vout=1.0V±5%

220P_0402_50V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2
2 1 VIN 3 JUMP_43X39

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1
VOUT1

PR9913

PC9924
4 @
1

JUMP_43X39 VOUT2
PC9922

PC9923

1
@ 9 EN 2 OPT@

GND

2
EPAD FB

PC9925

PC9926
2

1
@

2
+1.0V_FB

1
@ OPT@
APL5930CKAI-TRG_SO8 @ OPT@

1
OPT@

PR9915
PR9916 1 2 0_0402_5% @ 1.0VGS_EN OPT@

2
23 PXE_VDD_EN_R

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR-VGA-PMIC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 57 of 5
A B C D
 5 4 3 2 1

PWM-VID Specification
N17 Config N16 Config B RT8816 PSI UP1666 PSI Phase Configuration
Vmin(V) 0.3 0.6 1.6V~5.5V 1.6~5.5V 2Phase CCM
Vmax(V) 1.3 1.2 1.08~1.35V 1~1.4V 2Phase DEM
Vboot(V) 0.8 0.9 0.7~0.88V 0.4V~0.8V 1Phase CCM
Vstep(mV) 6.25 6.25 0~0.4V 0~0.2V 1Phase DEM
N(level) 160 96
Fpwm(KHz) 675 1.125 V9B+
Tdmin(nS) 9.26 9.26 +VGA_CORE_VIN PJ7000
D 1 2 D
T(uS) <100 <100 1 2 4A
JUMP_43X79
+5VALW @

1U_25V_K_X5R_0402
0.1U_0201_25V6-K
1 1 1

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
EMC_OPTNS@

1
PC7000

PC7001

PC7002

PC7003
2
PQ7000

1
OPT@ 2 2 2

5
PR7000 AON6380_DFN8-5
PU7000
2_0603_5%
OPT@ @
OPT@ OPT@

2
NVVDD_PVCC 18
PVCC 2 NVVDD_HG1 4
UGATE1

1
+3.3V_1.8V_AON PC7004 PR7003
PC7005
1U_0402_6.3V6K 2.2_0603_5% 0.22U_0603_25V7K
1 NVVDD_BS1 1 2 1 2
OPT@ OPT@