ISSCC 2005 / SESSION 5 / WLAN TRANSCEIVERS / 5.

5.2 An 802.11g WLAN SoC As shown in Fig. 5.2.2, the transmitter utilizes the same sliding-
IF frequency plan as the receiver. The digital baseband signal is
converted to a pair of analog currents by two 11b 176MS/s cur-
Srenik Mehta1, David Weber1, Manolis Terrovitis1, Keith Onodera1, rent-steering DACs. The lower 2 LSBs of the DACs enable fine
Michael Mack1, Brian Kaczynski1, Hirad Samavati1, Steve Jen1, transmit power control in the digital domain. The DAC current
Weimin Si1, MeeLan Lee1, Kalwant Singh1, Suni Mendis1, sources are implemented with cascoded PMOS I/O devices on a
Paul Husted1, Ning Zhang1, Bill McFarland1, David Su1, 3.3V supply. The current switches are driven by full-swing CMOS
Teresa Meng2, Bruce Wooley2 logic from a 1.8V supply. A third-order Butterworth gm-C low-pass
filter attenuates the DAC spectral images. The baseband signal
1
Atheros Communications, Sunnyvale, CA is up-converted by a pair of dual-conversion mixers to 2.4GHz. As
2
Stanford University, Stanford, CA shown in Fig. 5.2.2, image-reject mixers are not used in the RF
up-conversion because the image at 800MHz, which is not in the
The rapid adoption of the IEEE 802.11g wireless LAN (WLAN) FCC restricted band, is sufficiently filtered by the bandpass char-
standard has created a demand for low-cost, small-form-factor acteristics of the RF buffer, which is capable of delivering a satu-
implementations. An integrated SoC that implements all of the rated output power of 12dBm. Figure 5.2.5 shows the spectral
functions of an 802.11g WLAN in a 0.18µm CMOS technology is mask for a –2dBm transmit output with an error vector magni-
presented in this paper. As shown in Fig. 5.2.1, the SoC consists tude of –28dBc. The transmitted output has more than 10dB of
of a 2.4GHz RF transceiver, analog baseband filters, data con- adjacent channel power rejection margin compared to the IEEE
verters, digital physical layer (PHY), and media access controller 802.11g specifications for an external power amplifier.
(MAC). This IC essentially connects the RF antenna to the digital
host computer. The one-chip solution reduces overall package cost In a SoC, interconnection between the analog and digital blocks
and form factor. In addition, integration eliminates the area and is no longer constrained by the limited number of package pins.
power associated with driving package pins in a multi-chip imple- This design leverages the integration to implement a closed-loop
mentation [1,2]. Furthermore, the merging of the analog and digi- RF calibration. An RF loop-back path, shown in Fig. 5.2.2, is pro-
tal blocks on the same chip enables a wide digital-analog inter- vided from the output of the transmit RF mixer to the input of the
face that allows for the use of sophisticated digital signal pro- receive RF mixer. During calibration, a predetermined digital
cessing techniques to mitigate analog and RF impairments [2,3]. sequence is transmitted and looped back to the receiver. The
received digital code is used to correct for RF impairments such
Figure 5.2.2 shows the block diagram of the RF transceiver. A as DC offset, I/Q mismatch, and RF carrier leak. The calibration
sliding-IF dual-conversion architecture is employed for both the cycle eases the matching requirements of the transceiver, there-
receiver and transmitter. The RF local oscillator (LORF) frequen- by reducing power and area.
cy at 2/3 fRF (1.6GHz) and IF local oscillator (LOIF) frequency at
1/3 fRF (0.8GHz) are generated from an integer-N synthesizer A major challenge in an SoC is to prevent the corruption of sen-
operating at 3.2GHz (twice the LORF frequency). The voltage-con- sitive analog and RF signals by digital switching noise. Although
trolled oscillator (VCO) is a varactor-tuned, inductively loaded the RF and digital baseband circuits are widely separated in fre-
LC tank. The choice of a VCO frequency at 2⋅LORF reduces the quency, crosstalk can occur when the supply and bias voltages are
size of the on-chip spiral inductor. The VCO output is divided by modulated [4]. The use of fully differential analog and RF circuits
two and four to generate LORF and LOIF. Inductive tuning is not provides first-order rejection of common-mode digital switching
used in the high-speed dividers because of the high fT available in noise. Separate, or star-connected, power supplies are used to
the 0.18µm process. The loop filter is integrated on-chip using reduce supply crosstalk. For the more sensitive circuits, such as
poly resistors and NMOS device capacitors. The synthesizer those in the frequency synthesizer, further reduction of supply
phase noise measured at the transmitter output, shown in Fig. crosstalk is accomplished with on-chip voltage regulators. To
5.2.3, is –105dBc/Hz at 100kHz offset. reduce substrate coupling, a deep N-well trench of 150µm is used
between the digital circuits and the RF transceiver. The IC is
The receiver in Fig. 5.2.2 converts the incoming RF signal to packaged in a 224-pin ball grid array package with separate ana-
quadrature baseband outputs, while providing enough gain and log and digital ground substrate planes. Digital output pins are
interference rejection. The frequency allocation results in routed orthogonal to sensitive RF and analog signals. To avoid
approximately 1.6GHz (2/3 fRF) frequency separation between the coupling on the package, the sensitive VCO control voltage node
incoming RF signal and the image channel. As a result, the band- is kept completely on silicon with an integrated loop filter.
pass elements used in the RF stages provide adequate image
rejection, thereby eliminating the need for an explicit image Figure 5.2.6 shows a die micrograph of the single-chip WLAN
rejection filter. The low-noise amplifier (LNA) consists of a cas- SoC. It occupies a total die area of 41mm2 in a standard 0.18µm
coded differential pair with inductive degeneration and loading. CMOS technology with 72% of the chip being digital logic. The
The LNA has an adjustable RF gain to accommodate large RF measured performance of the radio is summarized in Fig. 5.2.7.
input signals. In the low gain setting, 75% of the bias current is The single-chip SoC has successfully implemented an IEEE
diverted from the output load to the supply, which results in a 802.11g-compliant WLAN.
12dB gain reduction. Figure 5.2.4 shows a circuit diagram of the
dual down-conversion mixers. The RF mixer down-converts the Acknowledgment:
2.4GHz signal to an IF frequency of 800MHz. NMOS diode loads, The implementation of an integrated WLAN SoC requires the effort of a
large engineering team for RF, analog, digital, architecture, algorithms,
which improve the IF gain stability over process and tempera-
software, and system design. The authors wish to acknowledge the effort
ture, are used instead of bulky inductors. The NMOS loads are of the entire Wireless LAN team at Atheros.
placed in deep N-wells to allow a source-to-bulk connection that
removes transistor body effects. A common-mode feedback circuit References:
biases the load transistors, setting the output common-mode volt- [1] M. Zargari et al., “A single-chip dual-band, tri-mode CMOS transceiver
age and allowing direct coupling to the PMOS differential pairs for IEEE 802.11a/b/g WLAN,” ISSCC Dig. Tech. Papers, pp. 96-97, Feb.,
of the IQ mixer. The output of the mixer is low-pass filtered by a 2004.
[2] J. Thomson et al., “A 5-GHz CMOS Transceiver for IEEE 802.11a
programmable-gain fourth-order Butterworth gm-C filter with on- Wireless LAN,” ISSCC Digest of Technical Papers, pp. 126-127, Feb., 2002.
chip frequency tuning [1]. Two 9b pipelined ADCs digitize the [3] A. Behzad et al., “Direct-conversion CMOS transceiver with automatic
analog signals for processing by the PHY. The measured receive frequency control for 802.11a wireless LANs,” ISSCC Dig. Tech. Papers,
chain NF is 5.5dB. The overall receiver sensitivity is –92dBm and pp. 356-357, Feb., 2003.
–73dBm for data rates of 6Mb/s and 54Mb/s, respectively. [4] M. Xu et al., “Measuring and modeling the effects of substrate noise on
the LNA for a CMOS GPS receiver,” IEEE J. Solid-State Circuits, vol. 36,
no. 3, pp. 473-485, March, 2001.

94 • 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE.

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 ISSCC 2005 / February 7, 2005 / Salon 9 / 1:30 PM

RECEIVER DAC
LOIF I Offset
DAC Control
I 9
ADC
40MHz
ADC crystal
Receiver

Digital Baseband PHY

Rx Gain Control

ADC LNA RFVGA 9

Interface Logic
ADC
REG REG

Digital MAC
PCI Bus Q
to Host
Computer
LORF
LOIF
DAC

DAC
Q Offset
Control
Loop Charge Phase
Ref
Div
5
VCO
Synthesizer 4
Filter Pump Detect
f
LOIF
Div. LORF Div. 3 RF
RF by 2 by 2
Loopback
16/17 P&S Re
LOIF Prescaler Counters time
DAC
Transmitter I
DAC
11
SYNTHESIZER
DAC
Tx Gain Control

TRANSCEIVER PA RFVGA IFVGA 11

DAC
Q
LORF
TRANSMITTER LOIF

Figure 5.2.1: Block diagram of an integrated IEEE 802.11g WLAN SoC. Figure 5.2.2: 2.4GHz CMOS transceiver.

Synthesizer Phase Noise @ 2.412GHz BIAS2

-95

-100
+ -
-105
dBc/Hz

-110 COMMON-MODE LOIF-

FEEDBACK

...
LOIF+ LOIF+
-115
LORF LORF
-120
LORF
RF+ RF-
-125 M1 M2
IBBQ+ IBBQ-
10 100 1000
BIAS1
kHz

Figure 5.2.3: Measured frequency synthesizer phase noise at 2.4GHz. Figure 5.2.4: Schematic of receive dual down-conversion mixer.

TX RX
DAC
ISOLATION

PHY SYNTH
ADC
BIAS

(a) CCK mode (b) OFDM mode MAC

Figure 5.2.5: Measured transmit output spectral mask for a –2dBm

output in (a) CCK (b) OFDM modes. Figure 5.2.6: Chip micrograph of WLAN SoC in 0.18µm CMOS technology.
Continued on Page 586

DIGEST OF TECHNICAL PAPERS • 95

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 ISSCC 2005 PAPER CONTINUATIONS

Transmit Mode Power Dissipation 180mA @ 1.8V 50mA @ 3.3V

RF Transceiver alone (excludes DAC) 128mA @ 1.8V 10mA @ 3.3V
Receive Mode Power Dissipation 175mA @ 1.8V 60mA @ 3.3V
RF Transceiver alone (excludes ADC) 65mA @ 1.8V 20mA @ 3.3V
Transmit EVM -28dBc @ -1dBm & 54 Mb/s
Receive Sensitivity -95dBm @ 1Mb/s
-92dBm @ 6Mb/s
-73dBm @ 54Mb/s
Receiver Noise Figure 5.5dB
Phase Noise (2.412GHz) -105dBc/Hz @ 100kHz offset
-120dBc/Hz @ 1MHz offset
Technology Standard 0.18µm CMOS
Die Size 41 sq mm
RF Transceiver + ADC, DAC, PLL 11.5 sq mm
Package 224-pin BGA

Figure 5.2.7: Summary of measured WLAN performance.

586 • 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE.
Authorized licensed use limited to: Yihui Chen. Downloaded on December 16,2020 at 06:54:47 UTC from IEEE Xplore. Restrictions apply.