Operating Systems

COMS(3010A)
Paging

Branden Ingram
[email protected]
 Recap
• Memory Virtualisation
• Address Translation
• Segmentation
• Free Space Management
 Paging

• In Operating Systems, Paging is a storage mechanism used to retrieve processes

from the secondary storage into the main memory in the form of pages.
 Paging

• In Operating Systems, Paging is a storage mechanism used to retrieve processes

from the secondary storage into the main memory in the form of pages.

• The main idea behind the paging is to divide each process(Address Space) into a
fixed-sized unit called a page
 Paging

• In Operating Systems, Paging is a storage mechanism used to retrieve processes

from the secondary storage into the main memory in the form of pages.

• The main idea behind the paging is to divide each process(Address Space) into a
fixed-sized unit called a page

• Segmentation: variable size of logical segments(code, stack, heap, etc.)

 Paging

• In Operating Systems, Paging is a storage mechanism used to retrieve processes

from the secondary storage into the main memory in the form of pages.

• The main idea behind the paging is to split each process(Address Space) into a
fixed-sized unit called a page

• Segmentation: variable size of logical segments(code, stack, heap, etc.)

• With paging, physical memory is also split into some number of pages called a page
frame.
 Paging Translation ?

• Page table per process is needed to translate the virtual address to physical address.

• Similar to the segment register

Segment Register

Segment Base Size

Code 256KB 4KB
Heap 260KB 60KB
Stack 128KB 64KB
 Paging Translation ?

• Page table per process is needed to translate the virtual address to physical address.

• Similar to the segment register

Page Table
Segment Register Page Page Frame
Segment Base Size 0 3
Code 256KB 4KB 1 7
Heap 260KB 60KB
Stack 128KB 64KB 2 5
3 2
 Advantages of Paging

• Flexibility: Supporting the abstraction of address space effectively

• Don’t need assumption how heap and stack grow and are used.
 Advantages of Paging

• Flexibility: Supporting the abstraction of address space effectively

• Don’t need assumption how heap and stack grow and are used.

• Simplicity: ease of free-space management

• The page in address space and the page frame are the same size.
• Easy to allocate and keep a free list
 Paging : Example
0
• 128-byte physical memory with 16 bytes page frames Operating System Page Frame 0
(code, data, etc.)
• 64-byte address space with 16 bytes pages 16
Free Page Frame 1
0 32
Page 0 Page 3 Page Frame 2
16 48
Page 1 Page 0 Page Frame 3
32 64
Page 2 Free Page Frame 4
48 80
Page 3 Page 2 Page Frame 5
64 96
64 byte Address Space Free Page Frame 6
112
Page 1 Page Frame 7
128
64 byte Address Space placed in
Physical Memory
 Address Translation : Example

• Two components in the virtual address

• VPN: virtual page number
• Offset: offset within the page
Va5 Va4 Va3 Va2 Va1 Va0

VPN Offset
 Address Translation : Example

• Two components in the virtual address

• VPN: virtual page number
• Offset: offset within the page
Va5 Va4 Va3 Va2 Va1 Va0

VPN Offset

• Example: virtual address 21 in 64-byte address space

Va5 Va4 Va3 Va2 Va1 Va0

0 1 0 1 0 1

VPN Offset
 Address Translation : Example

• Example: virtual address 21 in 64-byte address space

Va5 Va4 Va3 Va2 Va1 Va0

Virtual Address 0 1 0 1 0 1

VPN Offset
 Address Translation : Example

• Example: virtual address 21 in 64-byte address space

Va5 Va4 Va3 Va2 Va1 Va0

Virtual Address 0 1 0 1 0 1

VPN Offset

How do I know the Virtual Address is x bits ?

Address space= 64bytes
log_2(64) = 6
 Address Translation : Example

• Example: virtual address 21 in 64-byte address space

Va5 Va4 Va3 Va2 Va1 Va0

Virtual Address 0 1 0 1 0 1

VPN Offset

How do I know the Virtual Address is x bits ?

Address space= 64bytes
log_2(64) = 6 (Virtual Address)
How do I know its 2 bits for VPN and 4 bits for Offset
Page Size = 16
log_2(16) = 4 (offset)
 Address Translation : Example

• Example: virtual address 21 in 64-byte address space

Va5 Va4 Va3 Va2 Va1 Va0

Virtual Address 0 1 0 1 0 1

VPN Offset

How do I know the Virtual Address is 6 bits ?

Address space= 64bytes
log2(64) = 6 (Virtual Address)
How do I know its 2 bits for VPN and 4 bits for Offset
Page Size = 16bytes
log2(16) = 4 (offset)
How do I know 21 = 010101
2110 = 101012(5bits) = 0101012(6bits)
 Address Translation : Example

• Example: virtual address 21 in 64-byte address space

Va5 Va4 Va3 Va2 Va1 Va0

Virtual Address 0 1 0 1 0 1

VPN Offset

Address Translation

Pa6 Pa5 Pa4 Pa3 Pa2 Pa1 Pa0

1 1 1 0 1 0 1

Physical Address PFN Offset log2(128) = 7bits (Physical Address)

 Paging : Example
0
• 128-byte physical memory with 16 bytes page frames Operating System Page Frame 0
(code, data, etc.)
• 64-byte address space with 16 bytes pages 16
Free Page Frame 1
0 32
Page 0 Page 3 Page Frame 2
16 48
Page 1 Page 0 Page Frame 3
32 64
Page 2 Free Page Frame 4
48 80
Page 3 Page 2 Page Frame 5
64 96
64 byte Address Space Free Page Frame 6
112
VPN = 01 Page 1 Page Frame 7
PFN = 3bits 128
64 byte Address Space placed in
Physical Memory
 Paging : Example
0
• 128-byte physical memory with 16 bytes page frames Operating System Page Frame 0
(code, data, etc.)
• 64-byte address space with 16 bytes pages 16
Free Page Frame 1
0 32
Page 0 00 Page 3 Page Frame 2
16 48
Page 1 01 Page 0 Page Frame 3
32 64
Page 2 10 Free Page Frame 4
48 80
Page 3 11 Page 2 Page Frame 5
64 96
64 byte Address Space Free Page Frame 6
112
VPN = 01 Page 1 Page Frame 7
PFN = 3bits 128
64 byte Address Space placed in
Physical Memory
 Paging : Example
0
• 128-byte physical memory with 16 bytes page frames Operating System 000
(code, data, etc.)
• 64-byte address space with 16 bytes pages 16
Free 001
0 32
Page 0 00 Page 3 010
16 48
Page 1 01 Page 0 011
32 64
Page 2 10 Free 100
48 80
Page 3 11 Page 2 101
64 96
64 byte Address Space Free 110
112
VPN = 01 Page 1 111
PFN = 3bits 128
64 byte Address Space placed in
Physical Memory
 Address Translation : Example

• Example: virtual address 21 in 64-byte address space

Va5 Va4 Va3 Va2 Va1 Va0

Virtual Address 0 1 0 1 0 1

VPN Offset

Address Translation

Pa6 Pa5 Pa4 Pa3 Pa2 Pa1 Pa0

1 1 1 0 1 0 1

Physical Address PFN Offset

 Paging Translation ?

• Page table per process is needed to translate the virtual address to physical address.

• Similar to the segment register

Page Table

Page Page Frame

0 3
1 7
2 5
3 2
 Ok well where are these tables stored?

• Page tables can get large quickly

• 32 bit address space with 4KB pages, 20bits for the VPN
• 4MB = 220 entries x 4 bytes per page table entry

• This is too large to store entries in dedicated CPU register

 Ok well where are these tables stored?

• Page tables can get large quickly

• 32 bit address space with 4KB pages, 20bits for the VPN
• 4MB = 220 entries x 4 bytes per page table entry

• And Therefore all of that is stored in memory

 Page Table in Kernel Memory
0
Page Table 1 Operating System Page Frame 0
(code, data, etc.)
16
Page Table 2 Free Page Frame 1

32
Page Table 3 Page 3 Page Frame 2
48
Page Table 4 Page 0 Page Frame 3
64
Free Page Frame 4
80
Page 2 Page Frame 5
96
Free Page Frame 6
112
Page 1 Page Frame 7
128
64 byte Address Space placed in
Physical Memory
 What is in the Page Table?

• The page table is just a data structure that is used to map the virtual address to the
physical address
Page Table

Page Page Frame

0 3
1 7
2 5
3 2

• In its simplest form it is just an array

 What is in the Page Table?

• The page table is just a data structure that is used to map the virtual address to the
physical address
Page Table

Page Page Frame Page table Entry

0 3
1 7
2 5
3 2

• In its simplest form it is just an array

• The OS indexes the array by VPN and looks up the page table entry
 Page Table Entry : Example x86

PWT

R/W
PCD

U/S
PAT
PFN Avail

D
A

P
• P: present bit
• R/W: read/write bit
• U/S: supervisor
• A: accessed bit
• D: dirty bit
• PFN: the page frame number
 Page Table Entry : Example x86

PWT

R/W
PCD

U/S
PAT
PFN Avail

D
A

P
• Valid Bit(P): Indicating whether the particular translation is valid.

• Protection Bit(R/W): Indicating whether the page could be read from,

written to, or executed from

• Present Bit(P): Indicating whether this page is in physical memory or on

disk(swapped out)

• Dirty Bit(D): Indicating whether the page has been modified since it was
brought into memory

• Reference Bit(Accessed Bit -A): Indicating that a page has been

accessed
 What does it mean for you to install a
32/64bit OS

• Each byte of main storage has an address.

• Most modern processors use 32-bit addresses, so there are 2^32 possible
addresses.

Think of main storage as if it were an array:

byte[0x00000000 ... 0xFFFFFFFF] mainStorage;

What is the issue with Paging?
 What is the issue with Paging?

• Size – Page tables and entries take up a lot of space in memory

 What is the issue with Paging?

• Size – Page tables and entries take up a lot of space in memory

• Slow – 2 references per memory references
 Paging is Slow?

• We need to first reference the correct page table (1 reference)

• To find a location of the desired PTE, the starting location of the
page table is needed

• Then we can reference the correct page table entry (1 reference)

 Paging is Slow?

• We need to first reference the correct page table (1 reference)

• To find a location of the desired PTE, the starting location of the
page table is needed

• Then we can reference the correct page table entry (1 reference)

• Therefore, for every memory reference, paging requires the OS to perform one
extra memory reference
 Accessing Memory with Paging

1 // Extract the VPN from the virtual address

2 VPN = (VirtualAddress & VPN_MASK) >> SHIFT

3 // Form the address of the page-table entry (PTE)

4 PTEAddr = PTBR + (VPN * sizeof(PTE))

5 // Check if process can access the page

6 if (PTE.Valid == False)
7 RaiseException(SEGMENTATION_FAULT)

8 else if (CanAccess(PTE.ProtectBits) == False)

9 RaiseException(PROTECTION_FAULT)

10 else
11 // Access is OK: form physical address and fetch it
12 offset = VirtualAddress & OFFSET_MASK
13 PhysAddr = (PTE.PFN << PFN_SHIFT) | offset
14 Register = AccessMemory(PhysAddr)
 Accessing Memory with Paging

Example : A Simple Memory Access

int array[1000];
...
for(i = 0; i < 1000; i++)
array[i] = 0;

Compile and Execute

prompt> gcc –o array array.c –Wall -o
prompt> ./array

Resulting Assembly code

0x1024 : movl $0x0, (%edi,%eax,4)
0x1028 : incl %eax
0x102c : cmpl $0x03e8,%eax
0x1030 : jne 0x1024
 A Virtual( And Physical ) Memory Trace
1224
Page Table[39]

Page Table(PA)
1174

1124
Page Table[1]
1074

1024
 A Virtual( And Physical ) Memory Trace
1224
Page Table[39]

Page Table(PA)
1174

1124
Page Table[1]
1074

1024
jne
cmp

1124 4196
mov

inc
Code(VA)

Code(PA)
1074 4146

1024 4096
0 10 20 30 40 50

Memory Access
 A Virtual( And Physical ) Memory Trace
1224
Page Table[39]

Page Table(PA)
1174

1124
Page Table[1]
1074

1024

40100 7132
Array(VA)

Array(PA)
mov

40050 7282

40000 7232
jne
cmp

1124 4196
mov

inc
Code(VA)

Code(PA)
1074 4146

1024 4096
0 10 20 30 40 50

Memory Access
 A Virtual( And Physical ) Memory Trace
1224
Page Table[39]

Page Table(PA)
1174

1124
Page Table[1]
1074

1024

40100 7132
Array(VA)

Array(PA)
mov

40050 7282

40000 7232
jne
cmp

1124 4196
mov

inc
Code(VA)

Code(PA)
1074 4146

1024 4096
0 10 20 30 40 50

Memory Access
 A Virtual( And Physical ) Memory Trace
1224
Page Table[39]

Page Table(PA)
1174

1124
Page Table[1]
1074

1024

40100 7132
Array(VA)

Array(PA)
mov

40050 7282

40000 7232
jne
cmp

1124 4196
mov

inc
Code(VA)

Code(PA)
1074 4146

1024 4096
0 10 20 30 40 50

Memory Access
 Paging is Slow?

• We need to first reference the correct page table (1 reference)

• To find a location of the desired PTE, the starting location of the
page table is needed

• Then we can reference the correct page table entry (1 reference)

• Therefore, for every memory reference, paging requires the OS to perform one
extra memory reference

• How can we improve this access speed

 Translation Lookaside Buffers

• Part of the chip’s memory-management unit(MMU).

MMU

Base Register

Bounds Register
 Translation Lookaside Buffers

• Part of the chip’s memory-management unit(MMU).

MMU MMU

Base Register TLB

Page Table Base

Bounds Register
Register
 Translation Lookaside Buffers

Logical
Address

CPU

Address Translation without TLB

 Translation Lookaside Buffers

MMU

TLB

Logical
Page Table Base
Address
Register

CPU

Address Translation without TLB

 Translation Lookaside Buffers

MMU

TLB

Logical
Page Table Base
Address
Register Page Table

Page Page Frame

CPU 0 3
1 7
2 5
3 2
Address Translation without TLB
 Translation Lookaside Buffers

Page 0

MMU Page 1
Page 2
…
TLB
Page n Physical
Address
Logical Physical Memory
Page Table Base
Address
Register Page Table

Page Page Frame

CPU 0 3
1 7
2 5
3 2
Address Translation without TLB
 Translation Lookaside Buffers

• The TLB is a hardware cache of popular virtual-to-physical address translation

Logical
Address

CPU

Address Translation with TLB

 Translation Lookaside Buffers

• The TLB is a hardware cache of popular virtual-to-physical address translation

MMU

TLB
Stores popular v to p

Logical
Address

Page Table Base

Register
CPU

Address Translation with TLB

 Translation Lookaside Buffers

• The TLB is a hardware cache of popular virtual-to-physical address translation

Page 0
MMU
Page 1
Page 2
TLB …
TLB Hit
Stores popular v to p Page n
Logical Physical Memory
Address

Page Table Base

Register
CPU

Address Translation with TLB

 Translation Lookaside Buffers

• The TLB is a hardware cache of popular virtual-to-physical address translation

Page 0
MMU
Page 1
Page 2
TLB …
Stores popular v to p Page n Physical
Address
Logical Physical Memory
TLB Miss
Address
Page Table
Page Table Base
Register Page Page Frame
CPU 0 3
1 7
2 5
3 2
Address Translation with TLB
 TLB ALgortihm

1: VPN = (VirtualAddress & VPN_MASK ) >> SHIFT

2: (Success , TlbEntry) = TLB_Lookup(VPN)
3: if(Success == Ture){ // TLB Hit
4: if(CanAccess(TlbEntry.ProtectBit) == True ){
5: offset = VirtualAddress & OFFSET_MASK
6: PhysAddr = (TlbEntry.PFN << SHIFT) | Offset
7: AccessMemory( PhysAddr )
8: }else RaiseException(PROTECTION_ERROR)

• (1) extract the virtual page number(VPN).

• (2) check if the TLB holds the translation for this VPN.
• (5-8) extract the page frame number from the relevant TLB entry, and form
the desired physical address and access memory.
 TLB ALgortihm

11: }else{ //TLB Miss

12: PTEAddr = PTBR + (VPN * sizeof(PTE))
13: PTE = AccessMemory(PTEAddr)
14: if(PTE.VALID == FALSE){
15: RaiseException(SEGMENTATION_FAULT)
16: else if (CanAccess(PTE.ProtectBits) == False){
17: RaiseException(PROTECTION_FAULT)
18: }else{
19: TLB_Insert( VPN , PTE.PFN , PTE.ProtectBits)
20: RetryInstruction()
21: }
22:}

• (12-13) The hardware accesses the page table to find the translation.
• (19) updates the TLB with the translation.
 A TLB Entry

• The TLB is a hardware cache of popular virtual-to-physical address translation

Page 0
MMU
Page 1
Page 2
TLB …
Stores popular v to p Page n Physical
Address
Logical Physical Memory
TLB Miss
Address
Page Table
Page Table Base
Register Page Page Frame
CPU 0 3
1 7
2 5
3 2
Address Translation with TLB
 A TLB Entry

• TLB is managed by Full Associative method.

• A typical TLB might have 32, 64, or 128 entries.
• Hardware search the entire TLB in parallel to find the desired translation.
• Other bits: valid bits , protection bits, address-space identifier, dirty bit

VPN PFN other bits

Typical TLB entry look like this

Example : Accessing an Array

0: int sum = 0 ;
1: for( i=0; i<10; i++){
2: sum+=a[i];
3: }
 Example : Accessing an Array

OFFSET
00 04 08 12 16
0: int sum = 0 ;
VPN = 00

VPN = 01
1: for( i=0; i<10; i++){
VPN = 03 2: sum+=a[i];
VPN = 04 3: }
VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• When the first array element (a[0]) is
VPN = 08 a[7] a[8] a[9]
accessed, the CPU will see a load to virtual
VPN = 09 address 100
VPN = 10

VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET
00 04 08 12 16
0: int sum = 0 ;
VPN = 00

VPN = 01
1: for( i=0; i<10; i++){
VPN = 03 2: sum+=a[i];
VPN = 04 3: }
VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• When the first array element (a[0]) is
VPN = 08 a[7] a[8] a[9]
accessed, the CPU will see a load to virtual
VPN = 09 address 100
VPN = 10
• The hardware extracts the VPN from this
VPN = 11
(VPN=06), and uses that to check the TLB for a
VPN = 12
valid translation.
VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03

VPN = 04

VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• When the first array element (a[0]) is
VPN = 08 a[7] a[8] a[9]
accessed, the CPU will see a load to virtual
VPN = 09 address 100
VPN = 10
• The hardware extracts the VPN from this
VPN = 11
(VPN=06), and uses that to check the TLB for a
VPN = 12
valid translation.
VPN = 13
• Assuming this is the first time the program
VPN = 14
accesses the array, the result will be a TLB miss.
VPN = 15
• Add new TLB Entry
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03

VPN = 04

VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[1]
VPN = 08 a[7] a[8] a[9]
• The hardware extracts the VPN from this
VPN = 09 (VPN=06), and uses that to check the TLB for a
VPN = 10
valid translation.
VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03

VPN = 04

VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[1]
VPN = 08 a[7] a[8] a[9]
• The hardware extracts the VPN from this
VPN = 09 (VPN=06), and uses that to check the TLB for a
VPN = 10
valid translation.
VPN = 11
• Some good news here: a TLB hit! Because the
VPN = 12
second element of the array is packed next to
VPN = 13
the first, it lives on the same page which had
VPN = 14
already been loaded into the TLB
VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03

VPN = 04

VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[2]
VPN = 08 a[7] a[8] a[9]
• (VPN=06)
VPN = 09 • TLB hit!
VPN = 10

VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03
07 08 -
VPN = 04

VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[3]
VPN = 08 a[7] a[8] a[9]
• (VPN=07)
VPN = 09 • TLB miss!
VPN = 10
• Load translation into TLB
VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03
07 08 -
VPN = 04

VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[4]
VPN = 08 a[7] a[8] a[9]
• (VPN=07)
VPN = 09 • TLB hit!
VPN = 10

VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03
07 08 -
VPN = 04

VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[5]
VPN = 08 a[7] a[8] a[9]
• (VPN=07)
VPN = 09 • TLB hit!
VPN = 10

VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03
07 08 -
VPN = 04

VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[6]
VPN = 08 a[7] a[8] a[9]
• (VPN=07)
VPN = 09 • TLB hit!
VPN = 10

VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03
07 08 -
VPN = 04
08 02 -
VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[7]
VPN = 08 a[7] a[8] a[9]
• (VPN=08)
VPN = 09 • TLB miss!
VPN = 10
• Load translation into TLB
VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03
07 08 -
VPN = 04
08 02 -
VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[8]
VPN = 08 a[7] a[8] a[9]
• (VPN=08)
VPN = 09 • TLB hit!
VPN = 10

VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03
07 08 -
VPN = 04
08 02 -
VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[9]
VPN = 08 a[7] a[8] a[9]
• (VPN=08)
VPN = 09 • TLB hit!
VPN = 10

VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15
 Example : Accessing an Array

OFFSET TLB
00 04 08 12 16

VPN = 00 VPN PFN other bits

VPN = 01
06 03 -
VPN = 03
07 08 -
VPN = 04
08 02 -
VPN = 05

VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6]

• The next access is to a[9]
VPN = 08 a[7] a[8] a[9]
• (VPN=08)
VPN = 09 • TLB hit!
VPN = 10

VPN = 11
The TLB improves performance
due to spatial locality
VPN = 12

VPN = 13
3 misses and 7 hits.
VPN = 14 Thus TLB hit rate is 70%.
VPN = 15
 Locality

• Temporal Locality
• An instruction or data item that has been 1st access is page1.
2nd access is also page1.
recently accessed will likely be re-accessed
soon in the future

Page n
Page 6

Page 7
Page 1

Page 2

Page 3

Page 4

Page 5
…

Virtual Memory
 Locality

• Temporal Locality
• An instruction or data item that has been 1st access is page1.
2nd access is also page1.
recently accessed will likely be re-accessed
soon in the future

Page n
Page 6

Page 7
Page 1

Page 2

Page 3

Page 4

Page 5
…

Virtual Memory

• Spatial Locality
• If a program accesses memory at
address x, it will likely soon access 1st access is page1.
memory near x 2nd access is near by page1.

Page n
Page 1
Page 2

Page 3

Page 4

Page 5
…

Virtual Memory
 Who handles the TLB Miss?

• Well there are 2 approaches

 Who handles the TLB Miss?

• Hardware handle the TLB miss entirely on CISC

 Who handles the TLB Miss?

• Hardware handle the TLB miss entirely on CISC

• The hardware has to know exactly where the page tables are located in
memory.
• The hardware would “walk” the page table, find the correct page-table
entry and extract the desired translation, update and retry instruction.
• hardware-managed TLB.
 Who handles the TLB Miss?

• Hardware handle the TLB miss entirely on CISC

• The hardware has to know exactly where the page tables are located in
memory.
• The hardware would “walk” the page table, find the correct page-table
entry and extract the desired translation, update and retry instruction.
• hardware-managed TLB.

• RISC have what is known as a software-managed TLB

 Who handles the TLB Miss?

• Hardware handle the TLB miss entirely on CISC

• The hardware has to know exactly where the page tables are located in
memory.
• The hardware would “walk” the page table, find the correct page-table
entry and extract the desired translation, update and retry instruction.
• hardware-managed TLB
• Complex Instruction Set Computing

• RISC have what is known as a software-managed TLB

• On a TLB miss, the hardware raises exception( trap handler ).
• Trap handler is code within the OS that is written with the express purpose of
handling TLB miss.
• Reduced instruction set computer
 Ok so job Done?

• The TLB in its current form solves all our problems

 TLB Issue : Context Switching

Page 0
Page 1
Page 2 Insert TLB Entry
access VPN10
Process A …
Page n TLB Table

Virtual Memory VPN PFN valid prot

10 100 1 rwx
- - - -
Page 0 - - - -
Page 1 - - - -
Process B Page 2
…
Page n
Virtual Memory
 TLB Issue : Context Switching

Page 0
Page 1
Page 2
Process A …
Page n TLB Table
VPN PFN valid prot
Virtual Memory
Context 10 100 1 rwx
Switching - - - -
Page 0 10 170 1 rwx
Page 1 - - - -
access VPN10
Process B Page 2 Insert TLB Entry
…
Page n
Virtual Memory
 TLB Issue : Context Switching

Page 0
Page 1
Page 2
Process A …
Page n TLB Table
VPN PFN valid prot
Virtual Memory
10 100 1 rwx
- - - -
Page 0 10 170 1 rwx
Page 1 - - - -
Process B Page 2
… Can’t Distinguish which entry is
Page n meant for which process
Virtual Memory
 TLB Issue : Page Sharing

• Two processes share a page.

• Process 1 is sharing physical page 101 with Process2
• P1 maps this page into the 10th page of its address space
• P2 maps this page to the 50th page of its address space

VPN PFN valid prot

10 101 1 rwx Sharing of pages is
useful as it reduces the
- - - -
number of physical
50 101 1 rwx pages in use.
- - - -
 TLB Issue : Context Switching - Solution
• Provide an address space
identifier(ASID) field in the TLB Page 0
Page 1
Page 2
Process A …
TLB Table
Page n
VPN PFN valid prot ASID
Virtual Memory
10 100 1 rwx 1
- - - - -

Page 0 10 170 1 rwx 2

Page 1 - - - - -

Process B Page 2
…
Page n
Virtual Memory
What happens when we want to add a new
entry
• Problem – We need to add a new entry to the TLB
• Well where do we put it and if needed which entry do we replace
 TLB Issue : Replacement Policy

• In order to add new entries a replacement policy is used

• The general idea with these policies is that you want to minimize the miss rate and
hence maximise the hit rate
 TLB Issue : Replacement Policy

• In order to add new entries a replacement policy is used

• The general idea with these policies is that you want to minimize the miss rate and
hence maximise the hit rate

• LIFO
• FIFO
• Random
• LRU
 TLB Issue : Replacement Policy - Solution

• LRU (LEAST RECENTLY USED)

• Evict an entry that has not recently been used.

• Take advantage of locality in the memory-reference stream
 TLB Issue : Replacement Policy - Solution

• LRU (LEAST RECENTLY USED)

• Evict an entry that has not recently been used.

• Take advantage of locality in the memory-reference stream

• Add a register to every page frame - contain the last time that the page in that
frame was accessed
• Use a "logical clock" that advance by 1 tick each time a memory reference is
made.
• Each time a page is referenced, update its register
 TLB Issue : Replacement Policy - Solution

• LRU (LEAST RECENTLY USED)

• Evict an entry that has not recently been used.
• Take advantage of locality in the memory-reference stream

Page Reference Row

7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0

1 7 1 7 1 7 4 2 4 2 4 2 4 2 8 4 8 4 8 4 11 0 11 0 11 0 14 1 14 1 14 1
Page Frame:

2 0 2 0 2 0 5 0 5 0 7 0 7 0 7 0 10 3 10 3 12 3 12 3 12 3 12 3 16 0
3 1 3 1 3 1 6 3 6 3 6 3 9 2 9 2 9 2 9 2 13 2 13 2 15 2 15 2

Total 11 TLB miss

 A Real TLB Entry

All 64 bits of this TLB entry(example of MIPS R4000)

0 1 2 3 4 5 6 7 8 9 10 11 … 19 … 31
VPN G ASID

PFN C D V

Flag Content

19-bit VPN The rest reserved for the kernel.

24-bit PFN Systems can support with up to 64GB of main memory( 224 ∗ 4𝐾𝐵 pages )
Global bit(G) Used for pages that are globally-shared among processes.
ASID OS can use to distinguish between address spaces.
Coherence bit(C) determine how a page is cached by the hardware.
Dirty bit(D) marking when the page has been written.
Valid bit(V) tells the hardware if there is a valid translation present in the entry.