Prof.

Nabil Sabor
Associate Professor at Electrical Engineering Department
Faculty of Engineering, Assiut University
2024/2025

Faculty of Eng., Assiut University@ 2018

Digital Design 5th ed Morris Mano
Faculty of Eng., Assiut University@ 2018
Digital Design 5th ed Morris Mano 2
 Outline

 4.2 Combinational circuits

 4.3 Analysis procedure
 4.4 Design procedure
 4.5 Binary adder-subtractor
 4.9 Decoders
 4.10 Encoders
 4.11 Multiplexers

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Digital Design 5th ed Morris Mano 3
 Combinational Circuits

 Output is function of input only

i.e. no feedback

Combinational
n inputs •
•
•
•
m outputs
• Circuits •

When input changes, output may change (after a delay)

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 Combinational Circuits (cont.)

 Analysis
 Given a circuit, find out its function A
B
C
A
F1
?
B
C

 Function may be expressed as: A

B

A
C
F2
?
B

Boolean function
C

 Truth table
 Design
 Given a desired function, determine its circuit
 Function may be expressed as:
 Boolean function
 Truth table ?

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 Analysis Procedure
 Boolean Expression Approach
A
B
F1
C ABC
A A+B+C
B AB'C'+A'BC'+A'B'C
C
A
B (A’+B’)(A’+C’)(B’+C’)

A
F2
C
AB+AC+BC
B
C F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
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 Analysis Procedure (cont.)
 Truth Table Approach A B C F1 F2
A=0 0 0 0 0 0 0
B=0 0
F1
C= 0
A=0 0
B=0 0
C= 0
1
A=0 0
B=0

A=0 0 0
F2
C= 0

B=0 0
C
=0

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 Analysis Procedure (cont.)
 Truth Table Approach A B C F1 F2
A=0 0 0 0 0 0
B=0 0 1
F1 0 0 1 1 0
C= 1
A=0
B=0 1 1
C= 1
1
A=0 0
B=0

A 0 0
=0 F2
C
=1
B
C= 0 0
=1

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 Analysis Procedure (cont.)
 Truth Table Approach A B C F1 F2
A=0 0 0 0 0 0
B=1 0 1
F1 0 0 1 1 0
C= 0
0 1 0 1 0
A=0
B=1 1 1
C= 0
1
A=0 0
B=1

A 0 0
=0 F2
C
=0
B
C= 1 0
=0

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 Analysis Procedure (cont.)
 Truth Table Approach A B C F1 F2
A=0 0 0 0 0 0
B=1 0 0
F1 0 0 1 1 0
C= 1
A=0
0 1 0 1 0
B=1 1 0 0 1 1 0 1
C= 1
0
A=0 0
B=1

A 0 1
=0 F2
C
=1
B
C= 1 1
=1

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 Analysis Procedure (cont.)
 Truth Table Approach A B C F1 F2
A=1 0 0 0 0 0
B=0 0 1
F1 0 0 1 1 0
C= 0
A=1
0 1 0 1 0
B=0 1 1 0 1 1 0 1
C= 0 1 0
1 1 0 0
A=1 0
B=0

A 0 0
=1 F2
C
=0
B
C= 0 0
=0

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 Analysis Procedure (cont.)
 Truth Table Approach A B C F1 F2
A=1 0 0 0 0 0
B=0 0 0
F1 0 0 1 1 0
C= 1
A=1
0 1 0 1 0
B=0 1 0 0 1 1 0 1
C= 1
0 1 0 0 1 0
A=1 0 1 0 1 0 1
B=0

A 1 1
=1 F2
C
=1
B
C= 0 0
=1

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 Analysis Procedure (cont.)
 Truth Table Approach A B C F1 F2
A=1 0 0 0 0 0
B=1 0 0
F1 0 0 1 1 0
C= 0
A=1
0 1 0 1 0
B=1 1 0 0 1 1 0 1
C= 0
0 1 0 0 1 0
A=1 1 1 0 1 0 1
B=1
1 1 0 0 1
A 0 1
=1 F2
C
=0
B
C= 1 0
=0

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 Analysis Procedure (cont.)
 Truth Table Approach A B C F1 F2
A=1 0 0 0 0 0
B=1 1 1
F1 0 0 1 1 0
C= 1
A=1
0 1 0 1 0
B=1 1 0 0 1 1 0 1
C= 1
0 1 0 0 1 0
A=1 1 1 0 1 0 1
B=1
1 1 0 0 1
A 1 1
C
=1 F2 1 1 1 1 1
=1
B
C= 1 1
=1 B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
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 Design Procedure

 Given a problem statement:

 Determine the number of inputs and outputs
 Derive the truth table
 Simplify the Boolean expression for each output
 Produce the required circuit
Example:
Design a circuit to convert a “BCD” code to “Excess 3” code

4-bits ? 4-bits
0-9 values Value+3
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 Design Procedure (cont.)
 BCD-to-Excess 3 Converter
A B C D w x y z
C C
0 0 0 0 0 0 1 1
1 1 1
0 0 0 1 0 1 0 0
1 1 1 1
0 0 1 0 0 1 0 1
x x x x
B x x x x
B
0 0 1 1 0 1 1 0 A 1 1 x x
A 1 x x
0 1 0 0 0 1 1 1
D D
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C C
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x 1 1 1 1
x x x x
B x x x x
B
1 0 1 1 x x x x
A 1 x x
A 1 x x
1 1 0 0 x x x x
1 1 0 1 x x x x D D
1 1 1 0 x x x x
y = C’D’+CD z = D’
1 1 1 1 x x x x
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 Design Procedure (cont.)
 BCD-to-Excess 3 Converter
A B C D w x y z
0 0 0 0 0 0 1 1 A
0 0 0 1 0 1 0 0
w
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 x
B
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0 C y
1 0 1 0 x x x x
1 0 1 1 x x x x D z
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x
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 Seven-Segment Decoder
w x y z abcdefg
0 0 0 0 1111110 w a
0 0 0 1 0110000 b
x c a
0 0 1 0 1101101 d
0 0 1 1 1111001 y ? e
z f
0 1 0 0 0110011 g f b
0 1 0 1 1011011 g
0 1 1 0 1011111 BCD code
0 1 1 1 1110000 e c
1 0 0 0 1111111 y
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx 1 1 1
x d
1 0 1 1 xxxxxxx x x x x
w 1 1 x x b=...
1 1 0 0 xxxxxxx
z c=…
1 1 0 1 xxxxxxx d=…
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ e=…
1 1 1 1 xxxxxxx f=…
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 Binary Adder
 Half Adder
x S
 Adds 1-bit plus 1-bit HA
y C
 Produces Sum and Carry
x
+ y
───
x y C S
C S
0 0 0 0
0 1 0 1
x S
1 0 0 1
1 1 1 0
C
y

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Digital Design 5th ed Morris Mano 19
 Binary Adder (cont.)
 Full Adder x
y S
z FA
 Adds 1-bit plus 1-bit plus 1-bit C
 Produces Sum and Carry x
+ y
y + z
x y z C S
0 0 0 0 0 0 1 0 1 ───
0 0 1 0 1 x 1 0 1 0 C S
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1
0 0 1 0
1 0 1 1 0 C = xy + xz + yz
x 0 1 1 1
1 1 0 1 0
z
1 1 1 1 1
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 Binary Adder (cont.)
 Full Adder S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C
z
z
y
z

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 Binary Adder (cont.)
 Full Adder
x S
y HA HA

z C

x
S

y
C

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 Binary Adder (cont.)

Subscript i 3 2 1 0

Input carry 0 1 1 0 Ci

1 0 1 1 xi

0 0 1 1 yi
Sum 1 1 1 0 Si

Output carry 0 0 1 1 Ci+1

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 Binary Adder (cont.)
x3x2x1x0 y3y2y1y0
c3 c2 c1 .
+ x3 x2 x1 x0
Carry + y3 y2 y1 y0
Cy Binary Adder C0 Propagate ────────
Addition Cy S3 S2 S1 S0
S3S2S1S0

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0
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 Binary Adder (cont.)
 Carry Propagate Adder

x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0

Cy CPA C0 Cy CPA C0 0

S3 S2 S1 S0 S3 S2 S1 S0

S7 S6 S5 S4 S3 S2 S1 S0

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 Binary Subtractor
 Use 2’s complement with binary adder
 x – y = x + (-y) = x + y’ + 1

x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

F3 F2 F1 F0

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 Binary Adder/Subtractor
 M: Control Signal (Mode)
 M=0 x3 x2 x1 x0 y3 y2 y1 y0 M
y0=y
➔ F=x+y

 M=1
y 1 = y' A3 A2 A1 A0 B3 B2 B1 B0
➔F=x–y Cy Binary Adder Ci
S3 S2 S1 S0

F3 F2 F1 F0

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 Overflow (Unsigned numbers)

 When two numbers with n digits each are added and the sum is a
number occupying n + 1 digits, we say that an overflow occurred.
 When two unsigned numbers are added, an overflow is detected
from the end carry out.

x3 x2 x1 x0
1 y3 y2 y1 y0
70 1000110 0
80 1010000
FA FA FA FA
150 0010110
C4 C3 C2 C1
S3 S2 S1 S0
Overflow
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 Overflow (Signed numbers)

 An overflow may occur when the two numbers added are both (+)
or both (-).
 When two signed binary numbers, +70 and +80, are stored in two
eight-bit registers, are added:

 An overflow condition can be detected by observing the carry into

the sign bit position and the carry out of the sign bit position. If
these two carries are not equal, an overflow has occurred.
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Overflow (Signed numbers)
00 11
+2 0010 -2 1110
-4 1100 -3 1101
---- -------- --- --------
-2 1110 -5 1011
01 10
+3 0011 -3 1101
+6 0110 -6 1010
--- -------- --- --------
-7 1001
Overflow
+7 0111
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 Overflow (Signed numbers)

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

Overflow C4
S3
C3
S2
C2
S1
C1
S0

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Digital Design 5th ed Morris Mano
 Decoders
 A decoder is a combinational circuit that converts binary
information from n input lines to a maximum of 2n unique
output lines.
 Extract “Information” from the code
 n-to-m line decoder ( n inputs, m<= 2n output)

0 1 2 3

1
x1 0 0
Binary
0
x0 0 Decoder
0 Only one
lamp will
turn on
Example: 2-bit Binary Number
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 Decoders (cont.)
 2-to-4 Line Decoder
Y3

y3 Y2

Decoder
I1 Binary
y2
y1 Y1
I0 y0
Y0

I1 I0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3 = I1 I 0 Y2 = I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1 = I1 I 0 Y0 = I1 I 0
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 Decoders (cont.)
 3-to-8 Line Decoder Y7 = I 2 I1 I 0
Y6 = I 2 I1 I 0
Y7
Y6 Y5 = I 2 I1 I 0

Y5 Y4 = I 2 I1 I 0
Decoder

I2 Y4
Binary

Y3
Y3 = I 2 I1 I 0
I1
I0 Y2 Y2 = I 2 I1 I 0
Y1 Y1 = I 2 I1 I 0
Y0
Y0 = I 2 I1 I 0

Binary to Octal conversion I2

I1
I0
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 Binary to Octal conversion

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 Decoders (cont.)
 “Enable” Control Y3
Y3
Y2

Decoder
I1 Y2
Y1 Binary
I0
E Y0 Y1

Y0
E I1 I 0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
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 Decoders (cont.)
3 x8 decoder constructed with two 2 x 4 decoders
I I I Y Y Y Y Y Y Y Y I 2 I1 I0
2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0 Y3 Y7

Decoder
I0 Y2 Y6
0 1 1 0 0 0 0 1 0 0 0

Binary
I1 Y1 Y5
1 0 0 0 0 0 1 0 0 0 0
E Y0 Y4
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0 Y3 Y3
Y2

Decoder
I0 Y2

Binary
I1 Y1 Y1
E Y0 Y0
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 4 x16 decoder constructed with two 3 x 8 decoders

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 Decoders (cont.)
 Active-High / Active-Low

I1 I0 Y3 Y2 Y1 Y0 I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
Y3
1 1 1 0 0 0 1 1 0 1 1 1
Y2

Y3 Y3 Y1
Y2
Decoder

I1 Y2 I1 Decoder
Binary

Binary
Y0
Y1 Y1
I0 Y0 I0 Y0
I1
I0

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 Implementation Using Decoders
 Each output is a minterm
 All minterms are produced Binary
Decoder
 Sum the required minterms Y7
Example: Full Adder Y6
S(x, y, z)
x y z C S Y5
= ∑(1, 2, 4, 7) 0 0 0 0 0 x I2 Y4
0 0 1 0 1 y I1 Y3
C(x, y, z) 0 1 0 0 1 z I0 Y2
Y1
= ∑(3, 5, 6, 7) 0 1 1 1 0
1 0 0 0 1 Y0
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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S C 44
 Encoders
 Put “Information” into code Only one
switch
 Binary Encoder should be
 Example: 4-to-2 Binary Encoder activated at
a time
0 x0

1 x1 y1 x0 x1 x2 x3 y1 y0
Binary 1 0 0 0 0 0
x2 Encoder y0
2 0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1
3 x3

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 Encoders (cont.) I7
I6

Encoder
I5
 Octal-to-Binary Encoder (8-to-3)

Binary
I4 Y2
I3 Y1
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I2
Y0
I1
0 0 0 0 0 0 0 1 0 0 0 I0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0 I7
I6 Y2
0 0 0 0 1 0 0 0 0 1 1 I5
0 0 0 1 0 0 0 0 1 0 0 I4
I3 Y1
0 0 1 0 0 0 0 0 1 0 1 I2
0 1 0 0 0 0 0 0 1 1 0 I1
I0 Y0
1 0 0 0 0 0 0 0 1 1 1
Limitation:
1- Only one of the input is allowed to be 1 Y2 = I 7 + I 6 + I 5 + I 4
2- When all inputs are zeros, the output is zero Y1 = I 7 + I 6 + I 3 + I 2
but this situation is the same as input Y0=1!!
Y0 = I 7 + I 5 + I 3 + I1
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 Priority Encoders

 4-Input Priority Encoder ( V is a valid bit indicator)

D3

Encoder
V

Priority
D2 y
D1 x
D0

V: is the valid bit indicator that

is set to 1 when one or more
inputs are equal to 1.

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 Priority Encoders (cont.)

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 Priority Encoders (cont.)

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 Encoder / Decoder Pairs
Binary Binary
Encoder Decoder

7 I7 Y7
7
6 I6 Y6
6
5 I5 Y2
Y5 5
4 I4 Y1
I2 Y4 4
3 I3 Y0
I1 Y3 3
2 I2
I0 Y2 2
1 I1 Y1 1
0 I0 Y0 0

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 Multiplexers (Data Selector)
I0
I1
MUX Y
I2
I3
S 1 S0

S 1 S0 Y
0 0 I0
0 1 I1
(2n input lines and n selection lines) 1 0 I2
1 1 I3

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 Multiplexers (cont.)
 2-to-1 MUX
I0
I0 Y
I1 MUX Y I1
S
S
I0
 4-to-1 MUX
I1
Y
I0 I2

I1 I3
MUX Y
I2
I3
S 1 S0
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Digital Design 5th ed Morris Mano 52
 Multiplexers (cont.)
 Quad 2-to-1 MUX A3
Y3
A2
A3 I0 Y2
B3 MUX Y A1
I1 Y1
S A0
Y0
A2 I0 B3
B2 MUX Y A3
I1 B2
S A2
A1
B1 Y3
A0
A1 I0 Y2
MUX Y
B1 MUX Y B0 1
I1 B3
S Y0
B2
B1
A0 I0 S E B0
MUX Y S E
B0 I1
S
(two 4-bits input, one 4-bits output)
S
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 Multiplexers (cont.)
 Quad 2-to-1 MUX
A3
Y3
A2
Y2
A1
Y1 A3
A0
Y0 A2
B3 A1 Y3
B2
A0 Y
MUX 2
B1 Y1
B3
B0 Y0
B2
B1
Extra B0
Buffers S E
S E
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 Implementation Using Multiplexers
 Any Boolean function of n-variables can be
implemented using a MUX with n-1 selection lines
 Example
F(x, y) = ∑(0, 1, 3)
x y F I0
1
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3
S1 S0
1 1 1
x y

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 Implementation Using Multiplexers (cont.)

 Example
F(x, y, z) = ∑(1, 2, 6, 7)
0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3
MUX Y F
0 1 0 1 0 I4
0 1 1 0 0 I5
1 I6
1 0 0 0
1 I7
1 0 1 0 S2 S 1 S 0
1 1 0 1
1 1 1 1 x y z
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 Implementation Using Multiplexers (cont.)

 Example
F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0 z I0
0 0 1 1
F=z z I1 F
MUX Y
0 1 0 1 0 I2
0 1 1 0 F=z 1 I3
S 1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
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 Implementation Using Multiplexers (cont.)

 Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0 D I0
0 0 0 1 1 F=D
0 0 1 0 0
D I1
0 0 1 1 1
F=D D I2
0 1 0 0 1
0 1 0 1 0
F=D 0 I3
MUX Y F
0 1 1 0 0
F=0
0 I4
0 1 1 1 0
1 0 0 0 0
D I5
1 0 0 1 0 F=0 1 I6
1 0 1 0 0
1 0 1 1 1 F=D 1 I7
1 1 0 0 1 S2 S 1 S 0
F=1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
F=1 A B C
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 Multiplexer Expansion

 8-to-1 MUX using Dual 4-to-1 MUX

I0 I0
I1 I1
MUX Y
I2 I2
I3 I3
S1 S0 I0
I1 MUX Y Y
I0 S
I4
I5 I1
MUX Y
I6 I2
I7 I3
S 1 S0

1 0 0
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2 59
 DeMultiplexers

Y3
Y2
I DeMUX
Y1
S S Y0
1 0

Y3

Y2
I
S1 S0 Y3 Y2 Y1 Y0
Y1
0 0 0 0 0 I
Y0 0 1 0 0 I 0
1 0 0 I 0 0
S1
S0 1 1 I 0 0 0
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 Multiplexer / DeMultiplexer Pairs

MUX DeMUX

7 I7 Y7
7
6 I6 Y6
6
5 I5 Y5 5
4 I4 Y4 4
3 I3
Y I Y3 3
2 I2 Y2 2
1 I1 Y1 1
0 I0 Y0 0
S2 S1 S0 S2 S1 S0

x2 x1 x0 Synchronize y2 y1 y0
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 DeMultiplexers / Decoders

Y3 Y3

Decoder
I1 Y2

Binary
Y2
I DeMUX I0 Y1
Y1
E Y0
S S Y0
1 0

E I 1 I0 Y3 Y2 Y1 Y0
S 1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0

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Digital Design 5th ed Morris Mano 62
 Problems of Chapter Four

4.1, 4.2, 4.4, 4.13, 4.23, 4.25, 4.27, 4.31, 4.32,

4.33, 4.34, 4.35(a)

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