ELECTRICAL AND ELECTRONICS ENGINEERING
&
COMPUTER ENGINEERING
EEE 248 CNG 232
Logic Design
2 1 S P R I N G 2 2
HW I
Number of Questions: 4
Due: APRIL 11, 2022
Good Luck
Dr. Gürtaç Yemişcioğlu
Student Number:
Full Name:
Question Achieved Points
1 8
2 8
3 22
4 28
5 34
TOTAL 100
EEE 248 CNG 232
Logic Design
21 SPRING 22
HW1
Question 1 (8 pts.): Perform the following base conversions of unsigned numbers,
rounding fractional parts to 2 digits.
a. (38.45)10 = ( )2
25 24 23 22 21 20
38 1 0 0 1 1 0 0.45 x 2 = 0 . 9
0.9 x 2 = 1 . 8
0.8 x 2 = 1 . 6
0.6 x 2 = 1 . 2
1 0 0 1 1 0 . 0 1 1
b. (10110.010)2 = ( )10
1 0 1 1 0 . 0 1 0
24 23 22 21 20 . 2-1 2-2 2-3
16 4 2 . 0 0,25 0
22 . 25
c. (723. 52)8 = ( )16
7 2 3 . 5 2
111 010 011 . 101 010
0001 1101 0011 . 1010 1000
1 D 3 . A 8
d. (8EA3.4F)16 = ( )2
8 E A 3 . 4 F
1000 1110 1010 0011 . 0100 1111
Dr. Gürtaç Yemişcioğlu Page| 2
EEE 248 CNG 232
Logic Design
21 SPRING 22
HW1
Question 2 (8 pts.): Perform the following (unsigned) operations in binary number system.
a. 1001.01 x 11.11
1 0 0 1 . 0 1
x 1 1 . 1 1
1 0 0 1 0 1
1 0 0 1 0 1
1 0 0 1 0 1
+ 1 0 0 1 0 1
1 0 0 0 1 0 1 0 1 1
1 0 0 0 1 0 . 1 0 1 1
25 24 23 22 21 20 . 2-1 2-2 2-3 2-4
32 2 . 0.5 0.125 0.0625
34 . 6875
b. 0111.10 / 10.11
0 0 0 1 0 1 0 1 1
1 0 1 1 1 1 1 1 0 0 0 0 0
- 1 0 1 1
0 1 0 0 0 0 1 0 . 1 0 1 1
- 1 0 1 1
0 1 0 1 0 0
- 1 0 1 1
0 0 1 0 0 1 0
- 1 0 1 1
0 0 1 1 1
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EEE 248 CNG 232
Logic Design
21 SPRING 22
HW1
Question 3 (22 pts.):
a. (14 pts.) Convert the +29 and +41 to binary using the signed 2’s complement
representation and enough digits to accommodate numbers. Then perform the
binary equivalent of. Show all your calculations.
25 24 23 22 21 20 25 24 23 22 21 20
29 0 1 1 1 0 1 41 1 0 1 0 0 1
+29 0 0 1 1 1 0 1 +41 0 1 0 1 0 0 1
-29 1 1 0 0 0 1 1 -41 1 0 1 0 1 1 1
i. (4 pts.) (+29) + (-41)
1 1 1 1 1
+29 0 0 1 1 1 0 1
-41 + 1 0 1 0 1 1 1
1 1 1 0 1 0 0
-12 0 0 0 1 1 0 0
ii. (4 pts.) (-29) + (+41)
1 1 1 1
-29 1 1 0 0 0 1 1
+41 + 0 1 0 1 0 0 1
+12 1 0 0 0 1 1 0 0
iii. (4 pts.) (-29) + (-41)
1 1 1 1
-29 1 1 0 0 0 1 1
-41 + 1 0 1 0 1 1 1
1 0 1 1 1 0 1 0
-70 0 1 0 0 0 1 1 0
Dr. Gürtaç Yemişcioğlu Page| 4
EEE 248 CNG 232
Logic Design
21 SPRING 22
HW1
b. (8 pts.) Perform BCD addition of signed 347 + (- 192). Show your calculations both
in binary and decimal.
347 0 0 1 1 0 1 0 0 0 1 1 1
192 0 0 0 1 1 0 0 1 0 0 1 0
9 9 9 10
+ 0 1 9 2
9 8 0 8 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0
1 1 1
0347 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1
9808 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0
10155 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1
0 1 1 0 0 1 1 0 0 1 1 0
0 0 0 0 0 0 0 1 0 1 0 1
1 0 1 5 5
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EEE 248 CNG 232
Logic Design
21 SPRING 22
HW1
Question 4 (28 pts.):
a. (12 pts.) Use algebraic manipulation and simplify the following Boolean
expressions to a minimum number of literals:
i. (2 pts.) F = a’+ ab + ac’ + abc’
= a’+ab+ac’(1+b)
= a’+ab+ac’
= a’+b + ac’
= a’+b+c’
ii. (2 pts.) F = x’+ xyz + x (y⊕z) + xy’z’
= x’ + xyz + x (y’z + yz) + xy’z’
= x’ + xyz + xy’z + xyz’ + xy’z’
= x’ + xy(z+z’) + xy’(z+z’)
= x’ + xy + xy’
= x’ + x(y+y’)
= x’ + x = 1
iii. (2 pts.) F = ab’c + a’b’c + abc
= b’c(a+a’) + abc
= b’c + abc
= c (b’+ab)
= c (b’+a)
iv. (2 pts.) F = (a + bc’ + cd) (b’ + ef)
= ab’ + aef + bc’b’ + bc’ef + b’cd + cdef
= a (b’ + ef) + bc’ef + cd (b’ + ef)
= (a + cd) (b’ + ef) + bc’ef
v. (4 pts.) F (a,b,c) = Π (1, 3, 6, 7)
F’ = a’b’c + a’bc + abc’ + abc
F’= a’c (b’+b) + ab (c’+c)
F’ = a’c + ab
F = (a + c’) (a’+ b’)
Dr. Gürtaç Yemişcioğlu Page| 6
EEE 248 CNG 232
Logic Design
21 SPRING 22
HW1
b. (16 pts.) Given Boolean functions:
F(x,y,z)= Σ m (1, 2, 3, 6, 7), G(x,y,z)= Π M (0, 1, 3, 4, 6), H(x,y,z)= F XOR G;
i. (6 pts.) Develop the Truth Table for the three functions (on the same table).
x y z F G H
0 0 0 0 0 0
0 0 1 1 0 1
0 1 0 1 1 0
0 1 1 1 0 1
1 0 0 0 0 0
1 0 1 0 1 1
1 1 0 1 0 1
1 1 1 1 1 0
ii. (6 pts.) Use algebraic manipulation and express the function F as an
expanded maxterms using product of sums, and function G as an expanded
minterms using sum of products (do not use shorthand notation but write
down all products and sums openly).
F (POS) G SOP
F’ = x’y’z’ + xy’z’ + xy’z G = x’yz’ + xy’z + xyz
F = [x’y’z’ + xy’z’ + xy’z]’
F = (x + y + z) (x’+y+z) (x’+y+z’)
iii. (4 pts.) Implement the function H using a 2-level OR-AND circuit (show logic
schematic). Assume inverters are available. (4 pts)
H’ = x’y’z’ + x’yz’+xy’z’+xyz x
y
z
H = (x+y+z) (x+y’+z) (x’+y+z) (x’+y’+z’)
x
y’
z
F
x’
y
z
x’
y’
z’
Dr. Gürtaç Yemişcioğlu Page| 7
EEE 248 CNG 232
Logic Design
21 SPRING 22
HW1
Question 5 (34 pts.):
a. (18 pts.) Given the Boolean function
F(A, B, C, D) = Σ (0, 1, 2, 3, 4, 5, 7, 8, 10, 12, 14)
i. (6 pts.) Draw a Karnaugh Map.
CD
AB 00 01 11 10
00 1 1 1 1
01 1 1 1 0
11 1 0 0 1
10 1 0 0 1
ii. (2 pts.) Identify the prime implicants of F.
A’B’ , C’D’, A’D, AD’
iii. (2 pts.) Identify all Essential Prime Implicants of F.
AD’ , A’D
iv. (2 pts.) Derive minimal SOP expressions for F.
F = A’B’ + C’D’ + A’D + AD’
v. (2 pts.) Derive minimal POS expressions for F.
F’ = AD + A’BCD’
F = (A+D) (A + B’ + C’ + D)
vi. (4 pts.) Assume each inverter has a cost of 1, each 2-input NAND gate has a
cost of 2, and 4-input NAND gate has a cost of 4. Derive a solution using
NAND gates and inverters by minimizing the overall cost. What is the cost
of your solution?
A
A
B
B
C
C
D
D
F
F
= 4 x inverter + 4 x 2-NAND + 1 x 4-NAND = 4 + 8 + 4 = 16
Dr. Gürtaç Yemişcioğlu Page| 8
EEE 248 CNG 232
Logic Design
21 SPRING 22
HW1
b. (16 pts.) Given the Boolean function F(A,B,C,D) = ∑(0,1,6,7,10,11) together with
the don’t care conditions d(A,B,C,D) = A ⊕ B ⊕ C
i. (4 pts.) Simplify F in sum of products (SOP).
A B C D d
CD
0 0 0 0 0 AB 00 01 11 10
0 0 0 1 0
0 0 1 0 1 00 1 1 X X
0 0 1 1 1
0 1 0 0 1 01 X X 1 1
0 1 0 1 1
11 0 0 X X
0 1 1 0 0
0 1 1 1 0
10 X X 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0 F = A’ + C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1
ii. (4 pts.) Implement F with one NAND gate only.
A F A F
C’ C’
iii. (4 pts.) Simplify F in product of sums (POS).
F’ = AB
F = A’ + B’
iv. (4 pts.) Implement F with two NOR gates only.
A’ F
B’
Dr. Gürtaç Yemişcioğlu Page| 9
