UNIVERSITY OF SANTO TOMAS

ECE21121: MICROCOMPUTER SYSTEMS AND DESIGN

MODULE 1
INTRODUCTION TO
MICROPROCESSOR SYSTEMS

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INTRODUCTION
WHAT IS A MICROPROCESSOR SYSTEM?

A microprocessor is just an
integrated circuit. On its own, without
a surrounding circuit and applied
voltages, it is quite useless.
A useful microprocessor-based
computer system must have a
memory, I/O devices, and a
processing unit. Fig. 1. Intel 8086 Microprocessor

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INTRODUCTION
TERMINOLOGIES

• Microprocessor or MPU – the central processing of a computer

which includes the ALU, register unit, and control unit, all
integrated in a single IC.
• Microcomputer – a complete computing system with memory,
microprocessor, and I/O unit.
• Microcontroller or MCU – a single chip microcomputer
consisting of microprocessor, memory, and I/O unit.
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LEVELS OF INTEGRATION

According to Gordon
Moore, co-founder of Intel,
the number of transistors
per square inch on
Integrated Circuits doubles
approximately every two
years.
Fig. 2. Moore’s Law
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LEVELS OF INTEGRATION

Table 1. Levels of Integration

Level of Integration Number of Gates

Small Scale Integration (SSI) 10 to 100

Medium Scale Integration (MSI) 100 to 1,000

Large Scale Integration (LSI) 1,000 to 10,000

Very Large Scale Integration (VLSI) More than 10,000

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LOGIC CIRCUIT TERMINOLOGIES

1. Resistor-Transistor Logic (RTL) – a digital circuit which uses resistors as

the input network and BJT as switching device.
2. Diode-Transistor Logic (DTL) – the logic gating function is performed
by a diode network and the amplifying action is performed by
transistors.
3. Transistor-Transistor Logic (TTL) – both the logic gating function and
the amplifying function are performed by transistors.

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LOGIC CIRCUIT TERMINOLOGIES

Fig. 3. Resistor Transistor Logic Fig. 4. Diode Transistor Logic

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LOGIC CIRCUIT TERMINOLOGIES
4. Emitter-Coupled Logic (ECL) – a high speed bipolar transistor logic
family which uses an overdriven BJT differential amplifier with single-
ended input.
5. PMOS Logic – uses p-channel metal oxide semiconductor FET to
implement logic gates.
6. NMOS Logic – uses n-channel metal oxide semiconductor FET to
implement logic gates.
7. CMOS Logic – complementary MOSFETs designed using symmetrical
pairs of p- and n- channel.
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LOGIC CIRCUIT TERMINOLOGIES

Fig. 5. CMOS Logic

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LOGIC CIRCUIT TERMINOLOGIES

Advantages of using MOS technology:

• Less chip area is demanded by an Individual MOS transistor, which results
in more functions in less area.
• Critical defects per unit chip area is low for a MOS transistor because it
involves fewer steps in the fabrication of a MOS transistor.
• Dynamic circuit techniques are practical in MOS technology, but not in
bipolar technology. A dynamic circuit technique involves use of fewer
transistors to realize a circuit function.

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DEVELOPMENT OF MICROPROCESSOR
First IC was Intel was founded by
developed by Robert Noyce and
Jack Kilby Gordon Moore

1958 1959 1968 1971

First practical IC was First Microprocessor was

developed by Robert Noyce developed by BUSICOM
In partnership with Intel
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DEVELOPMENT OF MICROPROCESSOR
4 bit / 1 nibble
microprocessor
INTEL 8-bit microprocessor
1st microprocessor by Intel INTEL 8080
4004/4040 64 kb of memory
45 instructions
500 KIPS
Uses PMOS

1971 1972 1973 1975

8-bit (1st generation) Developed by MOSTECH

16 kb of memory INTEL 8008 8-bit microprocessor 6502
48 instructions 16-bit address
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DEVELOPMENT OF MICROPROCESSOR
1 MB of memory
INTEL 8086 1st 16 bit MPU (2.5 MIPS with 2000
INTEL 8088 instructions)
Capable of multiplication and division

1977 1978

8-bit (2nd generation) microprocessor

769, 230 Ips INTEL 8085
246 instructions
machine-code compatible with Z80
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SYSTEM BUS

Fig. 6. Block Diagram of a Generic Computer Organization

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SYSTEM BUS

What is a System Bus?

A System Bus is a physical group of signal lines that has a
related function within a microprocessor system and can be
classified into two:
• Internal Bus – a set of lines that connect two or more parts of
an element
• External Bus – a set of lines that connect two or more elements
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SYSTEM BUS

Types of System Bus

• Address Bus – a unidirectional bus that is used to locate a memory
location or an I/O device connected to the system.
• Data Bus – a bidirectional bus that carries data back and forth to a
specified location with basis to the address location provided by the
address bus.
• Control Bus – a collection of individual control signals used by the
microprocessor to send its generated control signals to any element of
the computer system.
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SYSTEM BUS

Bus Buffering Techniques

Bus buffering techniques refer to the various methods or
techniques that ensure the validity of a logic level when signals
are carried out on the bus.
• Type 1 – single source, multiple destination
• Type 2 – multiple source, single destination
• Type 3 – multiple source, multiple destination
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Type 1
Type 1 is a bus buffering technique which is characterized
by a single source and multiple destination transfer of signals.

Design Issues:
• Number of gates that can be driven
RAM ROM
• Necessity of Buffers
Microprocessor (Multiple Destination)
(Single Source)
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SYSTEM BUS

Type 2
Type 2 is a bus buffering technique which is characterized
by a multiple source and single destination transfer of signals.

Design Issues:
• Bus Contention

Registers MPU
(Multiple Source) (Single Destination)

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SYSTEM BUS
Type 2 - Bus Contention (Design Issue)
Bus contention is a Type 2 design which can possibly
damage the devices involved because an excessive current flows
from the logic 1 output to the logic 0 output.
Possible Solutions:
1. Using Tri-state
Buffers
2. Using Open Drain
3. Using Multiplexers
Fig. 7. Example of Bus Contention
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Type 2 – Solution for Bus Contention

1. Using Tri-state Buffers
A tri-state buffer allows an output port to assume a high
impedance state in addition to the 1 and 0 logic levels,
effectively removing the output from the circuit. This allows
multiple circuits to share the same output line or lines.

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SYSTEM BUS

Type 2 – Solution for Bus Contention

1. Using Tri-state Buffers
Table 1. Truth Table of
a Tri-state Buffer
x
Enable Input x y Output

0 0 1 0 Z
0 1 1 0 Z
y
1 0 1 1 0
Fig. 8. Schematic Symbol 1 1 0 0 1

Fig. 9. Equivalent Circuit

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SYSTEM BUS

Type 2 – Solution for Bus Contention IN1

1. Using Tri-state Buffers EN1

Note: IN2
Using Tri-state Buffers, the outputs share EN2
OUT
a common bus line but no more than one buffer IN3
is active at any given time.
EN3

IN4
EN4

Fig. 10. Application of Tri-state Buffers

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SYSTEM BUS
Type 2 – Solution for Bus Contention +Vcc

2. Using Open-Collector (Open-Drain) R

IN1 oc
OUT
IN2 oc

IN3 oc

IN4 oc

Fig. 11. Open-Collector Discussion Fig. 12. Application of Open-Collectors

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SYSTEM BUS
Type 2 – Solution for Bus Contention
3. Using Multiplexers
Note:
Using Multiplexers, the outputs share
a common bus line but no more than one input
is reflected at the output at any given time due
to the presence of select lines, S1 and S0.

Fig. 13. Application of Multiplexer

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SYSTEM BUS

Type 3
Type 3 is a bus buffering technique which is characterized
by a multiple source and multiple destination transfer of signals.

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DIGITAL CIRCUIT PARAMETERS

In this section, four digital circuit parameters will be discussed:

A. Noise Margin or Noise Immunity
B. Fan Out
C. Propagation Delay
D. Power Dissipation

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Logic 1 and Logic 0
These logic levels are not simply 5V and 0V, or even Vcc and
Ground. Within any family of ICs, voltages and currents indicating
1 and 0 cover defined ranges unique to that logic family.

Logic Families
TTL LSTTL CMOS

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TTL Family LSTTL Family CMOS
OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT
5V 5V 5V 5V 5V 5V
4.6 V LOGIC 1

3.5 V
LOGIC 1 LOGIC 1
2.7 V
INVALID
2.4 V
2V 2V
1.5 V
INVALID INVALID
0.8 V 0.5 V 0.8 V
0.4 V 0.4 V

0V LOGIC 0 0V 0V LOGIC 0 0V 0V LOGIC 0 0V

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Notice that logic levels for outputs (left column) and inputs
(right column) in all the families are different. This ensures that
provided that the output voltage of a gate is within its defined
logic limits for 1 and 0.
Hence, any compatible gate input connected to that output
will recognize the correct 1 or 0 levels.
The difference between levels at the output and input in
any particular family is called Noise Margin.
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A. Noise Margin or Noise Immunity

This is the maximum noise voltage added or subtracted to
the input signal of a digital circuit that does not cause any
undesirable change in the circuit output.
All gates are designed to tolerate a certain amount of noise
on their input and output ports.

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A. Noise Margin
LSTTL Family
OUTPUT INPUT
5V 5V
This is the difference
between the worst-case
voltage at the output and the LOGIC 1
2.7 V
minimum or maximum voltage HIGH
to be recognized at the input. NOISE MARGIN 2V

INVALID
0.5 V 0.8 V LOW
NOISE MARGIN
0V LOGIC 0 0V
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LSTTL Family High Noise Margin (HNM) = VOH – VIH
OUTPUT INPUT
5V 5V where:
VOH – worst-case voltage for logic 1 at the output
VOH VIH – minimum voltage required for logic 1 to be recognized
VIH at the input
LOGIC 1
2.7 V Low Noise Margin (LNM) = VIL – VOL
HIGH
where:
NOISE MARGIN 2V
VOL – worst-case voltage for logic 0 at the output
INVALID VIL – maximum voltage required for logic 0 to be recognized
LOW at the input
0.5 V 0.8 V
NOISE MARGIN
VO LOGIC 0 VIL Noise Margin (NM) = min(HNM, LNM)
L 0V 0V
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Current Sinking and Sourcing

These are terms used in the field of digital electronics to
refer to the direction of direct current flow between TTL gates.
They refer to the flow of conventional current from the positive,
which is the sourcing end, to the ground, which is the sinking
end.
In TTL logic gates, the sinking and sourcing action occurs
simultaneously when one gate feeds a signal to another gate.
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Current Sinking and Sourcing

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B. Fan Out
This specifies the number of standard loads or maximum
number of inputs that can be connected to the output of a gate
without degrading its normal operation.
It depends on the amount of electric current a gate can
source or sink while driving other gates.

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B. Fan Out
It is calculated from the amount of current available in the
output of the gate and the amount of current needed in each
input of a gate.
IOH IOL

0 1 IIH 1 0 IIL
0 1

IIH IIL
0 1

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IOH IOL

0 1 IIH 1 0 IIL
0 1

IIH IIL
0 1

Fan Out High (FOH) = |IOH/IIH| Fan Out Low (FOL) = |IOL/IIL|
where: where:
IOH – maximum high level output source current IOL – maximum low level output sink current
IIH – minimum high level input sink current IIL – minimum low level input source current

Fan Out (FO) = min(FOH, FOL)

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C. Propagation Delay
When gate inputs change, outputs do not change
instantaneously. This delay is known as gate or propagation
delay.
It is the time required for the input to be propagated to the
output. In other words, propagation delay is defined as the time
it takes for the effect of change in input to be visible at the
output.
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Terminologies
• tPHL – signal delay time between the input and output when the
output changes from high to low level.
• tPLH – signal delay time between the input and output when the
output changes from low to high level.
• tPDave – average propagation time equivalent to (tPHL+tPLH)/2

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C. Propagation Delay
Note that 50% is the logic threshold where output is
assumed to switch states.

2-input AND Gate

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C. Propagation Delay

AND and NOR gate:

tPHL= 20ns
tPLH = 20ns

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D. Power Dissipation
It is calculated from the supply voltage VCC and the current
ICC that is drawn by the circuit.
NOTE:
ICC = (ICCH + ICCL)/2
PDave = ICC*VCC where:
ICCH – current when the output of the gate is high logic level
ICCL – current when the output of the gate is low logic level

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Sample Problem No. 1
A 7400 TTL gate is driving a bus line with 74LS04 receiver.
Calculate the noise margin for this case.
Table 2. Voltage Level Specifications

Symbol Description TTL LSTTL CMOS

VOH Worst Case “1” at the output 2.4V 2.7V 4.6V

VIH Min Acceptable “1” Vin 2.0V 2.0V 3.5V
VOL Worst Case “0” at the output 0.4V 0.5V 0.4V
VIL Max Acceptable “0” Vin 0.8V 0.8V 1.5V
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Sample Problem No. 2
Assume that a type 1 bus is to be buffered with a 74LS04
source. Calculate the standard TTL loads that can be driven by
this source. Table 3. Current Level Specifications

Symbol Description TTL LSTTL CMOS

IOL Max ‘0’ level output sink current 16mA 8mA 0.36mA
IIL Min ‘0’ level input source current -1.6mA -0.4mA -1uA
IOH Max ‘1’ level output source current -400uA -400uA -360uA
IIH Min ‘1’ level input sink current 40uA 20uA 1uA
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Sample Problem No. 3
Calculate the number of 74LS04 loads that a 7400 source
can safely drive without exceeding its drive capabilities.
Table 3. Current Level Specifications

Symbol Description TTL LSTTL CMOS

IOL Max ‘0’ level output sink current 16mA 8mA 0.36mA
IIL Min ‘0’ level input source current -1.6mA -0.4mA -1uA
IOH Max ‘1’ level output source current -400uA -400uA -360uA
IIH Min ‘1’ level input sink current 40uA 20uA 1uA
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Sample Problem No. 4
The propagation delay times for a 74LS08 AND gate are
tpLH=15ns, tpHL=20ns and for a 7402 NOR gate, they are tpLH=20ns,
tpHL=15ns. Sketch Vout1 and Vout2 showing the effects of
propagation delay.

0ns 50ns 100ns 150ns 200ns

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Sample Problem No. 5

A standard TTL Quad 2-input NAND gate has the following
specifications: ICCH = 1mA, ICCL = 3mA, and VCC=5V. Calculate the
average total power dissipation if the circuit uses ten ICs.

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Seatwork No. 4
1. Explain the significance of noise margin, fan out, propagation
delay, and power dissipation based on your understanding of the
discussion.

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Seatwork No. 4
2. Determine the High-level and Low-level noise margins for both
type of CMOS by using the information on the table below.
Table 4. Voltage Level Specifications for CMOS

Symbol Description +5V CMOS +3.3 CMOS

VOH Worst Case “1” at the output 4.4V 2.4V

VIH Min Acceptable “1” Vin 3.5V 2.0V
VOL Worst Case “0” at the output 0.33V 0.4V
VIL Max Acceptable “0” Vin 1.5V 0.8V
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Seatwork No. 4
3. How many 7432 OR gates can a single OR gate safely drive?
Refer on the specification sheet for 7432 OR gate on the next
slides.

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Table 5. 7432 OR Gate Specification Sheet (Part 1)

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Table 6. 7432 OR Gate Specification Sheet (Part 2)

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Seatwork No. 4
4. Calculate the average total propagation delay of the circuit
below.

Input

Inverter:
tPHL= 15ns
tPLH = 22ns
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Seatwork No. 5
5. Speed Power Product (SPP) is a figure of merit of a logic circuit
which is based on the product of propagation delay and the power
dissipation at a specified frequency. Given the following values for
a certain gate: propagation delay of 5 ns, ICCH = 1 mA, and ICCL = 2.5
mA, with a DC supply of 5V. Determine the speed power product
or SPP.

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MICROPROCESSOR ARCHITECTURE
PROGRAM COUNTER (PC)
A STACK POINTER (SP) ACCUMULATOR
D D (AC)
INDEX REGISTER (IX) A
D
T GENERAL PURPOSE
R MEMORY ADDRESS
A REGISTER (GPR) STATUS
E REGISTER (MAR)
A B ALU REGISTER
S
S B
U
B MEMORY S
U
S
MEMORY DATA INSTRUCTION
CONTROL UNIT
REGISTER (MDR) REGISTER (IR)
Fig. 14. Basic Microprocessor Architecture
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Basic Microprocessor Structure or Architecture

A. Bus Unit
It is used to send information from one component into
another and has the job of establishing communication with the
external unit.

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Basic Microprocessor Structure or Architecture

Bus Classification:
1. Data Bus
A bidirectional bus that carries data back and forth to a specified
location with basis to the address location provided by the address bus.
The width of a data bus refers to the number of bits (electrical wires)
that make up a bus. For example, 1-, 4-, 8-, 16-, 32-, 64-bit data bus

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Basic Microprocessor Structure or Architecture
Bus Classification:
2. Address Bus
It is a group of wires or lines that are used to transfer the addresses
of Memory or I/O devices. It is unidirectional.
The number of bits of address bus determines the maximum size of
memory which the processor can access.
For instance, a 16-bit address bus can access 65,536 different
memory locations.
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Basic Microprocessor Structure or Architecture

B. Register Set
Registers are composed of group of flip flops, each one
shares a common clock and is capable of storing one bit of
information or modify stored binary word.

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Basic Microprocessor Structure or Architecture
B. Register Set in the given structure:
1. General Purpose Registers (GPR) A and B
2. Accumulator (AC)
3. Status Register
4. Instruction Register (IR)
5. Program Counter (PC)
6. Memory Data Register (MDR)
7. Memory Address Register (MAR)
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Basic Microprocessor Structure or Architecture

B. Register Set in the given structure:
8. Stack Pointer (SP)
9. Index Register (IX)

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PROGRAM COUNTER (PC)
A STACK POINTER (SP) ACCUMULATOR
D D (AC)
INDEX REGISTER (IX) A
D
T GENERAL PURPOSE
R MEMORY ADDRESS
A REGISTER (GPR) STATUS
E REGISTER (MAR)
A B ALU REGISTER
S
S B
U
B MEMORY S
U
S
MEMORY DATA INSTRUCTION
CONTROL UNIT
REGISTER (MDR) REGISTER (IR)
Fig. 14. Basic Microprocessor Architecture
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Basic Microprocessor Structure or Architecture
B. Register Set in the given structure:
1. General Purpose Registers (GPR) A and B
They are generally used as data storage and are directly
connected to the data bus.
The more the number of GPR, the more powerful the
microprocessor is.

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Basic Microprocessor Structure or Architecture

B. Register Set in the given structure:
2. Accumulator (AC)
The register that works very closely with the ALU. All results
of the processes performed by the ALU is stored in this register.
This is the major register that holds data for manipulation. It
is considered as the most versatile register because its content
always changes.
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Basic Microprocessor Structure or Architecture
B. Register Set in the given structure:
3. Status Register
It is used to hold the status of the microprocessor after
performing an operation.
It is sometimes referred to as Flag Register, Condition Code
Register, or the Indicator Register.

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Basic Microprocessor Structure or Architecture
B. Register Set in the given structure:
3. Status Register
Commonly Used Flags:
a. Carry (CF) – end carry of the parallel adder
b. Zero (ZF) – if the result of the ALU are all zero
c. SIGN (SF) – if the MSB in a signed operation has a value of 1
d. OVERFLOW (OF) – if the result of the ALU exceeds the
defined range of numbers
e. PARITY (PF) – use for error detection
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Basic Microprocessor Structure or Architecture

B. Register Set in the given structure:
4. Instruction Register (IR)
It is used to hold the instruction code or operation code
(opcode).
The outputs of this register are the inputs to the instruction
decoder.

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Basic Microprocessor Structure or Architecture
B. Register Set in the given structure:
5. Program Counter (PC)
It contains the address of the next instruction to be
performed by the MPU.
It automatically increments as soon as it is finished with the
memory location.

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Basic Microprocessor Structure or Architecture

B. Register Set in the given structure:
6. Memory Data Register (MDR)
This is where the data to be stored to or retrieved from the
memory are placed.
This register also loads the fetched instruction from the
memory going to instruction register.
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Basic Microprocessor Structure or Architecture

B. Register Set in the given structure:
7. Memory Address Register (MAR)
This is where the addresses of data and instructions can be
located.

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Basic Microprocessor Structure or Architecture

B. Register Set in the given structure:
8. Stack Pointer (SP)
This register points to the data or instruction on the top of
the stack. This is where data or instruction temporarily not in use
is stored. It uses a Last-In-First-Out (LIFO) algorithm.
Placing data to the stack invokes a PUSH operation while
retrieving data from the stack invokes a POP operation.
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OFFSET MACHINE CODE ASSEMBLY LANGUAGE
0000 B0 4000 START: MOV SP,4000H
…
MOV AL,01H
000A E8 0012 J1: CALL OUTPUT
000D D0 C0 ROL AL,1
…
0012 BA 3FD2 OUTPUT: MOV DX,BPORT3
0015 EE OUT DX,AL
0016 B9 A000 MOV CX,0A000H
0019 E2 FE LOOP $
001B C3 RET
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CALL Instruction
000A E8 0012 J1: CALL OUTPUT
000D D0 C0 ROL AL,1

SP 4000H XXH SP 4000H XXH

3FFFH XXH SP 3FFFH XXH
00H PUSH means placing data
into the stack.
3FFEH XXH SP 3FFEH 0DH
XXH
3FFDH XXH 3FFDH XXH To PUSH, decrement SP
then push or place
3FFCH XXH 3FFCH XXH data.
3FFBH XXH 3FFBH XXH
Before After
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RET Instruction
001B C3 RET

4000H XXH SP 4000H XXH

3FFFH 00H SP 3FFFH 00H POP means retrieving data
from the stack.
SP 3FFEH 0DH SP 3FFEH 0DH
3FFDH XXH 3FFDH XXH To POP, POP data then
increment
3FFCH XXH 3FFCH XXH SP.
3FFBH XXH 3FFBH XXH
Before After
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Basic Microprocessor Structure or Architecture
Structure of Data Storage in Memory
For multiple byte data items to be stored in the memory, there is a
need to know how the order is done.
The order of storage of data can be classified into two:
1. Little Endian – the least significant byte is to be stored in
lower address.
2. Big Endian – the most significant byte is to be stored in
lower address.
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Basic Microprocessor Structure or Architecture
Structure of Data Storage in Memory MACHINE
ADDRESS
CODE
MOV SP,4000H BC 4000 0000H BC
MOV AL,90H B0 90 0001H 00
0002H 40
HLT F4
0003H B0
0004H 90
Assembly Language Machine Code
0005H F4
What is Burned in Memory
(Little Endian)
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Basic Microprocessor Structure or Architecture

B. Register Set in the given structure:
9. Index Register (IX) or Base Index Register (BX)
Index or base index register is used as an aid in addressing
data in tables stored in memory.
It can be incremented or decremented.

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Basic Microprocessor Structure or Architecture

C. Arithmetic Logic Unit (ALU)
It contains the microprocessor’s data processing major logic
and performs arithmetic and logic operations.
It is composed of adders/subtracters, comparators, and
different combinational circuits.

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PROGRAM COUNTER (PC)
A STACK POINTER (SP) ACCUMULATOR
D D (AC)
INDEX REGISTER (IX) A
D
T GENERAL PURPOSE
R MEMORY ADDRESS
A REGISTER (GPR) STATUS
E REGISTER (MAR)
A B ALU REGISTER
S
S B
U
B MEMORY S
U
S
MEMORY DATA INSTRUCTION
CONTROL UNIT
REGISTER (MDR) REGISTER (IR)
Fig. 14. Basic Microprocessor Architecture
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Basic Microprocessor Structure or Architecture
C. Arithmetic Logic Unit (ALU)
Examples of arithmetic operations:
1.addition/subtraction
2.increment/decrement
3. shift left/right, circular shift left/right.
Examples of logic operations:
AND, OR, XOR, NOT
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Basic Microprocessor Structure or Architecture
D. Control Unit
The control unit directs the operation of the microprocessor. It tells
the computer’s memory, ALU, and I/O devices how to respond to program’s
instructions.
Components:
1. Instruction Decoder
2. Timing Circuit
3. Control Logic
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PROGRAM COUNTER (PC)
A STACK POINTER (SP) ACCUMULATOR
D D (AC)
INDEX REGISTER (IX) A
D
T GENERAL PURPOSE
R MEMORY ADDRESS
A REGISTER (GPR) STATUS
E REGISTER (MAR)
A B ALU REGISTER
S
S B
U
B MEMORY S
U
S
MEMORY DATA INSTRUCTION
CONTROL UNIT
REGISTER (MDR) REGISTER (IR)
Fig. 14. Basic Microprocessor Architecture
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Basic Microprocessor Structure or Architecture

D. Control Unit
1. Instruction Decoder
The instruction decoder is the circuit responsible for
synthesizing and decoding the instructions fed or received by the
microprocessor.

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Basic Microprocessor Structure or Architecture

D. Control Unit
2. Timing Circuit
The timing circuit is used to synchronize the operation of
the different parts of the microprocessor.

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Basic Microprocessor Structure or Architecture

D. Control Unit
3. Control Logic
The control logic is used to send the control signals flowing
in the control bus to enable the different parts of the
microprocessor unit.

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FACTORS

Factors Affecting the Performance of a Microprocessor

1. Wordlength
2. Addressable memory locations
3. Speed of Operation
4. Registers available to the programmer
5. Instruction set
6. Addressing modes
7. Data types
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1. Wordlength
Microprocessors are often described in terms of the length
of their data words. Each microprocessor work on data word or
fixed length.
An 8-bit microprocessor means that its wordlength is 8 bits.
Consequently, a 16-bit microprocessor has a wordlength of 16
bits.

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2. Addressable Memory Locations

Each word in the memory is assigned a location number or
address. The value of the address varies from one processor to
another depending on the number of bits available in the address
bus of the processor.
The number of addressable locations a microprocessor can
address is 2n, where n specifies the number of addressable lines in
the address bus.
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3. Speed of Operation
Microprocessor’s speed is determined by the time it takes
the microprocessor to complete the fetch-decode-execute cycle
for one program step. Each microprocessor has an oscillator
circuit that sets its pace.
There are two ways to specify the speed of operation of a
microprocessor: (1) speed at which the clock operates, and (2)
number of instructions per second or IPS
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How is an instruction executed?
1. The first step the CPU carries out is to fetch some data and instructions
from the main memory.
2. The CPU then decodes the instruction and understands a specific set of
commands.
3. Then, the CPU executes the instruction as specified on the decoding
part.
4. Once an instruction is executed, the CPU sets itself up to begin another
cycle.
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4. Registers available to the programmer

In Intel 8086 microprocessor, there are four general purpose
registers that are accessible to the user: Accumulator Register
(AX), Base Register (BX), Count Register (CX), and Data Register
(DX).

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5. Instruction Set
In designing the instruction set of a microprocessor, it is
important to consider orthogonal instructions or the redundancy
of instructions.

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INSTRUCTION SET

Opcode is the part of the instruction that identifies the

operation that is to be performed. Each opcode is assigned a
unique letter combination called a mnemonic. Examples of
opcode in 8086 assembly are ADD, SUB, and MOV.
Operands identify the data that are to be processed as the
microprocessor carries out the operation specified by the opcode.
Operands can be from registers, memory data, or immediate
values.
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INSTRUCTION SET

In 8086 assembly language, each of the instructions must

specify when operation is to be performed and what data are to
be processed.
The format of 8086 assembly instruction is as follows:

Opcode Destination, Source

mnemonic operands

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INSTRUCTION SET

Instruction Types
Microprocessor instructions can be categorized as data
transfer instructions, data operation instructions, or program
control instructions.
Table 4. Examples per Instruction Type
Data Transfer Program Control
Data Operation Instructions
Instructions Instructions
MOV Arithmetic Operations (ADD, SUB) Unconditional Jump (JMP)
OUT Logical Operations (AND, OR, XOR) Conditional Jump (JXX)
IN Shift Instructions (ROR, ROL)
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INSTRUCTION SET

Instruction Format
• Three-operand Instruction Format
ADD B,C,D ADD B C D
B ß C+D Mnemonic Operand 1 Operand 2 Operand 3

• Two-operand Instruction Format

ADD AL,0FH ADD AL 0FH
AL ß AL+0FH Mnemonic Operand 1 Operand 2
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INSTRUCTION SET

Instruction Format
• One-operand Instruction Format
DEC AH DEC AH
AH ß AH-1 Mnemonic Operand 1

• Zero-operand Instruction Format

HLT HLT
(CPU stops) Mnemonic
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ADDRESSING MODE
Instructing the microprocessor as to the source and destination
of data.
o Direct Mode
o Indirect Mode
o Register Direct Mode
o Register Indirect Mode
o Immediate Mode
o Implicit Mode
o Relative Mode
o Index Mode and Base Index
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ADDRESSING MODE

Direct Addressing
o LDAC 20H
AC ß contents of address 20H

Indirect Addressing
o LDAC @20H

AC ß contents of address pointed by address 20H

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ADDRESSING MODE

Register Direct Addressing

o LDAC R

AC ß contents of register R

Register Indirect Addressing

o LDAC @R
AC ß contents of the address pointed by
register R
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ADDRESSING MODE

Immediate Addressing
o LDAC #20H

AC ß constant value 20H

Implicit (or Inherent) Addressing

o LDAC

AC ß from stack

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ADDRESSING MODE

Relative Addressing
1000H: LDAC $05H (2-byte instruction)
1002H: Next Instruction
: :
1007H: 7BH à to AC

AC ß contents of
{address of next instruction + offset value}
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ADDRESSING MODE

Index Addressing and Base Index Addressing

o If IX = 2000H (Index Register)

LDAC 1000H(X)

AC ß contents of {1000H + 2000H}

AC ß contents of {Base Address + IX (offset)}

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7. Data Types
There are four data types that a microprocessor can
understand and process.
• Unsigned and Signed Integers
• Unpacked and Packed Binary Coded Decimal (BCD)
• Single and Double Precision Floating Point Format
• Alphanumeric Codes
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REFERENCES

o Digital Design by Morris Mano

o Digital Computer Electronics by Malvino and Brown
o Computer Systems Organization and Architecture by John D. Carpinelli
o Digital design : With an introduction to the Verilog HDL / M. Morris Mano, Michael D. Ciletti
o Lecture Notes of Angelo R dela Cruz, Kanny Krizzy D. Serrano, Cristine Jin D.S. Estrada

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