Microprocessor: 8086

By
Dr. Sikder Sunbeam Islam
Associate Professor
Department of Electrical and Electronic Engineering
International Islamic University Chittagong
Introduction:8086 Features
 8086 is Intel‟s first 16 bit Microprocessor
 HMOS technology based
 Packaged in 40-pin DIP(Dual in line package)
 5V Power Supply
 Cloak Speed: 5 MHz (up to 8MHz)
 Has 20-bit address bus, hence it can address
up to of memory. Use segmented
memory
 External clock generator (such as Intel 8284)
chip is needed.
Introduction:8086 Features
continues
 Has 16 bit data bus
 Can be configured as (i) uni-processor
and (ii) multi-processor system (Bus
controller 8288 chip needed).
 6 Instructions can be prefetched from
program memory and queues them in
order to speed up instruction
execution.
8086 Architecture
 The 8086 CPU is internally divided into
two independent functional units:

 Dividing the work between these two

units speeds up processing.
8086 Architecture
 Execution Unit (EU)
The Execution Unit of the 8086 tells the BIU
where to fetch instructions or data form, decodes
instructions and executes instructions.
 EU Registers:
 The EU has nine 16 bit
registers AX, BX, CX,
DX, SP, BP, SI, DI and
Flag Register.
 The 16 bit general
registers AX, BX, CX,
DX can be considered as
8 bit registers (AH, AL;
BH, BL; CH, CL; DH,
DL)

Fig. EU 16 bit registers

 EU Registers:
AX Resister(Accumulator Register) :
 It is called 16 bit accumulator while AL is the 8-bit
accumulator.
 The I/O instruction always uses AX or AL for
inputting/ outputting 16 or 8 bit data to or from an
I/O port.
 Multiplication and division instruction also use the
AX or AL.

BX Resister(Base Register) :
 It is called base Register because it sometimes holds
the offset address of a location in the memory
system in all version of microprocessor .
 EU Registers:
CX Resister(Counter Register) :
 It is known as “Counter Register” because some
instructions such as SHIFT, ROTATE and LOOP
use the content of CX or CL as a counter.
 Example: The instruction LOOP START will
automatically decrement CX by 1 without
affecting the flags and will check if [CX]=0 to
stop the loop.
DX Resister(Data Register) :
 This general purpose register holds a part of the
result from multiplication or part of the dividend
before a division and reminder after the division.
 EU Registers: Flag Register
 A flag register is flip flop that indicates some
condition produced by the execution of an
instruction or controls certain operations of the EU.
 A 16-bit flag register contains 9 active flags.
 Some flag changes after many arithmetic and logic
operations.
 Flag never changes for any data transfer or
program control instruction/operation.
 Six of the nine flags are used to indicate some
condition produced by an instruction. Let us now
discuss these flags:
EU Registers: Flag Register
 Flag Register: Conditional flags
 C (Carry) flag: This flag is set if a carry after addition or
the borrow after subtraction that has been generated out
of the most significant bit position during the last
result calculation. The carry flag also indicates error
condition, as dictated by some programs and procedures.
 P (parity): This flag is set if the result has even parity
(number of „1‟ bits) ; it is zero if odd parity results.
 For example, if a number contains three binary one bits, it
has odd parity.
 A(auxiliary carry): It is set if the carry (half carry) after
addition or the borrow after subtraction between bit
position 3 and 4 of the result. This flag is used by BCD
arithmetic instruction (like, DAA). Otherwise, the A is zero.
Flag Register: Conditional flags
 Z(Zero): This flag is set if the result of an
arithmetic or logic operation is zero. If Z=1, the
result is zero; if Z=0, the result is not zero.
 S (Sign): This flag is set if most significant bit of
the result is one; otherwise it is zero.
 O (Overflow): Overflows occur when signed
numbers are added or subtracted. An overflow
indicates that the result has exceeded the capacity of
the machine or destination location.

The 8086 has three control bits in the flag register

that can be set or cleared by the programmer:
 Flag Register: Control flags
 D (direction): The direction flag selects either the
increment and decrement mode for the DI (direction index)
and SI (source index) registers during string instructions.
 If D=1, the registers are automatically decremented; if
D=0; the register are automatically incremented.
 The D flag is set with the STD (set direction) and clear
with CLD (clear direction) instructions.
 I (interrupt): The interrupt flag controls the operation of
the INTR (interrupt request) input pin. If I=1, the
interrupt pin is enabled. If I=0, the interrupt pin is
disabled. The state of the I flag bit is controlled by the STI
(set I flag) and CLI (clear I flag) instruction.
 T (trap): Setting Trap flag puts the 8086 in a single step
mode. In this mode 8086 generates an internal interrupt
after execution of each instruction.
BUS Interface Unit (BIU)
 BIU: The Queue
 The BIU‟s instruction queue is a First-in-First-out (FIFO) group
of registers in which up to 6 bytes of instruction code are pre-
fetched from the memory ahead of time.
 When EU is ready for its next instruction it simply reads the
instruction byte from this queue.
 If BIU is interrupted by EU while in process of fetching an
instruction, the BIU first complete fetching and then services the
EU.
 This is much faster than sending out an address to the system
memory and waiting for memory to send back the next
instruction byte or bytes.
 Fetching the next instruction while the current instruction
executes is called pipelining.
 If an instruction such as “Jump” or “Call” is encountered, the BIU
will reset the queue and begin refilling after passing the new
instruction to EU.
 BIU: Segment Registers
 All segment registers are of 16-bits.
 Code Segment (CS) register contains the base or start of the
current code segment and Instruction pointer (IP) register
contains the distance or offset from this address to the next
instruction byte to be fetched. Immediate data are considered as
part of code segment. Thus 20-bit physical address (PA) of
instruction is calculated from CS and IP (CS×10+ IP=PA).
 The Stack segment (SS) register points to the current stack. It
is used to hold the 16 bits starting address for the program stack.
Stack is reserve area in the memory. Stack pointer (SP)
register is used as an offset from the current SS during
execution of an instruction. Thus 20-bit physical address of
current available stack is calculated from SS and SP (SS×10+
SP=PA).
 The memory location where a word was most recently stored is
called the top of the stack.
BIU: Segment Registers
 BIU: Segment Registers-Stack
 PUSH operation is defined as writing to the top
or bottom of the stack.
 POP operation means reading from top or bottom
of the stack.
 When the stack pointer is accessed from the
bottom, the stack pointer is incremented after a
PUSH and decremented after POP operation
(reverse is done for top access).
 When 8-bit accumulator is used, the stack pointer
(SP) is incremented and decremented by „1‟.
Whereas the SP is increment or decrement by „2‟
for16-bit registers.
BIU: Seg.Reg.-Stack: PUSH
 BIU: Seg.Reg.-Stack: POP

Problem/Q: Suppose that an 8 bit microprocessor has a 16 bit stack pointer and uses
a 16 bit register in order to access the stack from the bottom. Assume that initially
the stack pointer and the 16 bit register contain 20C5 and 0120 respectively. After
a PUSH operation what are the contents of the stack pointer? What are the contents
of 20C6 and 20C7?
 BIU: Stack Seg: PUSH & POP instructions
 Examples:
 PUSHA; (Push all)—copies the content of the internal register
set ( following order AX,CX,DX, BX,SP,BP,SI and DI ), except
segment registers to stack.
 PUSH ‘A’; pushes 0041 H (ASCII code of „A‟) to stack.
 PUSHF; (Push flag)—copies the content of the Flag register to
stack.
 PUSH BX, the first byte of data copied to stack (memory location
addressed by SP in the stack segment) .
 POP BX; the first byte of data removed from stack (memory
location addressed by SP in the stack segment) into register BL.
 POPA; (POP all), reverse of PUSHA.
 POPF; reverse of PUSHF.
 POPCS; not valid
 POP 1000H—not valid.
PUSH & POP
instructions
Examples:
PUSHA; (Push all)
PUSHF; (Push flag)
 Stack: Two Pointer Registers
 Two pointer registers are used to access data in the
stack segment (SS) remains in EU:
 Stack Pointer (SP) register is used as an offset (to
store data at stack memory) from the current SS
during execution of an Instruction. Its content is
automatically updated due to execution of a POP or
PUSH instruction.
 Base Pointer (BP) register points to the memory
location for memory data transfer. BP contains an
offset address in the current SS. This offset is used in
based addressing mode.
 BP may be considered as user stack pointer while
SP is the system stack pointer (as SP used by some
8086 instruction automatically like, CALL)
 BIU: Segment Registers
 Extra Segment (ES) register and Data
Segment (DS) register are used to hold
the starting address of the two memory
segments that are used for data.
 From DS-register operands for most
instructions are fetched.
 ES-register points to the extra segment in
which extra data is stored. String
instruction uses ES and DS to find 20-
bit physical address for the destination.
 Two Index Registers
 Two Index registers remains in EU: Source
Index (SI) and Destination Index(DI).
 String Instruction uses SI and DI registers
together with DS and ES respectively in order to
distinguish between source and destination
addresses.
 Addressing Modes
 There are various techniques to specify
address of data. These techniques are called
Addressing Modes.
 The 8086 provides various addressing modes
to access instruction operands.
 The 8086 has 12 addressing modes. These
modes can be classified into five groups:
Addressing Modes: Register and
Immediate addressing mode
 Register Addressing Mode: Register addressing transfers a
copy of a byte or word from the source register to destination
register. Example:

 Mixing an 8-bit register with 16-bit, it is not allowed in

microprocessor
 Code segment register (CS) is never used as destination.
 Segment to segment MOV instruction is not allowed.
 Addressing Modes: Register and Immediate
addressing mode
 Immediate Addressing Mode: Immediate addressing transfers
the source, an immediate byte or word data (i.e. constant
data), into the destination register.


 Memory Addressing Mode: 8086 can not directly access to memory

operands. For accessing memory operands 8086 produces 20-bit
physical address using BIU.
 Every memory addressing mode has a standard default segment
register. However, a segment override instruction can be placed before
most of the memory operand instructions whose default segment
register is to be overridden.
Addressing Modes: Memory Addressing
Mode


 Addressing Modes: Memory Addressing
Mode
 Register Indirect Addressing: Register addressing
transfers a byte or word between a register and memory
location addressed by an index or base register
(SI,DI,SP,BP).


 Based Addressing: In this mode effective address is the

sum of displacement value and the contents of register BX
or BP.
 Example: MOV AX, 4[BX]; moves the contents of 20-bit
address computed from segment register (DS or SS) and
offset [BX+4] into AX. Displacement can be 8 or 16 bit
signed.
 Addressing Modes: Memory Addressing Mode

 Indexed Addressing :Effective address is calculated from the

sum of displacement value and the contents of register SI or
DI.
 Example: MOV CX, [BX+DI] ; Copies the word content of the
data segment memory location addressed by BX plus DI into
CX.
 MOV [BP+DI], AH ; Copies AH into stack segment memory
location addressed by BP plus DI
 Based-Indexed Addressing : Effective address is calculated
from the sum of base register, index register and displacement
value .
 Example: MOV AX, 4[BX][DI] ; Moves the content s of 20-bit
address computed from the segment register (like, DS here)
and [BX]+[DI]+4 into AX.
 Remember that BX, DI or SI addresses data segment and BP
addresses the stack segment.
Addressing Modes: Memory Addressing Mode

 STRING ADDRESSING: This mode uses Index register. SI

is assumed to point to the first byte or word of the source
string and DI is assumed to point to the first byte or word of
the destination when string instruction is executed.
 SI or DI is automatically incremented or decremented to point
to the next byte or word depending on DF (Direction flag)
 The default segment register for Source is DS here.
 EXAMPLE: MOVS WORD;
 If [DF]=0, [DS]=3000H, [SI]=0020H, [ES]=5000H,
[DI]=0040H, [30020]=30H, [30021]=05H, [50040]=06H,
[50041]=20H.
 After MOVS WORD, [50040]=30H, [50041]=05H,
[SI]=0021H, [DI]=0041H.
 Addressing Modes: Port Addressing

 Two I/O port addressing is used : direct and

indirect port modes.
 In either case 8 or 16 bit I/O transfer must take
via AL or AX register.
 Example: Direct port mode: IN AL,02H; moves
the content of port 02 to AL register.
 Indirect port mode: If [DX]=0020H, [Port
0020]=01H; [Port 0021]=03H; then after
IN AX,DX; the contents of register AX=0301H
Or, IN AL,DX; the contents of register AL=01H
Addressing Modes: Relative Addressing

 Relative Addressing: Instruction in this mode

specify the operand as a signed 8-bit displacement
relative to PC.
 Example: JNC START; (JNC-Jump if No Carry)
here if carry=0, the PC (program counter) is
loaded with current PC contents + the 8-bit signed
value START, otherwise next instruction will be
executed.
 Implied Addressing: Instruction in this mode has
no operand.
 Example: CLC; which clears the carry flag to zero.
 Exercise:
Q1. Spot the syntax errors in the following instructions:

Q2. Suppose that DS=1300H, SS=1400H, BP=1500H, BX=0100H,

SI=0100H and LIST=0008H. Determine the physical address accessed by
each of the following instructions:
(i) MOV DL, [BX+100] (ii) MOV CL,LIST[BX+SI] (iii) MOV
[BP+SI],AH
References
 Microprocessor and Interfacing Programming and Hardware;
Douglas V Hall, 2nd Edition.
 Microprocessors and Microcomputer-Based System Design;
Mohammed Rafiquzzaman, revised edition.
 Microprocessor & Interfacing Lecture Materials ;Mohammed Abdul
kader, IIUC.
 The Intel Microprocessor; B.B. Brey, Seventh Edition.