Modes of I/O Data Transfer

• Data transfer between the central computer and I/O devices may be handled in a variety of
modes .
• Some modes use the CPU as an intermediate path others transfer the data directly to and from the
memory unit.
• Data transfer between the central unit and I/O devices can be handled in generally three types of
modes which are given below:
1. Programmed I/O
2. Interrupt Initiated I/O
3. Direct Memory Access
Programmed I/O
• Programmed input/output (PIO) is a method of transferring data between the CPU and a
peripheral, such as a network adapter.
• Programmed I/O instructions are the result of I/O instructions written in computer program. Each
data item transfer is initiated by the instruction in the program.
• Usually the program controls data transfer to and from CPU and peripheral.

• Transferring data under programmed I/O requires constant monitoring of the peripherals by
the CPU.
• Once the data is initiated the CPU starts monitoring the interface to see when next transfer can
made. The instructions of the program keep close tabs on everything that takes place in the

interface unit and the I/O devices.

Programmed I/O
Programmed I/O
 Interrupt Initiated I/O

• In the programmed I/O method the CPU stays in the program loop until the I/O unit indicates that
it is ready for data transfer. This is time consuming process because it keeps the processor busy
needlessly.
• This problem can be overcome by using interrupt initiated I/O.
• In this when the interface determines that the peripheral is ready for data transfer, it generates an
interrupt.

• After receiving the interrupt signal, the CPU stops the task which it is processing and service
the I/O transfer and then returns back to its previous processing task.
 Interrupt Initiated I/O

• the interface meanwhile keeps monitoring the device. Whenever it is determined that the device
is ready for data transfer it initiates an interrupt request signal to the computer.
• Upon detection of an external interrupt signal the CPU stops momentarily the task that it was
already performing, branches to the service program to process the I/O transfer, and then return to
the task it was originally performing.
Interrupt Initiated I/O
 Direct Memory Access (DMA)
 The transfer of data between a fast storage device such as magnetic disk and memory
is often limited by the speed of the CPU. Removing the CPU from the path and
letting the peripheral device manage the memory buses directly would improve the
speed of transfer. This transfer technique is called Direct Memory Access (DMA).

• During the DMA transfer, the CPU is idle and has no control of the memory buses. A
DMA Controller takes over the buses to manage the transfer directly between the I/O
device and memory.
DMA module controls exchange of data between main memory and the I/O device.
CPU is only involved at the beginning and end of the transfer and interrupted only
after entire block has been transferred.
Direct Memory Access needs a special hardware called DMA controller (DMAC)
that manages the data transfers and arbitrates access to the system bus.
 Direct Memory Access (DMA)

During DMA transfer, the

CPU is idle and has no
control of the memory
buses.
• The buses can be
disabled by using two
special control signals.


Bus Request (BR)

Bus Grant(BG)
 Direct Memory Access (DMA)

Bus Request : It is used by the DMA controller to request

the CPU to relinquish the control of the buses.

Bus Grant: It is activated by the CPU to inform the

external DMA controller that the buses are in high
impedance state and the requesting DMA can take
control of the buses. Once the DMA has taken the
control of the buses it transfers the data. This transfer
can take place in many ways.
 DMA Controller

During the DMA transfer, the CPU is idle and has

no control of the memory buses. A DMA controller takes
over the buses to manage the transfer directly between
the I/O device(s) and main memory.The structure of
DMA controller is described below.
DMA Controller
 DMA Controller
The control unit communicates the CPU via data bus and control lines.
The DMA controls the system bus using BR (Bus Request) and BG (Bus Grant)
signals.
DMA operates read and write operations via RD (Read) and WR (Write) signals.
DMA sends request and acknowledge to I/O devices via DMA request and DMA
acknowledge signals.
The registers in DMA are selected by CPU through the address bus by enabling
DS (DMA Select) and RS (Register Select) inputs.
All registers in the DMA appear to the CPU as I/O interface registers.
The address register contains an address to specify the desired location in
memory.
The word count register holds the number of words to be transferred. The
control register specifies the mode of transfer.
 DMA Controller
Types of DMA transfer using DMA controller:

Burst or block transfer DMA


It is the fastest DMA mode.

In this mode, two or more data bytes are transferred
continuously.

Cycle Steal or Single Byte Transfer DMA


In cycle steal transfer only one byte of data is transferred at
a time.

This type of DMA is slower than burst DMA.
 I/O Processor

➢ I/O Processors also known as:

➢I/O Controllers
➢Channel Controllers
➢Peripheral Processing units (PPU)
➢Data Channel
 I/O Processor
• IOP is similar to a CPU except that is designed to handle the details of I/O
processing

• The IOP can fetch and execute its own instruction. IOP instruction are specifically
designed to facilitate I/O transfer.

• IOP may be classified as a processor with direct memory access capability that
communicate with I/O devices

• Each IOP takes care of input and output task , relieving the CPU from the house
keeping chores involved in I/O transfers.
I/O Processor
Central
processing
unit (CPU)

Peripheral
devices

Memory
Memory unit
Bus P P P P
D D D D

Input-output
processor
I/O
(IOP) bus
 I/O Processor
●
The memory unit occupies a central position
and can communicate with each processor by means of direct
memory access.
●

The CPU is responsible for processingdata needed in the solution

of computational tasks.
●

The IOP providesa path for transfer of data between

various peripheral devices and the memory unit.
●
The CPU usually assigned the task of initiating the I/O program.
●
From then on the IOP operates independent of the CPU and
continious to transfer data from external device and memory.
 CPU-IOP Communication
CPU
operations IOP
operations
Send instruction to test
IOP.path
Transfer status word
to memory
If status OK, then send
start I/O instruction
to IOP. Access memory for IOP
program

CPU continues with

another program Conduct I/O transfers
using DMA;
Prepare status report.

I/O transfer completed;

Interrupt CPU
Request IOP status

Transfer status word to

Check status word for memory location
correct transfer.

Continue
 CPU-IOP Communication
●
The CPU sends an instruction to test the IOP path.
●
The IOP respondsby inserting a status word in memory
for the CPU to check.
●
The staus word indicates the condition of the IOP and device. such
as : IOP overload condition , device busy with another transfer , or
device ready for I/O transfer.
●
The CPU refers to the status word in memory to decide what to
do next.
●
If all is in order , the CPU sends the instruction to start I/O
transfer.
●
The memory address recieved with the instruction tells the IOP
where to find its program.
 CPU-IOP Communication

The CPU can now continue with another program while the IOP
is busy with the I/O program.

IOP conduct I/O transfer using DMA.

When IOP complete the I/O transfer , it send an interrupt
request to the CPU and prepare a status report and place it
into a specified memory location.

The status word indicates whether the transfer has been
completed or if any errors occured during the transfer.
 Classification of Memory
Classification of Memory

Functionality Access Capability Technology

Cache Memory
Random Access Magnetic core
RAM
Main Memory
Sequential Magentic Bubble
Auxiliary Memory ROM

Semi random Semi conductor

Virtual Memory
By Functionality-Main Memory

Central Storage of Computer System.

Large & fast memory to store programs and data during computer
operations.

Mostly made up of RAM chips, but a portion of it is also used as
ROM to store program permenantly.

The average time required to read the contents of a location or
write into a location in main memory is called Access time.

Main memory has equal access time for all its locations that is why
it is called Random access memory.

After the access is over, main memory needs time to settle down
for the next transfer to start. This is known as settling time or
recovery time.

The sum of access time and settling time is known as cycle time.
By Functionality-Auxiliary
Memory

It is also known as Secondary Memory.

The most common secondary memory devices in our system
are magnetic disks, tapes and optical disk.

It stores a large amount of data and programs. As the
capacity is more they are slower and cheaper than main
memory.

The CPU generally brings a part of program from the
secondary memory into main memory and thus it treats
secondary devices as peripheral devices.
By Functionality-Cache Memory

Cache memory is a very high speed semiconductor memory which can
speed up the CPU.

It acts as a buffer between the CPU and the main memory. It is used to
hold those parts of data and program which are most frequently used
by the CPU.

The parts of data and programs are transferred from the disk to cache
memory by the operating system, from where the CPU can access
them.
By Functionality-Cache Memory

Characteristics of Cache Memory

Extremely fast memory type that acts as a buffer between
RAM and the CPU.

Holds frequently requested data and instructions, ensuring
that they are immediately available to the CPU when needed.

Costlier than main memory or disk memory but more
economical than CPU registers.

Used to speed up processing and synchronize with the high-
speed CPU.
By Functionality-Cache Memory

Levels of Memory

Level 1 or Register: It is a type of memory in which data is stored and
accepted that are immediately stored in the CPU. The most commonly
used register is Accumulator, Program counter , Address Register, etc.

Level 2 or Cache memory: It is the fastest memory that has faster
access time where data is temporarily stored for faster access.

Level 3 or Main Memory: It is the memory on which the computer
works currently. It is small in size and once power is off data no longer
stays in this memory.

Level 4 or Secondary Memory: It is external memory that is not as
fast as the main memory but data stays permanently in this memory.
By Functionality-Cache Memory


Types of Cache Memory:-

1. Unified cache: it is a common cache memory that can store

both instructions and data
2. Split cache: it has a separate cache to store instructions and
data
By Functionality-Virtual Memory

Virtual memory is a concept used to construct large programs though the physical
memory has limited space.

The Operating System the keeps the large program in the secondary memory and
brings only a part of the program in main memory.

The address generated by the CPU is known as Virtual Address.

Each virtual address is mapped to physical address in main memory.

The mapping or translation is handled by the operating system and the CPU Hardware.

The user is given an illustration of a large memory for his use, even though the system
has small main memory.
By Access Method-Random
Access Method

It is termed as the method to access the different locations of
memory.

Main memory is a Random Access Memory as any location can
be accessed within same access time. i.e. access time is constant
and independent of the location accessed.

Semi conductor memory is example of Random Access Memory.
By Access Method-Sequential
Access Method

The location to be accessed is brought under the read/write head.
The read-write head is shared by the storage locations.

They must be assigned to different locations at different times
either by moving the storage location or read-write head or both.
Many sequential access memories operate by moving the stored
information around a closed path known as track.

A particular location can be accessed when it passes the fixed
read-write head.

Thus the acces time depends on the location.

Magnetic tape is example of Sequential Access Memory.
By Access Method-Sequential
Access Method
By Access Method-Semi Random
Method

In Semi Random Memory, access to the location is done
by (1) one random access and (2) one sequential access.

Hard disk and floppy disk are examples of Semi Random
Memory. These memory devices contain many rotating
storage tracks.

If each track has its own read-write head, the tracks can
be accessed randomly, but access within the track is
serial.
By Capability-RAM

Random Access Memory

It allows both read and write operation. It is
also known as RAM (Random Access
Memory).

The memory capacity is 128 words having
word length of 8 bits Thus it requires a 7-bit
address (as 128=27) and an 8-bit
bidirectional data bus.

The RD (read) and WR (write) signal indicates
the operation to be performed. The two chip
select lines CSI and CS2 are used for
enabling the chip when it is selected by the
microprocessor.

When CS1-land CS2-0, the chip is activated.
By Capability-ROM

Random Access Memory

Since ROM does not allow write
operation, only RD signal for read
operation is present.

The 8-bit data bus is in output mode
only.

The two chip select lines CSL and are
used for enabling the chip.

The read and write signal indicates the
operation to be performed.

Though technically ROM is also
random access memory.
By Technology-Magnetic Core

Earlier, mainframes and minicomputers used magnetic core
memory but nowadays they are replaced by semiconductor
memories.

Magnetic core memories required more power and were
slow. They were non volatile in nature i.e. the contents of
memory did not get erased after the power is removed.

But after every read operation it is necessary to perform a write
operation to restore its contents. Thus, the cycle time is more.
By Technology-Semiconductor
Semiconductor memory consumed less power, has low access time
(fast) and the write operation was not needed after every read operation
By Technology-Semiconductor
RAM (Random Access Memory)

RAM refers to the magnetic memory which permits read as well as
write operation. Main memory is a random access memory i.e. the
memory can be accessed for information transfer from any random
location. As a result, the access from the memory becomes
independent of the location There are two important types of RAM's:


SRAM (Static RAM): In static RAM, the data stored is lost when the
power is switched off Each cell is like Flip-flop, which can store Dar
1 till the power supply is provided.
By Technology-Semiconductor
RAM (Random Access Memory)

DRAM (Dynamic RAM): In Dynamic RAM, the cell is like a
capacitor which can store 0 or 1 but gets discharged after some
time. Thus it loses its contents in a short time even though
power is on Therefore, the contents of the cell should be written
again. This is known as refreshing. DRAM is cheaper than
SRAM but has slow speed of operation than SRAM. Most of the
modern processor's memory is composed of DRAM. SRAM and
DRAM use CMOS technology which consumes less power.
By Technology-Semiconductor
RAM (Random Access Memory)

Type of DRAM::
FPM Dram: First page mode DRAM
EDO Dram: Extended data-out DRAM
SDRAM: Synchronous DRAM
DDR SDRAM: Double data rate synchronous DRAM
RDRAM:Rambus DRAM
Dual ported DRAM
SIMM and DIMM: Single inline and Double inline.
By Technology-Semiconductor
ROM (Read Only Memory)

ROM: ROM (Read Only Memory) is a non erasable storage device which
has the data fixed in it at the time of manufacture. It is possible to read
from ROM but data cannot be written on or deleted from it. ROM's are
cheaper than RAM's when produced in large volumes.

CD-ROM is an example of this type of memory.

By Technology-Semiconductor
ROM (Read Only Memory)

PROM (Programmed Read Only Memory): It is a field programmable

device. As in ROM the contents cannot be modified after
manufacturing, PROM gives the facility to the user to program ROM as
per his requirements. But once programmed, the contents cannot be
deleted. It is cheaper as the user purchases the chip from the market and
programs it rather than order the ROM with the manufacturer. A special
equipment PROM programmer is used to store programs in a PROM.
By Technology-Semiconductor
ROM (Read Only Memory)

EPROM (Erasable Programmable Read Only Memory): EPROM as the

name suggests allows the contents of PROM to be deleted by using
ultraviolet rays. The chip has to be removed from the system to be
exposed to UV light. Deleting one or more locations is not possible
but the entire contents of EPROM are erased. Thus, contents of PROM
which is used as ROM in a system can be erased and reprogrammed to
suit the changed requirements.
By Technology-Semiconductor
ROM (Read Only Memory)

EAROM (Electrically Alterable ROM) or EEPROM (Electrically Erase

PROM))

In EAROM the contents are deleted electrically. The contents of any

location can be altered without erasing the complete contents. It can
be reprogrammed and erased more than 10,000 times. Also it requires
less time to erase the data i.e. few milliseconds as compared to EPROM
which takes 10-20 minutes.
By Technology-Semiconductor

Flash Memory

It is a special type of EEPROM which can be modified and erased in

blocks of words in one operation. Individual words can also be erased and
modified. It uses one transistor for memory cell resulting in high packaging
density, low power consumption and low cost. Due to its low power
consumption it is used in battery driven digital devices like mobile phones,
digital cameras etc. They are faster but costly.