BASIC PROCESSING UNIT

28 March 2025 11:45

INTRODUCTION
Instruction Set Processor
SOME FUNDAMENTAL CONCEPTS:-
Q) How to execute and process a set of instruction given?
 To execute a program, the instruction is first fetched one at a time and performs the operations
specified.
 Instructions are fetched from successive memory locations until the jump or branch instruction is
occurred.
 Processor keeps track of the memory location containing the next instruction that is to be fetched
using the program counter.
 After fetching an instruction, the contents of the program counter are updated to point the next
instruction of the sequence.
 A branch instruction may load different value to the program counter.
 Another key register in the processor is the instruction register.
Q) What are the steps the processor has to perform in order to execute an instruction?
 Fetch the contents of memory location pointed by the program counter. The contents of this location
are interpreted as instruction that is to be executed. They are loaded to IR.
IR <- [PC]
 Assuming that the memory is byte addressable, increment the contents of the program counter by 4.
 PC <- [PC] + 4
 Carrying out the instructions specified by the instruction register.
Q) Draw a single bus organisation of the Datapath inside a inside a processor?

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 The internal processor bus is connect to the MAR and MDR registers.
 The address lines and data lines of the memory bus are connected to the MAR & MDR and then to the
internal processor bus.
 Registers provided are special purpose registers namely index registers and stack pointers.
 Registers Y, Z & Temp are used for temporary storage for execution of an instruction.
 The mux select either the output value of register Y or the constant value of 4 to be provided as the
input A of the ALU.
Select 4 or Select Y
REGISTER TRANSFERS:-
 Instruction execution steps involve transferring data from one register to another
register.
 For each register, two control signals are present.
 What does that control signal do?
-> for each register, two control signals are present which is used to place the
contents of the register on the bus or load the data on the bus into the register.
 So there are two option that is load the data on the bus into Ri or place the contents
of Ri on the bus.
 There is a register Ri which contains input and output register: Ri in and Ri out
which are connected to the bus via switches.
 If Ri in = 1, the data on the bus are loaded to Ri.
 If Ri out = 1, the contents of the register Ri are placed on the bus.
 If Ri out = 0, the bus can be used for transferring data from other registers.
Q) What do we have to do if we want to transfer the contents of register R1 to register
R4?
 Enable the output of register R1out =1.
 This places the contents of the register R1 into the processor bus.
 Enable the input of register R4in =1 .
 This load the data from the processor bus into register R4.
Q) What is a processor clock?
 All operation and data transfer within the processor takes places within the time
period defined as processor clock. The control signal that control the specific
instruction transfer are asserted at the start of the clock cycle.
Q) What are multiphase clocking?
 Data transfers can use both the rising and falling edges of the clock.
 When edge triggered flipflops are not used, two or more clock signals may be needed
to guarantee proper transfer of data.
 This is known as multiphase clocking.
PERFORMING AN ARITHMETIC OR LOGIC OPERATION
 ALU -> combinational circuit -> no internal storage.
 Performs arithmetic and logic operations.

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

Q) Add the contents of register R1 to those of register R2 and store in the result in register R3?
 R1 out, Yin
 R2 out, Select Y, Add, Zin
 Zout, R3in
Q) Explain how can we execute these programs?
 The programs or instructions that are given in certain steps are activated respectively for the
duration of the clock cycle corresponding to the next step. All other instructions other than the
instructions mentioned in the step are inactive.
 Hence step is R1out, Yin therefore , R1out = Yin = 1 that causes the contents of this register to be
transferred over the data bus.
 The contents of R2 are gated onto the bus and hence to the input B.
 The function performed by ALU depends on the signals applied to its control lines.
 In this case, Add line is set to 1, causing the output of the ALU to be the sum of two numbers at the
inputs A & B.
 The sum is loaded into register Z because its input control signal is activated.
 The contents of register Z are transferred to the destination register R3.
 This last transfer cannot be carried out during step 2 because only one register output can be
connected to the bus during any clock cycle.
Q) What is the function of ALU?
 ALU can perform eight different operations, three control signals would suffice to specify the required
operation.
FETCHING A WORD FROM MEMORY
Q) How to fetch a word from memory?
 To fetch a word or an information from the memory, first the processor has to specify the address of
the memory location where the information is stored and request a read operation.
 This applies whether the information to be fetched represents an instruction in a program or an
operand specified by an instruction.

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 operand specified by an instruction.
 The processor transfers the required address to the MAR, whose output is connected to the address
lines of the memory bus.
 At the same time the processor uses the control lines of the memory bus to indicate that a read
operation is needed.
 When the requested data are received from the memory, they are stored in register MDR, from where
they can be transferred to other registers in the processor.
Q) Explain the purpose of MDR in the processor?
 The connections for register MDR are there in the figure:

 MDR has four control signals: MDRin and MDR out is used for the internal bus
 MDRinE and MDRoutE are used for the external bus.
 A three input multiplexer can be used with the memory bus data line that is connected to the third
input.
 This input is selected when MDRinE = 1.
 A second tri-state gate is controlled by MDRoutE can be used to connect the output of the flip-flop to
the memory bus.
EXTRA POINTS
 During the Read & Write operations, the timing of internal processor operations must be co ordinated
with the response of the addressed device on the memory bus.
 The processor completes one data transfer in one clock cycle.
 The speed of operation of the addressed device varies with the device.
 Modern processor includes a cache memory on the same chip as the processor.
 A cache will respond to a memory read request in one clock cycle.
 When a cache miss occurs the request is forwarded in to the main memory which introduces a delay of
several clock cycles.
 A read or write request may also be intended for a register in a memory-mapped I/O device.
 Such I/O registers are not cached, so their accesses always take a number of clock cycles.

Whatever we request whether it is a read or write operation, the data will be inside MDR and from here
the data will be transferred to the corresponding devices.
Suppose we have a data A which contains data 10, it will first go to MDR and then to register R1 and to
do this once we read the data and store the data in MDR and to complete the total process a control
signal will be used and the function is known as Memory- Function- Completed (MFC) control.
If MFC = 1 then we get to know that the specific work has been completed and then the processor will
transfer the data from MDR to other location.
Q) What are the actions needed to execute the instruction Move(R1), R2:
 The actions needed to execute the instruction Move(R1), (R2):-
 Suppose we have the data 10 which is stored in 100th location of register R1. Therefore according to
the first step the MAR operation will be performed which will read the data from the register.
MAR <- [R1]
Start the Read operation on the memory bus.

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  Start the Read operation on the memory bus.
 Wait for the MFC response from the memory. If MFC=1 then we can transfer the data to the other
location from the MDR.
 Load MDR from the memory bus.
 R2 <- [MDR]
 Except action 3, each action can be completed in one clock cycle.
Q) What are required steps that follow the memory read operation?
 R1out, MARin, Read
 MDRinE, WMFC
 MDRout, R2in
 WMFC is the control signal that causes the processor's control circuitry to wait for the arrival of the
MFC signal.
TIMING OF A MEMORY READ OPERATION

STORING A WORD IN MEMORY

Q) Execute Move R2,(R1)?
 R1out , MARin
 R2out, MDRin, Write
 MDRoutE, WMFC
EXECUTION OF A COMPLETE INSTRUCTION
Suppose we have instruction Add (R3), R1

Suppose the data given is stored in the Instruction Register IR. The data from the instruction register
goes to the instruction decoder or control logic as output and the decoder will tell what operation to
perform.
So at first we have to take the data from Program Counter (PC) to MARin and we know that MARin is
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 So at first we have to take the data from Program Counter (PC) to MARin and we know that MARin is
used to read the instruction or operand in an operation. Then we have to go to program counter to
update it as pc holds the address of next instruction. The data comes in MDR and to perform any
arithmetic and logic operations, we have to go to ALU.
Execution Of Complete Instruction In Computer Architecture- Hindi

 PC out, MARin, Read, Select 4, Add, Zin

 Zout, Pcin, Yin, WMFC
 MDRout, Irin
 Offset-field-of-IRout, Add, Zin
 Zout, Pcin, End
This is the control sequence for an unconditional branch instruction.
In case of conditional branch, we need to check the status of the condition codes before loading a new
value into the PC.
For a Branch-on-negative (Branch < 0) instruction, step 4 is replaced with
Offset-field-of-IRout, Add, Zin. If N=0 then End.
If N=0, then the processor return to step 1 immediately after step 4 and if N=1 then the step 5 is
performed to load a new value into PC and therefore performing the branch operation.
MULTIPLE BUS ORGANIZATION

Three ports
There are two outputs allowing the contents of two different registers to be accessed simultaneously and
their contents placed on buses A and B. The third port allows the data on bus C to be loaded into a third
register during the same clock cycle.
Buses A & B :- transfer source operands to the A & B inputs of the ALU, where the arithmetic and logic
operation maybe performed. The result is transferred to destination through the bus C.
Using the incrementor eliminated the need to add 4 to the PC using the main ALU.
The source for the constant 4 can be useful for the other address such as the memory address in
LoadMultiple and StoreMultiple instructions.

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 HARDWIRED CONTROL
Each state, or count, of this counter corresponds to one control step.
Q) How can the required control signals be determined?
 The required control signals are determined by the following information:
 Contents of the control step counter.
 Contents of the instruction register
 Contents of the condition code flags
 External input signals, such as MFC and interrupt requests.
Control Unit Organization

The decoder/ encoder block in the figure is a combinational circuit that generated the
required control outputs, depending on the state of all its inputs.
The step decoder provides a separate signal line of each step, or time slot, in the
control sequence.
Similarly the output of the instruction decoder consists of a separate line for each
machine instruction.
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machine instruction.
For any instruction loaded in the IR, one of the output lines INS1 through INSm is set
to 1 and all other lines are set to 0.
Zin = T1 + T6.ADD + T4.BR+…..
End = T7.ADD + T5.BR+ (T5.N + T4.N bar).BRN+….

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 A COMPLETE PROCESSOR

A single cache stores both instructions and data. The processor is connected to the
system bus and hence to the rest of the computer by means of a bus interface.

MICROPROGRAMMED CONTROL
Q) For the given the control sequence for execution of the instruction Add(R3),R1 then make the
microinstruction of the same?
 PCout, MARin, Read, Select4, Add, Zin
 Zout, Pcin, Yin, WMFC
 MDRout, Irin
 R3out, MARin, Read
 R1out, Yin, WMFC
 MRDout, Select Y, Add, Zin
 Zout, R1in, End

The control word corresponding to 7 steps are shown here.

Here we have assumed Select Y=0 and Select 4=1
A sequence of control words corresponding to the control sequence of a machine instruction
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  A sequence of control words corresponding to the control sequence of a machine instruction
constitutes the micro routine for that instruction and the individual word in a micro routine is known
as micro instruction.
Q) what is a control store?
 Micro routines for all instructions in the instruction set of a computer are stored in special memory
known as the control store.
 To read the control words from the control store, a micro program counter is used.
Q) What does the micro program counter do?
 Every time a new instruction is loaded to instruction register, the starting address generator is loaded
into the micro program counter.
 The micro program counter is then automatically incremented by the clock causing the successive
micro instructions to be read from the control store.
 Hence the control signals are delivered to various parts of the processor in the correct sequence.

 The figure explains the basic organization of a micro programmed control unit.
Q) Mention the micro routine for the branch instruction Branch < 0?

Q) Draw the flowchart for the organization of the control unit to allow conditional branching in the
micro program?

 In the control unit the micro program counter is incremented every time a new micro instruction is
fetched from the microprogram except in the following situations:-
When a new instruction is loaded in IR, the micro program counter is loaded with the starting address
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 When a new instruction is loaded in IR, the micro program counter is loaded with the starting address
of the micro routine for that instruction.
 When a branch instruction is encountered and the branch condition is satisfied, the micro program
counter is loaded with the branch address.
 When an End micro instruction is encountered, the micro program counter is loaded with the address
of the first control word in the micro routine for the instruction fetch cycle.
MICRO INSTRUCTIONS:

MICRO PROGRAM SEQUENCING

 A micro routine is entered by decoding the machine instruction into a starting address that is loaded
into the micro program counter.
 Add src, Rdst:- Add the source operand to the contents of register Rdst and places the sum in Rdst,
the destination register.
 Let us assume that the source operand can be specified in the following addressing modes: register,
auto increment, auto decrement and indexed as well as the indirect forms of these modes.
 Very very important:- flowchart of a microprogram for the Add src, Rdst instruction:-

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

Branch Adress Modification Using Bit- Oring

 Branches are not always made up of single branch address.
 The most efficient way to bypass micro instruction 170 in the figure is to have a preceding branch
micro instructions specify the address 170 and then use an OR gate to change the least significant bit
of this address to 1 if the direct addressing mode is involved. This is known as bit - Oring technique
for modifying branch addresses.
 170 = 001 111 000 ; 171 = 001 111 001
WIDE BRANCH ADDRESSING
 In the above flow chart a wide branch instruction is located at location 003.
 Instruction decoder: generated the starting address of the micro routine that
implements instruction that has just been loaded into the IP.
 The addressing modes specified in the chart:- Indexed, Auto increment, Auto
decrement, Register direct, Register Indirect : 161, 141, 121, 101, 111 are the
addressing modes used in the instruction.
 If the branch is allowed to happen in the first clock cycle, the micro instruction at
location 171 would be fetched and executed transfer in progress to be completed, that
is the WMFC signal must inhibit any change in the contents of the micro program
counter during the waiting period.

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