EE477L MOS VLSI Circuit Design

- Spring 2025
Lab3
Due: By the end of March 21, 2024

Notes:
1. This assignment is based on individual work. No collaboration is allowed.
2. The design you did in this lab will be used as part of your final project. If you aim for the
top team for winning the bonus points, be sure to optimize your design with regards to
area/delay etc.
3. You are expected to submit a pdf file as your lab report, which includes screenshots
and any explanatory text you find necessary. Notice that lab reports with other formats
will not be graded. You don’t need to submit any source file unless specifically stated.
4. Submit the pdf file to DEN→Assignments→Lab3.
5. Ask your questions ONLY in Piazza discussion section or use office hours. Do NOT
send emails asking technical questions.

Submission guideline

1. Report should be named as LAB3_FirstnameLastname_USCID.pdf. For example,

LAB3_TommyTrojan_1234567890.pdf.
2. In the report, include all required screenshots and make sure your every screenshot
shows your username. Include any text you find necessary for helping grader to grade
your report.

Part A: 1-bit Full Adder Schematic

The half adder adds two inputs A and B, generates a Sum and a Carry-out. The truth table
for a half adder is shown below.
 Input Output

A B S Cout

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

The full adder adds two inputs A and B and the Carry-in, generates a Sum and a Carry-out.
The truth table for a full adder is shown below.

Input Output

A B Cin S Cout

0 0 0 0 0

0 1 0 1 0

1 0 0 1 0

1 1 0 0 1

0 0 1 1 0

0 1 1 0 1

1 0 1 0 1

1 1 1 1 1

The schematic of a 1-bit full adder is given as:

1) Draw the schematic of the 1-bit full adder.
• You need to use 1X design for all five gates. For example, gate#1 should be
XOR_1X, gate#3 should be NAND_1X. You don’t need to scale up any gates at
this moment.
• Full adder cell name: FA_1b
• Inputs: A, B, Cin; outputs: S, Cout
2) Draw the symbol of the 1-b full adder.

3) Perform functional test for all input patterns.

• Waveform should clearly show all 5 signals and all 8 possible input combinations
and their corresponding output.
• FO4 testbench is required for Cout and S. However, for simplicity, the BUFFER for
each DUT input is two INV_1X connected in series, the LOAD of each DUT output is no
longer four DUT copies but instead a simple INV_4X.

4) Delay measurement for path Cin→S

In this step, you need to scale some certain gates and measure the rising propagation
delay and falling propagation delay.
1. The gates you can scale: Gate#1 and #2
Note: You need to try different combinations of their 1X, 2X and 4X version.
There are 9 combinations in total.
2. The gates you shouldn’t touch: Gate#3, #4, and #5
Note: They all should be fixed at 1X.
You need to calculate average delay of rising and falling for each gate size combination.
• Cin→S rising delay happens when (A,B,Cin): (011)→(010)
• Cin→S falling delay happens when (A,B,Cin): (010)→(011)
• FO4 Testbench is required. The BUFFER for each DUT input is two INV_1X
connected in series, the LOAD of each DUT output is a simple INV_4X.
 • Note: When plotting the waveform in simulation, you need to probe the DUT’s
inputs/outputs, not the global inputs/outputs of the testbench.

5) Report the gate size combination with minimum average delay for path Cin→S. Also,
tabulate your rising, falling, and average delay for all gate size combinations.
●​ If more than one size combination has minimum average delay, report the gate
size combination with minimum area. E.g., (Gate#1, Gate#2): (1X, 2X) has less
area than (Gate#1, Gate#2): (1X, 4X).

6) Delay measurement for path Cin→Cout -------Similar to task (3) In this step, you need
to scale some certain gates and measure the rising propagation delay and falling
propagation delay.
1. The gates you can scale: Gate#3 and #5
2. The gates you shouldn’t touch: Gate#1, #2, and #4
You need to calculate average delay of rising and falling for each gate size combination.
• Cin→Cout rising delay happens when (A,B,Cin): (010)→(011)
• Cin→Cout falling delay happens when (A,B,Cin): (011)→(010)
• FO4 Testbench is required. The BUFFER for each DUT input is two INV_1X
connected in series, the LOAD of each DUT output is a simple INV_4X.

7) Report the gate size combination with minimum average delay for path Cin→Cout. Also,
tabulate your rising, falling, and average delay for all gate size combinations.

Part B: 1-bit Full Adder Layout

You are asked to draw two layouts for optimizing two different paths.
1) Measure rising delay and falling delay for path Cin→S
• Choose the gate size combination you report and draw the layout.
• Extract the layout.
• Measure the rising/falling delays of Cin→S and calculate the average.
• FO4 Testbench is required. The BUFFER for each DUT input is two
INV_1X connected in series, the LOAD of each DUT output is a simple
INV_4X.
2) Measure rising delay and falling delay for path Cin→Cout
• Choose the gate size combination you report and draw the layout.
• Extract the layout.
• Measure the rising/falling delays of Cin→Cout and calculate the average.
• FO4 Testbench is required. The BUFFER for each DUT input is two
INV_1X connected in series, the LOAD of each DUT output is a simple
INV_4X.
 Part C: 4-bit Adder Schematic & Layout

In this part, you will design the schematic and layout for a 4-bit full adder using the
previously implemented 1-bit full-adders. The schematic of a 4-bit full-adder is given below.

• A3, A2, A1, A0, B3, B2, B1, B0 and C0 are input bits and S3, S2, S1, S0, COUT are output
bits. This adder adds two 4-bit unsigned numbers A and B, generates a 4-bit unsigned
number S. We define binary of A = A3A2A1A0, B = B3B2B1B0, S = S3S2S1S0
• For the least significant 3 bits (i.e., S0,S1,S2), use the FA_1b cell optimized for the
path CIN→COUT
• For the most significant bit, use the FA_1b cell optimized for the path CIN→S
• 4-bit full adder cell name: FA_4b

In the schematic of FA_4b, you need to perform functional test in the simulation using the
following binary numbers:
●​ Test case#1: A=1100, B=0011, C0=0
●​ Test case#2: A=1111, B=1001, C0=1
●​ Test case#3: A=0001, B=0101, C0=1
●​ Test case#4: A=0101, B=1010, C0=1
●​ Test case#5: A=0111, B=1110, C0=0
You need to show the waveform of all inputs and outputs for these test cases and convert
the analog waveforms to unsigned decimals. In addition, find the A, B that give the worst
propagation delay from C0 to S3 and report that worst case falling/rising/average delays
(average delay is the average of falling and rising delay). Hint: for a certain pair of (A, B),
the change of C0 will propagate all the way to the end and will to be reflected on S3. For
delay measurement, the FO4 testbench is required. The BUFFER for each DUT input is
two INV_1X connected in series, the LOAD of each DUT output is a simple INV_4X.
●​ Example: To measure the rising/falling delay from C0 to S3, select the time point tA
when the voltage equals 0.5v during C0 transit from 0/1 to 1/0, and select the time
point tB when the voltage equals 0.5v during S3 transit from 0/1 to 1/0. The delay is
calculated as tB - tA.
 Checklist for Submission

Part A
1. The schematic of FA_1b; the testbench.
2. The symbol of FA_1b
3. Waveform of all possible input patterns and their corresponding output.
4. The schematic of FA_1b optimized for Cin->S; the testbench; rising/falling/average; delay
for optimum gate size combinations; the optimal gate size you chose; the minimum Cin->S
propagation delay shown on the waveform.
5. The schematic of FA_1b optimized for Cin->Cout; the testbench; rising/falling/average
delay for optimum gate size combinations; the optimal gate size you chose; the minimum
Cin->Cout propagation delay shown on the waveform.

Part B
1. The layout of FA_1b optimized for Cin->S; DRC/LVS; the rising/falling/average delay of
Cin->S
2. The layout of FA_1b optimized for Cin->Cout; DRC/LVS; the rising/falling/average delay of
Cin->Cout

Part C
1. The schematic of FA_4b
2. The simulation results of all test cases (Show both waveforms and decimal numbers)
3. One possible input transition that leads to the worst-case C0->S3 propagation delay
4. The worst-case C0->S3 falling/rising/average delay
5. The layout of FA_4b; DRC/LVS
6. The extracted FA_4b and the worst-case C0->S3 falling/rising/average delay