STA TOPICS
1. How many stages you will get db?
A. We will get db from 3 stages. They are
• Placement db
• CTS db
• Routing db
2. What are the inputs for STA?
A. The inputs for STA are
1. Netlist (.v) = It contains the logical connectivity of the all
standard cells and macros.
2. Library (.lib) = It contains all the timing information of all the
standard cells like cell delay, cell transition, setup time, hold time
and also contains the electrical characteristics of cells.
3. SDC-Synopsys Design Constraints (.sdc / .tcl) = Sdc contains all
the constraint informations that is clock definitions, input and
output delay, exceptions like multicycle path, false path, half
cycle path, disable timing arc, case analysis, clock groups, targets
like uncertainty, latency, skew, etc.
4. SPEF-Standard Parasitic Extraction Format (.spef) = It contains
the parasitic information of all the nets in a design.
5. UPF-Unified Power Format (.upf) = It contains the power related
information. In case of multi voltages we need upf file.
6. MMMC-Multi Mode Multi Corner (.mmmc) = It contains the list
of all corners.
7. DEF-Design Exchange Format (.def) = The physical location and
coordinates of each cell in our design.
3. What are the STA outputs?
A. The outputs for STA are
1. DRVs - Design Rule Violations
In DRVs, we have max transition, max capacitance, max fanout.
2. SI – Signal Integrity
In SI, we have Crosstalk, Noise, Min Period and Minimum Pulse
Width
3. Timing - Setup & Hold
4. Sanity Checks?
A. Netlist: Check if there are any errors while reading the Verilog file, we need
to check in the log file.
“read_verilog” command is used to read netlist.
Linking Issues: When the inputs in the netlist doesn’t match with the library file
then we will get linking issues. LNK_005 & LNK_006 are the synopsys prime
time codes present in the log file if there is a linking issue. If linking issues are
present then as a STA engineer check from your side like the given path is correct
or not and if it’s not from your side then inform to pnr team.
SDC: While reading sdc, if we have any constraint issues then check in the log
file. “read_sdc” command is used to read SDC inputs.
Check_timing >check_timing.rpt
check_timing: Shows possible timing problems for design.
grep "Information: Checking" checktiming.rpt
Information: Checking 'no_input_delay'.
Information: Checking 'no_driving_cell'.
Information: Checking 'unconstrained_endpoints'.
Information: Checking 'unexpandable_clocks'.
Information: Checking 'latch_fanout'.
Information: Checking 'no_clock'.
Information: Checking 'partial_input_delay'.
Information: Checking 'generic'.
Information: Checking 'loops'.
Information: Checking 'generated_clocks'.
Information: Checking 'pulse_clock_non_pulse_clock_merge'.
Information: Checking 'pll_configuration'.
Check_timing -verbose: This command will give the complete timing report
SPEF: “read_parasitics” command is used to read spef input.
• All the cells we have should be metal connected.
• Those metal information should be in the spef file.
• While reading the spef file, open nets should not be there.
• The open nets which are not connected are called Not Annotated numbers.
Command: report_annotated_parasitics
If we get some number of not annotated numbers in the report then you have to
take the nets names by giving the command
report_annotated_parasitics -list_not_annotated -internal_nets -pin_to_pin_nets -
max_nets 50
After giving this command what and all nets are there it will display and
dump those into one file and give this feedback file to pnr team so that they
will debug.
5.What is the difference between Error, Warning and Violation?
A. Error: It is not able to perform the function properly. It will stop the run.
Violation: If you are not able to meet the target. It will not stop the run.
Warning: It won’t stop the execution, but it alerts a condition that might cause a
problem in the future.
6. What are the Annotated numbers?
• All the cells we have should be metal connected.
• Those metal information should be in the spef file.
• While reading the spef file, open nets should not be there.
• The open nets which are not connected are called Not Annotated numbers.
Command: report_annotated_parasitics
7.How to launch the pt?
A. PT means prime time tool used for the timing in Synopsys.
pt_shell | tee file.log = command to launch the pt
8.How to read inputs?
A. To read the inputs in prime time:
For Netlist (.v) → read_verilog .v/.v.gz (given by PNR)
For SDC (.sdc) → read_sdc/source file .sdc/.tcl (given by SYNTHESIS)
For SPEF (.spef) → read_parasitics .SPEF/.SPEF.gz (given by PNR)
For DEF (.def) → read_def .def (given by PNR)
For Library (.lib) → read_db .db (given by FOUNDRY)
For MMMC → source mmmc.tcl (given by TOP LEVEL)
For UPF (.upf) (given by TOP LEVEL)
9.What is Corner?
• The set of libraries characterised for process, voltage and temperature
variations.
• Corners are not dependent on functional settings, they are meant to capture
variations in manufacturing process, along with expected variations in the
voltage and temperature of the environment in which the chip will operate.
STA Corners
1. Parasitic Corners: RC interconnect corners and operating conditions
used for parasitic extraction. Those are worstRC, worstC, bestC,
bestRC and typical.
2. PVT Corners: The PVT Corners dictate at what conditions and STA
analysis takes place. The most common PVT corners are:
• WCS (slow process, low power supply, high temperature)
• BCF (fast process, high power supply, low temperature)
• Typical (typical process, nominal power supply, nominal
temperature)
• WCL (worst case slow at cold: slow process, low power supply,
low temperature)
• Or any other point in the PVT condition
10. What is mode?
A. Mode: It is defined as the set of clocks, supply voltages, timing constraints
& libraries. It is defined by the DFT team.
1. Func mode
2. Test mode
3. JTAG
Func Mode: It checks the functionality of the design.
• It focuses on path timing analysis.
• Its objective is to meet the frequency requirements. So func mode run
at higher frequency.
• Prone for setup violations and it is timing critical.
Test mode: In test mode we have scan shift mode and scan capture mode.
• It checks for manufacturing defects through the connectivity of flops.
• No need to focus on timing.
• Hence it runs at lower frequency.
• It is prone for hold violations because data path is bypassed.
• Scan Shift mode tells how the cell is switching.
• Scan Capture mode tells how the output is capturing.
JTAG: Joint Test Action Group
• The JTAG/boundary-scan test architecture was originally developed
as a method to test interconnects between ICs mounted on a PCB
without using physical test probes.
• It is used to solve the manufacturing issues that occurred within
electronic boards or printed circuit boards.
11. What is MMMC?
A. MMMC is Multi Mode Multi Corner
• It is in .tcl extension
• By creating PVT conditions we create corners.
• It gives the analysis of the design over varied modes & corners.
• MMMC file during the physical design gives the analysis of the
design over varied modes and corners.
• VLSI design can be modeled in either functional or test mode etc.,
with each mode at varied process corners.
• We need to ensure that the design is stable across all corners, to be
specific in technical terms PVT Corners (Process, Voltage &
Temperature)
• During the process flow of physical design, MMMC file takes all
relevant details for obtaining the desired design.
12. What are the PVT conditions?
• By using the PVT conditions, we create corners.
• Process: Either Slow Slow or Fast Fast
• Voltage: Based on the requirement of the chip
• Temperature: -40C to +125C.
• Example: 1. P = SS, V = 0.7, T = 40C
• P = FF, V = 0.7, T = 125C
o Given by SS_0P7V_M40C
• FF_0P7V_125C
• Scenario: Func_sgnp_0p765_125c_rcworst_ccworst_T
13. What is Pre-layout & Post-layout STA?
A. Layout = Physical Design (PD) or Place and Route (PNR)
Synthesis = Pre-layout (In this we check DRVs & Setup)
PD = Layout
In Placement, we check DRVs & Setup
In CTS, we check DRVs, Setup & Hold
In Routing, we check DRVs, SI, Setup & Hold
STA = Post-layout (In this we check DRVs, SI, Setup & Hold)
14. What is cell delay and net delay?
A. Cell delay: Transistors within a gate take a finite time to switch. This means
that a change on the input of a gate takes a finite time to cause a change on the
output.
Cell delay =function of (input transition (slew) time, Cnet+Cpin)
(or)
Cell delay =function of (input transition (slew) time, Cload)
where Cload=Cnet+Cpin
Cnet-->Net capacitance
Cpin-->pin capacitance of the driven cell
Cell delay is also same as Gate delay.
Net delay:
Net delay is the difference between the time a signal is first applied to the
net and the time it reaches other devices connected to that net.
It is due to the finite resistance and capacitance of the net. It is also known
as wire delay.
Wire delay = function of (Rnet, Cnet+Cpin)
This is output pin of the cell to the input pin of the next cell.
Net delay is calculated using Rs and Cs.
There are several factors which affect net parasitic:
• Net Length
• Net cross-sectional area
• Resistively of material used for metal layers (Aluminum vs.
copper)
• Number of vias traversed by the net
• Proximity to other nets (crosstalk)
15. Clock tree structure and how to build the clock tree?
A. Clock Tree:
Clock Tree Synthesis is a technique for distributing the clock equally
among all sequential parts of a VLSI design.
Purpose: To reduce skew and delay.
• It is a collection of buffer and inverter from source to sinks.
• Equal delay of clock from source to all sinks.
• Zero clock skew and balanced fanout.
A clock tree can have different structures such as:
1. Fish bone
2. H-tree
3. X-tree
4. Multi-level clock tree
5. Once the Clock Tree Synthesis is complete, we must double-
check the timing.
Optimizations to the clock tree are: Buffer sizing, gate sizing, HFN
synthesis and buffer relocation are used to achieve this.
The cells used to build the clock tree are
a. Clock Inverter – it has less power when compared to buffer
b. Clock Buffer – it has more power consumption
c. Mux – to propagate the clock
d. ICG (Integrated Circuit Gate) – AND gates are used more and it is used to
reduce the dynamic power dissipation.
16. What is Skew?
A. Skew: Difference between the arrival time of two sequential elements in a
design.
Skew = T2 – T1
There are 5 types of skew. They are
1. Positive Skew: When the capture flop delay is greater than the launch flop
delay, it is positive skew. If skew is positive then it will help setup.
2. Negative Skew: When the capture flop delay is lesser than the launch flop
delay, it is negative skew. If skew is negative then it will help hold.
3. Local Skew: It is also called short path. The timing path between the two
flipflops within the module is called local skew.
4. Global skew: It is also called long path. The skew between unrelated
registers or flops is called global skew.
5. Useful Skew: Intentionally adding of skew to resolve the timing violations
is called useful skew. It will be build only at the CTS stage.
17. What is Uncertainty & Latency?
A. Uncertainty: Variations of a clock period is called Uncertainty.
• Parameters of Uncertainty are Jitter, Margin and Skew.
• Jitter is the deviation of a clock edge from its ideal position.
• The margin for uncertainty is 10 – 20 % of clock period.
• The margin of uncertainty for setup is 7.5 and for hold is 2.5.
• For pre-layout design:
Clock uncertainty = skew + jitter
• For post-layout designs:
Clock uncertainty = jitter
• Before CTS there is no way of knowing what is the delay in the clock tree.
So an appropriate value has to be used while performing the “pre-layout
STA”
• After CTS is performed (propagated clock mode), the delay values will be
propagated along the clock path and hence skew will be eliminated.
Command: pt_shell> report_clock_timing -type skew -
include_uncertainty_in_skew
Latency: Latency is also called the Insertion Delay.
• Latency is defined as the time delay between clock source to input clock
pins of flops or it can also be defined as the time needed for an input change
to produce an output change.
• Latency margin is 10 – 15 % of clock period.
• Latency is of two types. They are Source Latency and Network Latency.
Source Latency: The delay from the clock root pin to clock definition point
is called source latency.
Network Latency: The delay from the clock definition point to the sink of
capture flop is called network latency.
• Here only clock inverters and clock buffers are used as cells.
Command: pt_shell> report_clock_timing -type latency
18. What is CRPR?
A. Clock Reconvergence Pessimism Removal (CRPR) is defined as the delay
difference along the common paths of the launching and capturing clock paths. It
is used to reduce pessimism. In clock path or required path you will see CRPR.
pt_shell> report_crpr -from <LD1/CP > -to < LD2/CP>
Example timing report showing CRPR
19. What is Useful skew?
A. The skew which is purposely added in the design to meet the timing, especially
in the clock paths where timing is failing so that timing is passed in that path. But
useful skew cannot be added blindly. This needs to be done carefully by making
sure the margin is available in previous path and the next timing path.
Uncontrolled addition of skew can lead to more timing violations instead of fixing
them. It can be used to fix both setup and hold violations.
Clock Pulling: Removing of buffers from clock path
Clock Pushing: Adding of buffers in clock path
The push and pull is the adding the skew and removing the skew. Let’s
consider path having 2 flipflops and between combinational logic. For setup
fixing we used to push the clock at capture clock path and pull at the launch clock
path (adding the skew at capture clock path and remove the skew at launch clock
path) and vice versa for hold fixing.
20. What is LVT, HVT, SVT and ULVT?
A. VT: It is defined as the transition time to switch the voltage. Each standard
cell is designed in multiple flavors of threshold voltage (Vt).
LVT → Low Vt cells
• It is faster and it has the disadvantage of leakage power.
SVT → Standard Vt cells some times also referred as Nominal/Regular Vt cells
• It has medium speed and it has medium leakage power.
HVT → High Vt cells
• It is slower and it has less leakage power.
ULVT → Ultra Low Vt cells
• It is more faster and has more leakage power than LVT cells.
Important points:
• Vt of a cell is altered by altering the channel doping of a MOS transistor.
• As doping in the channel increases the gate threshold voltage increases
because the gate voltage needs to deplete more majority carriers before a
minority carrier channel can form.
• Increasing order of channel doping LVT→SVT→HVT
• Increasing order of output drive current of a cell (of the same cell size)
HVT→SVT→LVT
• Cell delay reduces in this order HVT→SVT→LVT
• Cell leakage increases in this order HVT→SVT→LVT
• We typically allow Synthesis/PnR tools to use multiple Vt flavored cells.
• Wherever tools need to reduce cell/net delays to meet setup timing in a
timing path, it can use lower Vt cells. Otherwise they would use higher Vt
cells to save leakage.
21. What is difference between normal inverter, buffer and clock inverter,
buffer?
A. The difference between normal buffer, normal inverter and clock buffer,
clock inverter:
• Normal inverter and normal buffer doesn’t have exact 50 – 50% rise
and fall time.
• Clock inverter and clock buffer does have the exact 50 – 50%
rise and fall time for 100% sure.
• Clock inverter & clock buffer are faster while normal inverter and
normal buffer are slower.
22. What is WNS, TNS & FEP?
A. WNS: WNS is worst negative slack of timing path.
TNS: TNS is the total negative slack, which is the sum of all WNS in design.
FEP: Number of failing endpoints gives the total number of violated paths in that
particular timing path.
23. What is DRVs?
A. DRVs – Design Rule Violation
DRVs are defined as the calculation between two standard cells.
1. Max Transition
2. Max Capacitance
3. Max Fanout
1. Maximum Transition: The longest time required for its driving pin to
change the logic values.
Reasons: It occurs due to the long net length and less drive strength.
Fixes:
a. Upsizing the cell
b. Swapping the cell
c. Adding thee buffers
d. Re-route the net
Command: report_constraints -max_transition = for the complete design
2. Maximum Capacitance: The total capacitive load that an output pin can
drive.
Fixes: Upsizing the cell
Command: report_constraints -max_capacitance
3. Maximum Fanout: It refers to the cells, how many cells it can drive. Like
the output of the cell connected to how many inputs of the cells.
Fixes: Adding Buffer
Command: report_constraints -max_fanout
For a particular timing path, to get the max transition, max capacitance and
max fanout give the command with these switches like
report_timing -transition_time -capacitance -nets
24. What is OCV, AOCV & POCV?
A. On Chip Variation:
In OCV a fixed timing derate factor is applied to the delay of all the cells
present in the design so that in case of process variation affects the delay of any
cells during the fabrication, it will not affect the timing requirements and the chip
will not fail after fabrication.
• STA tool would consider early or late timing derate based on the path
and type of analysis.
• The derate factor for setup and hold will be given by the margin 5% to
10%.
Example:
set_timing_derate – setup – late 1.05 –cell_delay – net_delay
set_timing_derate – hold – early 0.95 –cell_delay – net_delay
From before and after figures, show the derate factor considered by the STA
tool while setup and hold analysis for different paths.
• In reg2reg path timing analysis there is a launch flop from where
data is launched and a capture flop where data is captured.
• The path between the clock source to the clock pin of the launch flop
is called the launch clock path and the path from the clock source to
the clock pin of the capture flop is called the capture clock path.
• In setup analysis worse case could be a late data path, late launch
clock path and early capture clock path which could fail the setup
timing.
• So STA tool will consider late timing derate for data path and launch
clock path and early derate for the capture clock path.
• For hold analysis, a fast data path, early launch clock and late capture
clock could be the worst scenario.
• So STA tool will consider always the worst scenario and take the
early derate factor for the data path and launch clock path and the
late derate factor for capture clock path.
• On Chip Variation: cell_delay ( > 28nm )
• Advanced On Chip Variation: cell_delay + net_delay ( >= 10nm )
• Parametric On Chip Variation: cell_delay + net_delay +
cell_switching ( <= 10nm )
• Cell Delay: The amount of delay from input to output of a logic
gate. All the values of cell delays can be taken from .lib file.
• Net Delay: The amount of delay from the output of a cell to the input
of the next cell in a timing path.
• Cell Switching: It is defined as how it is switching from input to
output.
Advanced On Chip Variation:
• The concept of Advance On Chip Variation (AOCV) has evolved
which does not use the fixed derate.
• In AOCV derate is applied on each cell based on path depth and path
distance of the cell in the timing path and it also varies with cell type
and drive strength of the cell.
• Path Distance: If the distance increases, systematic variation would
increase and to mitigate the variation, we need to use higher derate
value. So along with the distance, derate value increases.
• Path Depth: In the case of distance is fixed and path depth
increases, systematic variation would be constant but the random
variation would tend to cancel each other. Therefore as path depth
increases the derate factor would decrease.
ISSUES IN AOCV:
• AOCV does not perform very well below 40nm technology node and
to improve that we need to improve the timing pessimism further.
• Distance and Depth based derate factor used in the AOCV is good
for technology nodes above 40nm but for the below node we need to
improve it further.
• To address these issues Parametric On Chip Variation (POCV) has
been developed.
Parametric On Chip Variation:
• POCV is very effective in technology nodes 20nm and below.
• POCV is a more realistic approach than that of OCV and AOCV.
• This method does not use distance and depth based derate factors.
• It uses delay sigma to model the delay variation of the cell.
• An advantage of POCV over AOCV is also that it reduces the slack
pessimism between Graph-Based Analysis (GBA) and Path Based
Analysis (PBA).
• In POCV instead of applying the specific derate factor to a cell, cell
delay is calculated based on delay variation (σ) of the cell.
Cell delay calculation using POCV:
1. Using single POCV coefficient (C):
An external file containing the delay coefficient value C for each
library cell, hierarchical cell or design. There is only one value of C
for each timing arc of the cell irrespective of the input transition or
output load. The delay variation σ is calculated based on C as
follows.
The Delay variation (σ) = C * Nominal delay (µ)
An example of POCV coefficient file:
version: 4.0
ocvm_type: pocvm
object_type: lib_cell
rf_type: rise fall
delay_type: cell
derate_type: early
object_spec: */INV*
coefficient: 0.0693
2. Using Library Variation Format (LVF):
The information of POCV variation is directly provided into the
library itself in LVF format. In LVF format there are two indexes
used one for input transition and other for output load. An example
of the POCV LVF format has shown below.
ocv_sigma_cell_rise (“pocv_template_4x4”) {
sigma_type : “late”;
index_1(“0.01, 0.04, 0.12, 0.80”);
index_2(“0.01, 0.02, 0.03, 0.10”);
values( “σ11, σ12, σ13, σ14”,
“σ21, σ22, σ23, σ24”,
“σ31, σ32, σ33, σ34”,
“σ41, σ42, σ43, σ44”, );
}
Typically index-1 denotes the input transition and index-2 denotes
the output load.
If both data types are present in the design then by default the file
with single POCV coefficient has higher precedence than POCV
slew-load table or LVF format file.
POCV delay calculation:
Delay of a cell = Nominal delay (µ) ± (C * Nominal delay) * N
Where C = POCV coefficient and
N = Number of standard deviation
OR
Delay of cell = Nominal delay (µ) ± Variation
COMMANDS
• To enable AOCV
set timing_aocvm_enable_analysis true
• Report AOCV
report_ocvm –type aocvm
• To enable POCV
set timing_pocvm_enable_analysis true
• Report POCV
report_ocvm –type pocvm
25. What is derate factor?
A. To take care of OCV we need to add some pessimism in the timing of
standard cells. We basically apply ±x% of additional delay to all the standard
cells. Which is called OCV derate.
OCV derate factor: Derate factor is a very simple approach to take of on
chip variation. For OCV a fixed derate factor is applied on throughout the design.
So that in case of any variation occurs will not cause the failure of the chip. But
it added too much of timing pessimism which leads to difficulties in the timing
closure, especially in the lower nodes. So, the industry has moved to different
concepts from the fixed derate to distance and depth based derate which is called
Advance On Chip Variation (AOCV). As the technology node further shrank
more, AOCV also is not a good option and further Parametric On Chip Variation
(POCV) evolved. In short, we can say that as we moved from OCV to POCV
timing pessimism reduced.
26. What is DMSA?
A. Distributed Multi-Scenario Analysis (DMSA)
It allows multiple scenarios to run at once which reduces clock time and produces
a single timing report. To invoke prime time in DMSA, use multi_scenario option.
pt_shell ‘-multi_scenario’
Used for
• Run multiple corners at the same time
• Tool take minimum 3 to 4 hours of runtime for a single PVT Corner
run, so it’s hard to check the design for all corners within a specific
time.
• Hence, enabling DSMA makes tool to check the design at all
corners parallelly in a mean time.
• Used to fix ECO rolling (or) ECO run (or) ECO fire
• If 100 paths are violating, it takes huge time to manually fix each
and every path.
• With the help of DMSA, all the 100 violating path endpoints are
grepped and save into a file. As is inserted in script of ECO rolling.
• ECO rolling is done at all corners using DMSA.
27. What is PBA & GBA?
A. GBA (Graph Based Analysis):
• In Graph Based Analysis, the worst slew propagation is ON, and the timing
engine computes the worst case delays of all standard cells assuming the
worst case slew for all the inputs of a gate.
• For example, assuming we need to compute the gate delays while doing
setup analysis in a graph-based methodology for the path from FF1 to FF2:
The delay of the A-> Z (output) arc of the OR gate (in brown) would be
computed assuming the real slew, i.e., slew at pin A.
• However, the slew that will be propagated to the output pin of the OR gate
would be the worst slew, which in this case would be computed taking into
account the load at the output of the OR gate and slew at B.
• Similarly, the delay of NAND gate (in blue) would be computed using the
propagated slew coming from the previous stage i.e., the slew at pin B, but
the slew that is propagated to the output would be according to the worst
input slew, in this case slew at A. And so on and so forth.
• While performing hold analysis in a graph-based methodology, the
situation reverses, the delays of all cells would be computed assuming the
best propagated slews (fast slews) for all nodes along the timing path!
• This method of timing analysis is faster and uses lower memory footprint
because the engine has to simple keep a tab of worst propagated slews for
every pin in the design.
• This surely is pessimistic but again faster and therefore does not encumber
the optimization tool by bounding the problem.
• For example, for the OR gate, the slew propagated to its output is the worst
slew, therefore the delays of subsequent gates after the OR gate could be
pessimistic.
PBA (Path Based Analysis):
In Path-based analysis, the tools takes into account the actual slew for the
arcs encountered while traversing any particular timing path. For example
for the path shown above from FF1 to FF2, the arcs encountered are- A->
Z for OR gate; B-> Z for NAND gate; B-> Z for XOR gate and A-> Z for
the inverted AND gate.
To choose the path-based analysis mode, specify the -pba_mode option with one
of the following arguments:
• path – Does not perform a path search to determine whether those paths are truly
the worst recalculated paths. This method is useful for quickly gaining an idea of
how much improvement is provided by path-based analysis without the runtime
of a full path search. The slack results either match those from a full path search
or are slightly optimistic.
• exhaustive – Performs an exhaustive recalculated path search, recalculating as
many paths as necessary to ensure that the paths returned are the worst
recalculated paths that meet the specified options.
Relation b/w PBA and GBA
To enable PBA & GBA and their reporting commands
set pba_derate -only_mode = True – PBA
report_timing -pba_mode path (report for PBA)
report_timing -pba_mode exhaustive (report for PBA)
set pba_derate -only_mode = False – GBA
report_timing -pba_mode none (report for GBA)
28. What is SI?
A. Signal Integrity is the ability of an electrical signal to carry information
reliably and resist the effects of high frequency electromagnetic interference from
nearby signals. When two signals are interacting with each other then variations
will occur. The effects of Signal Integrity are
• Crosstalk
• Noise
• Minimum Period
• Minimum Pulse Width
29. What is Crosstalk & Noise?
A. Crosstalk: Unintentional coupling between two signals is called as Crosstalk.
When there is no proper distance between the aggressive net and the victim net
then due to the coupling capacitance these two nets get hit then the cells in the
victim net gets slow. So the propagation doesn’t take place.
• Violation appears due to the slowing of the victim net.
• The crosstalk occurs because the victim net gets slower.
Command: report_timing -crosstalk_delta
Crosstalk fixes:
• Upsizing the victim net
• Downsizing the aggressor net
• Add the buffer
• Shielding
• Re-routing
• Proper NDR rule
Types of Crosstalk
1. Crosstalk Delta Delay: Victim & aggressor both are switching.
Negative Crosstalk: If the aggressive net and victim net travels/switches
in the same direction of the logic, it is called Negative Crosstalk.
• When the both nets are switching in the same direction due to
crosstalk, the delay reduces in the victim net which results in hold
violations in data path and setup violations in clock path.
• In this negative crosstalk, delay will be reduced and more speed
will be there.
Positive Crosstalk: If the aggressive net and victim net travels/switches
in the opposite direction of the logic, it is called Positive Crosstalk.
• When the both nets are switching in the opposite direction due to
crosstalk, the delay increases in the victim net which results in
setup violations in data path and hold violations in clock path.
• In this positive crosstalk, delay will be increased and less speed
will be there.
2. Crosstalk Glitch: Victim is steady & aggressor is switching.
Crosstalk Noise/glitch: The Crosstalk noise refers to unintentional coupling of
activity between two or more signals, which can either effect the functionality or
the timing of the devices. During the transition on the aggressor net causes a bump
or glitch (under shoot or over shoot) on the victim, net this phenomenon is called
crosstalk noise.
Types of glitches:
a. Rise Glitch
b. Fall Glitch
c. Overshoot Glitch
d. Undershoot Glitch
a. Rise Glitch: It happens when the aggressor net switching from 0 to 1 and
victim net will be in steady state low or 0. This aggressor net trying to pull
the victim net from low to high.
b. Fall Glitch: It happens when the aggressor net switching from 1 to 0 and
victim net will be in steady state high or 1. This aggressor net trying to pull
the victim net from high to low.
c. Overshoot Glitch: When aggressor switching from low to high, victim net
already high in that case victim net pulled even higher is called overshoot
glitch.
d. Undershoot Glitch: When aggressor switching from high to low, victim net
already low in that case victim net pulled even low is called undershoot
glitch.
Noise fixes:
• Add buffer to the victim net
Command: report_noise
30. What is Shielding?
A. Shielding is an effective and very common technique to reduce crosstalk noise
as well as delay uncertainty at the cost of the increased routing area. In the lower
technology nodes, due to capacitive and inductive coupling effects, inserting a
shield line is necessary to keep the signal integrity efficiently.
• The shielding will be done for the victim net only which is the effected
net.
• The shielding net is connected to strong Vdd and Vss.
• By shielding a net two things will happen, one is the direct coupling
capacitance between the aggressor and victim net will vanish and
secondly the shielding net will remain at a constant logic. So, there are
no chances of crosstalk.
Disadvantages of Shielding: It requires more area in a design and adding more
parasitic capacitance.
