EE 6309: Topic #5

Design for Testability (DFT)

Prof. Tony T. Kim

Nanyang Technological University
School of Electrical and Electronic Engineering

http://sites.google.com/view/tonykim
[email protected]
 Design for Testability (DFT)
• Basics
• Design-for-Testability (DFT) Techniques
– Ad Hoc DFT
– Structural Methods
• Scan, Partial Scan, BIST, Boundary Scan, Syndrome-Testable
Design, and C-Testable Design
• Built-In Self-Test (BIST) Techniques
– Signature Analysis
– Pseudorandom Pattern Generator (PRPG)
– Built-In Logic Block Observer (BILBO)
• Summary

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 Design for Testability (DFT)
• A fault is testable if there exists a well-specified procedure
to expose it, which is implementable with a reasonable cost
using current technologies. A circuit is testable with respect
to a fault set when each and every fault in this set is
testable.
• Design for testability (DFT) refers to those design
techniques that make test generation and test application
cost-effective .
• Electronic systems contain three types of components: (a)
digital logic, (b) memory blocks, and (c) analog or mixed-
signal circuits.
• In this chapter, we discuss DFT techniques for digital logic

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 Important Factors of Testability
• Controllability: Measure the ease of controlling a
line.
• Observability: Measure the ease of observing a line
at a PO
• In general, DFT deals with ways for improving
controllability and observability

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 Cost Associated with DFT
• Pins
• Area/Yield
• Performance
• Design Time

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 Ad Hoc DFT Guidelines
• Partition large circuits into smaller subcircuits to
reduce test generation cost (using MUXed and/or
scan chains)

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 Ad Hoc DFT Guidelines
• Insert test points to enhance controllability &
observability
– Test points: control points & observation points

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 Ad Hoc DFT Guidelines
• Design circuits to be easily initializable
• Provide logic to break global feedback paths
• Partition large counter into smaller ones
• Avoid the use of redundant logic
• Keep analog and digital circuits physically apart
• Avoid the use of asynchronous logic
• Consider tester requirements (pin limitation, etc)
• Etc

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 Problems in Ad Hoc DFT
• Large number of I/O pins
– Add MUX’s to reduce number of I/O pins
– Serially shifts control point values
• Long testing time

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 Scan Design Approaches
• They are effective for circuit partitioning
• They provide controllability and observability of
internal state variables for testing
• They turn the sequential test problem into a
combinational one
• Four major approaches
– Shift-register modification
– Scan path
– Level-sensitive scan design (LSSD)
– Random access
• Circuit is designed using pre-specified design rules.

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 Scan Design Approaches
• Consider a representation of sequential circuits

• To make elements of state vector controllable and

observable, we add
– A TEST mode pin (T)
– A SCAN-IN pin (SI)
– A SCAN-OUT pin (SO)
– A MUX (switch) in front of each FF (M)
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Adding Scan Structure

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Scan Test Generation & Design Rules
• Test pattern generation
– Use combinational ATPG to obtain tests for all testable
faults in the combinational logic
– Add shift register tests and convert ATPG tests into scan
sequences for use in manufacturing test
• Scan design rules
– Use only clocked D-type of flip-flops for all state
variables
– At least one PI pin must be available for test; more pins,
if available, can be used
– All clocks must be controlled from PIs
– Clocks must not feed data inputs of flip-flops

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 Correcting a Rule Violation
• All clocks must be controlled from PIs

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 Correcting a Rule Violation
• Adding a scan FF and a mux allows a feedback loop
to be opened for testing

• Testing derived clocks requires the use of a mux to

bypass the division stages

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 Correcting a Rule Violation
• The AND gates keep the bus drivers from being
activated by the normal logic during testing

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 Scan Test Procedure
• Step 1: Switch to the shift-register mode and check
the SR operation by shifting in an alternating
sequence of 1s and 0s, e.g., 00110 (functional test)
• Step 2: Initialize the SR---load the first pattern
• Step 3: Return to the normal mode and apply the
test pattern
• Step 4: Switch to the SR mode and shift out the
final state while setting the starting state for the
next test. Go to Step 3

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Combining Test Vectors

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Combining Test Vectors

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 Testing Scan Register
• Scan register must be tested prior to application of
scan test sequences
• A shift sequence 00110011 . . . of length nsff+4 in
scan mode (TC=0) produces 00, 01, 11 and 10
transitions in all flip-flops and observes the result
at SCAN-OUT output
• Example: 2,000 scan flip-flops, 500 comb. vectors,
total scan test length ~ 106 clocks
• Multiple scan registers reduce test length

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 Multiple Scan Registers
• Scan flip-flops can be distributed among any
number of shift registers, each having a separate
SCAN-IN and SCAN-OUT pin
• Test sequence length is determined by the longest
scan shift register
• Just one test control (TC) pin is essential

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 Hierarchical Scan
• Scan flip-flops are chained within subnetworks
before chaining subnetworks
• Advantages:
– Automatic scan insertion in netlist
– Circuit hierarchy preserved – helps in debugging and
design changes
• Disadvantage: Non-optimum chip layout

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Optimum Scan Layout

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Automated Scan Design

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An Example of DFT Compiler Flow

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Shift Registers

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 Random Access Scan
• Uses addressable latches
• Provides random access to FFs via multiplexing—
address selection

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 Random Access Scan
• Random access scan cell

• Advantages
– Fast; minimal impact on normal path
– Fast for testing—random access
– Ability to ‘watch’ a node in normal operation mode
• Disadvantages
– Hardware cost is large; more pins added
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 Random Access Architecture

• During normal operation the storage cells operate

in their parallel-load mode
• To scan in a bit, the appropriate cell is addressed,
the data are applied to sin
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 Test Procedure
1. Set test input to all test points
2. Apply the master reset signal to initialize all
memory elements
3. Set scan-in address and data, and then apply the
scan clock
4. Repeat step 3 until all internal test inputs are
scanned in
5. Clock once for normal operation
6. Check states of the output points
7. Read the scan-out states of all memory elements
by applying appropriate X-Y signals

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 Scan-Hold FFs (SHFFs)
• HOLD=0→Q & Q’ are fixed

• The control input HOLD keeps the output steady at

previous state of flip-flop
• Applications
– Reduce power dissipation during scan, etc.

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 Scan Enters the Nanometer Era
• Trend in flip flop count with design size

• Adaptive scan architecture is required

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 Problems with Full Scan
• Area overhead
– Due to larger flip-flops
– Due to extra routing
• Possible performance degradation
– Extra gate delay due to the multiplexer
– Extra capacitive loading delay due to scan wiring at the
flip-flop output
• Long test application time
• Not applicable to all designs (e.g. asynchronous
designs, designs violating scan design rules)
• High power dissipation during testing

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 Issues for Multiple-Clock Design
• Clock skew might occur between different domains
• To minimize skew during scan shift, scan chains
should be ordered.
• All FFs in same clock domain are grouped together
– minimizing locations where clock skew can occur
• To completely avoid skew where the scan/clock
domains cross, a lockup latch can be inserted.

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 General Issues of Scan Design
• Scan chain ordering
– To prevent skew during shift
– To minimize routing overhead
– Use placement info to determine a good ordering
• Balancing scan chains
– To minimize total test time
– Total scan cycles = (Scan patterns +1)*(Length of longest
scan chains)
– # of scan chains is normally limited by the package (pins
available to borrow or dedicate for scan) as well as the
tester (channels available with memory depth that can
handle scan vectors).

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 Partial Scan
• Basic idea
– Select a subset of flip-flops for scan
– Lower overhead (area and speed)
– Relaxed design rules
• Cycle-breaking technique
– Cheng & Agrawal, IEEE Trans. on Computers, 1990
– Select scan flip-flops to simplify sequential ATPG
• Timing-driven partial scan
– Jou & Cheng, ICCAD, Nov. 1991
– Allow optimization of area, timing and testability
simultaneously

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 Practice: Scan Chain Reordering
1. The nodes on the grid shown in the following figure are flip-
flops that are to be switched to form a scan path. Show
how they can be connected for minimal interconnect length.

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 Practice: Scan Test
1. Convert the circuit by adding scan to the three flip-flops. Create a
complete scan test for the indicated faults (, , ). Show the sequence
of test vectors that are applied to this circuit in order to detect the
faults, and show the sequence required to scan out and observe the
results.

=Q0’•Q1•Q2’

=Q1•In

=Q0•Q1’•Q2’•In

=Q0’ •Q1’•Q2•In

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 Syndrome-Testable Design
• Definition
– The syndrome of a Boolean function is , where
k is the number of 1s (minterms) in f and n is the number
of independent input variables
– A typical syndrome testing set-up

– 0  S(f)  1
– A circuit is syndrome testable iff fault , S(f)  S(f)
– Syndromes of logic gates

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 Syndrome Computation
• Consider a circuit having 2 blocks, f and g, with
unshared inputs

• Example
– Calculate the syndrome of the following circuit

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 Syndrome-Testable Design
• Consider the function f = xz + yz’. The circuit is
syndrome untestable
– Sf = 1/2
– If the circuit has a fault   z/0, then the corresponding
syndrome of the faulty circuit is Sf’ = 1/2
– Thus the circuit is syndrome untestable
• A realization C of a function f is said to be
syndrome-testable if no single stuck-at fault causes
the circuit to have the same syndrome as the fault-
free circuit
• Syndrome is a property of function, not of
implementation
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 Syndrome-Testable Design
• Definition
– A logic function is unate in a variable xi if it can be
represented as an SOP or POS expression in which the
variable xi appears either only in an uncomplemented
form or only in a complemented form
• For example:

• Theorem
– A 2-level irredundant circuit realizing a unate function in
all its variables is syndrome testable

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 Syndrome-Testable Design
• Theorem
– Any 2-level irredundant circuit can be made syndrome-
testable by adding control inputs to the AND gates
• For example:

• Drawbacks
– Only for combinational logic
– Exhaustive; modification doubles test set size
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 Practice: Syndrome Calculation
1. Calculate the syndrome of the following circuit using the syndromes of
logic gates.

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 DFT: Summary
• Design-for-testability techniques
– Ad-hoc techniques
– Scan
– Random access scan
– Syndrome-testable
• Scan is a popular DFT technique in modern IC
design
• DFT can increase the controllability and
observability of the circuit under test

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 EE 6309: Topic #6
Built-in-Self-Test (BIST)

Prof. Tony T. Kim

Nanyang Technological University
School of Electrical and Electronic Engineering

http://sites.google.com/view/tonykim
[email protected]
 Introduction to Built-In Self-Test
• Built-in self-test (BIST):
– The capability of a circuit to test itself
• Advantages of BIST
– Test patterns generated on-chip → controllability
increased
– (Compressed) response evaluated on-chip →
observability increased
– Test can be on-line (concurrent) or off-line
– Test can run at circuit speed → more realistic; shorter test
time; easier delay testing
– External test equipment greatly simplified, or even totally
eliminated
– Easily adopting to engineering changes
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 Introduction to Built-In Self-Test
• On-line BIST
– Concurrent (EDAC, NMR, totally self-checking checkers,
etc.):
• Coding or modular redundancy techniques (fault tolerance)

• Instantaneous correction of errors caused by temporary or

permanent faults
– Nonconcurrent (diagnostic routines):
• Carried out while a system is in an idle state

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 Introduction to Built-In Self-Test
• Off-line BIST
– A typical BIST architecture

• Test generation
– Prestored TPG, e.g., ROM or shift register
– Exhaustive TPG, e.g., binary counter
– Pseudo-exhaustive TPG, e.g., constant-weight counter,
combined LFSR and SR
– Pseudo-random pattern generator, e.g., LFSR
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 Introduction to Built-In Self-Test
• Response analysis
– Check-sum
– Ones counting
– Transition counting
– Parity checking
– Syndrome analysis
– Etc.
• Linear feedback shift register (LFSR) can be both the
test generator and response analyzer
• We need a gold unit to generate the good signature
or a simulator

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 Signature Analysis
• A compression technique based on the concept of
cyclic redundancy checking (CRC) and realized in
hardware using linear feedback shift registers
• Definition
– A function f(x1,x2,…,xn) is said to be linear if it can be
expressed in the form
f = a0 + a1x1 + a2x2 + ... + anxn
where ai  {0, 1} i = 0, 1,...,n
• There are 2n+1 linear functions of n variables
• Linear operations: modulo addition, module scalar
multiplication, & delay
• Nonlinear operations: AND, OR, NAND, NOR, etc.

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 Linear Feedback Shift Register
• Definition
– A linear feedback shift register is a shift register with
feedback paths which consist only of unit delays and XOR
operators
• Let M=fault-free circuit response, B=faulty circuit
response, and E=error syndrome (Hamming), where
E=M + B→thus M=B + E and B=M + E
– We need a circuit to take B as input and compact it but
still be able to tell if M!=B
• LFSR is considered as a popular approach for test
response compaction

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 Structures of LFSR
• Two types of generic standard LFSRs
External Feedback

Internal Feedback

Higher clock frequency

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 LFSR for Signature Analysis
• A serial input stream mn, mn-1,…, m1, m0 entering
the LFSR can be considered as the coefficients of a
polynomial

• The LFSR is said to have a characteristic polynomial

defined as follows

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 LFSR for Signature Analysis
• Assume that the initial state of the LFSR is Di=0,
i=0,…,r-1, then the LFSR effectively divides any m(X)
by c(X), i.e.,

• The quotient q(X) appears serially at the output of

the SR. The remainder s(X) is in the SR after n+1
shifts:

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 LFSR Example
• The following LFSR divides any m(X) by
c(X)=X5+X4+X2+1

• Suppose m(x)=X7+X6+X5+X4+X2+1, then q(X)=X2+1,

and s(X)=X4+X2

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 Signature Analysis
• Let m(X) be the input polynomial of degree k-1, q(X)
the quotient, and s(X) the signature (remainder).
• Then
– m(X)=q(X)c(X)+s(X)
• The error syndrome can be represented as a
polynomial e(X)
– E.g., let m(X)=X4+X3+1(11001), and an erroneous input
b(X)=X3+X+1(01011), then the error syndrome is 11001
01011=10010, and is represented by e(X)=X4+X
• In general, an erroneous input polynomial can be
represented by
– B(X)=m(X)e(X)

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 Signature Analysis
• Theorem1: Input streams m(X) and b(X) have the same
signature if e(X) is a multiple of c(X)
– Proof: an error is not detected when m(X) and b(X) have the same
signature, i.e., b(x)=q’(X)c(X)+s(X). Since m(X)=q(X)c(X)+s(X), we
obtain
e(X)=m(X)+b(X)=c(X)(q’(X)-q(X))

• Theorem2: Undetected errors correspond to error patterns

which are multiples of c(X)

• Theorem3: If c(X) has 2 or more nonzero coefficients—i.e., at

least 1 feedback term—then it can detect all single-bit errors
– Proof: all nonzero multiples of c(X) must have at least 2 nonzero
coefficients. Therefore, any error with only 1 nonzero coefficient
cannot be a multiple of c(X) and must be detectable.
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 Aliasing Probability
• Theorem4: for a k-bit response sequence, if all possible error
patterns are equally likely, then the probability of failing to
detect an error (i.e., the aliasing probability) by the LFSR of
length r is

• Proof: For a k-bit response, deg(m(X))=k-1, and deg(e(X))<=k-

1. Therefore, the number of possible error polynomial is
represented by e(X)=c(X)p(X) for some nonzero p(X). Since
deg(c(X))=r, the number of possible p(X)’s is 2k-r-1. Thus

• For a long sequence, k>>r→Pal~1/2r

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 Response Compaction
• Usually, we think of data compression as a process
that preserves data integrity. This is why we give
more attention here to data compaction, which may
result in some losses
• There are several compaction testing techniques
– Parity testing
– One counting
– Transition counting
– Syndrome calculation
– Signature analysis

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 Parity Testing
• This is the simplest of all techniques but also the
most lossy
• The parity of responses to the test patterns is
calculated as
– , where L is the length of the test and ri is the
response for the ith test pattern
• The response of the circuit under test (CUT) to
pattern i and the partial product Pi-1 is illustrated as
below

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 One Counting
• The number of 1’s in the response stream is
calculated and compared to the number of 1’s in
the fault-free responses
• Consider the circuit shown below

• If we have a test of length L and the fault-free count

is m, the possibility of aliasing is [C(L,m)-1] patterns
out of a total number of possible strings of length L,
(2L-1)
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 Transition Counting
• In transition counting compaction, it is only the
number of transition 0→1 and 1→0 that are
counted. Thus the signature is given by
– , where the summation is ordinary addition
and  is XOR operation

• The compaction scheme is shown below

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Pseudorandom Pattern Generator
• Logic BIST uses mostly pseudorandom (PR) tests.
They are usually much longer than deterministic
tests, but are definitely less costly to generate.
• PR tests are generated using a LFSR or cellular
automata.
• By means of a simple circuit called an autonomous
linear feedback shift register (ALFSR).
• Definition: an ALFSR is a LFSR with no external
inputs.
• Faults that are hard to detect with PR tests are
called random pattern resistant faults.

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Pseudorandom Pattern Generator
• Example: the following ALFSR generates the pseudorandom
sequence shown in the table below

– The output sequence is 000111101011001, which repeats after 15(2n-

1) clocks
– Max period for an n-stage ALFSR=2n-1
– All-0 state of the register cannot occur in the max-length cycle
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Built-In-Logic-Block-Observer (BILBO)
• A BILBO is a multi-purpose test module which serves as a
test generator or a signature analyzer. It is composed of a
row of FFs and some additional gates for shift and feedback
operation

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 Practice: LFSR
1. Derive the signature of the 4-bit input string of 1110 using the LFSR
shown below. Show the content of the flip-flops over the shifting cycles.
2. Verify the answer in Q.1 using polynomial division with the
characteristic polynomial of the LFSR.

0111 R1 R2 R3

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 Practice: Signature Analysis
1. Suppose that a modular LFSR whose characteristic
polynomial is 1+X+X4 is used as a signature analyzer for the
circuit and the test shown below.
a) Calculate the signature of the good circuit.
b) Let line a have an SA0. Calculate the signature if the test sequence is
1,2,3,...,15.

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 BIST: Summary
• Built-in self-test methodology is more and more
important for deep submicron designs
• Two key components of BIST
– Test pattern generator
• E.g., LFSR
– Response evaluator
• E.g., BILBO

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