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UNIT I: BOOLEAN ALGEBRA AND LOGIC GATES

S.N Question Mark C PO BT

O s O L
1 A person on Saturn, possessing 18 fingers, has property worth (100000)18. He has three 5 1 1,2,9 4
daughters and two sons. He decides to distribute half of the property to his children and
use the remaining half for his own expenses.

a) Half of the property is equally distributed among his sons, and the other half (meant for
the children) is equally distributed among his daughters. How much does each son and
daughter get in Indian currency?

b) The expenditure for his own use on Saturn is allocated in the ratio 1:2:7 for food,
clothing, and traveling, respectively. How much will he spend on each item in Saturn
currency?

2 A bulb in a staircase has two switches. one switch being at the ground floor and the 5 1 1,2,3,6,7,8,9,10,11,1 5
other one at the first floor. The bulb can be turned ON and also can be turned OFF 2
by one of the switches irrespective of the status of the other switch. Design the
logic circuit for the above set of switches using minimum number of universal
gates.
3 When the elevator moves from one floor to another, only one positional bit should change 5 1 1,2,3,6,7,8,9,10,11,1 4
to minimize errors during operation. Design a logic circuit which determines the next floor 2
of a multi-story elevator control system ?

4 An AC is controlled by 4- variables, Temperature (T), Humidity(H), time of the 5 1 1,2,3,6,7,8,9,10,11,1 5

day (D) and day of the week (W) . The unit is turned on under 2
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i) T exceeds 78oF and D is between 8AM and 5 PM

ii) H exceeds 85% , T exceeds 78oF and D is between 8AM and 5 PM
iii) H exceeds 85%,T exceeds 78oF and it is a weekend
iv) It is a Saturday or Sunday and H exceeds 85%
Design the logic circuit for controlling AC unit with minimum number of gates.
5 An Indian Army major needs to transmit a secret code, "2024" to his soldiers. The code 5 1 1,2,3,6,7,8,9,10,11,1 5
must be designed to allow the soldiers to detect and correct any single errors that may 2
occur during transmission. How can a coding scheme be designed to meet these criteria?

UNIT II: GATE LEVEL MINIMIZATION

S.N Question Mark C PO BT

O s O L
1 A weighing machine accepts coins of denominations 2 or 5 or 10. Design a logic 5 2 1,2,3,6,7,8,9,10,11,1 4
circuit using basic logic gates to accept only these coins and produce the output. 2
Note: People are using some fake coins numbered as 1,3,4,6,7,8,9.
2 An insurance policy issued if the applicant is 5 2 1,2,3,6,7,8,9,10,11,1 4
2
a) A married female 25 years old or over (or)
b) A female under 25 years (or)
c) A married male under 25 years who has not been involved in car accident (or)
d) A married male who has been involved in a car accident (or)
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e) A married male 25 years or over who has not been involved in a car accident.
Design a simplified logic circuit which decides to issue the insurance policy.
3 When data is transmitted from one computer to another, there is a possibility of 5 2 1,2,3,6,7,8,9,10,11,1 5
errors occurring during transmission. How can you design a circuit to detect these 2
errors?
4 A lawn-sprinkling system is automatically controlled by the following parameters: 5 2 1,2,6,7,9 4
season (S), Moisture content of soil (M), Outside temperature (T), Humidity(H).
Sprinkler is turned on under following circumstances.
1) Moisture content is low in winter
2) Temperature is high and moisture content is low in summer
3) Temperature is high and humidity is high in summer
4) Temperature is low and moisture content is low in summer
5) Temperature is high and humidity is low
Find simplest possible logic expression to turn on sprinkler system.

5 In a quiz competition with 16 participants, each participant answers 4 questions. Design a 5 2 1,2,3,6,7,8,9,10,11,1 4
simplified logic circuit that selects the winners based on the criterion that a participant must 2
answer 2 or more questions correctly. How would you approach this design?

UNIT III: COMBINATIONAL LOGIC CIRCUITS

Mark C PO BT
s O L
1 Design a circuit which executes the following code: 5 3 1,2,3,6,7,8,9,10,11,1 6
If(A+B>9) 2
then S=A+B+6
else
S=A+B
A,B are 4-Bit Binary Numbers.
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2 A Combinational logic circuit has 4 inputs (A, B, C, D) and one output (Z). The 5 3 1,2,3,6,7,8,9,10,11,1 5
Output is 1 if the input has three Consecutive 0’s or Three Consecutive 1’s. For 2
example, if A=1, B=0, C=0, and D=0, then Z=1, but if A=0, B=1, C=0 and D=0,then
Z=0. Design the Circuit using one Four input OR gate and four three input AND
gates.

3 Identify the circuit in Fig and design it using basic gates with corresponding truth 5 3 1,2,3,6,7,8,9,10,11,1 6
tables and expressions. 2
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4 5 3 1,2,3,6,7,8,9,10,11,1 5
2

The above figure indicates the 7 segment display with common cathode
configuration. List out the segments to be enabled to display the all Characters from
0-9. Design the circuit that lighting up the first segment “A” of 7-Segment display.
5 A 3-Bit calculator produces both the results as ‘0’ when all the inputs are zero and 5 3 1,2,3,6,7,8,9,10,11,1 5
produces both the results as ‘1’ when all the inputs are one and both the outputs are 0 2
and 1 respectively when two inputs are 0. Identify the Operation of Calculator and
Design it with 4*1 MUX which can add 3 bits.

UNIT IV: SEQUENTIAL LOGIC CIRCUITS

1 Imagine you're teaching a group of fireflies to line up in a row. At every clap of your 5 4 1,2,3,6,7,8,9,10,11,1 5
hands, each firefly moves one spot to the right, the one at the end flies away, and a 2
new firefly joins from the left. Which type of shift register represents this behavior,
and how would you teach this process to the fireflies?
2 The ripple counter shown in Fig. is made up negative edge triggered J-K flips flops. 5 4 1,2,3,6,7,8,9,10,11,1 6
The signal levels at J and K inputs of all the flip-flops are maintained at logic 1. 2
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Assume that all outputs are cleared just prior to applying the clock signal.

(a) Create a table of Q0,Q1,Q2 and A in the format given below for 10 successive
input cycles of the clock CLK1.
(b) Determine the module number of the counter.

3 The shift register shown in Fig. is initially loaded with the bit 5 4 1,2,3,6,7,8,9,10,11,1 6
pattern 1010. Subsequently the shift register is clocked, and with each clock pulse 2
the pattern gets shifted by one bit position to the right. With each shift, the bit at the
serial input is pushed to the left most position (MSB). After how many clock pulses
will the content of the shift register become 1010 again?
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4 Reduce state table and state diagram for the sequential machine 5 4 1,2,3,6,7,8,9,10,11,1 5
2

5 Design a digital clock that displays time in seconds using LEDs to represent a cyclic 5 4 1,2,3,6,7,8,9,10,11,1 6
counting pattern. Use a 4-bit ring counter and a 4-bit Johnson counter to manage the 2
states.
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UNIT V: MEMORIES AND ASYNCHRONOUS SEQUENTIAL LOGIC

1 Design an adder which accepts three inputs, adds them and produces their sum as 5 5 1,2,3,6,7,8,9,10,11,1 5
output using Programmable Array Logic 2
2 Design BCD to 7 Segment Decoder Using PROM 5 5 1,2,3,6,7,8,9,10,11,1 5
2
3 Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and 5 5 1,2,3,6,7,8,9,10,11,1 5
generates an output binary number equal to the square of the input number. 2
4 Suppose you're designing a microcontroller-based project, such as a temperature 5 5 1,2,3,6,7,8,9,10,11 6
logging system. Explain why you would choose specific types of RAM and ROM
for this application. How would your choice differ if the data needed to be saved
after power-off?
5 The following is a truth table of a 3-input,4-output combinational circuit. Tabulate the PAL 5 5 1,2,3,6,7,8,9,10,11 6
programming table for the circuit and mark the fuse map in PAL diagram.

Inputs Outputs
x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
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1 1 1 0 1 1 1

OBJECTIVE QUESTIONS
UNIT I
Multiple Choice Questions
1. Decimal number 21.125 may be written in binary system as: [ ]

(a)10101.010 (b)10100.001 (c)10101.001 (d)10100.100

2. The largest positive number that can be stored in a computer that has16-bitword length and uses twos
complement arithmetic is [ ]
(a)32767 (b)32768 (c)32 (d)65536
3. Binary 1000 when multiplied by binary 1111 results in binary: [ ]

(a)1110000 (b)1111111 (c)1111000 (d)1111100

4. 1k-byte is precisely equal to: [ ]
(a)1020bits (b)1012bits (c)1000bits (d)1024bits
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5. The1’s compliment of 1’s compliment of a given number is

[ ]
(a)1’scompliment (b)9’scompliment (c)the same number itself (d) 2’scompliment
6. The dual of a Boolean theorem is obtained by [ ]
(a) inter changing all zeros and ones only (b) inter changing operators and identity elements
(c) changing all ones to zeros only (d)changing all zeros to ones only
7. AB+A+1= [ ]
(a)B (b) 1 (c) A (d) 0
8. Which of the following gates is known as coincidence detector? [ ]
(a)NOT gate (b)AND gate (c)NAND gate (d)OR gate
9. The NAND can function as NOT gate if [ ]
(a)one input is set to 0 (b) inputs are left open (c)inputs are connected together (d)one input is set to 1
10. AB+A+0= [ ]
(a) B (b)1 (c)0 (d)A

Fill in the Blanks :

11. Decimal equivalent of octal number 57 is_______________.

12. The2‘s compliment of binary number 001011 is______.

13. Hexadecimal equivalent of decimal number 1000 is:_________

14. Decimal number 74 may be written in binary system as:_______________.

15. The1’s compliment of 1’s compliment of a given number is _____________________________.

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16. Excess-3 equivalent of decimal number 10 is _____________________________.

17. The minimum number of bits required to represent negative numbers in the range of -1 to -11 using 2’s complement arithmetic
is _____________________.
18. A 15-bit hamming code requires _______________Parity bits
19. When two n bit binary numbers are added , the sum will contain at the most _____________________________.
20.In a digital system performance accuracy depends on _____________________________.

KEY:

1.(c) 2(a) 3.(c) 4(d) 5.(c) 6(a) 7(b) 8.(c) 9.(c) 10(d)

15. The
14.100101 same
11. 47 12.110101 13. 3E8 16. 1101 17. 5 18.parity bits 19.n+1 bits 20.word length
0 number
itself

OBJECTIVE QUESTIONS
UNIT II
1. Which of the following code is used in K-map for representing them in terms? [ ]

(a)BCD (b) Gray code (c)8421 (d) Excess-3code

2. The given max term is A+B+C, its equivalent Binary representation is [ ]

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(a)000 (b)101 (c)111 (d)010

3. A 1ine cell of k-map can be combined with three other1‘sin Only one combination The resulting term of these four 1‘s is [ ]

(a) not prime implicant (b)Don’t care (c)Essential Prime Implicant (d)Minterm

4. The minterm, designator of the term B‘CD is [ ]

(a)12 (b)15 (c)11 (d)10
5. The necessary condition to combine the two minterms is Both minterm values must Be differentiated by power of [ ]

(a)2 (b)6 (c)4 (d)3

6. If F(A,B,C,D)=1then the K-map contains number of Logic1‘s is [ ]

(a)8 (b)32 (c)4 (d)16

7. The Essential Prime Implicant of the function covers all the Minterms then there resultant expression is a [ ]

(a)logical expression (b)arithematic expression (c)not a unique expression (d)Unique expression

8. In Don’t care a minterm /maxterm in a logic function which [ ]

(a)is always‘0’ (b) must be included (c)may or may not be included (d)ignored

9.Which of the following code is used in K-map for representing the minterms ? [ ]

(a) Graycode (b)BCD (c)8421 (d)Excess-3codeA

10.A Prime Implicant which includes at least a1cell that is not covered by any other Prime Implicant is called [ ]

(a)self complimenting (b)Dominent (c)essential prime implicant (d)prime implicant itself

Fill in the Blanks :

11.The X mark in a cell may be assumed to be Upon which one leads to a simpler expression____________.
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12.A maxterm is _________term,which contains all the variables either in complemented or uncomplimented form.

13. The number of cells in a 6-variable K-map is__________.

14. A minterm corresponding to Don’t care condition may have a value of _________________.

15. The necessary condition to combine the two minterms is Both min term values must Be differentiated by power of _______.

16. If sqrt(41)=5,the base(radix) of the number system is ________.

17. The hexadecimal number system is used in digital computers and digital systems to ___________________.
18. The code used for labeling cells of the K-map is ___________________.
19.Each term in the standard SOP form is called a __________________.
20. ___________ is the minimum number of NOR gates required to realize an X-OR gate.
ANSWERS:
1(b) 2(a) 3(c) 4(c) 5(a) 6(d) 7(d) 8(c) 9(a) 10(c)

17. Input binary data into

11. only 0 12. sum 13. 64 14. 0or1 15. 2 16.6 18. Gray 19. minterm 20. 5
the system.

UNIT III
1. Adder is an example for [ ]
(a)Combinational digital circuit (b)Registers (c) Both combinational and sequential (d)sequential digital circuit
2. Decoder with ‘n’ inputs produces maximum of number of minterms [ ]
(a)2n (b) 2n-1 (c)2n-1 (d)2n
3. A full adder can be realized by [ ]
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(a)one half-adder, one OR gate (b)two-half-adder, two OR gates (c)one half-adder, two OR gate (d)two-half-adder, one OR gates
4. What is the number of inputs, outputs of a decoder that accepts 64 different input combinations? [ ]
(a)5 (b)64 (c)6 (d)7
5. How many 2*1 MUXs are needed to construct 4*1 MUX [ ]
(a) 4 (b)1 (c)3 (d)2
6. An one-of-16 line decoder can be constructed by using number Of one-of-2 lined Encoder [ ]
(a)6 (b)3 (c)4 (d)5
7.The size of the decoder required to implement 3-variable Boolean Function is [ ]
(a)3 to 8 line (b)2 to 4 line (c) 4 to 8 line (d) 4 to 16 line
8. The circuit used for parallel to serial conversion of data is known as [ ]
(a)Adder (b)Multiplexer (c)parity encoder (d) Demultiplexer
9. The no of NAND gates needed to construct half adder [ ]
(a)4 (b)5 (c)3 (d)6

10. In combinational circuits, output depends on ______ [ ]

(a) Previous input (b) Previous output (c)Present input (d) Both a&b

Fill in the Blanks :

11. ___________number of full adders required to add two 4-bit data in a Serial adder
12. How many selection lines are needed for 16:1 MUX__________________.
13. A gate is enabled when its enable input is at logic 0. The gate is ______________.
14. Digital multiplexer is basically a combinational logic circuit to perform the operation_______________.
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15. In _____________ adder circuit the carry ripple delay eliminated
16) A serial adder requires only one ___________.
17) The carry propagation can be expressed as ________.
18) A Full Adder adds _____________ number of bits.
19) In order to design 5-Bit Comparator ______ number of outputs are needed.
20. _______________ is also called Data Selector.
ANSWERS:
1 (a) 2 (d) 3 (d) 4 (c) 5 (c) 6 (d) 7 (a) 8 (b) 9 (b) 10 (c)

12. 4 13. NOR 14.AND-OR 15.carry-look- 16.full - 17.Cp = A + 18. 3 19. 3 20.
11. 4
ahead adder adder B Multiplexer.

OBJECTIVE QUESTIONS
UNIT IV
1. The basic latch consists of ___________ [ ]

a) Two inverters b) Two comparators c) Two amplifiers d) Two adders

2. A modulus-12 ring counter requires a minimum of ________. [ ]

a) 10 flip-flops b)12 flip-flops c)6 flip-flops d)2 flip-flops

3. The output of latches will remain in set/reset until___________ [ ]
a) The trigger pulse is given to change the state b) Any pulse given to go into previous state
c) They don’t get any pulse more d) The pulse is edge-triggered

4. Latches are___________ triggered [ ]

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a) Level b) Edge c)Both d)None of the Above

5. How is a J-K flip-flop made to toggle? [ ]

a) J = 0, K = 0 b) J = 1, K = 0 c) J = 0, K = 1 d) J = 1, K = 1
6. On a master-slave flip-flop, when is the master enabled? [ ]

a) when the CLK is LOW b) when the CLK is HIGH c) both of the above d) neither of the above
7. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________. [ ]

a) constantly LOW b) constantly HIGH c) a 20 kHz square wave d) 10 kHz square wave
8. How many different states does a 3-bit asynchronous counter have? [ ]

a) 2 b)4 c)8 d)16

9. The final output of a modulus-8 counter occurs one time for every ________. [ ]

a) 8 clock pulses b)16 clock pulses c)24 clock pulses d)32 clock pulses
10. Generally _____________ is used to construct shift registers [ ]

a)D flip flop b) T flip flop c) J-K flip flop d) S-R flip flop
Fill in the Blanks :
11. Asynchronous counters are often called ________ counters.

12. In a 6-bit Johnson counter sequence there are a total of ________ states, or bit patterns?

13. In S-R flip-flop, if Q = 0 the output is said to be ___________

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14. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock
pulses, the register contains ________.

15. A sequence of equally spaced timing pulses may be easily generated by ________type of counter circuit.

16. A Flip flop has ______________ stable states.

17. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
________________.

18. To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ________.
19. The terminal count of a modulus-11 binary counter is ________.

20. When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.

ANSWERS

1.a 2.c 3.a 4.a 5.d 6.b 7.d 8.c 9.a 10.a
11.Ripple 12.12 13.Reset 14.0111 15.Ring 16.2 17.Sequential logic circuit 18. strobe line 19.1010 20.Product
OBJECTIVE QUESTIONS
UNITV
1. The storage element for a static RAM is the ________. [ ]

a) Diode b)Resistor c)Capacitor d)flip-flop

2. In a DRAM, what is the state of R/W during a read operation? [ ]

a) Low b)High c)Hi-Z d)None of the above

3. One of the most important specifications on magnetic media is the ________. [ ]
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a) rotation speed b)tracks per inch c)data transfer rate d)polarity reversal rate
4. How many 2K × 8 ROM chips would be required to build a 16K × 8 memory system? [ ]

a) 2 b)4 c)8 d)16

5. Which of the following is best suited for parity checking and parity generation? [ ]

a) AND, OR, NOT gates b)XOR, Exclusive NOR gate c)NAND gates d)NOR gates
6. Which of the following best describes EPROMs? [ ]

a) EPROMs can be programmed only once. b)EPROMs can be erased by UV.

c)EPROMs can be erased by shorting all inputs to the ground. d)All of the above.
7. Which of the following best describes volatile memory? [ ]

a) memory that retains stored information when electrical power is removed

b) memory that loses stored information when electrical power is removed
c) magnetic memory d)nonmagnetic
8. The table that is not a part of the asynchronous analysis procedure is [ ]

a) transition table b) state table c) flow table d) excitation table

9. The race in which stable state depends on an order is called [ ]

a) critical race b) identical race c) non critical race d) defined race

10. In primitive flow table for the gated latch, each state has [ ]

a) 1 row b) 2 rows c) 3 rows d) 4 rows

Fill in the Blanks:

11. CCD stands for ________.
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12. ________ type of ROM can be erased by an electrical signal.

13. Data is written to and read from the disk via a magnetic ________ head mechanism in the floppy drive.

14. ________ is the computer main memory.

15. The periodic recharging of DRAM memory cells is called ________.

16. The complexity of the asynchronous circuit is involved in timing problems of________.

17. Asynchronous sequential logic circuits are used when a primary need is________.

18. Memory elements in asynchronous circuits are________.

19. Asynchronous sequential logic circuits usually perform operations in________ mode.

20. In fundamental mode, the circuit is assumed to be in ________ state.

ANSWERS

1.d 2.b 3.c 4.c 5.b 6.b 7.b 8.d 9.a 10.a
11. charge-coupled 12. 13. 14. 15. 16.feedback 17. 18. Unclocked 19. fundamental 20. stable
device EEPROM read/write RAM refreshing path speed flip-flops mode
and
ROM