Scribd
Upload
61 views2 pages

CST202 Computer Organization and Architecture, December 2024

This document outlines the examination structure for the B.Tech Degree in Computer Organization and Architecture at APJ Abdul Kalam Technological University for December 2024. It includes details on question types, marking schemes, and topics covered in both Part A and Part B of the exam, such as instruction execution, addressing modes, processor organization, and I/O device access mechanisms. The exam consists of multiple-choice questions and full questions from various modules, each with specific marks allocated.

Uploaded by

mr.appu008
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
61 views2 pages

CST202 Computer Organization and Architecture, December 2024

This document outlines the examination structure for the B.Tech Degree in Computer Organization and Architecture at APJ Abdul Kalam Technological University for December 2024. It includes details on question types, marking schemes, and topics covered in both Part A and Part B of the exam, such as instruction execution, addressing modes, processor organization, and I/O device access mechanisms. The exam consists of multiple-choice questions and full questions from various modules, each with specific marks allocated.

Uploaded by

mr.appu008
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

B

Reg No.:
0200csT202L2240L

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY


ffi 3l*-iC

B.Tech Degree 54 (S, FE) / 52 (PT) (S, FE) / 54 (WP) (S) Examination December 2024 (2019 Scheme)

Course Code: CST 202


Course Name: Computer Organization and Architecture
Max. Marks: 100 Duration: 3 Hours

PART A
(Answer all questions; each question carries 3 marks) Marks
.
I Explain the steps involved in the execution of an instruction. 3

2 Write the control sequence for the execution of conditional branch instruction. J

J Draw and explain about true/complement circuit? 3

4 Describe about logic and shift micro operations. Listing the available operations in 3

each category.

) Explain the steps involved in restoring division. 3


a
6 Describe about instruction pipeline. J

a
7 Differentiate between horizontal and vertical m icroinstructions. J

8 Explain PLA based control organization with the help of a diagram. 3

9 What are intemrpts? List the sequence of steps following an intemrpt request? 5

l0 Draw and explain the memory hierarchy. 3

PART B
(Answer onefull questionfrom each module, each question carries 14 mnrks)
Module -1
ll a) Describe the following addressing modes with suitable examples.
i) Relative addressing mode ii) Register addressing mode
iii)Auto increment addressing mode iv)I*mediate addressing mode
b) Differentiate between big endian and little endian byte ordering with examples 6

12 a) Write the three-address, two-address and one-address representations of the 6

given operation (A+B) * (C+D) with relevant assumptions.


b) Explain multi-bus organization with neat sketches. Write the control sequence for
the instruction Add R4, R5, R6 for the multi-bus organization.

Module -2
l3 a) Explain 4 bit complete accumulator with neat sketches.

Page 1 of 2
?
0200csT202L22401

b) Describe processor organization with. diagram using 6

i) scratchpad memory. ii) Two-port memory


14 a) Illustrate and explain the organization of a processor unit where procesSor registers 7

and ALU are connected through common buses. Explain how the micro operation
Rl +- R2+R3 would be performed using this organization, where Rl, R2 and R3
are processor registers.

b) Design a 4-bit combinational logic shifter with two control variables, Hl and H0. 7

Specifu the operations for each control variable and explain its working.
Module -3
l5 a) Draw the flowchart of Booth's multiplication algorithm and multiply -9 X -13 l0
b) Design and draw the block diagram for a 3 by 2 anay multiplier. 4
16 a) List and explain the different pipeline hazards and their possible solutions. l0
b) Write notes on arithmetic pipeline. 4
Module -4
17 a) Design a hardwired control unit used to perform addition/subtraction of numbers 14

represented in sign magnitude form.

l8 a) With the help of a diagram explain the functioning of a micro-program l0


sequencer in a micro-programmed controlled processor?

b) Write a note on Sequence register and decoder method. 4


Module -5
19 a) Explain in detail about the mechanisms for accessing I/O devices? E

b) List and explain the different types of ROMs. 6


20 a) Explain the various mapping functions available in cache memory. 9

b) Briefly explain content addressable memory. 5


* rt*

Page2 of 2
?
\

You might also like