Sheet 1

Revistion
PROBLEMS
1- Design the BCD (Binary coded Decimal) –to- Excess-
3 code converter.
The converter must implement minimum number of
gates.

2- Design a combinational circuit that multiplies two-bit

numbers a1 a0 and b1 , b0 to produce a 4-bit product
P3P2P1P0 . Use half-adders and AND gates.

3- Design a combinational circuit with three inputs and 6

outputs . The output binary number is the square of the
input binary number.

4- Design a combinational circuit that detects an error in

the decimal digit in BCD. The output must detect also
any of the six unused states in the BCD code.

5- Assume that 4 inputs D0D1D2D3 have priorities such

that Dj always have a priority than Di if j< i .
The outputs are defined according to the allocated table.
V0 is the valid output indicator which is set to 1 iff one
or more inputs is equal to 1.
1
 Inputs Outputs
D0 D1 D2 D3 X1 X2 V0
0 0 0 0 0 0 0
1 0 0 0 0 0 1
Ø 1 0 0 0 1 1
Ø Ø 1 0 1 0 1
Ø Ø Ø 1 1 1 1

Priority table for prob. 5

6- Suggest a general procedure for implementing a logic

function of n+1 variables with an 2n-to-1 multiplexer.
Explain this procedure by the help of the function of
three variables F(a,b,c) = ∑(1,3,5,6) using 4-to-1
multiplexer.

7- Use the proposed procedure in prob.6 to realize the

function
F (a,b,c,d) = ∑( 0,1,3,4,8,9,15)

8- Construct the BCD-to-excess-3- code converter in

prob. 1 using a 4-bit adder.
9- Design a combinational circuit that compares two 4-
bit numbers

2
 X = x3x2x1x0 and Y = y3y2y1y0 . The output z =1 if
they are equal and 0 other- wise.
A0

A5
A1
10- Design the ROM that drives a seven A segment
4 A 2

indicator.
The indicator indicates only numbers from 0 toA 9 .3

A3
Assume positive logic. Use diode matrix
implementation.

11- If z = x2-3x+6 and x is an integer ; 0 ≤ x ≤ 7

Design the ROM that realizes this function using diode

matrix encoder, and OR gates.

3
 Sheet 2
FF

X Full S
adder
1- Construct a D-flip-flop using NOR y C

and AND gates. Q D

Q
CP
2- Construct a D-flip-flop using NOR Fig. (a)

gates only.

3- For the D-flip-flop circuit shown in Fig. (a). Derive

the state table for this circuit. Realize the same
Circuit by EX.OR, AND and OR elementary circuits

4- The JN flip-flop has an equivalent input to J but

N=K
a- Construct the truth table (characteristic table) for
that flip-flop.
b- Tabulate the excitation table for that flip-flop.
c- Show that we can obtain a D flip-flop if J and N are
short circuited.

5- Show that the circuit connected in Fig (b) is equivalent

to a T-flip-flop. T
D Q

CP
Fig- (b)
4
6- Convert a D-flip-flop to a J-K flip-flop by inserting input
gates to the D-flip-flop. The sequential circuit achieved
will act as one D-flip-flop and two inputs J-K flip-flop.

7- Draw the logic diagram of a master – slave D-flip-flop

using NAND gates only.

8- Design the AB flip-flop given by the characteristic table

shown in fig. (c) , Use S-R flip-flop in your design .
Derive the excitation function and draw the logic
diagram Of your realization.
A B Qn+1
0 0 Qn
0 1 1
1 0 0
1 1 Qn
Fig. (c)

9-The MN flip-flop expressed by the state map in Fig. (d) is to be realized by T.

flip-flop.
Derive the excitation functions and draw the logical diagram.

Qn+1 N M
1 1 0 0
Qn 1 0 0 1

Fig. (d)

5
 Sheet 3
SR & counters

1- A 4- bit register has its contents initially at 1101 .

The register is shifted six times to the right with a
serial input 101101 being applied tabulate the
contents of register after each shift .

2- Design the sequential circuit having two memory

cells M1 and M2 and one input x such that :
M1n+1 = ∑(4,6)
M2n+1 = ∑(1,2,5,6)
Z (M1 , M2 , x ) = ∑( 3,7)

(a) Design this circuit using a register with two

memory elements and combinational logic gates.
(b) Design the same circuit using a two memory
element register and a ROM.

3- Design a serial adder using one of the following

alternatives :

6
 (a) Two shift-registers, full adder and D flip-
flop in the carry branch to fulfill the delay
required.
(b) Using two shift-registers and a JK flip-
flop with the associated excitation logic.

4- If the design in prob. 3(a) uses two 4-bit registers. If

register A holds the number 0101 while register B
holds 0111 while the carry flip-flop is 0 .
List the binary values in register A and the carry
flip-flop after each shift.

5- For the binary counter with parallel load

given before with the function table shown use this
MSI chip to fulfill the following:
(a) The counter counts states 0,1,2,3,4,5.
(b) The counter counts the states
10,11,12,13,14,15 .
(c) The counter counts the states 3,4,5,6,7,8 .

7
 Cle C Lo Cou
Function
ar P ad nt
0 Ø Ø Ø Clear to 0
1 Ø 0 0 No change
1 1 Ø Load inputs
Count next
1 0 1
binary state

6- The counter in Fig. (IV – 1) is to be designed on

the principle that if the counter enters erroneously
any of the unused states it resets automatically
to initial state 3 without giving an alarm that an error
occurred . Carry out the design using JK flip-flops
and compare this design with the design introduced
before.
3

0 2

Fig. (IV-1)

8
7-
- The initial contents of the sift register Fig. (IV-2) is 1101
tabulate the contents of this shift register for the following 16 clock pulses .

A B C D
D Q D Q D Q D Q

Q Q Q Q
CP

Fig. (IV – 2)

8- Design the clocked counter counting the BCD

representation . The counter has an enable input x
which in case x=0 the counter keeps its present state ,
and counts up 0-1-2 …… - 9 when x=1 . Design this
counter using JK flip-flops. Design the optimum
decoder of states which drives lamps indicating
counter states and the circuit which rests the counter to
0 state if it enters one of the six unused states.

9- Design the random counter in Fig . (IV -3) .

The counter resets to initial state 1 if IS
It enters one of the unused states and
Design the optimum decoder of used states .
Realize the counter
14
(a) Using D flip-flops
10
1
(b) Using J-K flip-flops
3
4

9
6
9
Fig (IV-3)
10- For the following memory sizes and word lengths,
how many address lines and input/ output data lines
are needed in each case?
(a) 2K x 16 (b) 64K x 8
(c) 16 M x 32 (d) 96 K x 12

10
 Sheet 4
VHDL

1. In what aspect, HDLs differ from other computer

programming languages?
a) No aspect; both are same
b) HDLs describe hardware rather than executing a
program on a computer
c) HDLs describe software and not hardware
d) Other computer programming languages have more
complexity

2. Which of the following HDLs are IEEE standards?

a) VHDL and Verilog
b) C and C++
c) Altera and Xilinx
d) Quartus II and MaxPlus II

3. Why we needed HDLs while having many traditional

Programming languages?
a) Traditional programming languages are complex
b) HDLs are complementary to traditional programming
languages to complete the design process
c) Some characteristics of digital hardware couldn’t be
captured by traditional languages
d) HDLs offer more complexity than traditional
programming languages.

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4. An HDL can’t describe Hardware at Gate level as well
as switch level?
a) True
b) False

5. Describe the entity and architecture design units in

VHDL code
i. OR gate.
ii. Memory.
iii. A Full adder.
iv. 8-bit ripple carry adder.
v. +ve edge trigger D F.F.
vi. 8-bit register

6. The 2 VHDL code listed below, contain some

syntax errors:
a. Identify the mentioned syntax errors. Then how can
these errors be corrected.
b. Draw the circuit diagram implemented by that
VHDL.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Test is
Port ( A; B IN std_logic_vector (3 DOWN TO 0 ),
AeqB, AgtB Altb : OUT STD_LOGIC};
END TEST;
ARCHITECTURE Behavior of Test IS
BEGIN
AeqB <= "1" WHEN A=B else "0";
AgtB <= "1" WHEN A>B else "0";
ALTB <= "1" WHEN A<B else "0";
END Behavior of Test;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Test1 is
Port ( D IN std_logic_vector (3 DOWN TO 0 ),
Q : OUT std_logic_vector (1 DOWN TO 0 ),
END TEST1;
ARCHITECTURE Behavior of Test2 IS
BEGIN
Q <= "00" WHEN D= "0001"; else
"01" WHEN D= "0010" else
Sheet "10"6 WHEN D= "0100" else
RAM "11"& ROMD=&"1000";
WHEN PLA else
Mcq"XX";Questions
END ARCHITECTURE;

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14
 (1) Design 2-Dimenional 1K-word memory
(2) Construct 32X8 ROM
(3) Programming the ROM according to the truth
table 7-3

(4) Design a combinational circuit using a ROM. The

circuit accepts a 3-bit number and generates an
output binary number equal to the square of the
input number.
Derive truth table first.

15