INPUT/OUTPUT.

Ch-4

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 INPUT/OUTPUT.
The input output of subsystem of a computer provides an efficient mode of communication between the
central system and the outside environment. It handles all the input-output operation of the computer system.
Major functions of an I/O module
✓ Interface to CPU and memory via system bus or central switch
✓Interface to one or more peripheral devices by tailored data links
Basic structure of an external device
▪Data - bits sent to or received from the I/O module
▪Control signals - determine the function that the device will perform
▪Status signals - indicate the state of the device (esp. READY/NOT-READY)
▪Control logic - interprets commands from the I/O module to operate the device
▪ Transducer - converts data from computer-suitable electrical signals to the form of energy used by the
external device
▪Buffer - temporarily holds data being transferred between I/O moduleCOMPILED
and the external
BY ABEL H.
device 2
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 I/O MODULE
An I/O Module is the entity within a computer responsible for:
1. control of one or more external devices
2. exchange of data between those devices and main memory and/or CPU
registers
And It must have two interfaces:
1. internal, to CPU and main memory
2. external, to the device(s)

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 MAJOR FUNCTION/REQUIREMENT CATEGORIES
Control and Timing
Coordinates the flow of traffic between internal resources and external
devices
Cooperation with bus arbitration o CPU Communication
Command Decoding
Data
Status Reporting
Address Recognition.
Device Communication (see diagram under External Devices)
Commands
Status Information
Data
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 CONT.
Data Buffering
Rate of data transfer to/from CPU is orders of magnitude faster than to/from
external devices
I/O module buffers data so that peripheral can send/receive at its rate, and
CPU can send/receive at its rate
Error Detection
 Must detect and correct or report errors that occur
 Types of errors
 Mechanical/electrical malfunctions
 Data errors during transmission

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I/O MODULE STRUCTURE

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 PERIPHERAL DEVICES
Input or output devices that are connected to computer are called peripheral
devices. These devices are designed to read information into or out of the
memory unit upon command from the CPU and are considered to be the part
of computer system. These devices are also called peripherals.
Types of peripherals
A. Input peripheral. Allows user input, from the outside world to the computer.
B. Output peripheral. Allows information output, from the computer to the
outside world.
C. Input-output peripherals. Allows both input from the outside world to
computer. As well as, from the computer to the outside world.

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 INTERFACES
Interface is a shared boundary between two separate components of the computer
system which can be used to attach two or more components to the system for
communication purposes.
Two types of interfaces
1. CPU Interface
2. I/O interface
Input output interface
Peripherals connected to a computer need special communication links for interfacing
with CPU. In compute system, there are special hardware components between the
CPU and peripherals to control or manage the input-output transfers. These
components are called input-output interface units because they provide
communication links between processor bus and peripherals. They provide a method
for transferring information between internal system and input-output devices.
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 MODES OF I/O DATA TRANSFER
Data transfer between the central unit and I/O devices can be handled in generally three types of modes
which are given below.
a. Programmed I/O
b. Interrupt driven(initiated) I/O
c. Direct Memory Access (DMA)
Programmed I/O
❖Programmed I/O instructions are the result of I/O instructions written in computer program. Each data item
transfer is initiated by the instruction in the program.
❖With programmed I/O, data is exchanged under complete control of the CPU
❑CPU encounters an I/O instruction
❑ CPU issues a command to appropriate I/O module
❑ I/O module performs requested action and sets I/O status register bits
❑CPU must wait, and periodically check I/O module status until it finds that the operation is complete

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 CONT.
To execute an I/O instruction, the CPU issues:
❖an address, specifying I/O module and external device
❖ 4 command types:
 control - activate a peripheral and tell it what to do
 test - querying the state of the module or one of its external devices
 read - obtain an item of data from the peripheral and place it in an internal buffer
(data register from preceding illustration)
 write - take an item of data from the data bus and transmit it to the peripheral
❖With programmed I/O, there is a close correspondence between the I/O instructions used by the
CPU and the I/O commands issued to an I/O module
❖Each I/O module must interpret the address lines to determine if a command is for itself.

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 CONT.
Two modes of addressing are possible:
Memory-mapped I/O
 there is a single address space for memory locations and I/O devices.
 allows the same read/write lines to be used for both memory and I/O transactions
Isolated I/O
 full address space may be used for either memory locations or I/O devices.
 requires an additional control line to distinguish memory transactions from I/O
transactions
 programmer loses repertoire of memory access commands, but gains memory address
space

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 INTERRUPT INITIATED I/O
❖In The programmed I/O method the CPU stays in the program loop until the I/O unit indicates
that it is ready for data transfer. This is time consuming process because it keeps the processor
busy needlessly.
❖Problem with programmed I/O is CPU has to wait for I/O module to be ready for either
reception or transmission of data, taking time to query status at regular intervals.
Interrupt-driven I/O is an alternative
 It allows the CPU to go back to doing useful work after issuing an I/O command.
 When the command is completed, the I/O module will signal the CPU that it is ready with an
interrupt.

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INTERRUPT PROCESSING DIAGRAM

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 DESIGN ISSUES
How does the CPU determine which device issued the interrupt?
 Multiple Interrupt Lines
 most straightforward solution
 impractical to dedicate many lines
 multiple I/O modules are likely attached to each line
 one of other 3 techniques must be used on each line
 Software Poll
 interrupt service routine polls each device to see which caused the interrupt
 using a separate command line on the system bus (TESTI/O) ? raise TESTI/O ? place
I/O module address on address lines ? check for affirmative response
 each I/O module contains an addressable status register, which CPU reads
 time consuming
 Daisy Chain (hardware poll, vectored)
 interrupt occurs on interrupt request line which is shared by all I/O modules
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 CONT.
 CPU senses interrupt
 CPU sends interrupt acknowledge, which is daisy-chained through all I/O modules
 When it gets to requesting module, it places its vector (either an I/O address, or an ID
which the CPU uses as a pointer to the appropriate device-service routine) on the data
lines
 No general interrupt-service routine needed (still need specific ones) Bus
Arbitration (vectored)
 requires an I/O module to first gain control of the bus before it can interrupt
 thus only one module can interrupt at a time
 when CPU detects the interrupt, it ACK’s
 requesting module then places its vector on the data lines
 another type of vectored interrupt

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 DIRECT MEMORY ACCESS
❖Removing the CPU from the path and letting the peripheral deices manage the
memory buses directly would improve the speed of transfer . This technique is known
as DMA.
❖In this, the interface transfer data to and from the memory through memory bus. A
DMA controller manages to transfer data between peripherals and memory unit.
❖Drawbacks of Programmed and Interrupt-Driven I/O
The I/O transfer rate is limited by the speed with which the CPU can test and
service a device
The CPU is tied up in managing an I/O transfer; a number of instructions must be
executed for each I/O transfer

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DMA FUNCTION

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 CONT. (DMA)
❖ Involves adding a DMA module to the system bus
 can take over system from CPU
 can mimic certain CPU operations o When CPU wishes to read or write a block of data
it issues a command to the DMA module containing:
 Whether a read or write is requested
 The address of the I/O device involved
 The starting location in memory to read from or write to
 The number of words to be read or written o CPU continues with other work
 DMA module handles entire operation. When memory has been modified as ordered, it
interrupts the CPU
 CPU is only involved at beginning and end of the transfer
 DMA module can force CPU to suspend operation while it transfers a word called
cycle stealing
 not an interrupt, just a wait state
 slows operation of CPU, but not as badly as non-DMA COMPILED BY ABEL H. [email protected] 18