Invoking GNU Make Built-in target names
To invoke GNU make type the following command line: .PHONY define targets which are not files (e.g. clean)
.DEFAULT the default target
make [-f makefile-name] [options] [targets]
.IGNORE ignore errors in prerequisites of this rule
The following file names will be searched for in the current directory automatically:
GNUMakefile, Makefile, makefile.
Variables
By default, the first target will be invoked if not target are given.
HEADER = prg.h
FILES = $(HEADER)
Rule
then $(FILES) is expanded to prg.h running make program.
target : dependency [dependency ...]
command Automatic variables
[command]
$@ the file name of the target of the rule
where target is the result of the operation, command are the recipes to execute and $< the name of the first prerequisite
dependency is the input of the operation. Beware of tabulations before commands! $^ the names of all the prerequisites
$(XD) and $(XF) can be used to extract the directory and the file part of the name corre-
Dependency between rules sponding to $X. For instance, if $@ is src/foo.c, then $(@D) is src and $(@F) is foo.c
target : target1 target2
... Suffix rules (aka pattern rules)
target1 : dependencies_1
... Rules used to process a depency of two given types of files (defined by extensions).
target_2 : dependencies_2 %.o : %.c
... gcc -c $<
make program builds a dependency-tree from these rules. This will compile any C code, supposing it’s extension is .c.
Some rules are built-in, for instance for C compilation.
Standard target names
Mainly taken from autotools, please use them: Including another makefile
all build application include PATH_TO_MAKEFILE
install install what needs to be installed
clean erase all files built by make all
distclean erase also all configuration files
GNU Make reference card – Christophe Garion IN323
Using functions Using shell for loop
Functions can be called from a Makefile. To call a function foo with arguments x and y: To use shell for loop in a recipe, do not forget to add \ at the end of each lines and to use
$$ to get the variables values:
$(foo x,y)
target:
Functions already defined (more to find in [1]):
for number in 1 2 3 4 ; do \
$(subst FROM,TO,TEXT) replaces all occurences of FROM by TO in TEXT echo $$number \
$(suffix NAMES...) extract the suffix of each file names in NAMES done
$(suffix NAMES...) extract the suffix of each file names in NAMES
$(basename NAMES...) extract all but the suffix of each file names in
NAMES Foreach loop
The foreach function can be used to repeatedly use a piece of text:
Using conditionals
$(foreach VAR,LIST,TEXT)
Using conditionals with the following constructs:
The following example sets the variable C_FILES to the list of all files with suffix .c in the
ifeq (ARG1, ARG2) ARG1 equals to ARG2? directories specified in the list DIRS (the wildcard function allows to use wildcards in file
ifneq (ARG1, ARG2) ARG1 not equals to ARG2? names):
ifdef VAR-NAME is VAR-NAME defined? DIRS = ./src ./tests
ifndef VAR-NAME is VAR-NAME not defined? C_FILES = $(foreach dir, DIRS, $(wildcard $(dir)/*.c))
For instance in a command:
ifndef PROXY Ignoring errors in command
PROXY = proxy.isae.fr
endif Put “ -” before command to ignore potential errors, e.g.
clean :
Conditional functions can be used (particulary in a functional context): - rm *.o
$(if CONDITION,THEN-PART[,ELSE-PART])
$(or CONDITION1,CONDITION2[,CONDITION3...])
$(and CONDITION1,CONDITION2[,CONDITION3...])
References
[1] Free Software Foundation. GNU Make. 2014. url: http://www.gnu.org/software/make/.
GNU Make reference card – Christophe Garion IN323
