HT48F06E/HT48F10E/HT48F30E

I/O Flash Type MCU with EEPROM

Technical Document
· Tools Information
· FAQs
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note

Features
· Operating voltage: · Power Down and Wake-up Feature for Power Saving
fSYS=4MHz: 2.2V~5.5V Operation
fSYS=8MHz: 3.3V~5.5V · Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=12MHz: 4.5V~5.5V at VDD=5V
· Multi-programmable Flash Type Program Memory · Bit Manipulation Instructions
· From 13 to 23 Bidirectional I/O with Pull-high Options · Table Read Function
· External Interrupt Input · 63 Powerful Instructions
· Full Timer Functions with Prescaler and Interrupt · All Instructions executed in 1 or 2 Machine Cycles
· Timer External Input · Low Voltage Reset Function
· Crystal and RC System Oscillator · Programming Interface
· Watchdog Timer Function · Full Suite of Supported Hardware and Software
· PFD/Buzzer Driver Outputs Tools Available

General Description
The HT48F06E, HT48F10E and HT48F30E are 8-bit tures are common to all devices, however, they differ in
high-performance, RISC architecture microcontroller areas such as I/O pin count, Program Memory and Data
devices specifically designed for multiple I/O control Memory capacity, package types, etc.
product applications. Device flexibility is enhanced with
All devices utilise a Flash type Program Memory, and
their internal special features such as power-down and
therefore have multi-programmable capabilities offering
wake-up functions, oscillator options, buzzer driver, etc.
the advantages of easy and efficient program updates.
These features combine to ensure applications require
The non-volatile internal EEPROM also offers the capa-
a minimum of external components and therefore re-
bility of storing information such as product part num-
duce overall product costs.
bers, calibration data and other specific product
Having the advantages of low-power consumption, information. etc. The devices are fully supported by the
high-performance, I/O flexibility as well as low-cost, Holtek range of fully functional development and pro-
these devices have the versatility to suit a wide range of gramming tools, providing a means for fast and efficient
application possibilities such as industrial control, con- product development cycles.
sumer products, subsystem controllers, etc. Many fea-

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 HT48F06E/HT48F10E/HT48F30E

Selection Table
The devices include a comprehensive range of features, with most features common to all devices. The main features
distinguishing them are Program Memory and Data Memory capacity, I/O count, stack size and package types. The
functional differences between the devices are shown in the following table.

Program Data Data 8-bit Interrupt Package

Part No. VDD I/O PFD Stack
Memory Memory EEPROM Timer Ext. Int. Types
16NSOP
HT48F06E 2.2V~5.5V 1K´14 64´8 128´8 13 1 1 1 Ö 2 18DIP/SOP,
20SSOP
HT48F10E 2.2V~5.5V 1K´14 64´8 128´8 19 1 1 1 Ö 4 24SKDIP/SOP
24SKDIP/SOP,
HT48F30E 2.2V~5.5V 2K´14 96´8 128´8 23 1 1 1 Ö 4
28SKDIP/SOP

Note: For devices that exist in more than one package formats, the table reflects the situation for the larger package.

Block Diagram

W a tc h d o g T im e r
F la s h P r o g r a m R A M D a ta In - c ir c u it R e s e t O s c illa to r
E E P R O M
M e m o ry M e m o ry P r o g r a m m in g C ir c u itr y C ir c u it
D a ta M e m o ry
W a tc h d o g
T im e r
8 - b it
R IS C C o re L o w V o lta g e
R e s e t

I/O 8 - b it P r o g r a m m a b le R C /C ry s ta l In te rru p t
S ta c k
P o rts T im e r F re q u e n c y G e n e ra to r O s c illa to r C o n tr o lle r

Pin Assignment
P A 3 1 2 0 P A 4
P A 3 1 1 8 P A 4 P A 2 2 1 9 P A 5
P A 3 1 1 6 P A 4 P A 2 2 1 7 P A 5 P A 1 3 1 8 P A 6
P A 2 2 1 5 P A 5 P A 1 3 1 6 P A 6 P A 0 4 1 7 P A 7
P A 1 3 1 4 P A 6 P A 0 4 1 5 P A 7 P B 2 5 1 6 O S C 2
P A 0 4 1 3 P A 7 P B 2 5 1 4 O S C 2 P B 1 /B Z 6 1 5 O S C 1
P B 0 /B Z 5 1 2 O S C 2 P B 1 /B Z 6 1 3 O S C 1 P B 0 /B Z 7 1 4 V D D
V S S 6 1 1 O S C 1 P B 0 /B Z 7 1 2 V D D V S S 8 1 3 R E S
P C 0 /IN T 7 1 0 V D D V S S 8 1 1 R E S P C 0 /IN T 9 1 2 P C 1 /T M R
P C 1 /T M R 8 9 R E S P C 0 /IN T 9 1 0 P C 1 /T M R N C 1 0 1 1 N C

H T 4 8 F 0 6 E H T 4 8 F 0 6 E H T 4 8 F 0 6 E
1 6 N S O P -A 1 8 D IP -A /S O P -A 2 0 S S O P -A

P B 5 1 2 8 P B 6
P B 4 2 2 7 P B 7
P B 5 1 2 4 P B 6 P B 5 1 2 4 P B 6 P A 3 3 2 6 P A 4
P B 4 2 2 3 P B 7 P B 4 2 2 3 P B 7 P A 2 4 2 5 P A 5
P A 3 3 2 2 P A 4 P A 3 3 2 2 P A 4 P A 1 5 2 4 P A 6
P A 2 4 2 1 P A 5 P A 2 4 2 1 P A 5 P A 0 6 2 3 P A 7
P A 1 5 2 0 P A 6 P A 1 5 2 0 P A 6 P B 3 7 2 2 O S C 2
P A 0 6 1 9 P A 7 P A 0 6 1 9 P A 7 P B 2 8 2 1 O S C 1
P B 3 7 1 8 O S C 2 P B 3 7 1 8 O S C 2 P B 1 /B Z 9 2 0 V D D
P B 2 8 1 7 O S C 1 P B 2 8 1 7 O S C 1 P B 0 /B Z 1 0 1 9 R E S
P B 1 /B Z 9 1 6 V D D P B 1 /B Z 9 1 6 V D D V S S 1 1 1 8 P C 5
P B 0 /B Z 1 0 1 5 R E S P B 0 /B Z 1 0 1 5 R E S P G 0 /IN T 1 2 1 7 P C 4
V S S 1 1 1 4 P C 2 V S S 1 1 1 4 P C 2 P C 0 /T M R 1 3 1 6 P C 3
P C 0 /IN T 1 2 1 3 P C 1 /T M R P G 0 /IN T 1 2 1 3 P C 0 /T M R P C 1 1 4 1 5 P C 2

H T 4 8 F 1 0 E H T 4 8 F 3 0 E H T 4 8 F 3 0 E
2 4 S K D IP -A /S O P -A 2 4 S K D IP -A /S O P -A 2 8 S K D IP -A /S O P -A

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Pin Description
HT48F06E
Pad Name I/O Options Description
Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up
Pull-high input by configuration option. Software instructions determine if the pin is a
PA0~PA7 I/O
Wake-up CMOS output or Schmitt Trigger input. A configuration option determines if all
pins on this port have pull-high resistors.
Bidirectional 3-bit input/output port. Software instructions determine if the pin
PB0/BZ
Pull-high is a CMOS output or Schmitt Trigger input. A configuration option determines
PB1/BZ I/O
I/O or BZ/BZ if all pins on this port have pull-high resistors. Pins PB0 and PB1 are
PB2
pin-shared with BZ and BZ, respectively.
Bidirectional 2-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. A configuration option determines
PC0/INT
I/O Pull-high if all pins on this port have pull-high resistors. PC0 is pin-shared with the ex-
PC1/TMR
ternal interrupt pin INT and PC1 is pin-shared with the external timer input pin
TMR.
OSC1, OSC2 are connected to an external RC network or external crystal,
OSC1 I determined by configuration option, for the internal system clock. If the RC
Crystal or RC
OSC2 O system clock option is selected, pin OSC2 can be used to measure the sys-
tem clock at 1/4 frequency.
RES I ¾ Schmitt trigger reset input. Active low.
VDD ¾ ¾ Positive power supply
VSS ¾ ¾ Negative power supply, ground.

Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is chosen for
a particular port, then all input pins on this port will be connected to pull-high resistors.
3. Pins PB1/BZ and PB2 do not exist on the 16-pin NSOP package type.

HT48F10E
Configuration
Pin Name I/O Description
Option
Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up
Pull-high input by configuration option. Software instructions determine if the pin is a
PA0~PA7 I/O Wake-up CMOS output or input. Configuration options determine if all pins on this port
Schmitt Trigger have pull-high resistors and if the inputs are Schmitt Trigger or non-Schmitt
Trigger.
Bidirectional 8-bit input/output port. Software instructions determine if the pin
PB0/BZ
Pull-high is a CMOS output or Schmitt Trigger input. A configuration option determines
PB1/BZ I/O
I/O or BZ/BZ if all pins on this port have pull-high resistors. Pins PB0 and PB1 are
PB2~PB7
pin-shared with BZ and BZ, respectively.
Bidirectional 3-bit input/output port. Software instructions determine if the pin is
PC0/INT
a CMOS output or Schmitt Trigger input. A configuration option determines if all
PC1/TMR I/O Pull-high
pins on this port have pull-high resistors. Pin PC0 is pin-shared with external in-
PC2
terrupt pin INT and PC1 shared with external timer pin TMR.
OSC1, OSC2 are connected to an external RC network or external crystal,
OSC1 I determined by configuration option, for the internal system clock. If the RC
Crystal or RC
OSC2 O system clock option is selected, pin OSC2 can be used to measure the sys-
tem clock at 1/4 frequency.
RES I ¾ Schmitt Trigger reset input. Active low.
VDD ¾ ¾ Positive power supply
VSS ¾ ¾ Negative power supply, ground

Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is chosen for
a particular port, then all input pins on this port will be connected to pull-high resistors.

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 HT48F06E/HT48F10E/HT48F30E

HT48F30E
Configuration
Pin Name I/O Description
Option
Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up
Pull-high input by configuration option. Software instructions determine if the pin is a
PA0~PA7 I/O Wake-up CMOS output or input. Configuration options determine if all pins on this port
Schmitt Trigger have pull-high resistors and if the inputs are Schmitt Trigger or non-Schmitt
Trigger.
Bidirectional 8-bit input/output port. Software instructions determine if the pin
PB0/BZ
Pull-high is a CMOS output or Schmitt Trigger input. A configuration option determines
PB1/BZ I/O
I/O or BZ/BZ if all pins on this port have pull-high resistors. Pins PB0 and PB1 are
PB2~PB7
pin-shared with BZ and BZ, respectively.
Bidirectional 6-bit input/output port. Software instructions determine if the pin
PC0/TMR is a CMOS output or Schmitt Trigger input. A configuration option determines
I/O Pull-high
PC1~PC5 if all pins on this port have pull-high resistors. PC0 is pin-shared with external
timer pin TMR.
Bidirectional 1-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. A configuration option determines
PG0/INT I/O Pull-high
if the pin has a pull-high resistor. PG0 is pin-shared with external interrupt pin
INT.
OSC1, OSC2 are connected to an external RC network or external crystal,
OSC1 I determined by configuration option, for the internal system clock. If the RC
Crystal or RC
OSC2 O system clock option is selected, pin OSC2 can be used to measure the sys-
tem clock at 1/4 frequency.
RES I ¾ Schmitt Trigger reset input. Active low.

VDD ¾ ¾ Positive power supply

VSS ¾ ¾ Negative power supply, ground

Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is chosen for
a particular port, then all input pins on this port will be connected to pull-high resistors.
3. Pins PC1 and PC3~PC5 only exist on the 28-pin package. On the 24-pin package, these pins are not
available.

Absolute Maximum Ratings

Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................150mA IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

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D.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

¾ fSYS=4MHz 2.2 ¾ 5.5 V

VDD Operating Voltage ¾ fSYS=8MHz 3.3 ¾ 5.5 V

¾ fSYS=12MHz 4.5 ¾ 5.5 V

3V ¾ 0.6 1.5 mA
IDD1 Operating Current (Crystal OSC) No load, fSYS=4MHz
5V ¾ 2 4 mA

3V ¾ 0.8 1.5 mA
IDD2 Operating Current (RC OSC) No load, fSYS=4MHz
5V ¾ 2.5 4 mA
Operating Current
IDD3 5V No load, fSYS=8MHz ¾ 4 8 mA
(Crystal OSC, RC OSC)
3V No load, ¾ ¾ 5 mA
ISTB1 Standby Current (WDT Enabled)
5V system HALT ¾ ¾ 10 mA
3V No load, ¾ ¾ 1 mA
ISTB2 Standby Current (WDT Disabled)
5V system HALT ¾ ¾ 2 mA
VIL1 Input Low Voltage for I/O Ports ¾ ¾ 0 ¾ 0.3VDD V
VIH1 Input High Voltage for I/O Ports ¾ ¾ 0.7VDD ¾ VDD V
VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V
VLVR Low Voltage Reset ¾ LVR enabled 2.7 3.0 3.3 V

3V 4 8 ¾ mA
IOL I/O Port Sink Current VOL=0.1VDD
5V 10 20 ¾ mA

3V -2 -4 ¾ mA
IOH I/O Port Source Current VOH=0.9VDD
5V -5 -10 ¾ mA

3V ¾ 20 60 100 kW
RPH Pull-high Resistance
5V ¾ 10 30 50 kW

A.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

¾ 2.2V~5.5V 400 ¾ 4000 kHz

System Clock
fSYS ¾ 3.3V~5.5V 400 ¾ 8000 kHz
(RC OSC, Crystal OSC)
¾ 4.5V~5.5V 400 ¾ 12000 kHz

¾ 2.2V~5.5V 0 ¾ 4000 kHz

fTIMER Timer I/P Frequency (TMR)
¾ 3.3V~5.5V 0 ¾ 8000 kHz

3V ¾ 45 90 180 ms
tWDTOSC Watchdog Oscillator Period
5V ¾ 32 65 130 ms

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Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

Watchdog Time-out Period 3V 11 23 46 ms

tWDT1 Without WDT prescaler
(WDT Internal Clock Source) 5V 8 17 33 ms
Watchdog Time-out Period
tWDT2 ¾ Without WDT prescaler ¾ 1024 ¾ *tSYS
(Instruction Clock Source)
tRES External Reset Low Pulse Width ¾ ¾ 1 ¾ ¾ ms
tSST System Start-up Timer Period ¾ Wake-up from HALT ¾ 1024 ¾ *tSYS

tLVR Low Voltage Reset Time ¾ ¾ 1 ¾ 2 ms

tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms

Note: *tSYS=1/fSYS

EEPROM - A.C. Characteristics Ta=25°C

VCC=5V±10% VCC=2.2V±10%
Symbol Parameter Unit
Min. Max. Min. Max.
fSK Clock Frequency 0 2 0 1 MHz
tSKH SK High Time 250 ¾ 500 ¾ ns
tSKL SK Low Time 250 ¾ 500 ¾ ns
tCSS CS Setup Time 50 ¾ 100 ¾ ns
tCSH CS Hold Time 0 ¾ 0 ¾ ns
tCDS CS Deselect Time 250 ¾ 250 ¾ ns
tDIS DI Setup Time 100 ¾ 200 ¾ ns
tDIH DI Hold Time 100 ¾ 200 ¾ ns
tPD1 DO Delay to ²1² ¾ 250 ¾ 500 ns
tPD0 DO Delay to ²0² ¾ 250 ¾ 500 ns
tSV Status Valid Time ¾ 250 ¾ 250 ns
tPR Write Cycle Time Per Word ¾ 2 ¾ 5 ms

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System Architecture
A key factor in the high-performance features of the Program Counter is incremented at the beginning of the
Holtek range of microcontrollers is attributed to the inter- T1 clock during which time a new instruction is fetched.
nal system architecture. The range of devices take ad- The remaining T2~T4 clocks carry out the decoding and
vantage of the usual features found within RISC execution functions. In this way, one T1~T4 clock cycle
microcontrollers providing increased speed of operation forms one instruction cycle. Although the fetching and
and enhanced performance. The pipelining scheme is execution of instructions takes place in consecutive in-
implemented in such a way that instruction fetching and struction cycles, the pipelining structure of the
instruction execution are overlapped, hence instructions microcontroller ensures that instructions are effectively
are effectively executed in one cycle, with the exception executed in one instruction cycle. The exception to this
of branch or call instructions. An 8-bit wide ALU is used are instructions where the contents of the Program
in practically all operations of the instruction set. It car- Counter are changed, such as subroutine calls or
ries out arithmetic operations, logic operations, rotation, jumps, in which case the instruction will take one more
increment, decrement, branch decisions, etc. The inter- instruction cycle to execute.
nal data path is simplified by moving data through the
When the RC oscillator is used, OSC2 is freed for use as
Accumulator and the ALU. Certain internal registers are
a T1 phase clock synchronizing pin. This T1 phase clock
implemented in the Data Memory and can be directly or
has a frequency of fSYS/4 with a 1:3 high/low duty cycle.
indirectly addressed. The simple addressing methods of
these registers along with additional architectural fea- For instructions involving branches, such as jump or call
tures ensure that a minimum of external components is instructions, two machine cycles are required to com-
required to provide a functional I/O control system with plete instruction execution. An extra cycle is required as
maximum reliability and flexibility. the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
Clocking and Pipelining execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
The main system clock, derived from either a Crys-
sensitive applications
tal/Resonator or RC oscillator is subdivided into four in-
ternally generated non-overlapping clocks, T1~T4. The

O s c illa to r C lo c k
( S y s te m C lo c k )

P h a s e C lo c k T 1

P h a s e C lo c k T 2

P h a s e C lo c k T 3

P h a s e C lo c k T 4

P ro g ra m C o u n te r P C P C + 1 P C + 2

F e tc h In s t. (P C )
P ip e lin in g
E x e c u te In s t. (P C -1 ) F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C ) F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )

System Clocking and Pipelining

1 M O V A ,[1 2 H ] F e tc h In s t. 1 E x e c u te In s t. 1
2 C A L L D E L A Y F e tc h In s t. 2 E x e c u te In s t. 2
3 C P L [1 2 H ] F e tc h In s t. 3 F lu s h P ip e lin e
4 : F e tc h In s t. 6 E x e c u te In s t. 6
5 : F e tc h In s t. 7
6 D E L A Y : N O P

Instruction Fetching

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 HT48F06E/HT48F10E/HT48F30E

Program Counter The lower byte of the Program Counter is fully accessi-
During program execution, the Program Counter is used ble under program control. Manipulating the PCL might
to keep track of the address of the next instruction to be cause program branching, so an extra cycle is needed
executed. It is automatically incremented by one each to pre-fetch. Further information on the PCL register can
time an instruction is executed except for instructions, be found in the Special Function Register section.
such as ²JMP² or ²CALL², that demand a jump to a
Stack
non-consecutive Program Memory address. Note that
the Program Counter width varies with the Program This is a special part of the memory which is used to
Memory capacity depending upon which device is se- save the contents of the Program Counter only. The
lected. However, it must be noted that only the lower 8 stack can have either 2 or 4 levels depending upon
bits, known as the Program Counter Low Register, are which device is selected and is neither part of the data
directly addressable by user. nor part of the program space, and can neither be read
from nor written to. The activated level is indexed by the
When executing instructions requiring jumps to
Stack Pointer, SP, which can also neither be read from
non-consecutive addresses such as a jump instruction,
nor written to. At a subroutine call or interrupt acknowl-
a subroutine call, interrupt or reset, etc., the
edge signal, the contents of the Program Counter are
microcontroller manages program control by loading the
pushed onto the stack. At the end of a subroutine or an
required address into the Program Counter. For condi-
interrupt routine, signaled by a return instruction, RET or
tional skip instructions, once the condition has been
RETI, the Program Counter is restored to its previous
met, the next instruction, which has already been
value from the stack. After a device reset, the Stack
fetched during the present instruction execution, is dis-
Pointer will point to the top of the stack.
carded and a dummy cycle takes its place while the cor-
rect instruction is obtained. If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the ac-
The lower byte of the Program Counter, known as the
knowledge signal will be inhibited. When the Stack
Program Counter Low register or PCL, is available for
Pointer is decremented, by RET or RETI, the interrupt
program control and is a readable and writable register.
will be serviced. This feature prevents stack overflow al-
By transferring data directly into this register, a short
lowing the programmer to use the structure more easily.
program jump can be executed directly, however, as
However, when the stack is full, a CALL subroutine in-
only this low byte is available for manipulation, the
struction can still be executed which will result in a stack
jumps are limited to the present page of memory, that is
overflow. Precautions should be taken to avoid such
256 locations. When such program jumps are executed
cases which might cause unpredictable program
it should also be noted that a dummy cycle will be in-
branching.
serted.

Program Counter Bits

Mode
b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Initial Reset 0 0 0 0 0 0 0 0 0 0 0
External Interrupt 0 0 0 0 0 0 0 0 1 0 0
Timer/Event Counter
0 0 0 0 0 0 0 1 0 0 0
Overflow
Skip Program Counter + 2
Loading PCL PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: PC10~PC8: Current Program Counter bits

@7~@0: PCL bits
#10~#0: Instruction code address bits
S10~S0: Stack register bits
For the HT48F10E and the HT48F06E, since their Program Counter is 10 bits wide, the b10 column in the table
is not applicable.

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P ro g ra m C o u n te r Flash Program Memory

The Program Memory is the location where the user
S ta c k L e v e l 1 code or program is stored. For these devices the Pro-
gram Memory is a Flash type, which means it can be
S ta c k S ta c k L e v e l 2 P ro g ra m programmed and reprogrammed a large number of
P o in te r S ta c k L e v e l 3 M e m o ry
times, allowing the user the convenience of code modifi-
S ta c k L e v e l 4 cation using the same device. By using the appropriate
programming tools, these devices offer users the flexi-
bility to conveniently debug and develop their applica-
Note: 1. For the HT48F06E, N=2, i.e. 2 levels of stack
tions while also offering a means of field programming.
available.
2. For the HT48F10E and HT48F30E, N=4,
Organization
i.e. 4 levels of stack available.
The Program Memory has a capacity of 1K by 14 or 2K
Arithmetic and Logic Unit - ALU by 14 bits depending upon which device is selected. The
Program Memory is addressed by the Program Counter
The arithmetic-logic unit or ALU is a critical area of the
and also contains data, table information and interrupt
microcontroller that carries out arithmetic and logic op-
entries. Table data, which can be setup in any location
erations of the instruction set. Connected to the main
within the Program Memory, is addressed by a separate
microcontroller data bus, the ALU receives related in-
table pointer register.
struction codes and performs the required arithmetic or
logical operations after which the result will be placed in Special Vectors
the specified register. As these ALU calculation or oper-
ations may result in carry, borrow or other status Within the Program Memory, certain locations are re-
changes, the status register will be correspondingly up- served for special usage such as reset and interrupts.
dated to reflect these changes. The ALU supports the · Location 000H
following functions: This vector is reserved for use by the device reset for
· Arithmetic operations ADD, ADDM, ADC, ADCM, program initialisation. After a device reset is initiated, the
SUB, SUBM, SBC, SBCM, DAA program will jump to this location and begin execution.
· Logic operations AND, OR, XOR, ANDM, ORM, · Location 004H
XORM, CPL, CPLA This vector is used by the external interrupt. If the ex-
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, ternal interrupt pin on the device goes low, the pro-
RLC gram will jump to this location and begin execution if
the external interrupt is enabled and the stack is not
· Increment and Decrement INCA, INC, DECA, DEC
full.
· Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA,
SDZA, CALL, RET, RETI

H T 4 8 F 0 6 E
H T 4 8 F 1 0 E H T 4 8 F 3 0 E
0 0 0 H
In itia lis a tio n In itia lis a tio n
V e c to r V e c to r
0 0 4 H
E x te rn a l E x te rn a l
In te rru p t V e c to r In te rru p t V e c to r
0 0 8 H
T im e r /E v e n t C o u n te r T im e r /E v e n t C o u n te r
In te rru p t V e c to r In te rru p t V e c to r
0 0 C H

0 1 0 H

0 1 4 H

0 1 8 H

3 F F H
4 0 0 H
N o t Im p le m e n te d
7 F F H
1 4 b its 1 4 b its

Program Memory Structure

Rev. 1.00 9 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

· Location 008H The following diagram illustrates the addressing/data

This internal vector is used by the Timer/Event Coun- flow of the look-up table:
ter. If a counter overflow occurs, the program will jump
P ro g ra m C o u n te r
to this location and begin execution if the timer/event H ig h B y te P ro g ra m
counter interrupt is enabled and the stack is not full. M e m o ry
T B L P

Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed T B L H S p e c ifie d b y [m ]
data. To use the look-up table, the table pointer must H ig h B y te o f T a b le C o n te n ts L o w B y te o f T a b le C o n te n ts
first be setup by placing the lower order address of the
Look-up Table
look up data to be retrieved in the table pointer register,
TBLP. This register defines the lower 8-bit address of
the look-up table. Table Program Example

After setting up the table pointer, the table data can be The following example shows how the table pointer and
retrieved from the current Program Memory page or last table data is defined and retrieved from the HT48F06E
or HT48F10E devices. This example uses raw table
Program Memory page using the ²TABRDC[m]² or
data located in the last page which is stored there using
²TABRDL [m]² instructions, respectively. When these in-
the ORG statement. The value at this ORG statement is
structions are executed, the lower order table byte from
²300H² which refers to the start address of the last page
the Program Memory will be transferred to the user de-
within the 1K Program Memory of the microcontroller.
fined Data Memory register [m] as specified in the in-
The table pointer is setup here to have an initial value of
struction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special ²06H². This will ensure that the first data read from the
register. Any unused bits in this transferred higher order data table will be at the Program Memory address
byte will have uncertain values. ²306H² or 6 locations after the start of the last page.
Note that the value for the table pointer is referenced to
the first address of the present page if the ²TABRDC
[m]² instruction is being used. The high byte of the table
data which in this case is equal to zero will be trans-
ferred to the TBLH register automatically when the
²TABRDL [m]² instruction is executed.

tempreg1 db ? ; temporary register #1

tempreg2 db ? ; temporary register #2
:
:
mov a,06h ; initialise table pointer - note that this address
; is referenced
mov tblp,a ; to the last page or present page
:
:
tabrdl tempreg1 ; transfers value in table referenced by table pointer
; to tempregl
; data at prog. memory address ²306H² transferred to
; tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one

tabrdl tempreg2 ; transfers value in table referenced by table pointer

; to tempreg2
; data at prog.memory address ²305H² transferred to
; tempreg2 and TBLH
; in this example the data ²1AH² is transferred to
; tempreg1 and data ²0FH² to register tempreg2
; the value ²0FH² will be transferred to the high byte
; register TBLH
:
:
org 300h ; sets initial address of HT48F06E or HT48F10E last page

dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

:
:

Rev. 1.00 10 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Because the TBLH register is a read-only register and in-circuit programming of the devices are beyond the
cannot be restored, care should be taken to ensure its scope of this document and will be supplied in supple-
protection if both the main routine and Interrupt Service mentary literature.
Routine use table read instructions. If using the table
C o n n e c to r
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause P o w e r V D D

errors if used again by the main routine. As a rule it is G ro u n d V S S

recommended that simultaneous use of the table read D a ta P A 0
instructions should be avoided. However, in situations
C lo c k P A 4
where simultaneous use cannot be avoided, the inter-
rupts should be disabled prior to the execution of any R e s e t R E S
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to In-circuit Programming Interface
complete their operation.

RAM Data Memory

In Circuit Programming
The RAM Data Memory is a volatile area of 8-bit wide
The provision of Flash type Program Memory gives the
RAM internal memory and is the location where tempo-
user and designer the convenience of easy upgrades
rary information is stored. Divided into two sections, the
and modifications to their programs on the same device.
first of these is an area of RAM where special function
As an additional convenience, Holtek has provided a
registers are located. These registers have fixed loca-
means of programming the microcontroller in-circuit.
tions and are necessary for correct operation of the de-
This provides manufacturers with the possibility of man-
vice. Many of these registers can be read from and
ufacturing their circuit boards complete with a pro-
written to directly under program control, however,
grammed or un-programmed microcontroller, and then
some remain protected from user manipulation. The
programming or upgrading the program at a later stage.
second area of RAM Data Memory is reserved for gen-
This enables product manufacturers to easily keep their
eral purpose use. All locations within this area are read
manufactured products supplied with the latest program
and write accessible under program control.
releases without removal and re-insertion of the device.
Pin Name Function Organization
PA0 Serial data input/output The RAM Data Memory is subdivided into two banks,
known as Bank 0 and Bank 1, all of which are imple-
PA4 Serial clock
mented in 8-bit wide RAM. Most of the RAM Data Mem-
RES Device reset ory is located in Bank 0 which is also subdivided into two
VDD Power supply sections, the Special Purpose Data Memory and the
General Purpose Data Memory. The length of these
VSS Ground
sections is dictated by the type of microcontroller cho-
sen. The start address of the RAM Data Memory for all
The Program Memory and EEPROM memory can both
be programmed serially in-circuit using a 5-wire inter- devices is the address ²00H², and the last Data Memory
face. Data is downloaded and uploaded serially on a address is ²7FH². Registers which are common to all
single pin with an additional line for the clock. Two addi- microcontrollers, such as ACC, PCL, etc., have the
tional lines are required for the power supply and one same Data Memory address.
line for the reset. The technical details regarding the

Table Location Bits

Instruction
b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TABRDC [m] PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table Location

Note: PC10~PC8: Current Program Counter bits

@7~@0: Table Pointer TBLP bits
For the HT48F30E, the Table address location is 11 bits, i.e. from b10~b0.
For the HT48F10E and the HT48F06E, the Table address location is 10 bits, i.e. from b9~b0.

Rev. 1.00 11 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

H T 4 8 F 0 6 E Special Purpose Data Memory

H T 4 8 F 1 0 E H T 4 8 F 3 0 E
0 0 H 0 0 H This area of Data Memory, is located in Bank 0, where
S p e c ia l P u r p o s e S p e c ia l P u r p o s e registers, necessary for the correct operation of the
D a ta M e m o ry D a ta M e m o ry
1 7 H microcontroller, are stored. Most of the registers are
1 F H
2 0 H both readable and writable but some are protected and
are readable only, the details of which are located under
4 0 H G e n e ra l P u rp o s e the relevant Special Function Register section. Note
G e n e ra l P u rp o s e D a ta M e m o ry
(9 6 B y te s )
that for locations that are unused, any read instruction to
D a ta M e m o ry
(6 4 B y te s ) these addresses will return the value ²00H². Although
7 F H 7 F H the Special Purpose Data Memory registers are located
: U n u s e d , re a d a s "0 0 " in Bank 0, they will still be accessible even if the Bank
Pointer has selected Bank 1.
Bank 0 RAM Data Memory Structure
H T 4 8 F 0 6 E
H T 4 8 F 1 0 E H T 4 8 F 3 0 E
Bank 1 of the RAM Data Memory contains only one spe- 0 0 H IA R 0 IA R 0
cial function register, known as the EECR register, 0 1 H M P 0 M P 0
0 2 H IA R 1 IA R 1
which is used for EEPROM control and located at ad-
0 3 H M P 1 M P 1
dress ²40H² for all devices. 0 4 H B P B P
0 5 H A C C A C C
4 0 H E E C R 0 6 H P C L P C L
0 7 H T B L P T B L P
Bank 1 RAM Data Memory Structure 0 8 H T B L H T B L H
0 9 H W D T S W D T S
Note: 0 A H S T A T U S S T A T U S
Most of the RAM Data Memory bits can be di- 0 B H IN T C IN T C
rectly manipulated using the ²SET [m].i² and 0 C H
0 D H T M R T M R
²CLR [m].i² instructions with the exception of a
0 E H T M R C T M R C
few dedicated bits. The RAM Data Memory can 0 F H
also be accessed through the Memory Pointer 1 0 H
registers MP0 and MP1. 1 1 H
1 2 H P A P A
1 3 H P A C P A C
General Purpose Data Memory 1 4 H P B P B
1 5 H P B C P B C
All microcontroller programs require an area of 1 6 H P C P C
read/write memory where temporary data can be stored 1 7 H P C C P C C
and retrieved for use later. It is this area of RAM memory 1 8 H
1 9 H
that is known as General Purpose Data Memory. This
1 A H
area of Data Memory is fully accessible by the user pro- 1 B H
gram for both read and write operations. By using the 1 C H
1 D H
²SET [m].i² and ²CLR [m].i² instructions individual bits
1 E H P G
can be set or reset under program control giving the 1 F H P G C
user a large range of flexibility for bit manipulation in the : U n u s e d , re a d a s "0 0 "
Data Memory.
Special Purpose Data Memory Structure

Rev. 1.00 12 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Special Function Registers

To ensure successful operation of the microcontroller, sponding Memory Pointer, MP0 or MP1. Acting as a
certain internal registers are implemented in the RAM pair, IAR0 and MP0 can together only access data from
Data Memory area. These registers ensure correct op- Bank 0, while the IAR1 and MP1 register pair can ac-
eration of internal functions such as timers, interrupts, cess data from both Bank 0 and Bank 1. As the Indirect
watchdog, etc., as well as external functions such as I/O Addressing Registers are not physically implemented,
data control. The location of these registers within the reading the Indirect Addressing Registers indirectly will
RAM Data Memory begins at the address ²00H². Any return a result of ²00H² and writing to the registers indi-
unused Data Memory locations between these special rectly will result in no operation.
function registers and the point where the General Pur-
pose Memory begins is reserved for future expansion Memory Pointer - MP0, MP1
purposes, attempting to read data from these locations For all devices, two Memory Pointers, known as MP0
will return a value of ²00H². and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be
Indirect Addressing Register - IAR0, IAR1 manipulated in the same way as normal registers pro-
The Indirect Addressing Registers, IAR0 and IAR1, al- viding a convenient way with which to address and track
though having their locations in normal RAM register data. When any operation to the relevant Indirect Ad-
space, do not actually physically exist as normal regis- dressing Registers is carried out, the actual address that
ters. The method of indirect addressing for RAM data the microcontroller is directed to, is the address speci-
manipulation uses these Indirect Addressing Registers fied by the related Memory Pointer. MP0, together with
and Memory Pointers, in contrast to direct memory ad- Indirect Addressing Register, IAR0, are used to access
dressing, where the actual memory address is speci- data from Bank 0 only, while MP1 and IAR1 are used to
fied. Actions on the IAR0 and IAR1 registers will result in access data from both Bank 0 and Bank 1. Note that bit
no actual read or write operation to these registers but 7 of the Memory Pointers is not required to address the
rather to the memory location specified by their corre- full memory space and will return a value of ²1² if read.

The following example shows how to clear a section of four RAM locations already defined as locations adres1 to
adres4.
data .section ¢data¢
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ¢code¢
org 00h
start:
mov a,04h ; setup size of block
mov block,a
mov a,offset adres1; Accumulator loaded with first RAM address
mov mp0,a ; setup memory pointer with first RAM address
loop:
clr IAR0 ; clear the data at address defined by MP0
inc mp0 ; increment memory pointer
sdz block ; check if last memory location has been cleared
jmp loop
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.

Rev. 1.00 13 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Bank Pointer - BP another, it is necessary to do this by passing the data

The RAM Data Memory is divided into two Banks, through the Accumulator as no direct transfer between
known as Bank 0 and Bank 1. With the exception of the two registers is permitted.
EECR register, all of the Special Purpose Registers and
Program Counter Low Register - PCL
General Purpose Registers are contained in Bank 0.
Bank 1 contains only one register, which is the To provide additional program control functions, the low
EEPROM Control Register, known as EECR. Selecting byte of the Program Counter is made accessible to pro-
the required Data Memory area is achieved using the grammers by locating it within the Special Purpose area
Bank Pointer. If data in Bank 0 is to be accessed, then of the Data Memory. By manipulating this register, direct
the BP register must be loaded with the value ²00², jumps to other program locations are easily imple-
while if data in Bank 1 is to be accessed, then the BP mented. Loading a value directly into this PCL register
register must be loaded with the value ²01². will cause a jump to the specified Program Memory lo-
cation, however, as the register is only 8-bit wide, only
Using Memory Pointer MP0 and Indirect Addressing
jumps within the current Program Memory page are per-
Register IAR0 will always access data from Bank 0, irre-
mitted. When such operations are used, note that a
spective of the value of the Bank Pointer. The EECR
dummy cycle will be inserted.
register is located at memory location 40H in Bank 1 and
can only be accessed indirectly using memory pointer Look-up Table Registers - TBLP, TBLH
MP1 and the indirect addressing register, IAR1, after the
These two special function registers are used to control
BP register has first been loaded with the value ²01².
operation of the look-up table which is stored in the Pro-
Data can only be read from or written to the EEPROM
gram Memory. TBLP is the table pointer and indicates
via this register.
the location where the table data is located. Its value
The Data Memory is initialised to Bank 0 after a reset, must be setup before any table read commands are ex-
except for the WDT time-out reset in the Power Down ecuted. Its value can be changed, for example using the
Mode, in which case, the Data Memory bank remains ²INC² or ²DEC² instructions, allowing for easy table data
unaffected. It should be noted that Special Function pointing and reading. TBLH is the location where the
Data Memory is not affected by the bank selection, high order byte of the table data is stored after a table
which means that the Special Function Registers can be read data instruction has been executed. Note that the
accessed from within either Bank 0 or Bank 1. Directly lower order table data byte is transferred to a user de-
addressing the Data Memory will always result in Bank 0 fined location.
being accessed irrespective of the value of the Bank
Pointer. Watchdog Timer Register - WDTS

Accumulator - ACC The Watchdog feature of the microcontroller provides

an automatic reset function giving the microcontroller a
The Accumulator is central to the operation of any means of protection against spurious jumps to incorrect
microcontroller and is closely related with operations Program Memory addresses. To implement this, a timer
carried out by the ALU. The Accumulator is the place is provided within the microcontroller which will issue a
where all intermediate results from the ALU are stored. reset command when its value overflows. To provide
Without the Accumulator it would be necessary to write variable Watchdog Timer reset times, the Watchdog
the result of each calculation or logical operation such Timer clock source can be divided by various division ra-
as addition, subtraction, shift, etc., to the Data Memory tios, the value of which is set using the WDTS register.
resulting in higher programming and timing overheads. By writing directly to this register, the appropriate divi-
Data transfer operations usually involve the temporary sion ratio for the Watchdog Timer clock source can be
storage function of the Accumulator; for example, when setup. Note that only the lower 3 bits are used to set divi-
transferring data between one user defined register and sion ratios between 1 and 128.

b 7 b 0
B P 0 B a n k P o in te r

B P 0 D a ta M e m o ry
0 B a n k 0
1 B a n k 1
N o t u s e d , m u s t b e re s e t to "0 "

Rev. 1.00 14 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Status Register - STATUS

· TO is cleared by a system power-up or executing the
This 8-bit register contains the zero flag (Z), carry flag ²CLR WDT² or ²HALT² instruction. TO is set by a
(C), auxiliary carry flag (AC), overflow flag (OV), power WDT time-out.
down flag (PDF), and watchdog time-out flag (TO). In addition, on entering an interrupt sequence or execut-
These arithmetic/logical operation and system manage- ing a subroutine call, the status register will not be
ment flags are used to record the status and operation of pushed onto the stack automatically. If the contents of
the microcontroller. the status registers are important and if the subroutine
With the exception of the TO and PDF flags, bits in the can corrupt the status register, precautions must be
status register can be altered by instructions like most taken to correctly save it.
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, opera- Interrupt Control Register - INTC
tions related to the status register may give different re- This 8-bit register, known as the INTC register, controls
sults due to the different instruction operations. The TO the operation of both external and internal timer inter-
flag can be affected only by a system power-up, a WDT rupts. By setting various bits within this register using
time-out or by executing the ²CLR WDT² or ²HALT² in- standard bit manipulation instructions, the enable/dis-
struction. The PDF flag is affected only by executing the able function of the external and timer interrupts can be
²HALT² or ²CLR WDT² instruction or during a system independently controlled. A master interrupt bit within
power-up. this register, the EMI bit, acts like a global enable/dis-
The Z, OV, AC and C flags generally reflect the status of able and is used to set all of the interrupt enable bits on
the latest operations. or off. This bit is cleared when an interrupt routine is en-
tered to disable further interrupt and is set by executing
· C is set if an operation results in a carry during an ad-
the ²RETI² instruction.
dition operation or if a borrow does not take place dur-
ing a subtraction operation; otherwise C is cleared. C Note: In situations where other interrupts may require
is also affected by a rotate through carry instruction. servicing within present interrupt service rou-
tines, the EMI bit can be manually set by the
· AC is set if an operation results in a carry out of the
program after the present interrupt service rou-
low nibbles in addition, or no borrow from the high nib-
tine has been entered.
ble into the low nibble in subtraction; otherwise AC is
cleared.
Timer/Event Counter Registers
· Z is set if the result of an arithmetic or logical operation
Each device contains an 8-bit Timer/Event Counter,
is zero; otherwise Z is cleared.
which has an associated register known as TMR, and is
· OV is set if an operation results in a carry into the high- the location where the timer¢s 8-bit value is located. An
est-order bit but not a carry out of the highest-order bit, associated control register, known as TMRC, contains
or vice versa; otherwise OV is cleared. the setup information for the timer.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.

b 7 b 0
T O P D F O V Z A C C S T A T U S R e g is te r

A r ith m e tic /L o g ic O p e r a tio n F la g s

C a r r y fla g
A u x ilia r y c a r r y fla g
Z e r o fla g
O v e r flo w fla g

S y s te m M a n a g e m e n t F la g s
P o w e r d o w n fla g
W a tc h d o g tim e - o u t fla g
N o t im p le m e n te d , re a d a s "0 "

Status Register

Rev. 1.00 15 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Input/Output Ports and Control Registers storage allows information such as product identification
Within the area of Special Function Registers, the I/O numbers, calibration values, specific user data, system
registers and their associated control registers play a setup data or other product information to be stored di-
prominent role. All I/O ports have a designated register rectly within the product microcontroller.
correspondingly labeled as PA, PB, PC, etc. These la-
EEPROM Data Memory Structure
beled I/O registers are mapped to specific addresses
within the Data Memory as shown in the Data Memory The internal EEPROM Data Memory has a capacity of
table, which are used to transfer the appropriate output 128´8 bits. Unlike the Program Memory and RAM Data
or input data on that port. with each I/O port there is an Memory, the EEPROM Data Memory is not directly
associated control register labeled PAC, PBC, PCC, mapped and is therefore not directly accessible in the
etc., also mapped to specific addresses with the Data same way as the other types of memory. Instead it has
Memory. The control register specifies which pins of that to be accessed indirectly through the EEPROM Control
port are set as inputs and which are set as outputs. To Register.
setup a pin as an input, the corresponding bit of the con-
trol register must be set high, for an output it must be set Accessing the EEPROM Data Memory
low. During program initialization, it is important to first The EEPROM Data Memory is accessed using a set of
setup the control registers to specify which pins are out- seven instructions. These instructions control all func-
puts and which are inputs before reading data from or tions of the EEPROM such as read, write, erase, enable
writing data to the I/O ports. One flexible feature of these etc. The internal EEPROM structure is similar to that of a
registers is the ability to directly program single bits us- standard 3-wire EEPROM, for which four pins are used
ing the ²SET [m].i² and ²CLR [m].i² instructions. The for transfer of instruction, address and data information.
ability to change I/O pins from output to input and vice These are the Chip Select pin, CS, Serial Clock pin, SK,
versa by manipulating specific bits of the I/O control reg- Data In pin, DI and the Data Out pin, DO. All actions re-
isters during normal program operation is a useful fea- lated to the EEPROM must be conducted through the
ture of these devices. EECR register which is located in Bank 1 of the RAM
Data Memory, in which each of these four EEPROM
EEPROM Control Register - EECR pins is represented by a bit in the EECR register. By ma-
This register is used to control all operations to and from nipulating these four bits in the EECR register, in accor-
the EEPROM Data Memory. As the EEPROM Data dance with the accompanying timing diagrams, the
Memory is not mapped like the other memory types, all microcontroller can communicate with the EEPROM
data to and from the EEPROM must be made through and carry out the required functions, such as reading
this register. The EECR register is located in Bank 1 of and writing data.
the Data Memory, so before use the Bank Pointer must Bit No. Label EEPROM Function
be setup to a value of ²1². The EECR register can only
be read and written to indirectly using the MP1 address
0~3 ¾ Not implemented bit, read as ²0²
pointer. 4 CS EEPROM Data Memory select
Serial Clock: Used to clock data
5 SK
EEPROM Data Memory into and out of the EEPROM

One of the special features within all these devices is Data Input: Instructions, address
6 DI and data information are written to
their internal EEPROM Data Memory. EEPROM, which
the EEPROM on this pin
stands for Electrically Erasable Programmable Read
Only Memory, is by its nature a non-volatile form of Data Output: Data from the
memory, with data retention even when its power supply EEPROM is readout with this bit.
7 DO
Will be in a high-impedance con-
is removed. By incorporating this kind of data memory a
dition if no data is being read.
whole new host of application possibilities are made
available to the designer. The availability of EEPROM EECR Register - Control Bit Functions

b 7 b 0
D O D I S K C S E E C R

N o t im p le m e n te d , re a d a s "0 "
E E P R O M D a ta M e m o r y S e le c t
E E P R O M S e r ia l C lo c k In p u t
E E P R O M S e r ia l D a ta In p u t
E E P R O M S e r ia l D a ta O u tp u t
EEPROM Control Register

Rev. 1.00 16 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

When reading data from the EEPROM, the data will The related instruction is transmitted to the EEPROM
clocked out on the rising edge of SK and appear on DO. via the DI bit, after CS has first been set to ²1² to enable
The DO pin will normally be in a high-impedance condi- the EEPROM and a start bit ²1² has been transmitted.
tion unless a READ statement is being executed. When For the READ, WRITE and ERASE instructions, each of
writing to the EEPROM the data must be presented first the three instructions has its own two bit related instruc-
on DI and then clocked in on the rising edge of SK. After tion code. The 7-bit address should then be transmitted.
all the instruction, address and data information has The address is transmitted in MSB first format.
been transmitted, CS should be cleared to ²0² to termi-
For the other four instructions, ²EWEN², ²EWDS²,
nate the instruction transmission. Note that after power
²ERAL² and ²WRAL², after the start bit has been trans-
on the EEPROM must be initialised as described.
mitted a ²00² instruction code should then follow. The
As indirect addressing is the only way to access the 7-bit address information should then follow. The first
EECR register, all read and write operations to this reg- two bits of this address is instruction dependant as
ister must take place using the Indirect Addressing Reg-
shown in the table while the remaining bits have don¢t
ister, IAR1, and the Memory Pointer, MP1. Because the
care values and can be either high or low.
EECR control register is located in Bank 1 of the RAM
Data Memory at location 40H, the MP1 Memory Pointer After any write or erase instruction is issued, the internal
must first be set to the value 40H and the Bank Pointer write function of the EEPROM will be used to write the
set to ²1². data into the device. As this internal write operation uses
the EEPROM¢s own internal clock, no further instruc-
EEPROM Data Memory Instruction Set tions will be accepted by the EEPROM until the internal
write function has ended. After power on and before any
Control over the internal EEPROM, to execute functions
instruction is issued the EEPROM must be properly in-
such as read, write, disable, enable etc., is implemented
itialised to ensure proper operation.
through instructions of which there are a total of seven.

tC S S
C S tC D S

tS K H tS K L
tC S H
S K
tD IS
t D IH
D I V a lid D a ta V a lid D a ta

tP D 0 tP D 1

D O
1

Clocking Data In and Out of the EEPROM

Instruction
Instruction Function Start Bit Address Data
Code
READ Read Out Data Byte(s) 1 10 A6~A0 D7~D0
ERASE Erase Single Data Byte 1 11 A6~A0 ¾
WRITE Write Single Data Byte 1 01 A6~A0 D7~D0
EWEN Erase/Write Enable 1 00 11 XXXXX ¾
EWDS Erase/Write Disable 1 00 00 XXXXX ¾
ERAL Erase All 1 00 10 XXXXX ¾
WRAL Write All 1 00 01 XXXXX ¾

Instruction Set Summary

Rev. 1.00 17 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

READ WRITE
The ²READ² instruction is used to read out one or more The ²WRITE² instruction is used to write a single byte of
bytes of data from the EEPROM Data Memory. To insti- data into the EEPROM. To instigate a WRITE instruc-
gate a ²READ² instruction, the CS bit should be set high, tion, the CS bit should be set high, followed by a high
followed by a high start bit and then the instruction code start bit and then the instruction code ²01², all transmit-
²10², all transmitted via the DI bit. The address informa- ted via the DI bit. The address information should then
tion should then follow with the MSB being transmitted follow with the MSB bit being transmitted first. After the
first. After the last address bit, A0, has been transmitted, last address bit, A0, has been transmitted, the data can
the data can be clocked out, bit D7 first, on the rising be immediately transmitted MSB first. After all the
edge of the SK clock signal and can be read via the DO WRITE instruction code, address and data have been
bit. However, a dummy ²0² bit will first precede the read- transmitted, the data will be written into the EEPROM
ing of the first data bit, D7. After the full byte has been when the CS bit is cleared to zero. The EEPROM does
read out, the internal address will be automatically incre- this by executing an internal write-cycle, which will first
mented allowing the next consecutive data byte to be erase and then write the previously transmitted data
read out without entering further address data. As long byte into the EEPROM. This process takes place inter-
as the CS bit remains high, data bit D7 of the next ad- nally using the EEPROM¢s own internal clock and does
dress will automatically follow data bit D0 of the previous not require any action from the SK clock. No further in-
address with no dummy ²0² being inserted between structions can be accepted by the EEPROM until this in-
them. The address will keep incrementing in this way ternal write-cycle has finished. To determine when the
until CS returns to a low value. DO will normally be in a write cycle has ended, CS should be again brought high
high impedance condition until the ²READ² instruction is and the DO bit polled. If DO is low this indicates that the
executed. Note that as the ²READ² instruction is not af- internal write-cycle is still in progress, however, the DO
bit will change to a high value when the internal
fected by the condition of the ²EWEN² or ²EWDS² in-
struction, the READ command is always valid and write-cycle has ended. Before a ²WRITE² instruction is
independent of these two instructions. transmitted an ²EWEN² instruction must have been
transmitted at some point earlier to ensure that the
erase/write function of the EEPROM is enabled.

tC D S
C S

S K

D I 1 1 0 A 6 A 0
S ta r t b it

D O 1 0 D 7 D 0 D 7 1

T h e a d d r e s s is a u to m a tic a lly in c r e m e n te d a t th is p o in t.

READ Timing

tC D S

C S V e r ify S ta n d b y

S K

D I 1 0 1 A 6 A 5 A 4 A 1 A 0 D 7 D 0
S ta r t b it tS V
1
B u s y
D O R e a d y
tP R

WRITE Timing

Rev. 1.00 18 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

EWEN/EWDS cycle has ended, CS should be again brought high and

The ²EWEN² instruction is the Erase/Write Enable in- the DO bit polled. If D0 is low this indicates that the inter-
nal write-cycle is still in progress, however the D0 bit will
struction and the ²EWDS² instruction is the Erase/Write
change to a high value when the internal write-cycle has
Disable instruction. To instigate an ²EWEN² or ²EWDS²
ended. Before an ²ERAL² instruction is transmitted an
instruction, the CS bit should first be set high, followed
²EWEN² instruction must have been transmitted at
by a high start bit and then the instruction code ²00². For
some point earlier to ensure that the erase/write function
the ²EWEN² instruction, a ²11² should then be transmit-
of the EEPROM is enabled.
ted and for the ²EWDS² instruction a ²00² should be
transmitted. Following on from this, 5-bits of ²don¢t care² WRAL
data should then be transmitted to complete the instruc-
The WRAL instruction is used to write the same data
tion. If the device is already in the Erase Write Disable
into the entire EEPROM. To instigate this instruction, the
mode then no write or erase operations can be executed
CS bit should be set high, followed by a high start bit and
thus protecting the internal EEPROM data. Before any
then the instruction code ²00². Following on from this, a
write or erase instruction is executed an ²EWEN² in-
²01² should then be transmitted. This should be fol-
struction must be issued. After the ²EWEN² instruction
lowed by 5-bits of ²don¢t care² data. The data informa-
is executed, the device will remain in the Erase Write
tion should then follow with the MSB bit being
Enable mode until a subsequent ²EWDS² instruction is
transmitted first. After the instruction code and data
issued or until the device is powered down.
have been transmitted, the data will be written into the
ERAL EEPROM when the CS bit is cleared to zero. The
EEPROM does this by executing an internal write-cycle.
The ²ERAL² instruction is used to erase the whole con- This process takes place internally using the
tents of the EEPROM memory. After it has been exe- EEPROM¢s own internal clock and does not require any
cuted all the data in the EEPROM will be set to ²1². To action from the SK clock. No further instructions can be
instigate this instruction, the CS bit should be set high, accepted by the EEPROM until this internal write-cycle
followed by a high start bit and then the instruction code has finished. To determine when the write cycle has
²00². Following on from this, a ²10² should then be ended, CS should be again brought high and the DO bit
transmitted. This should be followed by 5-bits of ²don¢t polled. If D0 is low this indicates that the internal
care² data to complete the instruction. After the ²ERAL² write-cycle is still in progress, however the D0 bit will
instruction code has been transmitted, the EEPROM change to a high value when the internal write-cycle has
data will be erased when the CS bit is cleared to zero. ended. Before a ²WRAL² instruction is transmitted an
The EEPROM does this by executing an internal ²EWEN² instruction must have been transmitted at
write-cycle. This process takes place internally using some point earlier to ensure that the erase/write function
the EEPROM¢s own internal clock and does not require of the EEPROM is enabled. The WRAL instruction will
any action from the SK clock. No further instructions can automatically erase any previously written data making
be accepted by the EEPROM until this internal it unnecessary to first issue an erase instruction.
write-cycle has finished. To determine when the write

C S S ta n d b y

S K

D I 1 0 0
S ta r t b it E W E N = 1 1 X X X X X - - 5 - b it d o n 't c a r e
E W D S = 0 0
EWEN/EWDS Timing

tC D S

C S V e r ify S ta n d b y

S K

D I 1 0 0 1 0
S ta r t b it X X X X X - - 5 - b it d o n 't c a r e
1 tS V
D O B u s y R e a d y
tP R

ERAL Timing

Rev. 1.00 19 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

tC D S

C S V e r ify S ta n d b y

S K

D I 1 0 0 0 1 D 7 D 0
S ta r t b it X X X X X - - 5 - b it d o n 't c a r e

1 tS V
D O B u s y R e a d y
tP R

WRAL Timing

ERASE Internal Write Cycle

The ²ERASE² instruction is used to erase data at a The write or erase instructions, ²WRITE², ²ERASE²,
specified address. The data at the address specified will ²ERAL² or ²WRAL² will all use the EEPROM¢s internal
be set to ²1². To instigate an ²ERASE² instruction, the write cycle function. As this function is completely inter-
CS bit should be set high, followed by a high start bit and nally timed, the SK clock is not required. As the MCU has
then the instruction code ²11², all transmitted via the DI no control over the timing of this write cycle, it must still
bit. The address information should then follow with the have some way of knowing when the internal write cycle
MSB bit being transmitted first. After all the ²ERASE² in- has completed. This is because, when the internal write
struction code and address have been transmitted, the cycle is executing, the EEPROM will not accept any fur-
data at the specified address will be erased when the ther instructions from the MCU. The MCU must therefore
CS bit is cleared to zero. The EEPROM does this by ex- wait until the write cycle has finished before sending any
ecuting an internal write cycle which will set all data at further instructions.
the specified address to ²1². This process takes place One way for the MCU to know when the write cycle has
internally using the EEPROM¢s own internal clock and terminated is to poll the DO bit after the CS bit has is-
does not require any action from the SK clock. No fur- sued a low pulse. The low going edge of this CS bit
ther instructions can be accepted by the EEPROM until pulse will initiate the internal write cycle, when the bit is
the write cycle has finished. To determine when the write returned high the DO bit will go low to indicated that the
cycle has ended, the CS should be again brought high write cycle is in progress. When the DO bit returns high
and the DO bit polled. If the DO bit is low this indicates this indicates that the internal write cycle has ended and
that the write-cycle is still in progress, however, the DO that the EEPROM is ready to receive further instruc-
bit will change to a high value when the write-cycle has tions.
ended. Before an ²ERASE² instruction is transmitted,
an ²EWEN² instruction must have been transmitted at
some point earlier to ensure that the erase/write function
of the EEPROM is enabled.

tC D S
C S V e r ify S ta n d b y

S K

D I 1 1 1 A 6 A 5 A 4 A 1 A 0
S ta r t b it tS V
1
B u s y
D O R e a d y
tP R

ERASE Timing

Rev. 1.00 20 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Is s u e in s tr u c tio n
A d d re s s , D a ta

C S
In te r n a l w r ite c y c le in itia te d
tC D S d e la y

C S

tS V d e la y
D O w ill g o lo w h e r e to in d ic a te in te r n a l
w r ite c y c le s till in p r o g r e s s
D O = "1 "
N o
Y e s
In te r n a l w r ite
c y c le fin is h e d

Internal Write Cycle Busy Polling

Initialising the EEPROM gle address in the EEPROM. The initialisation

After the MCU is powered on and if the EEPROM is to procedure can then be terminated by issuing an EWDS
be used, it must be initialised in a specific way before instruction, however at this point, if actual user data is to
any user instructions are transmitted. This is achieved be imminently written to the EEPROM, this last step is
by first transmitting an EWEN instruction, then by issu- optional.
ing a WRITE instruction to write random data to any sin-

The following is an example program of how this can be implemented:

mov A,01h
mov BP,A ; set to bank 1
mov A,40h
mov MP1,A ; set MP1 to EECR address
call EWEN ; subroutine to run EWEN instructions
mov A, 7Fh
mov EEADDR, A
mov A, 55h
mov EEDATA, A
call WRITE ; subroutine to run WRITE instruction
; write 55h data to address 7Fh
call EWDS ; optional subroutine to run EWDS instruction

EEPROM Program Examples

The following short programs gives examples of how to send instructions, read and write to the EEPROM. These pro-
grams can form a basis of understanding as to how the internal EEPROM memory is to be used to store and retrieve
data.
Example 1 - Definitions and Sending Instructions to the EEPROM
_CS EQU IAR1.4 ; EEPROM lines setup to have a corresponding
_SK EQU IAR1.5 ; Bit in the Indirect Addressing Register IAR1
_DI EQU IAR1.6 ; EEPROM can only be indirectly addressed using
; MP1
_DO EQU IAR1.7
_EECR EQU 40H ; Setup address of the EEPROM control register
C_Addr_Length EQU 7 ; Address length - 7-bits
C_Data_Length EQU 8 ; Data length - always 8-bits
;
DATA .SECTION at 70h ¢DATA¢
EE_command DB ? ; Stores the read or write instruction
; information
ADDR DB ? ; Store write data or read data address
WR_Data DB ? ; Store read or write data
COUNT DB ? ; Temporary counter
;

Rev. 1.00 21 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

WriteCommand: ; Write instruction code subroutine

MOV A,3 ; Read, write and erase instructions are 3 bits
; long
MOV COUNT,A
WriteCommand_0:
CLR _DI ; Prepare the transmitted bit
SZ EE_command.7 ; Check value of highest instruction code bit
SET _DI
SET _SK
CLR _SK
CLR C
RLC EE_command ; Get next bit of instruction code
SDZ COUNT ; Check if last bit has been transmitted
JMP WriteCommand_0
CLR _DI
RET

Example 2 - Transmitting an Address to the EEPROM

WriteAddr: ; Write address subroutine
MOV A,C_Addr_Length ; Setup address length
MOV COUNT,A
WriteAddr_0:
CLR _DI
SZ ADDR.7 ; Check value of address MSB
SET _DI
CLR C
RLC ADDR ; Get next address bit
SET _SK
CLR _SK
SDZ COUNT ; Check if address LSB has been written
JMP WriteAddr_0
CLR _DI
RET

Example 3 - Writing Data to the EEPROM

WriteData:
MOV A,C_Data_Length ; Setup data length
MOV COUNT,A
WriteData_0:
CLR _DI
SZ WR_Data.7 ; Check value of data MSB
SET _DI
CLR C
RLC WR_Data ; Get next address bit
SET _SK
CLR _SK
SDZ COUNT ; Check if data LSB has been written
JMP _0
CLR _CS ; CS low edge initiates internal write cycle
SET _CS ; CS high edge allows DO to be used to indicate
; end of write cycle
SNZ _DO ; Poll for DO high to indicate end of write
; cycle
JMP $-1
RET

Rev. 1.00 22 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Example 4 - Reading Data from the EEPROM

ReadData:
MOV A,C_Data_Length ; Setup data length
MOV COUNT,A
CLR WR_Data
ReadData_0:
CLR C
RLC WR_Data
SET _SK
SZ _DO ; check value of data MSB
SET WR_Data.0
CLR _SK
SDZ COUNT ; check if LSB has been received
JMP _0
MOV A,WR_Data
RET

Input/Output Ports
Holtek microcontrollers offer considerable flexibility on other low-power applications. Various methods exist to
their I/O ports. With the input or output designation of ev- wake-up the microcontroller, one of which is to change
ery pin fully under user program control, pull-high op- the logic condition on one of the Port A pins from high to
tions for all ports and wake-up options on certain pins, l o w . A f t e r a ² H A L T² i n s t r u c t i o n f o r c e s t h e
the user is provided with an I/O structure to meet the microcontroller into entering a HALT condition, the pro-
needs of a wide range of application possibilities. cessor will remain idle or in a low-power state until the
Depending upon which device or package is chosen, logic condition of the selected wake-up pin on Port A
the microcontroller range provides from 13 to 23 changes from high to low. This function is especially
bidirectional input/output lines labeled with port names suitable for applications that can be woken up via exter-
PA, PB, PC, etc. These I/O ports are mapped to the nal switches. Note that each pin on Port A can be se-
RAM Data Memory with specific addresses as shown in lected individually to have this wake-up feature.
the Special Purpose Data Memory table. All of these I/O
I/O Port Control Registers
ports can be used for input and output operations. For
input operation, these ports are non-latching, which Each I/O port has its own control register PAC, PBC,
means the inputs must be ready at the T2 rising edge of PCC, etc., to control the input/output configuration. With
instruction ²MOV A,[m]², where m denotes the port ad- this control register, each CMOS output or input with or
dress. For output operation, all the data is latched and without pull-high resistor structures can be reconfigured
remains unchanged until the output latch is rewritten. dynamically under software control. Each pin of the I/O
ports is directly mapped to a bit in its associated port
Pull-high Resistors control register. For the I/O pin to function as an input,
the corresponding bit of the control register must be writ-
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an exter- ten as a ²1². This will then allow the logic state of the in-
nal resistor. To eliminate the need for these external re- put pin to be directly read by instructions. When the
sistors, all I/O pins, when configured as an input have corresponding bit of the control register is written as a
the capability of being connected to an internal pull-high ²0², the I/O pin will be setup as a CMOS output. If the pin
resistor. These pull-high resistors are selectable via is currently setup as an output, instructions can still be
configuration options and are implemented using a used to read the output register. However, it should be
weak PMOS transistor. Note that if the pull-high option noted that the program will in fact only read the status of
is selected, then all I/O pins on that port will be con- the output data latch and not the actual logic status of
nected to pull-high resistors, individual pins cannot be the output pin. Note that with the exception of the
selected for pull-high resistor options. HT48F06E device, there is an additional configuration
option for Port A that can select whether the inputs on
Port A Wake-up this port are Schmitt Trigger types or non-Schmitt Trig-
ger types. Inputs for the other ports are all Schmitt Trig-
Each device has a HALT instruction enabling the
ger type.
microcontroller to enter a Power Down Mode and pre-
serve power, a feature that is important for battery and

Rev. 1.00 23 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Pin-shared Functions · External Timer/Event Counter Input

Each device contains a single 8-bit Timer/Event
The flexibility of the microcontroller range is greatly en-
Counter which has an external pin known as TMR.
hanced by the use of pins that have more than one func- This is pin-shared with I/O pin PC0 or PC1. If this
tion. Limited numbers of pins can force serious design shared pin is to be used as a Timer/Event Counter in-
constraints on designers but by supplying pins with put, then the Timer/Event Counter must be configured
multi-functions, many of these difficulties can be over- to be in the Event Counter or Pulse Width Measure-
come. For some pins, the chosen function of the ment Mode. This is achieved by setting the appropri-
multi-function I/O pins is set by configuration options ate bits in the relevant Timer/Event Counter Control
while for others the function is set by application pro- Register. The pin must also be setup as an input by
gram control. setting the appropriate bit in the Port Control Register.
Pull-high resistor options can also be selected via the
· Buzzer appropriate port pull-high configuration option. If the
The buzzer pins BZ and BZ are pin-shared with I/O shared pin is to be used as a normal I/O pin, then the
pins PB0 and PB1. The buzzer function is selected via external timer input function must be disabled, by en-
a configuration option and remains fixed after the de- suring that the corresponding Timer/Event Counter is
vice is programmed. Note that the corresponding bits configured to be in the Off Mode or Timer Mode.
of the port control register, PBC, must setup the pins
· I/O Pin Structures
as outputs to enable the buzzer outputs. If the PBC
port control register has setup the pins as inputs, then The following diagrams illustrate the I/O pin internal
the pins will function as normal logic inputs with the structures. As the exact logical construction of the I/O
usual pull-high options, even if the buzzer configura- pin may differ from these drawings, they are supplied
tion option has been selected. as a guide only to assist with the functional under-
standing of the I/O pins. Note also that the specified
· External Interrupt Input pins refer to the largest device package, therefore not
The external interrupt pin INT is pin-shared with the all pins specified will exist on all devices.
I/O pin PC0 or PG0 depending upon which device is
used. For the shared function pins to operate as an
external interrupt pin and not as a normal I/O pin, the
corresponding external interrupt enable bits in the
INTC interrupt control register must be correctly set.
For applications not requiring an external interrupt in-
put, the pin-shared external interrupt pin can be used
as a normal I/O pin, however to do this, the external in-
terrupt enable bits in the INTC register must be dis-
abled.

V D D
P u ll- H ig h
C o n tr o l B it O p tio n W e a k
D a ta B u s D Q P u ll- u p
W r ite C o n tr o l R e g is te r C K Q
S
C h ip R e s e t

P A 0 ~ P A 7
R e a d C o n tr o l R e g is te r
D a ta B it
D Q
W r ite D a ta R e g is te r C K Q
S

M
U
R e a d D a ta R e g is te r X S c h m itt T r ig g e r In p u t O p tio n
S y s te m W a k e -u p
W a k e - u p O p tio n

PA Input/Output Port

Rev. 1.00 24 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

V D D
P u ll- H ig h
C o n tr o l B it O p tio n W e a k
D a ta B u s D Q P u ll- u p
W r ite C o n tr o l R e g is te r C K Q
S
C h ip R e s e t

P B 0 /B Z
R e a d C o n tr o l R e g is te r
P B 1 /B Z
D a ta B it
D Q
W r ite D a ta R e g is te r C K Q
S

M
P B 0 D a ta B it U
B Z ( P B 1 o n ly ) X
B Z ( P B 0 o n ly )
M B Z O p tio n
U
X
R e a d D a ta R e g is te r

PB0~PB1 Input/Output Port

V D D

P u ll- H ig h
C o n tr o l B it O p tio n W e a k
D a ta B u s D Q P u ll- u p
W r ite C o n tr o l R e g is te r C K Q
S
C h ip R e s e t

R e a d C o n tr o l R e g is te r P B 2 ~ P B 7
P C 0 ~ P C 5
D a ta B it P G 0
D Q
IN T /T M R
W r ite D a ta R e g is te r C K Q S h a r e d P in s
S

M
U
X
R e a d D a ta R e g is te r
IN T ( P C 0 /P G 0 o n ly )
T M R ( P C 0 /P C 1 o n ly )

PB, PC and PG Input/Output Ports

Rev. 1.00 25 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Programming Considerations different operating modes, they can be configured to op-

Within the user program, one of the first things to con- erate as a general timer, an external event counter or as
sider is port initialization. After a reset, all of the I/O data a pulse width measurement device. The provision of an
and port control registers will be set high. This means internal prescaler to the clock circuitry gives added
that all I/O pins will default to an input state, the level of range to the timer.
which depends on the other connected circuitry and There are two types of registers related to the
whether pull-high options have been selected. If the port Timer/Event Counters. The first is the register that con-
control registers, PAC, PBC, PCC, etc., are then pro- tains the actual value of the Timer/Event Counter and
grammed to setup some pins as outputs, these output into which an initial value can be preloaded, and is
pins will have an initial high output value unless the as- known as TMR. Reading from this register retrieves the
sociated port data registers, PA, PB, PC, etc., are first contents of the Timer/Event Counter. The second type
programmed. Selecting which pins are inputs and which of associated register is the Timer Control Register,
are outputs can be achieved byte-wide by loading the which defines the timer options and determines how the
correct values into the appropriate port control register Timer/Event Counter is to be used, and has the name
or by programming individual bits in the port control reg- TMRC. All devices can have the timer clock configured
ister using the ²SET [m].i² and ²CLR [m].i² instructions. to come from the internal clock source. In addition, the
Note that when using these bit control instructions, a timer clock source can also be configured to come from
read-modify-write operation takes place. The an external timer pin.
microcontroller must first read in the data on the entire
An external clock source is used when the Timer/Event
port, modify it to the required new bit values and then re-
Counter is in the event counting mode, the clock source
write this data back to the output ports.
being provided on the external timer pin. This pin has
T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 the name TMR and is pin-shared with an I/O pin. De-
S y s te m C lo c k pending upon the condition of the TE, T0E or T1E bit in
P o rt D a ta
the Timer Control Register, each high to low, or low to
high transition on the external timer input pin will incre-
W r ite to P o r t R e a d fro m P o rt ment the Timer/Event Counter by one.

Read/Write Timing Configuring the Timer/Event Counter Input Clock

Source
Port A has the additional capability of providing wake-up The Timer/Event Counter's clock can originate from var-
functions. When the device is in the Power Down Mode, ious sources. The system clock source is used when the
various methods are available to wake the device up. Timer/Event Counter is in the timer mode or in the pulse
One of these is a high to low transition of any of the Port width measurement mode. The system clock is divided
A pins. Single or multiple pins on Port A can be setup to by a prescaler, the division ratio of which is conditioned
have this function. by the Timer Control Register bits PSC2~PSC0.
An external clock source is used when the Timer/Event
Timer/Event Counters Counter is in the event counting mode, the clock source
The provision of timers form an important part of any being provided on the external timer pin, TMR. De-
microcontroller, giving the designer a means of carrying pending upon the condition of the TE bit, each high to
out time related functions. Each device contains a single low, or low to high transition on the external timer pin will
count-up timer of 8-bit capacity. As each timer has three increment the counter by one.

D a ta B u s

R e lo a d
P r e lo a d R e g is te r

P S C 2 ~ P S C 0 T M 1 T M 0
(1 /2 ~ 1 /2 5 6 )
fS Y S 8 - S ta g e P r e s c a le r T im e r /E v e n t C o u n te r T im e r /E v e n t C o u n te r O v e r flo w
M o d e C o n tro l to In te rru p t
T O N
T M R
8 - B it T im e r /E v e n t C o u n te r ¸ 2 B Z
B Z
T E

8-bit Timer/Event Counter Structure

Rev. 1.00 26 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Timer Register - TMR different modes, the options of which are determined by
The timer register is a special function register located in the contents of their control register, which has the
the Special Purpose RAM Data Memory and is the place name TMRC. It is the Timer Control Register together
where the actual timer value is stored. This register is with its corresponding timer register that control the full
known as TMR. The value in the timer register increases operation of the Timer/Event Counter. Before the
by one each time an internal clock pulse is received or Timer/Event Counter can be used, it is essential that the
an external transition occurs on the external timer pin. Timer Control Register is fully programmed with the
The timer will count from the initial value loaded by the right data to ensure its correct operation, a process that
preload register to the full count of FFH at which point is normally carried out during program initialisation.
the timer overflows and an internal interrupt signal is To choose which of the three modes the Timer/Event
generated. The timer value will then be reset with the ini- Counter is to operate in, either in the timer mode, the
tial preload register value and continue counting. event counting mode or the pulse width measurement
To achieve a maximum full range count of FFH the mode, bits 7 and 6 of the Timer Control Register, which
preload register must first be cleared to all zeros. It are known as the bit pair TM1/TM0, must be set to the
should be noted that after power-on, the preload register required logic levels. The Timer/Event Counter on/off
will be in an unknown condition. Note that if the bit, which is bit 4 of the Timer Control Register and
Timer/Event Counter is switched off and data is written known as TON, provides the basic on/off control of the
to its preload register, this data will be immediately writ- Timer/Event Counter. Setting the bit high allows the
ten into the actual timer register. However, if the Timer/Event Counter to run, clearing the bit stops it run-
Timer/Event Counter is enabled and counting, any new ning. Bits 0~2 of the Timer Control Register determine
data written into the preload data register during this pe- the division ratio of the input clock prescaler. The
riod will remain in the preload register and will only be prescaler bit settings have no effect if an external clock
written into the timer register the next time an overflow source is used. If the Timer/Event Counter is in the
occurs. event count or pulse width measurement mode, the ac-
tive transition edge level type is selected by the logic
Timer Control Register - TMRC level of bit 3 of the Timer Control Register which is
known as TE.
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three

b 7 b 0
T M 1 T M 0 T O N T E P S C 2 P S C 1 P S C 0 T M R C R e g is te r

T im e r P r e s c a le r R a te S e le c t
P S C 2 P S C 1 P S C 0 T im e r R a te
0 0 0 1 :2
0 0 1 1 :4
0 1 0 1 :8
0 1 1 1 :1 6
1 0 0 1 :3 2
1 0 1 1 :6 4
1 1 0 1 :1 2 8
1 1 1 1 :2 5 6

E v e n t C o u n te r A c tiv e E d g e S e le c t
1 : c o u n t o n fa llin g e d g e
0 : c o u n t o n r is in g e d g e
P u ls e W id th M e a s u r e m e n t A c tiv e E d g e S e le c t
1 : s ta rt c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e
0 : s ta rt c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "

O p e r a tin g M o d e S e le c t
T M 1 T M 0
0 0 n o m o d e a v a ila b le
0 1 e v e n t c o u n te r m o d e
1 0 tim e r m o d e
1 1 p u ls e w id th m e a s u r e m e n t m o d e

Timer/Event Counter Control Register

Rev. 1.00 27 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Configuring the Timer Mode vided by the internal prescaler. After the other bits in the
In this mode, the Timer/Event Counter can be utilised to Timer Control Register have been setup, the enable bit,
measure fixed time intervals, providing an internal inter- which is bit 4 of the Timer Control Register, can be set
rupt signal each time the Timer/Event Counter over- high to enable the Timer/Event Counter to run. If the Ac-
flows. To operate in this mode, the Operating Mode tive Edge Select bit, which is bit 3 of the Timer Control
Select bit pair in the Timer Control Register must be set Register, is low, the Timer/Event Counter will increment
to the correct value as shown. each time the external timer pin receives a low to high
transition. If the Active Edge Select bit is high, the coun-
Control Register Operating Mode Bit7 Bit6
ter will increment each time the external timer pin re-
Select Bits for the Timer Mode 1 0 ceives a high to low transition. When it is full and
overflows, an interrupt signal is generated and the
In this mode the internal clock, fSYS, is used as the
Timer/Event Counter will reload the value already
Timer/Event Counter clock. However, this clock source
loaded into the preload register and continue counting.
is further divided by a prescaler, the value of which is de-
The interrupt can be disabled by ensuring that the
termined by the Prescaler Rate Select bits, which are
Timer/Event Counter Interrupt Enable bit in the Interrupt
bits 0~3 in the Timer Control Register. After the other
Control Register, INTC, is reset to zero.
bits in the Timer Control Register have been setup, the
enable bit, which is bit 4 of the Timer Control Register, As the external timer pin is shared with an I/O pin, to en-
can be set high to enable the Timer/Event Counter to sure that the pin is configured to operate as an event
run. Each time an internal clock cycle occurs, the counter input pin, two things have to happen. The first is
Timer/Event Counter increments by one. When it is full to ensure that the Operating Mode Select bits in the
and overflows, an interrupt signal is generated and the Timer Control Register place the Timer/Event Counter in
Timer/Event Counter will reload the value already the Event Counting Mode, the second is to ensure that
loaded into the preload register and continue counting. the port control register configures the pin as an input. It
The interrupt can be disabled by ensuring that the should be noted that in the event counting mode, even if
Timer/Event Counter Interrupt Enable bit in the Interrupt the microcontroller is in the Power Down Mode, the
Control Register, INTC, is reset to zero. Timer/Event Counter will continue to record externally
changing logic events on the timer input pin. As a result
Configuring the Event Counter Mode when the timer overflows it will generate a timer interrupt
and corresponding wake-up source.
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be re-
Configuring the Pulse Width Measurement Mode
corded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair in the Timer In this mode, the Timer/Event Counter can be utilised to
Control Register must be set to the correct value as measure the width of external pulses applied to the ex-
shown. ternal timer pin. To operate in this mode, the Operating
Mode Select bit pair in the Timer Control Register must
Control Register Operating Mode Bit7 Bit6
be set to the correct value as shown.
Select Bits for the Event Counter Mode 0 1
Control Register Operating Mode Bit7 Bit6
In this mode the external timer pin is used as the Select Bits for the Pulse Width Measure-
Timer/Event Counter clock source, however it is not di- ment Mode 1 1

P r e s c a le r O u tp u t

In c re m e n t
T im e r C o n tr o lle r T im e r + 1 T im e r + 2 T im e r + N T im e r + N + 1

Timer Mode Timing Diagram

E x te r n a l T im e
P in In p u t
T E = 1

In c re m e n t
T im e r + 1 T im e r + 2 T im e r + 3
T im e r C o u n te r

Event Counter Mode Timing Diagram

Rev. 1.00 28 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

In this mode the internal clock, fSYS, is used as the bit in the Interrupt Control Register, INTC, is reset to
Timer/Event Counter clock. However, this clock source zero.
is further divided by a prescaler, the value of which is de- As the external timer pin is shared with an I/O pin, to en-
termined by the Prescaler Rate Select bits, which are sure that the pin is configured to operate as a pulse
bits 0~3 in the Timer Control Register. After the other width measurement pin, two things have to happen. The
bits in the Timer Control Register have been setup, the first is to ensure that the Operating Mode Select bits in
enable bit, which is bit 4 of the Timer Control Register, the Timer Control Register place the Timer/Event Coun-
can be set high to enable the Timer/Event Counter, how- ter in the Pulse Width Measurement Mode, the second
ever it will not actually start counting until an active edge is to ensure that the port control register configures the
is received on the external timer pin. pin as an input.
If the Active Edge Select bit, which is bit 3 of the Timer
Control Register, is low, once a high to low transition has Programmable Frequency Divider (PFD) and Buzzer
been received on the external timer pin, the Timer/Event Application
Counter will start counting until the external timer pin re- Operating similar to a programmable frequency divider,
turns to its original high level. At this point the enable bit the buzzer function within the microcontroller provides a
will be automatically reset to zero and the Timer/Event means of producing a variable frequency output suitable
Counter will stop counting. If the Active Edge Select bit for applications, such as piezo-buzzer driving or other
is high, the Timer/Event Counter will begin counting interfaces requiring a precise frequency generator.
once a low to high transition has been received on the
The BZ and BZ are a complimentary pair and pin-shared
external timer pin and stop counting when the external
with I/O pins, PB0 and PB1. The function is selected via
timer pin returns to its original low level. As before, the
configuration option, however, if not selected, the pins
enable bit will be automatically reset to zero and the
can operate as normal I/O pins. Note that the BZ pin is
Timer/Event Counter will stop counting. It is important to
the inverse of the BZ pin generating a kind of differential
note that in the Pulse Width Measurement Mode, the
output and supplying more power to connected inter-
enable bit is automatically reset to zero when the exter-
faces such as buzzers. Note that the 16-pin NSOP
nal control signal on the external timer pin returns to its
package type only has a single BZ output as pin PB1/BZ
original level, whereas in the other two modes the en-
does not exist on this package.
able bit can only be reset to zero under program control.
The timer overflow signal is the clock source for the
The residual value in the Timer/Event Counter, which
buzzer circuit. The output frequency is controlled by
can now be read by the program, therefore represents
loading the required values into the timer prescaler and
the length of the pulse received on the external timer
timer registers to give the required division ratio. The
pin. As the enable bit has now been reset, any further
counter will begin to count-up from this preload register
transitions on the external timer pin will be ignored. Not
value until full, at which point an overflow signal is gen-
until the enable bit is again set high by the program can
erated, causing both the BZ and BZ outputs to change
the timer begin further pulse width measurements. In
state. The counter will then be automatically reloaded
this way, single shot pulse measurements can be easily
with the preload register value and continue count-
made.
ing-up.
It should be noted that in this mode the Timer/Event
If the configuration option has selected the buzzer func-
Counter is controlled by logical transitions on the exter-
tion, then for both buzzer outputs to operate, it is essen-
nal timer pin and not by the logic level. When the
tial that the Port B control register PBC bit 0 and PBC bit
Timer/Event Counter is full and overflows, an interrupt
1 are setup as outputs. If only one pin is setup as an out-
signal is generated and the Timer/Event Counter will re-
put, the other pin can still be used as a normal data input
load the value already loaded into the preload register
pin. However, if both pins are setup as inputs then the
and continue counting. The interrupt can be disabled by
buzzer will not function. The buzzer outputs will only be
ensuring that the Timer/Event Counter Interrupt Enable
E x te rn a l T M R
P in In p u t

T O N ( w ith T E = 0 )

P r e s c a le r O u tp u t

In c re m e n t
T im e r + 1 + 2 + 3 + 4
T im e r C o u n te r
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .

Pulse Width Measure Mode Timing Diagram

Rev. 1.00 29 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

T im e r O v e r flo w

B u z z e r C lo c k

P B 0 D a ta

B Z O u tp u t a t P B 0

B Z O u tp u t a t P B 1

PFD Output Control

activated if bit PB0 is set to ²1². This output data bit is internal interrupt signal directing the program flow to the
used as the on/off control bit for the buzzer outputs. respective internal interrupt vector. For the pulse width
Note that the BZ and BZ outputs will both be low if the measurement mode, the internal system clock is also
PB0 output data bit is cleared to ²0². The condition of used as the timer clock source but the timer will only run
data bit PB1 has no effect on the overall control of the when the correct logic condition appears on the external
BZ and BZ pins. timer input pin. As this is an external event and not syn-
chronised with the internal timer clock, the
Using this method of frequency generation, and if a
microcontroller will only see this external event when the
crystal oscillator is used for the system clock, very pre-
next timer clock pulse arrives. As a result there may be
cise values of frequency can be generated.
small differences in measured values requiring pro-
Prescaler grammers to take this into account during programming.
The same applies if the timer is configured to be in the
The single 8-bit timer in the devices all possess a event counting mode which again is an external event
prescaler. Bits 0~2 of the Timer Control Register, define and not synchronised with the internal system or timer
the prescaling stages of the internal clock source of the clock.
Timer/Event Counter.
When the Timer/Event Counter is read or if data is writ-
I/O Interfacing ten to the preload registers, the clock is inhibited to
avoid errors, however as this may result in a counting er-
The Timer/Event Counter, when configured to run in the
ror, this should be taken into account by the program-
event counter or pulse width measurement mode, re-
mer. Care must be taken to ensure that the timers are
quires the use of an external pin for correct operation.
properly initialised before using them for the first time.
As the external timer pin is pin-shared with an I/O pin, it
The associated timer enable bits in the interrupt control
must be configured correctly to ensure it is setup for use
register must be properly set otherwise the internal in-
as a Timer/Event Counter input and not as a normal I/O
terrupt associated with the timer will remain inactive.
pin. This is implemented by ensuring that the mode se-
The edge select, timer mode and clock source control
lect bits in the Timer/Event Counter control register, se-
bits in timer control register must also be correctly set to
lect either the event counter or pulse width
ensure the timer is properly configured for the required
measurement mode. Additionally the Port Control Reg-
application. It is also important to ensure that an initial
ister bit for this pin must be set high to ensure that the
value is first loaded into the timer register before the
pin is setup as an input. Any pull high configuration for
timer is switched on; this is because after power-on the
this pins will remain valid even if the pin is used as a
initial value of the timer register is unknown. After the
Timer/Event Counter input.
timer has been initialised the timer can be turned on and
Programming Considerations off by controlling the enable bit in the timer control regis-
ter. Note that setting the timer enable bit high to turn the
When configured to run in the timer mode, the internal timer on, should only be executed after the timer mode
system clock is used as the timer clock source and is bits have been properly setup. Setting the timer enable
therefore synchronized with the overall operation of the bit high together with a mode bit modification, may lead
microcontroller. In this mode, when the appropriate to improper timer operation if executed as a single timer
timer register is full, the microcontroller will generate an control register byte write instruction.

Rev. 1.00 30 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

When the Timer/Event counter overflows, its corre- quest flag should first be set high before issuing the
sponding interrupt request flag in the interrupt control HALT instruction to enter the Power Down Mode.
register will be set. If the timer interrupt is enabled this
will in turn generate an interrupt signal. However irre- Timer Program Example
spective of whether the timer interrupt is enabled or not, This program example shows how the Timer/Event
a Timer/Event counter overflow will also generate a Counter registers are setup, along with how the inter-
wake-up signal if the device is in a Power-down condi- rupts are enabled and managed. Note how the
tion. This situation may occur if the Timer/Event Counter Timer/Event Counter is turned on, by setting bit 4 of the
is in the Event Counting Mode and if the external signal Timer Control Register. The Timer/Event Counter can
continues to change state. In such a case, the be turned off in a similar way by clearing the same bit.
Timer/Event Counter will continue to count these exter- This example program sets the Timer/Event Counter
nal events and if an overflow occurs the device will be tobe in the timer mode, which uses the internal system
woken up from its Power-down condition. To prevent clock as the clock source.
such a wake-up from occurring, the timer interrupt re-

org 04h ; external interrupt vector

reti
org 08h ; Timer/Event Counter interrupt vector
jmp tmrint ; jump here when Timer overflows
:
org 20h ; main program
;internal Timer/Event Counter interrupt routine
tmrint:
:
; Timer/Event Counter main program placed here
:
reti
:
:
begin:
;setup Timer registers
mov a,09bh ; setup preload value - timer counts from this value to FFH
mov tmr,a;
mov a,081h ; setup Timer control register
mov tmrc,a ; timer mode and prescaler set to /4
; setup interrupt register
mov a,005h ; enable master interrupt and timer interrupt
mov intc,a
set tmrc.4 ; start Timer - note mode bits must be previously setup

Rev. 1.00 31 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Interrupts
Interrupts are an important part of any microcontroller with a new address which will be the value of the corre-
system. When an external event or an internal function sponding interrupt vector. The microcontroller will then
such as a Timer/Event Counter requires microcontroller fetch its next instruction from this interrupt vector. The
attention, their corresponding interrupt will enforce a instruction at this vector will usually be a JMP statement
temporary suspension of the main program allowing the which will take program execution to another section of
microcontroller to direct attention to their respective program which is known as the interrupt service routine.
needs. Each device contains a single external interrupt Here is located the code to control the appropriate inter-
and single internal timer interrupt functions. The exter- rupt. The interrupt service routine must be terminated
nal interrupt is controlled by the action of the external with a RETI statement, which retrieves the original Pro-
INT pin, while the internal interrupt is controlled by the gram Counter address from the stack and allows the
Timer/Event Counter overflow. microcontroller to continue with normal execution at the
point where the interrupt occurred.
Interrupt Register
The various interrupt enable bits, together with their as-
Overall interrupt control, which means interrupt enabling sociated request flags, are shown in the following dia-
and request flag setting, is controlled by a single INTC gram with their order of priority.
register, which is located in the RAM Data Memory. By
Once an interrupt subroutine is serviced, all the other in-
controlling the appropriate enable bits in this register
terrupts will be blocked, as the EMI bit will be cleared au-
each individual interrupt can be enabled or disabled.
tomatically. This will prevent any further interrupt nesting
Also when an interrupt occurs, the corresponding re-
from occurring. However, if other interrupt requests oc-
quest flag will be set by the microcontroller. The global
cur during this interval, although the interrupt will not be
enable flag if cleared to zero will disable all interrupts.
immediately serviced, the request flag will still be re-
Interrupt Operation corded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
A Timer/Event Counter overflow or the external interrupt
routine, the EMI bit should be set after entering the rou-
line being pulled low will all generate an interrupt re- tine, to allow interrupt nesting. If the stack is full, the in-
quest by setting their corresponding request flag, if their terrupt request will not be acknowledged, even if the
appropriate interrupt enable bit is set. When this hap- related interrupt is enabled, until the Stack Pointer is
pens, the Program Counter, which stores the address of decremented. If immediate service is desired, the stack
the next instruction to be executed, will be transferred must be prevented from becoming full.
onto the stack. The Program Counter will then be loaded

b 7 b 0
T F E IF E T I E E I E M I IN T C R e g is te r
M a s te r In te r r u p t G lo b a l E n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
E x te r n a l In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
N o im p le m e n te d , r e a d a s " 0 "

E x te r n a l In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o im p le m e n te d , r e a d a s " 0 "

Interrupt Control Register

Rev. 1.00 32 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

A u to m a tic a lly C le a r e d b y IS R A u to m a tic a lly D is a b le d b y IS R

M a n u a lly S e t o r C le a r e d b y S o ftw a r e C a n b e E n a b le d M a n u a lly
P r io r ity
E x te rn a l In te rru p t E E I E M I H ig h
R e q u e s t F la g E IF
In te rru p t
T im e r /E v e n t C o u n te r E T I P o llin g
In te r r u p t R e q u e s t F la g T F
L o w

Interrupt Structure

Interrupt Priority Timer/Event Counter Interrupt

Interrupts, occurring in the interval between the rising For a Timer/Event Counter interrupt to occur, the global
edges of two consecutive T2 pulses, will be serviced on interrupt enable bit, EMI, and the corresponding timer
the latter of the two T2 pulses, if the corresponding inter- interrupt enable bit, ETI, must first be set. An actual
rupts are enabled. In case of simultaneous requests, the Timer/Event Counter interrupt will take place when the
following table shows the priority that is applied. These Timer/Event Counter request flag, TF, is set, a situation
can be masked by resetting the EMI bit. that will occur when the Timer/Event Counter overflows.
When the interrupt is enabled, the stack is not full and a
Interrupt Source All Devices Priority
Timer/Event Counter overflow occurs, a subroutine call
External Interrupt 1 to the timer interrupt vector at location 08H, will take
Timer/Event Counter Overflow 2 place. When the interrupt is serviced, the timer interrupt
request flag, TF, will be automatically reset and the EMI
In cases where both external and internal interrupts are bit will be automatically cleared to disable other inter-
enabled and where an external and internal interrupt oc- rupts.
curs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable Programming Considerations
masking of the individual interrupts using the INTC reg- By disabling the interrupt enable bits, a requested inter-
ister can prevent simultaneous occurrences. rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
External Interrupt condition in the INTC register until the corresponding in-
For an external interrupt to occur, the global interrupt en- terrupt is serviced or until the request flag is cleared by a
able bit, EMI, and external interrupt enable bit, EEI, must software instruction.
first be set. An actual external interrupt will take place It is recommended that programs do not use the ²CALL
when the external interrupt request flag, EIF, is set, a situ- subroutine² instruction within the interrupt subroutine.
ation that will occur when a high to low transition appears Interrupts often occur in an unpredictable manner or
on the INT line. The external interrupt pin is pin-shared need to be serviced immediately in some applications. If
with an I/O pin PC.0 or PG.0 and can only be configured only one stack is left and the interrupt is not well con-
as an external interrupt pin if the corresponding external trolled, the original control sequence will be damaged
interrupt enable bit in the INTC register has been set. The
once a ²CALL subroutine² is executed in the interrupt
pin must also be setup as an input by setting the corre-
subroutine.
sponding PCC.0 or PGC.0 bit in the port control register.
When the interrupt is enabled, the stack is not full and a All of these interrupts have the capability of waking up
high to low transition appears on the external interrupt the processor when in the Power Down Mode. Only the
pin, a subroutine call to the external interrupt vector at lo- Program Counter is pushed onto the stack. If the con-
cation 04H, will take place. When the interrupt is ser- tents of the register or status register are altered by the
viced, the external interrupt request flag, EIF, will be interrupt service program, which may corrupt the de-
automatically reset and the EMI bit will be automatically sired control sequence, then the contents should be
cleared to disable other interrupts. Note that any pull-high saved in advance.
resistor configuration options on this pin will remain valid
even if the pin is used as an external interrupt input.

Rev. 1.00 33 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Reset and Initialisation

A reset function is a fundamental part of any inhibited. After the RES line reaches a certain voltage
microcontroller ensuring that the device can be set to value, the reset delay time tRSTD is invoked to provide
some predetermined condition irrespective of outside an extra delay time after which the microcontroller will
parameters. The most important reset condition is after begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, af- V D D
0 .9 V D D
ter a short delay, will be in a well defined state and ready R E S
to execute the first program instruction. After this tR S T D

power-on reset, certain important internal registers will S S T T im e - o u t

be set to defined states before the program com-
In te rn a l R e s e t
mences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to Power-On Reset Timing Chart
begin program execution from the lowest Program
Memory address.
For most applications a resistor connected between
In addition to the power-on reset, situations may arise VDD and the RES pin and a capacitor connected be-
where it is necessary to forcefully apply a reset condition tween VSS and the RES pin will provide a suitable ex-
when the microcontroller is running. One example of this ternal reset circuit. Any wiring connected to the RES
is where after power has been applied and the pin should be kept as short as possible to minimise
any stray noise interference.
microcontroller is already running, the RES line is force-
fully pulled low. In such a case, known as a normal oper-
V D D
ation reset, some of the microcontroller registers remain
1 0 0 k W
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return R E S
high. Another type of reset is when the Watchdog Timer 0 .1 m F
overflows and resets the microcontroller. All types of re- V S S
set operations result in different register conditions be- Basic Reset Circuit
ing setup.
For applications that operate within an environment
Another reset exists in the form of a Low Voltage Reset,
where more noise is present the Enhanced Reset Cir-
LVR, where a full reset, similar to the RES reset is imple- cuit shown is recommended.
mented in situations where the power supply voltage
0 .0 1 m F
falls below a certain threshold. V D D
1 0 0 k W
Reset Functions
R E S
There are five ways in which a microcontroller reset can 1 0 k W
occur, through events occurring both internally and ex-
0 .1 m F
ternally:
V S S
· Power-on Reset
The most fundamental and unavoidable reset is the Enhanced Reset Circuit
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program More information regarding external reset circuits is
Memory begins execution from the first memory ad- located in Application Note HA0075E on the Holtek
dress, a power-on reset also ensures that certain website.
other registers are preset to known conditions. All the
· RES Pin Reset
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to This type of reset occurs when the microcontroller is
inputs. already running and the RES pin is forcefully pulled
Although the microcontroller has an internal RC reset low by external hardware such as an external switch.
function, if the VDD power supply rise time is not fast In this case as in the case of other reset, the Program
enough or does not stabilise quickly at power-on, the Counter will reset to zero and program execution initi-
internal reset function may be incapable of providing ated from this point.
proper reset operation. For this reason it is recom- 0 .9 V D D
R E S 0 .4 V D D
mended that an external RC network is connected to
the RES pin, whose additional time delay will ensure tR S T D

that the RES pin remains low for an extended period S S T T im e - o u t

to allow the power supply to stabilise. During this time
In te rn a l R e s e t
delay, normal operation of the microcontroller will be
RES Reset Timing Chart

Rev. 1.00 34 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

· Low Voltage Reset - LVR Reset Initial Conditions

The microcontroller contains a low voltage reset circuit
The different types of reset described affect the reset
in order to monitor the supply voltage of the device,
flags in different ways. These flags, known as PDF and
which is selected via a configuration option. If the supply
voltage of the device drops to within a range of TO are located in the status register and are controlled
0.9V~VLVR such as might occur when changing the bat- by various microcontroller operations, such as the
tery, the LVR will automatically reset the device inter- Power Down function or Watchdog Timer. The reset
nally. The LVR includes the following specifications: For flags are shown in the table:
a valid LVR signal, a low voltage, i.e., a voltage in the
range between 0.9V~VLVR must exist for greater than the TO PDF RESET Conditions
value tLVR specified in the A.C. characteristics. If the low 0 0 RES reset during power-on
voltage state does not exceed 1ms, the LVR will ignore it
and will not perform a reset function. u u RES or LVR reset during normal operation

L V R
1 u WDT time-out reset during normal operation
tR S T D 1 1 WDT time-out reset during Power Down
S S T T im e - o u t
Note: ²u² stands for unchanged
In te rn a l R e s e t
The following table indicates the way in which the vari-
Low Voltage Reset Timing Chart ous components of the microcontroller are affected after
a power-on reset occurs.
· Watchdog Time-out Reset during Normal Operation
Item Condition After RESET
The Watchdog time-out Reset during normal opera-
tion is the same as a hardware RES pin reset except Program Counter Reset to zero
that the Watchdog time-out flag TO will be set to ²1². Interrupts All interrupts will be disabled
W D T T im e - o u t Clear after reset, WDT begins
WDT
tR S T D counting
S S T T im e - o u t
Timer/Event
Timer Counter will be turned off
In te rn a l R e s e t Counter

WDT Time-out Reset during Normal Operation The Timer Counter Prescaler will
Prescaler
be cleared
Timing Chart
Input/Output Ports I/O ports will be setup as inputs
· Watchdog Time-out Reset during Power Down Stack Pointer will point to the top
Stack Pointer
The Watchdog time-out Reset during Power Down is of the stack
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Pro- The different kinds of resets all affect the internal regis-
gram Counter and the Stack Pointer will be cleared to ters of the microcontroller in different ways. To ensure
²0² and the TO flag will be set to ²1². Refer to the A.C. reliable continuation of normal program execution after
Characteristics for tSST details. a reset occurs, it is important to know what condition the
W D T T im e - o u t microcontroller is in after a particular reset occurs. The
tS S T
following table describes how each type of reset affects
S S T T im e - o u t each of the microcontroller internal registers. Note that
where more than one package type exists the table will
WDT Time-out Reset during Power Down reflect the situation for the larger package type.
Timing Chart

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HT48F06E and HT48F10E

WDT Time-out WDT Time-out
Register Reset (Power-on) RES or LVR Reset
(Normal Operation) (HALT)
MP0 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu
MP1 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu
BP 0000 0000 0000 0000 0000 0000 uuuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu
PCL 0000 0000 0000 0000 0000 0000 0000 0000
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu
TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu
WDTS 0000 0111 0000 0111 0000 0111 uuuu uuuu
STATUS --00 xxxx --uu uuuu -- 1u uuuu --11 uuuu
INTC --00 -000 --00 -000 --00 -000 --uu -uuu
TMR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMRC 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu
PA 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB 1111 1111 1111 1111 1111 1111 uuuu uuuu
PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu
PC ---- -111 ---- -111 ---- -111 ---- -uuu
PCC ---- -111 ---- -111 ---- -111 ---- -uuu
EECR 1000 ---- 1000 ---- 1000 ---- uuuu ----

Note: ²u² stands for unchanged

²x² stands for unknown
²-² stands for unimplemented

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 HT48F06E/HT48F10E/HT48F30E

HT48F30E
WDT Time-out WDT Time-out
Register Reset (Power-on) RES or LVR Reset
(Normal Operation) (HALT)
MP0 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu
MP1 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu
BP 0000 0000 0000 0000 0000 0000 uuuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu
PCL 0000 0000 0000 0000 0000 0000 0000 0000
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu
TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu
WDTS 0000 0111 0000 0111 0000 0111 uuuu uuuu
STATUS --00 xxxx --uu uuuu -- 1u uuuu --11 uuuu
INTC --00 -000 --00 -000 --00 -000 --uu -uuu
TMR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMRC 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu
PA 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB 1111 1111 1111 1111 1111 1111 uuuu uuuu
PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu
PC --11 1111 --11 1111 --11 1111 --uu uuuu
PCC --11 1111 --11 1111 --11 1111 --uu uuuu
PG ---- ---1 ---- ---1 ---- ---1 ---- ---u
PGC ---- ---1 ---- ---1 ---- ---1 ---- ---u
EECR 1000 ---- 1000 ---- 1000 ---- uuuu ----

Note: ²u² stands for unchanged

²x² stands for unknown
²-² stands for unimplemented

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 HT48F06E/HT48F10E/HT48F30E

Oscillator
Various oscillator options offer the user a wide range of System RC Oscillator
functions according to their various application require- After selecting the correct configuration option, using
ments. Two types of system clocks can be selected the external system RC oscillator requires that a resis-
while various clock source options for the Watchdog
tor, with a value between 24kW and 1MW, is connected
Timer, are provided for maximum flexibility. All oscillator
between OSC1 and VDD, and a 470pF capacitor is con-
options are selected through the configuration options.
nected to ground. Although this is a cost effective oscil-
lator configuration, the oscillation frequency can vary
System Clock Configurations
with VDD, temperature and process variations and is
There are two methods of generating the system clock, therefore not suitable for applications where timing is
using an external crystal/ceramic oscillator or an exter- critical or where accurate oscillator frequencies are re-
nal RC network. The chosen method is selected through quired. For the value of the external resistor ROSC refer
the configuration options. to the Appendix section for typical RC Oscillator vs.
Temperature and VDD characteristics graphics.
System Crystal/Ceramic Oscillator
V D D
After selecting the correct oscillator configuration op-
tion, for most crystal oscillator configurations, the simple
R O S C
connection of a crystal across OSC1 and OSC2 will cre-
ate the necessary phase shift and feedback for oscilla- O S C 1
tion, without requiring external capacitors. However, for 4 7 0 p F
some crystal types and frequencies, to ensure oscilla-
tion, it may be necessary to add two small value capaci-
fS Y S /4 N M O S O p e n D r a in O S C 2
tors, C1 and C2. Using a ceramic resonator will usually
require two small value capacitors, C1 and C2, to be RC Oscillator
connected as shown for oscillation to occur. The values
of C1 and C2 should be selected in consultation with the
Note that it is the only microcontroller internal circuitry
crystal or resonator manufacturer's specification. In
together with the external resistor, that determine the
most applications, resistor R1 is not required, however
frequency of the oscillator. The external capacitor
for those applications where the LVR function is not
shown on the diagram does not influence the frequency
used, R1 may be necessary to ensure the oscillator
of oscillation. The external capacitor is added to improve
stops running when VDD falls below its operating range.
oscillator stability, especially if the open-drain OSC2
C 1 output is utilised in the application circuit.
O S C 1
Watchdog Timer Oscillator
R 1
O S C 2 The WDT oscillator is a fully integrated free running RC
C 2 oscillator with a typical period of 65ms at 5V, requiring no
external components. It is selected via configuration op-
Crystal/Ceramic Oscillator tion. If selected, when the device enters the Power
Down Mode, the system clock will stop running, how-
More information regarding the oscillator is located in ever the WDT oscillator will continue to run and keep the
Application Note HA0075E on the Holtek website. watchdog function active. However, as the WDT will
consume a certain amount of power when in the Power
Down Mode, for low power applications, it may be desir-
able to disable the WDT oscillator by configuration op-
tion.

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Power Down Mode and Wake-up

Power Down Mode Wake-up
All of the Holtek microcontrollers have the ability to enter After the system enters the Power Down Mode, it can be
a Power Down Mode, also known as the HALT Mode or woken up from one of various sources listed as follows:
Sleep Mode. When the device enters this mode, the nor- · An external reset
mal operating current, will be reduced to an extremely · An external falling edge on Port A
low standby current level. This occurs because when
· A system interrupt
the device enters the Power Down Mode, the system
· A WDT overflow
oscillator is stopped which reduces the power consump-
tion to extremely low levels, however, as the device If the system is woken up by an external reset, the de-
maintains its present internal condition, it can be woken vice will experience a full system reset, however, if the
up at a later stage and continue running, without requir- device is woken up by a WDT overflow, a Watchdog
ing a full reset. This feature is extremely important in ap- Timer reset will be initiated. Although both of these
plication areas where the MCU must have its power wake-up methods will initiate a reset operation, the ac-
supply constantly maintained to keep the device in a tual source of the wake-up can be determined by exam-
known condition but where the power supply capacity is ining the TO and PDF flags. The PDF flag is cleared by a
limited such as in battery applications. system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
Entering the Power Down Mode instruction. The TO flag is set if a WDT time-out occurs,
There is only one way for the device to enter the Power and causes a wake-up that only resets the Program
Down Mode and that is to execute the ²HALT² instruc- Counter and Stack Pointer, the other flags remain in
tion in the application program. When this instruction is their original status.
executed, the following will occur: Each pin on Port A can be setup via an individual config-
· The system oscillator will stop running and the appli- uration option to permit a negative transition on the pin
cation program will stop at the ²HALT² instruction. to wake-up the system. When a Port A pin wake-up oc-
· The Data Memory contents and registers will maintain curs, the program will resume execution at the instruc-
their present condition. tion following the ²HALT² instruction.
· The WDT will be cleared and resume counting if the
If the system is woken up by an interrupt, then two possi-
WDT clock source is selected to come from the WDT
ble situations may occur. The first is where the related
oscillator. The WDT will stop if its clock source origi-
interrupt is disabled or the interrupt is enabled but the
nates from the system clock.
stack is full, in which case the program will resume exe-
· The I/O ports will maintain their present condition.
cution at the instruction following the ²HALT² instruction.
· In the status register, the Power Down flag, PDF, will
In this situation, the interrupt which woke-up the device
be set and the Watchdog time-out flag, TO, will be will not be immediately serviced, but will rather be ser-
cleared.
viced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
Standby Current Considerations
where the related interrupt is enabled and the stack is
As the main reason for entering the Power Down Mode not full, in which case the regular interrupt response
is to keep the current consumption of the MCU to as low takes place. If an interrupt request flag is set to ²1² be-
a value as possible, perhaps only in the order of several fore entering the Power Down Mode, the wake-up func-
micro-amps, there are other considerations which must tion of the related interrupt will be disabled.
also be taken into account by the circuit designer if the
power consumption is to be minimized. Special atten- No matter what the source of the wake-up event is, once
tion must be made to the I/O pins on the device. All a wake-up situation occurs, a time period equal to 1024
high-impedance input pins must be connected to either system clock periods will be required before normal sys-
a fixed high or low level as any floating input pins could tem operation resumes. However, if the wake-up has
create internal oscillations and result in increased cur- originated due to an interrupt, the actual interrupt sub-
rent consumption. Care must also be taken with the routine execution will be delayed by an additional one or
loads, which are connected to I/Os, which are setup as more cycles. If the wake-up results in the execution of
outputs. These should be placed in a condition in which the next instruction following the ²HALT² instruction, this
minimum current is drawn or connected only to external will be executed immediately after the 1024 system
circuits that do not draw current, such as other CMOS clock period delay has ended.
inputs. Also note that additional standby current will also
be required if the configuration options have enabled the
Watchdog Timer internal oscillator.

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 HT48F06E/HT48F10E/HT48F30E

Watchdog Timer
The Watchdog Timer is provided to prevent program tem cannot be restarted by the WDT and can only be re-
malfunctions or sequences from jumping to unknown lo- started using external signals. For systems that operate
cations, due to certain uncontrollable external events in noisy environments, using the internal WDT oscillator
such as electrical noise. It operates by providing a de- is therefore the recommended choice.
vice reset when the WDT counter overflows. The WDT
Under normal program operation, a WDT time-out will
clock is supplied by one of two sources selected by con-
initialise a device reset and set the status bit TO. How-
figuration option: its own self-contained dedicated inter-
ever, if the system is in the Power Down Mode, when a
nal WDT oscillator, or the instruction clock which is the WDT time-out occurs, only the Program Counter and
system clock divided by 4. Note that if the WDT configu- Stack Pointer will be reset. Three methods can be
ration option has been disabled, then any instruction re- adopted to clear the contents of the WDT and the WDT
lating to its operation will result in no operation. prescaler. The first is an external hardware reset, which
The internal WDT oscillator has an approximate period means a low level on the RES pin, the second is using
of 65ms at a supply voltage of 5V. If selected, it is first di- the watchdog software instructions and the third is via a
vided by 256 via an 8-stage counter to give a nominal ²HALT² instruction.
period of 17ms. Note that this period can vary with VDD,
There are two methods of using software instructions to
temperature and process variations. For longer WDT
clear the Watchdog Timer, one of which must be chosen
time-out periods the WDT prescaler can be utilized. By
by configuration option. The first option is to use the sin-
writing the required value to bits 0, 1 and 2 of the WDTS
gle ²CLR WDT² instruction while the second is to use
register, known as WS0, WS1 and WS2, longer time-out
the two commands ²CLR WDT1² and ²CLR WDT2². For
periods can be achieved. With WS0, WS1 and WS2 all
the first option, a simple execution of ²CLR WDT² will
equal to 1, the division ratio is 1:128 which gives a maxi-
mum time-out period of about 2.1s. clear the WDT while for the second option, both ²CLR
WDT1² and ²CLR WDT2² must both be executed to
A configuration option can select the instruction clock,
successfully clear the WDT. Note that for this second
which is the system clock divided by 4, as the WDT clock
option, if ²CLR WDT1² is used to clear the WDT, succes-
source instead of the internal WDT oscillator. If the in-
sive executions of this instruction will have no effect,
struction clock is used as the clock source, it must be
only the execution of a ²CLR WDT2² instruction will
noted that when the system enters the Power Down
clear the WDT. Similarly, after the ²CLR WDT2² instruc-
Mode, as the system clock is stopped, then the WDT
clock source will also be stopped. Therefore the WDT tion has been executed, only a successive ²CLR WDT1²
will lose its protecting purposes. In such cases the sys- instruction can clear the Watchdog Timer.

b 7 b 0
W S 2 W S 1 W S 0 W D T S R e g is te r
W D T p r e s c a le r r a te s e le c t
W S 2 W S 1 W S 0 W D T R a te
0 0 0 1 :1
0 0 1 1 :2
0 1 0 1 :4
0 1 1 1 :8
1 0 0 1 :1 6
1 0 1 1 :3 2
1 1 0 1 :6 4
1 1 1 1 :1 2 8
N o t u s e d

Watchdog Timer Register

C L R W D T 1 F la g C le a r W D T T y p e
C L R W D T 2 F la g C o n fig u r a tio n O p tio n

1 o r 2 In s tr u c tio n s
C L R
C L R
fS Y S /4 W D T C lo c k S o u r c e 8 - b it C o u n te r
7 - b it P r e s c a le r
W D T O s c illa to r C o n fig u r a tio n O p tio n (¸ 2 5 6 )

W D T C lo c k S o u r c e
8 -to -1 M U X W S 0 ~ W S 2

W D T T im e - o u t

Watchdog Timer

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 HT48F06E/HT48F10E/HT48F30E

Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the Flash Type Program Mem-
ory device during the programming process. During the development process, these options are selected using the
HT-IDE software development tools. As these options are programmed into the device using the hardware program-
ming tools, once they are selected they cannot be changed later by the application software.
All options must be defined for proper system function, the details of which are shown in the table.

No. Options
1 Watchdog Timer: enable or disable
2 Watchdog Timer clock source: WDT oscillator or fSYS/4
3 CLRWDT instructions: 1 or 2 instructions
4 PA0~PA7: wake-up enable or disable (bit option)
5 PA, PB and PC: pull-high enable or disable (port numbers are device dependent)
6 PA input type: CMOS or Schmitt Trigger (HT48F06E excepted)
7 Buzzer function: enable or normal I/O
8 System oscillator: Crystal or RC
9 LVR function: enable or disable

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 HT48F06E/HT48F10E/HT48F30E

Application Circuits
The following application circuit although based around the HT48F30E device equally apply to the other devices.

V D D

V D D
P A 0 ~ P A 7 V D D

R e s e t P B 2 ~ P B 7
1 0 0 k W
C ir c u it R O S C
R C S y s te m O s c illa to r
P C 0 ~ P C 5
0 .1 m F O S C 1 2 4 k W < R O S C < 1 M W
R E S 4 7 0 p F
P B 0 /B Z
O S C 2
0 .1 m F P B 1 /B Z N M O S o p e n d r a in
T M R 0 C 1
O S C 1 C r y s ta l/C e ra m ic
V S S T M R 1 S y s te m O s c illa to r
R 1
P G 0 /IN T C 2 F o r d e ta ils re g a r d in g
O S C O S C 1 O S C 2 C 1 , C 2 a n d R 1 s e e
C ir c u it O s c illa to r S e c tio n
O S C 2

H T 4 8 F 3 0 E O S C C ir c u it

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Instruction Set
Introduction subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to en-
Central to the successful operation of any
sure correct handling of carry and borrow data when re-
microcontroller is its instruction set, which is a set of pro-
sults exceed 255 for addition and less than 0 for
gram instruction codes that directs the microcontroller to
subtraction. The increment and decrement instructions
perform certain operations. In the case of Holtek
INC, INCA, DEC and DECA provide a simple means of
microcontrollers, a comprehensive and flexible set of
increasing or decreasing by a value of one of the values
over 60 instructions is provided to enable programmers
in the destination specified.
to implement their application with the minimum of pro-
gramming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
The standard logical operations such as AND, OR, XOR
codes, they have been subdivided into several func-
and CPL all have their own instruction within the Holtek
tional groupings.
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
Instruction Timing
through the Accumulator which may involve additional
Most instructions are implemented within one instruc- programming steps. In all logical data operations, the
tion cycle. The exceptions to this are branch, call, or ta- zero flag may be set if the result of the operation is zero.
ble read instructions where two instruction cycles are Another form of logical data manipulation comes from
required. One instruction cycle is equal to 4 system the rotate instructions such as RR, RL, RRC and RLC
clock cycles, therefore in the case of an 8MHz system which provide a simple means of rotating one bit right or
oscillator, most instructions would be implemented left. Different rotate instructions exist depending on pro-
within 0.5ms and branch or call instructions would be im- gram requirements. Rotate instructions are useful for
plemented within 1ms. Although instructions which re- serial port programming applications where data can be
quire one more cycle to implement are generally limited rotated from an internal register into the Carry bit from
to the JMP, CALL, RET, RETI and table read instruc- where it can be examined and the necessary serial bit
tions, it is important to realize that any other instructions set high or low. Another application where rotate data
which involve manipulation of the Program Counter Low operations are used is to implement multiplication and
register or PCL will also take one more cycle to imple- division calculations.
ment. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one Branches and Control Transfer
more cycle will be required. Examples of such instruc- Program branching takes the form of either jumps to
tions would be ²CLR PCL² or ²MOV PCL, A². For the specified locations using the JMP instruction or to a sub-
case of skip instructions, it must be noted that if the re- routine using the CALL instruction. They differ in the
sult of the comparison involves a skip operation then sense that in the case of a subroutine call, the program
this will also take one more cycle, if no skip is involved must return to the instruction immediately when the sub-
then only one cycle is required. routine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
Moving and Transferring Data
the program to jump back to the address right after the
The transfer of data within the microcontroller program CALL instruction. In the case of a JMP instruction, the
is one of the most frequently used operations. Making program simply jumps to the desired location. There is
use of three kinds of MOV instructions, data can be no requirement to jump back to the original jumping off
transferred from registers to the Accumulator and point as in the case of the CALL instruction. One special
vice-versa as well as being able to move specific imme- and extremely useful set of branch instructions are the
diate data directly into the Accumulator. One of the most conditional branches. Here a decision is first made re-
important data transfer applications is to receive data garding the condition of a certain data memory or indi-
from the input ports and transfer data to the output ports. vidual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
Arithmetic Operations jump to the following instruction. These instructions are
The ability to perform certain arithmetic operations and the key to decision making and branching within the pro-
data manipulation is a necessary feature of most gram perhaps determined by the condition of certain in-
microcontroller applications. Within the Holtek put switches or by the condition of internal data bits.
microcontroller instruction set are a range of add and

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 HT48F06E/HT48F10E/HT48F30E

Bit Operations Other Operations

The ability to provide single bit operations on Data Mem- In addition to the above functional instructions, a range
ory is an extremely flexible feature of all Holtek of other instructions also exist such as the ²HALT² in-
microcontrollers. This feature is especially useful for struction for Power-down operations and instructions to
output port bit programming where individual bits or port control the operation of the Watchdog Timer for reliable
pins can be directly set high or low using either the ²SET program operations under extreme electric or electro-
[m].i² or ²CLR [m].i² instructions respectively. The fea- magnetic environments. For their relevant operations,
ture removes the need for programmers to first read the refer to the functional related sections.
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port Instruction Set Summary
with the correct new data. This read-modify-write pro- The following table depicts a summary of the instruction
cess is taken care of automatically when these bit oper- set categorised according to function and can be con-
ation instructions are used. sulted as a basic instruction reference using the follow-
ing listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using regis-
x: Bits immediate data
ters. However, when working with large amounts of
fixed data, the volume involved often makes it inconve- m: Data Memory address
nient to store the fixed data in the Data Memory. To over- A: Accumulator
come this problem, Holtek microcontrollers allow an i: 0~7 number of bits
area of Program Memory to be setup as a table where addr: Program memory address
data can be directly stored. A set of easy to use instruc-
tions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.

Mnemonic Description Cycles Flag Affected

Arithmetic
ADD A,[m] Add Data Memory to ACC 1 Z, C, AC, OV
ADDM A,[m] Add ACC to Data Memory 1Note Z, C, AC, OV
ADD A,x Add immediate data to ACC 1 Z, C, AC, OV
ADC A,[m] Add Data Memory to ACC with Carry 1 Z, C, AC, OV
ADCM A,[m] Add ACC to Data memory with Carry 1Note Z, C, AC, OV
SUB A,x Subtract immediate data from the ACC 1 Z, C, AC, OV
SUB A,[m] Subtract Data Memory from ACC 1 Z, C, AC, OV
SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z, C, AC, OV
SBC A,[m] Subtract Data Memory from ACC with Carry 1 Z, C, AC, OV
SBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory 1Note Z, C, AC, OV
DAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note C
Logic Operation
AND A,[m] Logical AND Data Memory to ACC 1 Z
OR A,[m] Logical OR Data Memory to ACC 1 Z
XOR A,[m] Logical XOR Data Memory to ACC 1 Z
ANDM A,[m] Logical AND ACC to Data Memory 1Note Z
ORM A,[m] Logical OR ACC to Data Memory 1Note Z
XORM A,[m] Logical XOR ACC to Data Memory 1Note Z
AND A,x Logical AND immediate Data to ACC 1 Z
OR A,x Logical OR immediate Data to ACC 1 Z
XOR A,x Logical XOR immediate Data to ACC 1 Z
CPL [m] Complement Data Memory 1Note Z
CPLA [m] Complement Data Memory with result in ACC 1 Z
Increment & Decrement
INCA [m] Increment Data Memory with result in ACC 1 Z
INC [m] Increment Data Memory 1Note Z
DECA [m] Decrement Data Memory with result in ACC 1 Z
DEC [m] Decrement Data Memory 1Note Z

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 HT48F06E/HT48F10E/HT48F30E

Mnemonic Description Cycles Flag Affected

Rotate
RRA [m] Rotate Data Memory right with result in ACC 1 None
RR [m] Rotate Data Memory right 1Note None
RRCA [m] Rotate Data Memory right through Carry with result in ACC 1 C
RRC [m] Rotate Data Memory right through Carry 1Note C
RLA [m] Rotate Data Memory left with result in ACC 1 None
RL [m] Rotate Data Memory left 1Note None
RLCA [m] Rotate Data Memory left through Carry with result in ACC 1 C
RLC [m] Rotate Data Memory left through Carry 1Note C
Data Move
MOV A,[m] Move Data Memory to ACC 1 None
MOV [m],A Move ACC to Data Memory 1Note None
MOV A,x Move immediate data to ACC 1 None
Bit Operation
CLR [m].i Clear bit of Data Memory 1Note None
SET [m].i Set bit of Data Memory 1Note None
Branch
JMP addr Jump unconditionally 2 None
SZ [m] Skip if Data Memory is zero 1Note None
SZA [m] Skip if Data Memory is zero with data movement to ACC 1note None
SZ [m].i Skip if bit i of Data Memory is zero 1Note None
SNZ [m].i Skip if bit i of Data Memory is not zero 1Note None
SIZ [m] Skip if increment Data Memory is zero 1Note None
SDZ [m] Skip if decrement Data Memory is zero 1Note None
SIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note None
SDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note None
CALL addr Subroutine call 2 None
RET Return from subroutine 2 None
RET A,x Return from subroutine and load immediate data to ACC 2 None
RETI Return from interrupt 2 None
Table Read
TABRDC [m] Read table (current page) to TBLH and Data Memory 2Note None
TABRDL [m] Read table (last page) to TBLH and Data Memory 2Note None
Miscellaneous
NOP No operation 1 None
CLR [m] Clear Data Memory 1Note None
SET [m] Set Data Memory 1Note None
CLR WDT Clear Watchdog Timer 1 TO, PDF
CLR WDT1 Pre-clear Watchdog Timer 1 TO, PDF
CLR WDT2 Pre-clear Watchdog Timer 1 TO, PDF
SWAP [m] Swap nibbles of Data Memory 1Note None
SWAPA [m] Swap nibbles of Data Memory with result in ACC 1 None
HALT Enter power down mode 1 TO, PDF

Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.

Rev. 1.00 45 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Instruction Definition

ADC A,[m] Add Data Memory to ACC with Carry

Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation ACC ¬ ACC + [m] + C
Affected flag(s) OV, Z, AC, C

ADCM A,[m] Add ACC to Data Memory with Carry

Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation [m] ¬ ACC + [m] + C
Affected flag(s) OV, Z, AC, C

ADD A,[m] Add Data Memory to ACC

Description The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation ACC ¬ ACC + [m]
Affected flag(s) OV, Z, AC, C

ADD A,x Add immediate data to ACC

Description The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation ACC ¬ ACC + x
Affected flag(s) OV, Z, AC, C

ADDM A,[m] Add ACC to Data Memory

Description The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation [m] ¬ ACC + [m]
Affected flag(s) OV, Z, AC, C

AND A,[m] Logical AND Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-
eration. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²AND² [m]
Affected flag(s) Z

AND A,x Logical AND immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²AND² x
Affected flag(s) Z

ANDM A,[m] Logical AND ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-
eration. The result is stored in the Data Memory.
Operation [m] ¬ ACC ²AND² [m]
Affected flag(s) Z

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 HT48F06E/HT48F10E/HT48F30E

CALL addr Subroutine call

Description Unconditionally calls a subroutine at the specified address. The Program Counter then in-
crements by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruc-
tion.
Operation Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s) None

CLR [m] Clear Data Memory

Description Each bit of the specified Data Memory is cleared to 0.
Operation [m] ¬ 00H
Affected flag(s) None

CLR [m].i Clear bit of Data Memory

Description Bit i of the specified Data Memory is cleared to 0.
Operation [m].i ¬ 0
Affected flag(s) None

CLR WDT Clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared.
Operation WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s) TO, PDF

CLR WDT1 Pre-clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s) TO, PDF

CLR WDT2 Pre-clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s) TO, PDF

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 HT48F06E/HT48F10E/HT48F30E

CPL [m] Complement Data Memory

Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation [m] ¬ [m]
Affected flag(s) Z

CPLA [m] Complement Data Memory with result in ACC

Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC ¬ [m]
Affected flag(s) Z

DAA [m] Decimal-Adjust ACC for addition with result in Data Memory
Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation [m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s) C

DEC [m] Decrement Data Memory

Description Data in the specified Data Memory is decremented by 1.
Operation [m] ¬ [m] - 1
Affected flag(s) Z

DECA [m] Decrement Data Memory with result in ACC

Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-
mulator. The contents of the Data Memory remain unchanged.
Operation ACC ¬ [m] - 1
Affected flag(s) Z

HALT Enter power down mode

Description This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation TO ¬ 0
PDF ¬ 1
Affected flag(s) TO, PDF

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 HT48F06E/HT48F10E/HT48F30E

INC [m] Increment Data Memory

Description Data in the specified Data Memory is incremented by 1.
Operation [m] ¬ [m] + 1
Affected flag(s) Z

INCA [m] Increment Data Memory with result in ACC

Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-
lator. The contents of the Data Memory remain unchanged.
Operation ACC ¬ [m] + 1
Affected flag(s) Z

JMP addr Jump unconditionally

Description The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation Program Counter ¬ addr
Affected flag(s) None

MOV A,[m] Move Data Memory to ACC

Description The contents of the specified Data Memory are copied to the Accumulator.
Operation ACC ¬ [m]
Affected flag(s) None

MOV A,x Move immediate data to ACC

Description The immediate data specified is loaded into the Accumulator.
Operation ACC ¬ x
Affected flag(s) None

MOV [m],A Move ACC to Data Memory

Description The contents of the Accumulator are copied to the specified Data Memory.
Operation [m] ¬ ACC
Affected flag(s) None

NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation No operation
Affected flag(s) None

OR A,[m] Logical OR Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-
ation. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²OR² [m]
Affected flag(s) Z

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OR A,x Logical OR immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-
eration. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²OR² x
Affected flag(s) Z

ORM A,[m] Logical OR ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-
ation. The result is stored in the Data Memory.
Operation [m] ¬ ACC ²OR² [m]
Affected flag(s) Z

RET Return from subroutine

Description The Program Counter is restored from the stack. Program execution continues at the re-
stored address.
Operation Program Counter ¬ Stack
Affected flag(s) None

RET A,x Return from subroutine and load immediate data to ACC
Description The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation Program Counter ¬ Stack
ACC ¬ x
Affected flag(s) None

RETI Return from interrupt

Description The Program Counter is restored from the stack and the interrupts are re-enabled by set-
ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed be-
fore returning to the main program.
Operation Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s) None

RL [m] Rotate Data Memory left

Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation [m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s) None

RLA [m] Rotate Data Memory left with result in ACC

Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-
main unchanged.
Operation ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s) None

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 HT48F06E/HT48F10E/HT48F30E

RLC [m] Rotate Data Memory left through Carry

Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation [m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s) C

RLCA [m] Rotate Data Memory left through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s) C

RR [m] Rotate Data Memory right

Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation [m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s) None

RRA [m] Rotate Data Memory right with result in ACC

Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-
tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s) None

RRC [m] Rotate Data Memory right through Carry

Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation [m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s) C

RRCA [m] Rotate Data Memory right through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s) C

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 HT48F06E/HT48F10E/HT48F30E

SBC A,[m] Subtract Data Memory from ACC with Carry

Description The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation ACC ¬ ACC - [m] - C
Affected flag(s) OV, Z, AC, C

SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory
Description The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation [m] ¬ ACC - [m] - C
Affected flag(s) OV, Z, AC, C

SDZ [m] Skip if decrement Data Memory is 0

Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation [m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s) None

SDZA [m] Skip if decrement Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s) None

SET [m] Set Data Memory

Description Each bit of the specified Data Memory is set to 1.
Operation [m] ¬ FFH
Affected flag(s) None

SET [m].i Set bit of Data Memory

Description Bit i of the specified Data Memory is set to 1.
Operation [m].i ¬ 1
Affected flag(s) None

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 HT48F06E/HT48F10E/HT48F30E

SIZ [m] Skip if increment Data Memory is 0

Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation [m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s) None

SIZA [m] Skip if increment Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s) None

SNZ [m].i Skip if bit i of Data Memory is not 0

Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation Skip if [m].i ¹ 0
Affected flag(s) None

SUB A,[m] Subtract Data Memory from ACC

Description The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation ACC ¬ ACC - [m]
Affected flag(s) OV, Z, AC, C

SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory
Description The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation [m] ¬ ACC - [m]
Affected flag(s) OV, Z, AC, C

SUB A,x Subtract immediate data from ACC

Description The immediate data specified by the code is subtracted from the contents of the Accumu-
lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-
tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation ACC ¬ ACC - x
Affected flag(s) OV, Z, AC, C

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 HT48F06E/HT48F10E/HT48F30E

SWAP [m] Swap nibbles of Data Memory

Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation [m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s) None

SWAPA [m] Swap nibbles of Data Memory with result in ACC

Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s) None

SZ [m] Skip if Data Memory is 0

Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruc-
tion.
Operation Skip if [m] = 0
Affected flag(s) None

SZA [m] Skip if Data Memory is 0 with data movement to ACC

Description The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-
tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation ACC ¬ [m]
Skip if [m] = 0
Affected flag(s) None

SZ [m].i Skip if bit i of Data Memory is 0

Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation Skip if [m].i = 0
Affected flag(s) None

TABRDC [m] Read table (current page) to TBLH and Data Memory
Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation [m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s) None

TABRDL [m] Read table (last page) to TBLH and Data Memory
Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation [m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s) None

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 HT48F06E/HT48F10E/HT48F30E

XOR A,[m] Logical XOR Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-
eration. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²XOR² [m]
Affected flag(s) Z

XORM A,[m] Logical XOR ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-
eration. The result is stored in the Data Memory.
Operation [m] ¬ ACC ²XOR² [m]
Affected flag(s) Z

XOR A,x Logical XOR immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²XOR² x
Affected flag(s) Z

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 HT48F06E/HT48F10E/HT48F30E

Package Information
16-pin NSOP (150mil) Outline Dimensions

1 6 9
A B
1 8

C '
G
D H

E F a

Dimensions in mil
Symbol
Min. Nom. Max.
A 228 ¾ 244
B 149 ¾ 157
C 14 ¾ 20
C¢ 386 ¾ 394
D 53 ¾ 69
E ¾ 50 ¾
F 4 ¾ 10
G 22 ¾ 28
H 4 ¾ 12
a 0° ¾ 10°

Rev. 1.00 56 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

18-pin DIP (300mil) Outline Dimensions

1 8 1 0
B
1 9

D
a
E G I
F

Dimensions in mil
Symbol
Min. Nom. Max.
A 895 ¾ 915
B 240 ¾ 260
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 335 ¾ 375
a 0° ¾ 15°

Rev. 1.00 57 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

18-pin SOP (300mil) Outline Dimensions

1 8 1 0

A B

1 9

C '
G
D H

E F a

Dimensions in mil
Symbol
Min. Nom. Max.
A 394 ¾ 419
B 290 ¾ 300
C 14 ¾ 20
C¢ 447 ¾ 460
D 92 ¾ 104
E ¾ 50 ¾
F 4 ¾ ¾
G 32 ¾ 38
H 4 ¾ 12
a 0° ¾ 10°

Rev. 1.00 58 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

20-pin SSOP (209mil) Outline Dimensions

2 0 1 1

A B

1 1 0

C '
G
D H

E F a

Dimensions in mil
Symbol
Min. Nom. Max.
A 291 ¾ 323
B 196 ¾ 220
C 9 ¾ 15
C¢ 271 ¾ 295
D 65 ¾ 73
E ¾ 25.59 ¾
F 4 ¾ 10
G 26 ¾ 34
H 4 ¾ 8
a 0° ¾ 8°

Rev. 1.00 59 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

24-pin SKDIP (300mil) Outline Dimensions

2 4 1 3
B
1 1 2

D
a I
E F G

Dimensions in mil
Symbol
Min. Nom. Max.
A 1235 ¾ 1265

B 255 ¾ 265

C 125 ¾ 135

D 125 ¾ 145

E 16 ¾ 20

F 50 ¾ 70

G ¾ 100 ¾
H 295 ¾ 315

I 345 ¾ 360

a 0° ¾ 15°

Rev. 1.00 60 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

24-pin SOP (300mil) Outline Dimensions

2 4 1 3

A B

1 1 2

C '
G
D H

E F a

Dimensions in mil
Symbol
Min. Nom. Max.
A 394 ¾ 419

B 290 ¾ 300

C 14 ¾ 20

C¢ 590 ¾ 614

D 92 ¾ 104

E ¾ 50 ¾
F 4 ¾ ¾
G 32 ¾ 38

H 4 ¾ 12

a 0° ¾ 10°

Rev. 1.00 61 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

28-pin SKDIP (300mil) Outline Dimensions

2 8 1 5
B
1 1 4

D
a I
E F G

Dimensions in mil
Symbol
Min. Nom. Max.
A 1375 ¾ 1395

B 278 ¾ 298

C 125 ¾ 135

D 125 ¾ 145

E 16 ¾ 20

F 50 ¾ 70

G ¾ 100 ¾
H 295 ¾ 315

I 330 ¾ 375

a 0° ¾ 15°

Rev. 1.00 62 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

28-pin SOP (300mil) Outline Dimensions

2 8 1 5

A B

1 1 4

C '
G
D H

E F a

Dimensions in mil
Symbol
Min. Nom. Max.
A 394 ¾ 419

B 290 ¾ 300

C 14 ¾ 20

C¢ 697 ¾ 713

D 92 ¾ 104

E ¾ 50 ¾
F 4 ¾ ¾
G 32 ¾ 38

H 4 ¾ 12

a 0° ¾ 10°

Rev. 1.00 63 September 10, 2007

 HT48F06E/HT48F10E/HT48F30E

Product Tape and Reel Specifications

Reel Dimensions

D
T 2

A B C

T 1

SOP 16N (150mil)

Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1
B Reel Inner Diameter 62±1.5
13+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2±0.5
16.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 22.2±0.2

SOP 18W

Symbol Description Dimensions in mm

A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 62±1.5
13.0+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2.0±0.5
24.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 30.2±0.2

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SSOP 20N (209mil)

Symbol Description Dimensions in mm

A Reel Outer Diameter 330±1
B Reel Inner Diameter 62±1.5
13+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2±0.5
16.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 22.2±0.2

SOP 24W

Symbol Description Dimensions in mm

A Reel Outer Diameter 330±1
B Reel Inner Diameter 62±1.5
13+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2±0.5
24.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 30.2±0.2

SOP 28W (300mil)

Symbol Description Dimensions in mm

A Reel Outer Diameter 330±1
B Reel Inner Diameter 62±1.5
13+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2±0.5
24.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 30.2±0.2

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Carrier Tape Dimensions

P 0 P 1
D t

F
W
B 0
C

D 1 P
K 0

A 0

SOP 16N (150mil)

Symbol Description Dimensions in mm
W Carrier Tape Width 16±0.3
P Cavity Pitch 8±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 7.5±0.1
D Perforation Diameter 1.55+0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4±0.1
P1 Cavity to Perforation (Length Direction) 2±0.1
A0 Cavity Length 6.5±0.1
B0 Cavity Width 10.3±0.1
K0 Cavity Depth 2.1±0.1
t Carrier Tape Thickness 0.3±0.05
C Cover Tape Width 13.3

SOP 18W

Symbol Description Dimensions in mm

24.0+0.3
W Carrier Tape Width
-0.1
P Cavity Pitch 16.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 11.5±0.1
D Perforation Diameter 1.5±0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 10.9±0.1
B0 Cavity Width 12.0±0.1
K0 Cavity Depth 2.8±0.1
t Carrier Tape Thickness 0.3±0.05
C Cover Tape Width 21.3

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SSOP 20N (209mil)

Symbol Description Dimensions in mm

16+0.3
W Carrier Tape Width
-0.1
P Cavity Pitch 12±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 7.5±0.1
D Perforation Diameter 1.5+0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4±0.1
P1 Cavity to Perforation (Length Direction) 2±0.1
A0 Cavity Length 7.1±0.1
B0 Cavity Width 7.2±0.1
K0 Cavity Depth 2±0.1
t Carrier Tape Thickness 0.3±0.05
C Cover Tape Width 13.3

SOP 24W

Symbol Description Dimensions in mm

W Carrier Tape Width 24±0.3
P Cavity Pitch 12±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 11.5±0.1
D Perforation Diameter 1.55+0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4±0.1
P1 Cavity to Perforation (Length Direction) 2±0.1
A0 Cavity Length 10.9±0.1
B0 Cavity Width 15.9±0.1
K0 Cavity Depth 3.1±0.1
t Carrier Tape Thickness 0.35±0.05
C Cover Tape Width 21.3

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SOP 28W (300mil)

Symbol Description Dimensions in mm

W Carrier Tape Width 24±0.3
P Cavity Pitch 12±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 11.5±0.1
D Perforation Diameter 1.5+0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4±0.1
P1 Cavity to Perforation (Length Direction) 2±0.1
A0 Cavity Length 10.85±0.1
B0 Cavity Width 18.34±0.1
K0 Cavity Depth 2.97±0.1
t Carrier Tape Thickness 0.35±0.01
C Cover Tape Width 21.3

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Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125

Holtek Semiconductor Inc. (Chengdu Sales Office)

709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591

Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com

Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.

Rev. 1.00 69 September 10, 2007