1

Module 1 Notes of VLSI Design & Testing

VLSI Design & Testing (BEC602)

Notes
Module 1. Introduction
1.1 A Brief History
Invention of the Transistor
• Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable
• 1947: first point contact transistor
– John Bardeen and Walter
Brattain at Bell Labs
– See Crystal Fire
by Riordan, Hoddeson

FIGURE 1.2 (a) First transistor (Property of AT&T Archives. Reprinted with permission of AT&T.)

• Transistor- is a resistor or semiconductor device which can amplify electrical signals as they are transferred through it,
composed of cold solid substances
• Invention of the transistor earned Nobel Prize in Physics in the year 1956 for Bardeen, Brattain and William Shockley.
• MOSFET – The basic principle by J. Lilinfeld – 1925.
• Modern structure – by O. Heil in 1935. Experiments led to the invention of BJT..
• Frank Walnlass at fairchild described logic gates using MOSFETs in 1963. These gates dissipated nanowatts in
comparison with milli watts with Bipolar gates.
• In 1958, Jack Kilby built first Integrated Circuit flipflop with two transistors at Texas Instruments.
• Kilby received Nobel Prize in Physics in 2000 for the invention of Integrated Circuit

(b)first integrated circuit (Courtesy of Texas Instruments.

• In 2003, Intel Pentium 4 microprocessor had 55 million transistors and 512 Mbit DRAM.
• In 2010 Intel Core i7 mprocessor
• 2.3 billion transistors,
64 Gb Flash memory
• > 16 billion transistors
Moore’s Law
In 1965, Gordon Moore observed that plotting the number of transistors that can be most economically
manufactured on a chip gives a straight line on a semilogarithmic scale [Moore65]. At the time, he found transistor
count doubling every 18 months. This obser- vation has been called Moore’s Law and has become a self-fulfilling
prophecy. Figure 1.4 shows that the number of transistors in Intel microprocessors has doubled every 26 months
since the invention of the 4004. Moore’s Law is driven primarily by scaling down the size of transistors and, to a
minor extent, by building larger chips.
Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi
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Module 1 Notes of VLSI Design & Testing

1.2 MOS Transistors

Silicon (Si), a semiconductor, forms the basic starting material for most integrated circuits [Tsividis99]. Pure silicon
consists of a three-dimensional lattice of atoms. Silicon is a Group IV element, so it forms covalent bonds with four
adjacent atoms, as shown in Fig- ure 1.7(a). The lattice is shown in the plane for ease of drawing, but it actually
forms a cubic crystal. As all of its valence electrons are involved in chemical bonds, pure silicon is a poor conductor. The
conductivity can be raised by introducing small amounts of impurities, called dopants, into the silicon lattice. A
dopant from Group V of the periodic table, such as arsenic, has five valence electrons. It replaces a silicon atom in
the lattice and still bonds to four neighbors, so the fifth valence electron is loosely bound to the arsenic atom, as
shown in Figure 1.7(b). Thermal vibration of the lattice at room temperature is enough to set the electron free to
move, leaving a positively charged As+ ion and a free electron. The free electron can carry current so the
conductivity is higher.

Each transistor consists of a stack of the conducting gate, an insulating layer of silicon dioxide (SiO2, better
known as glass), and the silicon wafer, also called the substrate, body, or bulk. Gates of early transistors
were built from metal, so the stack was called metal- oxide-semiconductor, or MOS. Since the 1970s, the
gate has been formed from polycrys- talline silicon (polysilicon), but the name stuck. (Interestingly, metal
gates reemerged in 2007 to solve materials problems in advanced manufacturing processes.)
An nMOS tran- sistor is built with a p-type body and has regions of n-type semiconductor adjacent to thegate
called the source and drain. They are physically equivalent and for now we will regard them as interchangeable.
The body is typically grounded.
A pMOS transistor is just the opposite, consisting of p-type source and drain regions with an n-type body. In
a CMOS technology with both flavors of transistors, the substrate is either n-type or p-type. The other flavor
of transistor must be built in a special well in which dopant atoms have beenadded to form the body of the
opposite type.

Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi

 Module 1 Notes of VLSI Design &3Testing

The gate is a control input: It affects the flow of electrical current between the sourceand drain. Consider an
nMOS transistor. The body is generally grounded so the p–n junc- tions of the source and drain to body are
reverse-biased.
If the gate is also grounded, no current flows through the reverse-biased junctions. Hence, we say the
transistor is OFF. Ifthe gate voltage is raised, it creates an electric field that starts to attract free electrons to
the underside of the Si–SiO2 interface. If the voltage is raised enough, the electrons out- number the holes
and a thin region under the gate called the channel is inverted to act as an n-type semiconductor. Hence, a
conducting path of electron carriers is formed from source to drain and current can flow. We say the
transistor is ON.

Operation of MOS Transistors

The MOS transistor operates by controlling the flow of current between the source and drain
terminals using the gate voltage. Applying a positive voltage to the gate of an nMOS transistor
attracts electrons, creating a conductive channel between the source and drain.

Applying a negative voltage to the gate of a pMOS transistor attracts holes, enabling conduction
between the source and drain. The source and drain terminals are interchangeable, and their
designation depends on the direction of current flow. The gate acts as a control terminal,
regulating the electrical connection between the drain and source.

nMOS Transistor as a Switch

An nMOS transistor operates as follows:
Gate = ‘1’ (VDD): The switch is ON (closed), allowing current flow.
Gate = ‘0’ (VSS): The switch is OFF (open), blocking current flow.

Passing Signals
Good for passing ‘0’ (LOW signal).
Imperfect for passing ‘1’ (HIGH signal is degraded due to threshold voltage drop
VDD − Vth).

pMOS Transistor as a Switch

A pMOS transistor operates as follows:
Gate = ‘0’ (VSS): The switch is ON (closed), allowing current flow.
Gate = ‘1’ (VDD): The switch is OFF (open), blocking current flow.

CMOS Technology and Transistor Types

CMOS (Complementary MOS) technology utilizes two types of MOS transistors

Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi

 9
Module 1 Notes of VLSI Design & Testing
1.3 CMOS Logic VDD

1.4.1 The Inverter A Y

Figure 1.11 shows the schematic and symbol for a CMOS inverter or NOT gate using
one nMOS transistor and one pMOS transistor. The bar at the top indicates VDD and GND
the trian- gle at the bottom indicates GND. When the input A is 0, the nMOS transistor
is OFF and the pMOS transistor is ON. Thus, the output Y is pulled up to 1 because it is (a)
connected to VDD but not to GND. Conversely, when A is 1, the nMOS is ON, the
pMOS is OFF, and Yis pulled down to ‘0.’ This is summarized in Table 1.1. A Y
TABLE 1.1 Inverter truth table
A Y
0 1 (b) FIGURE 1.11
Inverter schematic
1 0 (a)and symbol
(b)Y = A
1.4.2 The NAND Gate
Figure 1.12(a) shows a 2-input CMOS NAND gate. It consists of two series
Y
nMOS tran- sistors between Y and GND and two parallel pMOS transistors
between Y and VDD. If either input A or B is 0, at least one of the nMOS
A
transistors will be OFF, breaking thepath from Y to GND. But at least one of the
pMOS transistors will be ON, creating a path from Y to VDD. Hence, the output Y B
will be 1. If both inputs are 1, both of the nMOS transistors will be ON and both of
the pMOS transistors will be OFF. Hence, the output will be 0. The truth table is (b)
given in Table 1.2 and the symbol is shown in Figure 1.12(b). Note that by
DeMorgan’s Law, the inversion bubble may be placed on either side of the gate. In
the figures in this book, two lines intersecting at a T-junction are connected. Two
lines crossing are connected if and only if a dot is shown.

TABLE 1.2 NAND gate truth table

Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi

 10
Module 1 Notes of VLSI Design & Testing
A B Pull-Down Network Pull-Up Network Y
0 0 OFF ON 1 FIGURE 1.12 2-input NAND gate
0 1 OFF ON 1 schematic (a) and symbol
1 0 OFF ON 1
b) Y = A · B
1 1 ON OFF 0

k-input NAND gates are constructed using k series nMOS transistors and k parallel Y
A
pMOS transistors. For example, a 3-input NAND gate is shown in Figure 1.13. When any B
of the inputs are 0, the output is pulled high through the parallel pMOS transistors. When
C
all of the inputs are 1, the output is pulled low through the series nMOS transistors.

The pull-up and pull-down networks in the inverter each consist of a singletransistor. The NAND gate uses a series
pull-down network and a parallel pull-up network. More elaborate networks are used for more complex gates. Two or
more transistors in series are ON only if all of the series transistors are ON. Two or more transistors in parallel are
ON if any of the parallel transistors are ON.
In general, when we join a pull-up network to a pull-down network to form a logic gate as shown in Figure 1.14, they both will
attempt to exert a logic level at the output. The possible levels at the output are shown in Table 1.3. From this table it can be
seen that the output of a CMOS logic gate can be infour states. The 1 and 0 levels have been encountered with the inverter
and NAND gates, where either the pull-up or pull-down is OFF and the other structure is ON. When both pull-up and
pull-down are OFF, the high impedance or floating Z output state results. This is of importance in multiplexers, memory
elements, and tristate bus drivers. The crowbarred (or contention) X level exists when both pull-up and pull-down are
simultaneously turned ON. Contention between the two net- works results in an indeterminate output level and dissipates static
power. It is usually an unwanted condition.

pMOS

pull-up
Input Outut

nMOS

pull-

FIGURE 1.14 General logic gate usingpull-up and pull-down networks

TABLE 1.3 Output states of CMOS logic gates

pull-up OFF pull-up ON

pull-down OFF Z 1
pull-down ON 0 crowbarred (X)

1.4.3 The NOR Gate AB

A 2-input NOR gate is shown in Figure 1.16. The nMOS transistors are in parallel to Y
pull the output low when either input is high. The pMOS transistors are in series to
pull the output high when both inputs are low, as indicated in Table 1.4. The output is (a)
never crow- barred or left floating.

TABLE 1.4 NOR gate truth table

A B Y
0 0 1
0 1 0
1 0 0 (b)
1 1 0
FIGURE 1.16 2-input NOR

Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi

 gate schematic (a)11
and symbol
Module 1 Notes of VLSI Design & Testing
(b) Y = A + B
Example 1.1

Sketch a 3-input CMOS NOR gate.

SOLUTION: Figure 1.17 shows such a gate. If any input is high, the output is pulled
low through the parallel nMOS transistors. If all inputs are low, the output is pulled AB
high through the series pMOS transistors.

1.4.4 Compound Gates

A compound gate performing a more complex logic function in a single stage of logic FIGURE 1.17 3-input NOR
is formed by using a combination of series and parallel switch structures. For
example, the derivation of the circuit for the function Y (A · B) (C · D) is shown gate schematicY = A + B +
in Figure 1.18. This function is sometimes called AND-OR-INVERT-22, or AOI22 C
because it per- forms the NOR of a pair of 2-input ANDs. For the nMOS pull-down
network, take the uninverted expression ((A · B) (C · D)) indicating when the output
should be pulled to ‘0.’ The AND expressions (A · B) and (C · D) may be implemented
by series connections of switches, as shown in Figure 1.18(a). Now ORing the result
requires the parallel con- nection of these two structures, which is shown in Figure
1.18(b). For the pMOS pull-up network, we must compute the complementary
expression using switches that turn on with inverted polarity. By DeMorgan’s Law,
this is equivalent to interchanging AND and OR operations. Hence, transistors that
appear in series in the pull-down network must appear in parallel in the pull-up
network. Transistors that appear in parallel in the pull- down network must appear in
series in the pull-up network. This principle is called con- duction complements and
has already

This AOI22 gate can be used as a 2-input inverting multiplexer by connecting C A as a

select signal. Then, Y B if C is 0, while Y D if C is 1. Section 1.4.8 shows a way to improve
this multiplexer design.
Example 1.2

Sketch a static CMOS gate computing Y  (A  B  C) · D.

SOLUTION: Figure 1.19 shows such an OR-AND-INVERT-3-1 (OAI31) gate. The

nMOS pull-down network pulls the output low if D is 1 and either A or B or C are
Prof. S. S. Kamate, ECE Dept.
1, HIT,
so D Nidasoshi
is in series with the parallel combination of A, B, and C. The pMOS pull-up
 A
B

C D
Y 12
Module 1 Notes of VLSI Design & Testing

1.4.5 Pass Transistors and Transmission Gates

The strength of a signal is measured by how closely it approximates an ideal voltage
source. In general, the stronger a signal, the more current it can source or sink. The
power sup- plies, or rails, (VDD and GND) are the source of the strongest 1s and 0s.
An nMOS transistor is an almost perfect switch when passing a 0 and thus we
say it passes a strong 0. However, the nMOS transistor is imperfect at passing a 1.
The high voltage level is somewhat less than VDD, as will be explained in Section 2.5.4.
We say it passes a degraded or weak 1. A pMOS transistor again has the opposite
behavior, passing strong 1s but degraded 0s. The transistor symbols and behaviors are
FIGURE 1.19 summarized in Figure
1.20 with g, s, and d indicating gate, source, and drain.
CMOS When an nMOS or pMOS is used alone as an imperfect switch, we sometimes
compound gate call it a pass transistor. By combining an nMOS and a pMOS transistor in parallel
for function (Figure 1.21(a)), we obtain a switch that turns on when a 1 is applied to g (Figure
Y = (A+ B+ C) · D 1.21(b)) in which 0s and 1s are both passed in an acceptable fashion (Figure 1.21(c)).
We term this a transmission gate or pass gate. In a circuit where only a 0 or a 1 has to be
passed, the appro- priate transistor (n or p) can be deleted, reverting to a single
nMOS or pMOS device.
Note that both the control input and its complement are required by the transmission gate. This is called double rail logic.
1
Some circuit symbols for the transmission gate are shown in Figure 1.21(d). None are easier to draw than the simple
schematic, so we will use the schematic version to represent a transmission gate in this book.
In all of our examples so far, the inputs drive the gate terminals of nMOS transistors in the pull-down network and pMOS
transistors in the complementary pull-up network, as was shown in Figure 1.14. Thus, the nMOS transistors only need to
pass 0s and the pMOS only pass 1s, so the output is always strongly driven and the levels are never degraded. This is
called a fully restored logic gate and simplifies circuit design [Link] contrast to other forms of logic, where the pull
-up and pull-down switch networks haveto be ratioed in some manner, static CMOS gates operate correctly independently
of the physical sizes of the transistors. Moreover, there is never a path through ‘ON’ transistors from the 1 to the 0
supplies for any combination of inputs (in contrast to single-channel MOS, GaAs technologies, or bipolar). As we will find
in subsequent chapters, this is the basis for the low static power dissipation in CMOS.

Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi

 13
Module 1 Notes of VLSI Design & Testing
BAD A consequence of the design of static CMOS gates is that they must be inverting.
The nMOS pull-down network turns ON when inputs are 1, leading to 0 at the
VDD output. We might be tempted to turn the transistors upside down to build a noninverting
gate. For example, Figure 1.22 shows a noninverting buffer. Unfortunately, now both
A Y
the nMOS and pMOS transistors produce degraded outputs, so the technique should
be avoided. Instead, we can build noninverting functions from multiple stages of
inverting gates. Fig- ure 1.23 shows several ways to build a 4-input AND gate from
GND two levels of inverting static CMOS gates. Each design has different speed, size,
and power trade-offs.
A Y Similarly, the compound gate of Figure 1.18 could be built with two AND gates, an
OR gate, and an inverter. The AND and OR gates in turn could be constructed
from NAND/NOR gates and inverters, as shown in Figure 1.24, using a total of 20
FIGURE 1.22 transistors, as compared to eight in Figure 1.18. Good CMOS logic designers exploit
the efficiencies of compound gates rather than using large numbers of AND/OR
Bad noninverting gates.
buffer

ABCD
4 2
4 2 2
AND
4 2
OR

FIGURE 1.24 Inefficient discrete gate implementation of AOI22

with transistor counts indicated

FIGURE 1.23 Various implementationsof a CMOS 4-input AND gate

Tristates

1.4.6 Tristates
Figure 1.25 shows symbols for a tristate buffer. When the enable input EN is 1, the
output Y equals the input A, just as in an ordinary buffer. When the enable is 0, Y is left
floating (a ‘Z’ value). This is summarized in Table 1.5. Sometimes both true and
complementary enable signals EN and EN are drawn explicitly, while sometimes only
EN is shown.

TABLE 1.5 Truth table for tristate

EN / EN A Y
0/1 0 Z
0/1 1 Z
1/0 0 0
1/0 1 1

Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi

 14
Module 1 Notes of VLSI Design & Testing
Figure 1.27(a) shows a tristate inverter. The output
is actively driven from VDD or GND, so it is a restoring A A
logic gate. Unlike any of the gates considered so far, the
A
tristate inverter does not obey the conduction
EN
complements rule because it allows the output to float Y
under certain input com- binations. When EN is 0 (Figure Y Y
EN
1.27(b)), both enable tran- sistors are OFF, leaving the
output floating. When EN is 1 (Figure 1.27(c)), both
enable transistors are ON. They are conceptually
removed from the circuit, leaving a simple inverter. (a) EN = 0 EN = 1
Figure 1.27(d) shows symbols for the tristate The Y = 'Z' Y=A (d)
transmission gate in Figure 1.26 has the same truth (b) (c)
table as a tristate buffer. It only requires two transistors
but it is a nonrestoring circuit. If the input is noisy or
other- wise degraded, the output will receive the same noise.
We will see in Section 4.4.2 that the delay of a series of
nonrestoring gates increases rapidly with the number of
gates.

inverter. The complementary enable signal can be generated FIGURE 1.27 Tristate Inverter
internally or can be routed to the cell explicitly. A tristate
buffer can be built as an ordinary inverter followed by a
tristate inverter.
Tristates were once commonly used to allow multiple units to drive a common bus, as long as exactly one unit is enabled at
a time. If multiple units drive the bus, contention occurs and power is wasted. If no units drive the bus, it can float to an
invalid logic level that causes the receivers to waste power. Moreover, it can be difficult to switch enable sig- nals at exactly the
same time when they are distributed across a large chip. Delay between different enables switching can cause contention.
Given these problems, multiplexers arenow preferred over tristate busses.

1.4.8 Multiplexers
Multiplexers are key components in CMOS memory elements and data manipulation structures. A multiplexer chooses the
output from among several inputs based on a select signal. A 2-input, or 2:1 multiplexer, chooses input D 0 when the select is 0
and input D1 when the select is 1. The truth table is given in Table 1.6; the logic function is

TABLE 1.6 Multiplexer truth table

S/S D1 D0 Y
0/1 X 0 0
0/1 X 1 1 S
1/0 0 X 0
1/0 1 X 1 D0
S
Two transmission gates can be tied together to form a compact 2-input multiplexer, Y
as shown in Figure 1.28(a). The select and its complement enable exactly one of the
two transmission gates at any given time. The complementary select S is often not D1 S
drawn in the symbol, as shown in Figure 1.28(b).
Again, the transmission gates produce a nonrestoring multiplexer. We could build (a)
a restoring, inverting multiplexer out of gates in several ways. One is the compound
gate of Figure 1.18(e), connected as shown in Figure 1.29(a). Another is to gang
together two tristate inverters, as shown in Figure 1.29(b). Notice that the schematics
of these two approaches are nearly identical, save that the pull-up network has been
slightly simplifiedand permuted in Figure 1.29(b). This is possible because the select and
its complement are mutually exclusive. The tristate approach is slightly more
compact and faster because it FIGURE 1.28
Transmissiongate
multiplexer

Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi

 Module 1 Notes of VLSI Design & Testing

requires less internal wire. Again, if the complementary select is generated within the cell, it is omitted from the
symbol (Figure 1.29(c)).
Larger multiplexers can be built from multiple 2-input multiplexers or by directly ganging together several tristates.
The latter approach requires decoded enable signals for each tristate; the enables should switch simultaneously to
prevent contention. 4-input (4:1) multiplexers using each of these approaches are shown in Figure 1.30. In practice,
both inverting and noninverting multiplexers are simply called multiplexers or muxes.

1.4.9 Sequential Circuits

So far, we have considered combinational circuits, whose outputs depend only on the cur- rent inputs. Sequential
circuits have memory: their outputs depend on both current and previous inputs. Using the combinational circuits
developed so far, we can now build sequential circuits such as latches and flip-flops. These elements receive a
clock, CLK, anda data input, D, and produce an output, Q. A D latch is transparent when CLK 1, mean- ing that Q
follows D. It becomes opaque when CLK 0, meaning Q retains its previous value and ignores changes in D. An
edge-triggered flip-flop copies D to Q on the rising edge of CLK and remembers its old value at other times.

Latches A D latch built from a 2-input multiplexer and two inverters is shown inFigure 1.31(a). The multiplexer can
be built from a pair of transmission gates, shown in Figure 1.31(b), because the inverters are restoring. This latch also
produces a complemen- tary output, Q. When CLK 1, the latch is transparent and D flows through to Q (Figure
1.31(c)). When CLK falls to 0, the latch becomes opaque. A feedback path around the inverter pair is established
(Figure 1.31(d)) to hold the current state of Q indefinitely.

The D latch is also known as a level-sensitive latch because the state of the output is dependent on the level
of the clock signal, as shown in Figure 1.31(e). The latch shown isa positive-level-sensitive latch, represented by the
symbol in Figure 1.31(f ). By inverting the control connections to the multiplexer, the latch becomes negative-level-
sensitive.

[Link] Flip-Flops By combining two level-sensitive latches, one negative-sensitive and one positive-sensitive, we
construct the edge-triggered flip-flop shown in Figure 1.32(a– b). The first latch stage is called the master and the
second is called the slave.
While CLK is low, the master negative-level-sensitive latch output (QM ) follows the D input while the slave

Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi

 Module 1 Notes of VLSI Design & Testing

positive-level-sensitive latch holds the previous value (Figure 1.32(c)). When the clock transitions from 0 to 1, the
master latch becomes opaque and holds the D value at the time of the clock transition. The slave latch becomes
transparent, passing the stored master value (QM ) to the output of the slave latch (Q). The D input is blocked from
affecting the output because the master is disconnected from the D input (Figure 1.32(d)). When the clock
transitions from 1 to 0, the slave latch holds its value and the master starts sampling the input again.
While we have shown a transmission gate multiplexer as the input stage, good design practice would buffer the
input and output with inverters, as shown in Figure 1.32(e), to
CLK
CLK
Q Q
D1
0
D
CLK CLK

(a) (b)
CLK
Q Q
D D

CLK = 1 CLK = 0

(c) (d)

CLK

CLK
D

Q D Q
Latc

(e) (f)

FIGURE 1.31 CMOS positive-level-sensitive

D latch

Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi

 Module 1 Notes of VLSI Design & Testing

CLK

CLK

Latch

Latch
QM
D Q

(a)
CLK CLK
QM

D CLK CLK CLK CLK Q

CLK
(b)
CLK
QM
D

CLK = 0
Q

(c)

D QM Q

(d) CLK = 1
CLK CLK
QM

D
CLK CLK CLK CLK Q

CLK CLK
(e)

CLK K

D Q
Flop

(f)
(g)
FIGURE 1.32 CMOS positive-edge-triggered D
flip-flop

Prof. S. S. Kamate, ECE Dept. HIT, Nidasoshi

 Module 1 VLSI Design and Testing

preserve what we call “modularity.” Modularity is explained further in Section 1.6.2 and robust latches and registers are
discussed further in Section 10.3.
In summary, this flip-flop copies D to Q on the rising edge of the clock, as shown in Figure 1.32(f ). Thus, this device is called a
positive-edge triggered flip-flop (also called a D flip-flop, D register, or master–slave flip-flop). Figure 1.32(g) shows the circuit
symbol forthe flip-flop. By reversing the latch polarities, a negative-edge triggered flip-flop may beconstructed. A collection of
D flip-flops sharing a common clock input is called a register. A register is often drawn as a flip-flop with multi-bit D and Q
busses. In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e.,
if one flip-flop triggers early and another triggers late because of variations in clock arrival times. In industrial designs, a great deal
of effort is devoted to timing simulations to catch hold-time problems.

Alternate Circuit representations

Generally, a design can be expressed in terms of:

1. Behavioral representation
2. Structural representation
3. Physical representation

1.1 Behavioral representation

A behavioral representation defines how a system or circuit responds to a given
set of inputs.
This representation focuses on the functionality of a system rather than its
implementation details, making it independent of the underlying technology.

1.1.1 Behavioral Specification at the Logic Level

At the logic level, the behavior of a digital circuit can be described using Boolean
functions.
For example, the behavior of a logic gate can be expressed as:

F = ((A + B + C) · D)

This Boolean function specifies the logical operation without indicating how it is
implemented in hardware or its performance characteristics.

1.1.2 Higher-Level Behavioral Descriptions

Behavioral representation can also be expressed at a higher level using arithmetic
or logical operations.
For instance, an addition operation can be described in a high-level language as:

sum = a + b

Here, no specific method of addition is implied, and the word length is assumed to
be that of the machine.
1.1.3 Behavioral Representation of Sequential Circuits
For sequential circuits, behavior can be described using conditional statements.
Consider a flip-flop, where the output is updated based on the load signal (LD):
IF ( LD == 1) THEN
Q = D;
 Module 1 VLSI Design and Testing

This representation, however, may be ambiguous because it could also describe a

multiplexer, which selects inputs without necessarily storing a state.
 Module 1 VLSI Design and Testing

1.1.4 Higher Levels of Behavioral Specification

More abstract behavioral descriptions can specify:
– Types of registers used in a design.
– Data transfers between these registers.

These descriptions provide even less information about implementation details but
help define how the system should function.
Eventually, behavior can be described as an algorithm in a high-level programming
language.

1.1.5 Importance in Modern Design Systems

The objective of modern digital design tools is to convert high-level behavioral
specifications into optimized hardware designs efficiently.
This process ensures:
– Faster design time.
– Increased accuracy and reliability.

By using behavioral representations, designers can develop complex digital

systems while focusing on functionality before deciding on implementation details.

1.2 Structural representation

A structural specification defines how components are interconnected to perform
a function or achieve a specific behavior.
Unlike behavioral descriptions, which focus on logical operations, structural
descriptions specify the physical arrangement of circuit elements.
One example of a structural description language is MODEL, developed by Lattice
Logic Ltd. This language provides a formal way to define circuit components and
their interconnections.

1.2.1 Structural Representation in MODEL

In MODEL, circuit elements such as transistors are explicitly defined along with
their connections.
The general syntax follows this format:
Part < cir cuit _nam e > (< inputs >) -> <outputs >
< C om p on en t _T yp e > <drain > <gate > <source >
End
 Module 1 VLSI Design and Testing

Example 1: Inverter Description in MODEL

Part inv ( in) -> out Nfet

out in vss Pfet out
in vdd
End

The first line defines a part named inv with input in and output out.
The Nfet transistor has its drain = out, gate = in, and source = vss.

The Pfet transistor has its drain = out, gate = in, and source = vdd.

Example 2: 2-Input NAND Gate in MODEL

Part nand2 (a, b) -> out

Signal i1

Nfet i1 a vss
Nfet out b i1
Pfet out a vdd
Pfet out b vdd
End

An internal signal i1 is declared to facilitate the connection between transistors.

Two Nfet transistors form a series connection, while two Pfet transistors are in
parallel, implementing a NAND function.
The corresponding Boolean equation is:

out =∼ (a&b)

vdd
a b

out
b
i1
a

vss
Figure 21: Graphical representation of structural description for a Two - input CMOS NAND
gate
 Module 1 VLSI Design and Testing

1.2.2 Advantages of Structural Representation

1. Explicit Connectivity: The entire transistor-level structure is specified.

2. Performance Optimization: Allows modifications such as transistor sizing and

capacitance adjustments.
3. Hierarchical Design: Smaller components can be combined to build complex circuits.

Example 3: Adding Performance Parameters

Part nand2 (a, b) ->

out
Nfe i1 a
t out b i1
Nfe out a vdd size = 2
t t b vdd size = 2
Capacitanc
e i1 50

Capacitanc a 100
e
End

Transistor Sizing: size = 2 increases the size of Pfets, affecting speed and power.

Capacitance Values: Specified in arbitrary units to account for circuit delay effects.

1.2.3 Structural Representation of Complex Circuits

By using smaller predefined components, we can create more complex circuits.

Example 4: Transmission Gate in MODEL

Part tg (a, c, cb) - > b

Nfet a c b
Pfet a cb b
End

A transmission gate consists of an Nfet and a Pfet, controlled by complementary signals

(c and

cb).

Example 5: Flip-Flop (D Latch) Using Structural Components

 Module 1 VLSI Design and Testing

Part flipflop ( in , ld , ldbar , q, qbar)

Signal a

tg ( in , ld , ldbar) -> a
inv ( a) -> qbar
 Module 1 VLSI Design and Testing

tg (q, ldbar , ld) -> a

End

Figure 22: Schematic representation of CMOS flip-flop

The flip-flop (D latch) is implemented using transmission gates (tg) and inverters
(inv).

This hierarchical design approach enables scalability and reuse of components.

1.2.4 Structural vs. Behavioral Representation

Table 6: Comparison of Structural and Behavioral Representation

Feature Structural Representation Behavioral Representation

Focus Transistor-level connectivity Logical function
Example Nfet out in vss out = (a & b)
Performance Details Yes (e.g., capacitance, size) No
Flexibility Parameterized descriptions Limited parameterization
possible
Readability More detailed, hardware-specific More abstract, easier to
understand

Behavioral descriptions ensure correct logic implementation, but structural descriptions

define
real circuit performance.

1.2.5 Combining Structural and Graphical Representations

Structural descriptions (MODEL) provide a text-based, parameterized
method for defining circuits.
Graphical descriptions (schematics) visually represent circuit connectivity.

Emerging design tools integrate both approaches for flexibility and efficiency.
 Module 1 VLSI Design and Testing

Example: Parameterized Inverter

Part inv ( in) [n] -> out Nfet

out in vss size = n
Pfet out in vdd size = 2 * n
End

The size parameter n allows dynamic transistor scaling, useful for design automation.

1.2.6 Conclusion
Structural representation is essential in circuit design for detailed connectivity,
performance optimization, and hierarchical modeling.
By combining structural and behavioral descriptions, engineers can achieve
both logical correctness and physical efficiency in circuit design.

1.3 Physical representation

The physical specification for a circuit is used to define how a particular part
must be constructed to yield a specific structure and, consequently, a defined
behavior.
In an Integrated Circuit (IC) process, the lowest level of physical
specification is the photo-mask information, which is crucial for the
various processing steps during fabrication.
At this stage, we focus on a simplified model for the physical nature of a CMOS circuit.

1.3.1 Transistor Physical Representation

A typical physical representation for a transistor involves two rectangles,
representing the lithography required for the transistor’s fabrication.
These rectangles have precise dimensions defined by the design rules, which are
based on the specific process being used.
These rules often change for different processes, and the corresponding dimensions
may not change linearly.
Rather than focusing on these complex rules, we use a single symbol to represent
a transistor in a non-metric format, maintaining the essential physical nature of the
transistor.

n-Transistor representation
The physical symbol for an n-transistor is shown in figure below.
In n-transistor, two process levels are overlaid: one for the gate connection and
another for the source and drain.
These symbols are placed on a grid where:
 Module 1 VLSI Design and Testing

– The center grid point is for the gate.

– The grid point to the right (or above) is the drain.
– The grid point to the left (or below) is the source.

These grid points can be visualized as part of a schematic layout.

Figure 23: Physical Representation of n-Transistor

p-Transistor representation
Similarly, a p-transistor uses a similar symbol, as shown in figure below. The
“horizontal” transistor layout is used here, with the gate, source, and drain points
similarly defined on the grid.

Figure 24: Physical Representation of p-Transistor

 Module 1 VLSI Design and Testing

1.3.2 Physical Symbolic Layout for an Inverter

A symbolic layout for an inverter can be constructed using the transistor symbols.

Figure 25: Physical Representation of CMOS inverter

It resembles the schematic layout but requires careful consideration of the layers in
which connections are made.
The interaction of these layers is summarized in table below:
– OK denotes that a connection is possible between two layers.
– X signifies that a direct connection is not allowed, requiring a “contact” (C) to
connect the two layers.

Table 7: Physical Layer Interactions in CMOS Design

Physical Layer n-Diffusion p-Diffusion Polysilicon Aluminum

n-Diffusion OK X Transistor OK (C)
p-Diffusion X OK Transistor OK (C)
Polysilicon Transistor Transistor OK OK (C)
Aluminum OK (C) OK (C) OK (C) OK

1.3.3 Transmission Gate Layout

The symbolic layout for a transmission gate is shown in figure
below.

This layout is composed of the overlaid n- and p-transistor symbols, with grid
points connecting the appropriate terminals.
 Module 1 VLSI Design and Testing

Figure 26: Symbolic Layout for Transmission Gate

1.3.4 Building a Flip-Flop

Using the principles described, a physical sub-assembly for a flip-flop can be constructed.
Figure below shows the symbolic layout for a flip-flop.

Figure 27: Symbolic Layout for Flip-Flop

This layout combines multiple transmission gates and inverters, with appropriate
connections for Vss and Vdd supplies.
 Module 1 VLSI Design and Testing

1.3.5 Conclusion
CMOS IC design involves several critical steps:
1. Defining the behavior of the circuit.

2. Designing the logic that implements the behavior.

3. Translating this logic into a transistor-level description.

4. Finally, creating a physical layout for the designed logic.

CMOS-nMOS comparison
Table 8: Comparison of CMOS and nMOS Logic

Feature CMOS nMOS

Logic Levels Fully restored logic; output Output does not settle at GND,
settles at leading to degraded noise margin.
VDD or VSS (GND).
Transition Rise and fall times are of the same Rise times are inherently slower than
Times or- der. fall times.
Transmission Passes both logic levels well; Pass transistor transfers logic ‘0’ well,
Gates output can drive other transmission but logic ‘1’ is degraded. Cannot drive
gates. a sec- ond pass transistor.
Power Dissi- Almost zero static power Power dissipated in the circuit even
pation dissipation; power dissipated only when output is stable, in addition to
during logic tran- sition. switching losses.
Precharging Both n-type and p-type devices With enhancement-mode transistors,
Characteris- can precharge a bus to VDD or the best achievable precharge is
tics VSS. (VDD − Vt). Bootstrapping or hot
clocking is often re- quired.
Power Supply Voltage required to switch a gate Somewhat dependent on supply
is a fixed percentage of VDD; voltage; fixed.
variable range from 1.5V to 15V.
Packing Den- Requires 2N devices for N -input Requires (N + 1) devices for N -
sity com- plementary static gates; input gates.
fewer for dy- namic gates.
Pull-up to Load-to-driver ratio typically 2:1. Load-to-enhancement-driver ratio opti-
Pull-down mized for logic ‘0’ level and minimal cur-
Ratio rent consumption.
Layout Encourages regular layout styles. Depletion load and different driver
tran- sistor sizes inhibit layout
regularity.