a Wideband/Differential Output

Transimpedance Amplifier
AD8015
FEATURES FUNCTIONAL BLOCK DIAGRAM
Low Cost, Wide Bandwidth, Low Noise
Bandwidth: 240 MHz
AD8015
Pulse Width Modulation: 500 ps NC 1 8 +VS
10kΩ
Rise Time/Fall Time: 1.5 ns
50Ω
Input Current Noise: 3.0 pA/√Hz @ 100 MHz IIN 2 +1 7 +OUTPUT
Total Input RMS Noise: 26.5 nA to 100 MHz G = 30
G=3
Wide Dynamic Range NC 3
50Ω
6 –OUTPUT

Optical Sensitivity: –36 dBm @ 155.52 Mbps +1

Peak Input Current: 6350 mA VBYP 4 – + +VS 5 –VS

Differential Outputs 1.7V

Low Power: 5 V @ 25 mA NC = NO CONNECT

Wide Operating Temperature Range: –408C to +858C

APPLICATIONS
25.0E+3
Fiber Optic Receivers: SONET/SDH, FDDI, Fibre Channel
Stable Operation with High Capacitance Detectors DIFFERENTIAL
Low Noise Preamplifiers 20.0E+3
Single-Ended to Differential Conversion
I-to-V Converters
X-RESISTANCE – Ω

15.0E+3

SINGLE-ENDED
10.0E+3

PRODUCT DESCRIPTION 5.0E+3

The AD8015 is a wide bandwidth, single supply transimpedance
amplifier optimized for use in a fiber optic receiver circuit. It is a
complete, single chip solution for converting photodiode current 000.E+0
10.0E+6 100.0E+6 1.0E+9
into a differential voltage output. The 240 MHz bandwidth enables FREQUENCY – Hz
AD8015 application in FDDI receivers and SONET/SDH
receivers with data rates up to 155 Mbps. This high bandwidth
supports data rates beyond 300 Mbps. The differential outputs Figure 1. Differential/Single-Ended Transimpedance vs.
drive ECL directly, or can drive a comparator/ fiber optic post Frequency
amplifier.
5.0
EQUIVALENT INPUT CURRENT NOISE – pA√ Hz

In addition to fiber optic applications, this low cost, silicon al-

ternative to GaAs-based transimpedance amplifiers is ideal for 4.5 3.0pF
systems requiring a wide dynamic range preamplifier or single-
ended to differential conversion. The IC can be used with a 4.0
2.0pF

standard ECL power supply (–5.2 V) or a PECL (+5 V) power

supply; the common mode at the output is ECL compatible. 1.5pF
3.5
The AD8015 is available in die form, or in an 8-pin SOIC
package.
3.0

2.5 1.0pF
0.5pF

2.0
000.0E+0 20.0E+6 40.0E+6 60.0E+6 80.0E+6 100.0E+6
FREQUENCY – Hz

Figure 2. Noise vs. Frequency (SO-8 Package with

REV. A Added Capacitance)
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its © Analog Devices, Inc., 1996
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD8015–SPECIFICATIONS (SO Package @ T = +258C and V A S = +5 V, unless otherwise noted)

AD8015AR
Parameter Conditions Min Typ Max Units
DYNAMIC PERFORMANCE
Bandwidth 3 dB 180 240 MHz
Pulse Width Modulation 10 µA to 200 µA Peak 500 ps
Rise and Fall Time 10% to 90% 1.5 ns
Settling Time1 to 3%, 0.5 V Diff Output Step 3 ns
INPUT
Linear Input Current Range ± 2.5%, Nonlinearity ± 25 ± 30 µA
Max Input Current Range Saturation ± 200 ± 350 µA
Optical Sensitivity 155 Mbps, Avg Power –36 dBm
Input Stray Capacitance Die, by Design 0.2 pF
SOIC, by Design 0.4 pF
Input Bias Voltage +VS to IIN and VBYP 1.6 1.8 2.0 V
NOISE Die, Single Ended at POUT,
or Differential (POUT–NOUT),
CSTRAY = 0.3 pF
Input Current Noise f = 100 MHz 3.0 pA/√Hz
Total Input RMS Noise DC to 100 MHz 26.5 nA
TRANSFER CHARACTERISTICS
Transresistance Single Ended 8 10 12 kΩ
Differential 16 20 24 kΩ
Power Supply Single Ended 37.0 dB
Rejection Ratio Differential 40 dB
OUTPUT
Differential Offset 6 20 mV
Output Common-Mode Voltage From Positive Supply –1.5 –1.3 –1.1 V
Voltage Swing (Differential) Positive Input Current, RL = ∞ 1.0 V p-p
Positive Input Current, RL = 50 Ω 600 mV p-p
Output Impedance 40 50 60 Ω
POWER SUPPLY TMIN to TMAX
Operating Range Single Supply +4.5 +5 +11 V
Dual Supply ± 2.25 ± 5.5 V
Current 25 26 mA
NOTES
1
Settling Time is defined as the time elapsed from the application of a perfect step input to the time when the output has entered and remained within a specified error
band symmetrical about the final value. This parameter includes propagation delay, slew time, overload recovery, and linear settling times.
Specifications subject to change without notice.

NOTES
ABSOLUTE MAXIMUM RATINGS 1 1
Stresses above those listed under “Absolute Maximum Ratings” may cause
Supply Voltage (+VS to –VS). . . . . . . . . . . . . . . . . . . . . . . 12 V permanent damage to the device. This is a stress rating only and functional
Internal Power Dissipation2 operation of the device at these or any other conditions above those indicated in the
Small Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts operational section of this specification is not implied. Exposure to absolute
Output Short Circuit Duration . . . . . . . . . . . . . . . Indefinite maximum rating conditions for extended periods may affect device reliability.
2
Specification is for device in free air: 8-pin SOIC package: θJA = 155°C/W.
Maximum Input Current . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C ORDERING GUIDE
Operating Temperature Range (TMIN to TMAX)
AD8015ACHIP/AR . . . . . . . . . . . . . . . . . . –40°C to +85°C Temperature Package Package
Maximum Junction Temperature . . . . . . . . . . . . . . . . . +165°C Model Range Description Option
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
AD8015AR –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD8015ACHIPS –40°C to +85°C Die Form

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD8015 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–2– REV. A
 AD8015
PIN CONFIGURATION +VS
+VS
1.7V

AD8015 AD8015
1 8 V1
NC 1 8 +VS
10kΩ 10kΩ
LPF: R R
50Ω 50Ω 3dB@
2 +1 7 0.7 x F CLOCK CLK
IIN 2 +1 7 +OUTPUT
G = 30 LPF: RECOVERY DATA
G = 30
G=3 3dB@
G=3 3 6 0.7 x F QUANTIZER
NC 3 6 –OUTPUT 50Ω
50Ω +1 R > 40Ω
+1 . C1 >100pF
4 – + +VS 5 4.5V < VS < 11V
VBYP 4 – + +VS 5 –VS
1.7V
1.7V
C1
NC = NO CONNECT

METALIZATION PHOTOGRAPH Figure 3. Fiber Optic Receiver Application: Photodiode

Dimensions shown in microns. Not to scale. Referred to Positive Supply
OPTIONAL +VS
+VS CONNECTION PHOTODIODE REFERRED TO NEGATIVE SUPPLY
Figure 4 shows the AD8015 used in a circuit where the photo-
diode is referred to the negative supply. This results in a larger
back bias voltage than when referring the photodiode to the
positive supply. The larger back bias voltage on the photodiode
decreases the photodiode’s capacitance thereby increasing its
IIN
+OUTPUT bandwidth. The R2, C2 network shown in Figure 4 is added to
838µ
decouple the photodiode to the positive supply. This improves
998µ
PSRR.
+VS
–OUTPUT
+VS
AD8015
1 8 V1
10kΩ
C2 LPF: R R
50Ω 3dB@
2 +1 7 0.7 x F CLOCK CLK
+VS G = 30 LPF: RECOVERY DATA
1.7V G=3 3dB@
3 6 0.7 x F QUANTIZER
50Ω
R2 +1 R > 40Ω
VBYP C1 >100pF
–VS 4 – + +VS 5 4.5V < VS < 11V
813µ R2 AND C2 OPTIONAL
1.7V
FOR IMPROVED PSRR
973µ
C1
NOTE:
FOR BEST PERFORMANCE ATTACH PACKAGE
SUBSTRATE TO +VS.
MATERIAL AT BACK OF DIE IS SILICON. USE OF Figure 4. Fiber Optic Receiver Application: Photodiode
+VS OR –VS FOR DIE ATTACH IS ACCEPTABLE.
Referred to Negative Supply

FIBER OPTIC SYSTEM NOISE PERFORMANCE

FIBER OPTIC RECEIVER APPLICATIONS
The AD8015 maintains 26.5 nA referred to input (RTI) to 100
In a fiber optic receiver, the photodiode can be placed from the
MHz. Calculations below translate this specification into mini-
IIN pin to either the positive or negative supply. The AD8015
mum power level and bit error rate specifications for SONET
converts the current from the photodiode to a differential volt-
and FDDI systems. The dominant sources of noise are: 10 kΩ
age in these applications. The voltage at the VBYP pin is ≈1.8 V
feedback resistor current noise, input bipolar transistor base
below the positive supply. This node must be bypassed with a
current noise, and input voltage noise.
capacitor (C1 in Figures 3 and 4 below) to the signal ground. If
large levels of power supply noise exist, then connecting C1 to The AD8015 has dielectrically isolated devices and bond pads
+VS is recommended for improved noise immunity. For opti- that minimize stray capacitance at the IIN pin. Input voltage
mum performance, choose C1 such that C1 > 1/(2 π × 1000 × noise is negligible at lower frequencies, but can become the
fMIN); where fMIN is the minimum useful dominant noise source at high frequencies due to IIN pin stray
frequency in Hz. capacitance. Minimizing the stray capacitance at the IIN pin is
critical to maintaining low noise levels at high frequencies. The
PHOTODIODE REFERRED TO POSITIVE SUPPLY pins surrounding the IIN pin (Pins 1 and 3) have no internal
Figure 3 shows the AD8015 used in a circuit where the photo- connection and should be left unconnected in an application.
diode is referred to the positive supply. The back bias voltage on This minimizes IIN pin package capacitance. It is best to have no
the photodiode is ≈1.8 V. This method of referring the photo- ground plane or metal runs near Pins 1, 2, and 3 and to mini-
diode provides greater power supply noise immunity (PSRR) mize capacitance at the IIN pin.
than referring the photodiode to the negative supply. The signal The AD8015AR (8-pin SOIC) IIN pin total stray capacitance is
path is referred to the positive rail, and the photodiode capaci- 0.4 pF without the photodiode. Photodiodes used for SONET
tance is not modulated by high frequency noise that may exist or FDDI systems typically add 0.3 pF, resulting in roughly
on the negative rail. 0.7 pF total stray capacitance.

REV. A –3–
AD8015
SONET OC-3 SENSITIVITY ANALYSIS Sensitivity (minimum power level) = 492/0.85 nW
OC-3 Minimum Bandwidth = 0.7 × 155 MHz ≈ 110 MHz
= 579 nW (peak)
Total Current Noise = (π/2) × 26.5 nA
= –32.4 dBm (peak)
= 42 nA (assuming single pole response)
= –35.4 dBm (average)
To maintain a BER < 1 × 10–10 (1 error per 10 billion bits):
The FDDI specification allows for a minimum power level of
Minimum current level needs to be > 13 × Total Current Noise –28 dBm peak, or –31 dBm average. Using the AD8015 pro-
= 541 nA (peak) vides 4.4 dB margin.
Assume a typical photodiode current/power conversion ratio
= 0.85 A/W THEORY OF OPERATION
The simplified schematic is shown in Figure 5. Q1 and Q3 make
Sensitivity (minimum power level) = 541/0.85 nW up the input stage, with Q3 running at 300 µA and Q1 running
= 637 nW (peak) at 2.7 mA. Q3 runs essentially as a grounded emitter. A large
= –32.0 dBm (peak) capacitor (0.01 µF) placed from VBYP to the positive supply
shorts out the noise of R17, R21, and Q16. The first stage of the
= –35.0 dBm (average) amplifier (Q3, R2, Q4, and C1) functions as an integrator, inte-
The SONET OC-3 specification allows for a minimum power grating current into the IIN pin. The integrator drives a differen-
level of –31 dBm peak, or –34 dBm average. Using the AD8015 tial stage (Q5, Q6, R5, R3, and R4) with gains of +3 and –3.
provides 1 dB margin. The differential stage then drives emitter followers (Q41, Q42,
Q60 and Q61). The positive output of the differential stage pro-
FDDI SENSITIVITY ANALYSIS vides the feedback by driving RFB. The differential outputs are
FDDI Minimum Bandwidth = 0.7 × 125 MHz ≈ 88 MHz buffered using Q7 and Q8.
The bandwidth of the AD8015 is set to within +20% of the
Total Current Noise = (π / 2) ×
88 MHz
× 26.5 nA nominal value, 240 MHz, by factory trimming R5 to 60 Ω. The
100 MHz following formula describes the AD8015 bandwidth:
= 39 nA (assuming single pole response) Bandwidth = 1/(2 π × C1 × RFB × (R5 + 2 re)/R4)
where re (of Q5 and Q6) = 9 Ω each, constant over temperature,
and RFB/R4 = 43.5, constant over temperature.
To maintain a BER < 2.5 × 10 –10
(1 error per 4 billion bits):
The bandwidth equation simplifies, and the bandwidth depends
Minimum current level needs to be > 12.6 × Total Current Noise
only on the value of C1:
= 492 nA (peak)
Bandwidth = 1/(2 π × 3393 × C1).
Assume a typical photodiode current/power conversion ratio
= 0.85 A/W

+VS

R17 R1 R2 R3 R4
635 300 3k 230 230
Q4 Q42 330
R21
1.8k INPUT Q41
Q16 CLAMPS Q8 +OUTPUT
R44 50
Q7
VBYP Q1 Q3 IIN Q60
Q5 Q6
C1 0.2pF
330
+VS –OUTPUT
R5 60
I10 Q61 R43 50
0.75MA

Q56 RFB

10k

I1 I2 I3 I4 I5 I6 I7 I8 I9
1.5MA 3MA 1MA 3MA 3MA 1MA 1MA 1MA 1MA

–VS

Figure 5. AD8015 Simplified Schematiic

–4– REV. A
 AD8015
1.5 9
+85°C
+85°C
1.0
OUTPUT VOLTAGE – Volts

– 40°C
+ 25°C
0.5
–40°C AND 0°C
5

GAIN – dB
0

4k
–0.5
VOUT
0 IN
AD8015 50Ω
–1.0

–1.5
–100 –80 –60 –40 –20 0 20 40 60 80 100
1 10 100 1000
INPUT CURRENT – µA
FREQUENCY – MHz

Figure 6. Differential Output vs. Input Current Figure 9. Gain vs. Frequency

0 10

–0.5 +85°C
PIN 7 +25°C
OUTPUT VOLTAGE – Volts

5V, +25°C

GROUP DELAY – ns
–1.0
–40°C
0
–1.5 –40°C
PIN 6

–2.0
+25°C
+85°C

–2.5
–100 –80 –60 –40 –20 0 20 40 60 80 100 10 100 1000
INPUT CURRENT – µA
FREQUENCY – MHz

Figure 7. Single-Ended Output vs. Input Current Figure 10. Group Delay vs. Frequency

300 9.0

290
8.5
280 11.0V
8.0
270
BANDWIDTH – MHz

260 7.5
GAIN – dB

5.0V
250 7.0 4.5V

240
6.5
230
6.0
220

210 5.5

200
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 5.0
TEMPERATURE – °C 10.0E+6 100.0E+6 1.0E+9
FREQUENCY – Hz

Figure 8. Bandwidth vs. Temperature Figure 11. Differential Gain vs. Supply

REV. A –5–
AD8015
100 APPLICATION
5V, +25°C
155 Mbps Fiber Optic Receiver
The AD8015 and AD807 can be used together for a complete
155 Mbps Fiber Optic Receiver (Transimpedance Amplifier,
Post Amplifier with Signal Detect Output, and Clock Recovery
IMPEDANCE – Ω

PIN 7
and Data Retiming) as shown in Figure 16.
50 The PIN diode front end is connected to a single mode, 1300 nm
laser source. The PIN diode has 3.3 V reverse bias, 0.8 A/W
PIN 6
responsivity, 0.7 pF capacitance, and 2.5 GHz bandwidth.
The AD8015 outputs (POUT and NOUT) drive a differential, con-
stant impedance (50 Ω) low-pass π filter with a 3 dB cutoff of
100 MHz. The outputs of the low-pass filter are ac coupled to
0 the AD807 inputs (PIN and NIN). The AD807 PLL damping
1 10 100 1000
factor is set at 10 using a 0.22 µF capacitor.
FREQUENCY – MHz
The entire circuit was enclosed in a shielded box. Table I sum-
marizes results of tests performed using a 223–1 PRN sequence,
Figure 12. Output Impedance vs. Frequency and varying the average power at the PIN diode.
100 The circuit acquires and maintains lock with an average input
power as low as –39.25 dBm.
30 DEVICES, 2 LOTS:
(+OUT, –OUT) × (25°C, –40°C, 85°C) × (5V, 4.5V, 11.0V)
80 100
VOLTAGE – mV

70 90

0 80
60
POPULATION – Parts

70

CUMULATIVE – %
50
60

40 50

40
30

–100 30
0 10 20 20
20
TIME – ns
10
10

0 0
Figure 13. Small Signal Pulse Response
200.000E+6
205.000E+6
210.000E+6
215.000E+6
220.000E+6
225.000E+6
230.000E+6
235.000E+6
240.000E+6
245.000E+6
250.000E+6
255.000E+6
260.000E+6
265.000E+6
270.000E+6
275.000E+6
280.000E+6
285.000E+6
290.000E+6
295.000E+6
300.000E+6
2

0 FREQUENCY – Hz
1pF

–2
Figure 15. Bandwidth Distribution Matrix
GAIN – dB

–4
5pF
0pF
–6
8pF 3pF

–8

–10

–12
10.0E+6 100.0E+6 1.0E+9
FREQUENCY – Hz

Figure 14. Differential Gain vs. Input Capacitance

–6– REV. A
 AD8015
C1
0.1µF
SDOUT
TP8 TP7
C1
C2 R1 R2 R11 R10 100pF
0.1µF 100 100 R5 100 R17 C12 R16 C13
154 154 3.65k 2.2µF 301
DATAOUTN 1 DATAOUTN VEE 16 0.1µF
C3
0.1µF R6 100
DATAOUTP 2 DATAOUTP SDOUT 15 C11
C4 3 VCC2 AVCC 14 R14 R15
0.1µF R7 100 C7 50 50
CLKOUTN 4 CLKOUTN PIN 13
R8 100
CLKOUTP 5 CLKOUTP NIN 12
C10
C5
0.1µF 6 VCC1 AVCC 11
C8 TP6
TP1
R3 R4 7 CF1 THRADJ 10
100 100 CD 100 R13 C15 C14
R11 R12 8 CF2 9 pF 0.1µF 0.1µF
154 154 AVEE THRADJ
C6
TP2 AD807 TP5
0.1µF DAMPING
CAP,0.22µF

C9
GND 10µF 0.1µF 50Ω 50Ω
TP4 5V LINE LINE
TP3
10µF
ABB HAFO
1A227 1 NC +VS 8
FC HOUSING 150nH
2 IIN +OUT 7
NOTES 0.8 A/W, 0.7pF 15pF
1. ALL CAPS ARE CHIP, 2.5GHz 3 NC –OUT 6
15pF ARE MICA. 150nH 15pF
2. 150 nH ARE SMT 4 VBYP –VS 5
NC = NO CONNECT AD8015
0.1µF 0.01µF

Figure 16. 155 Mbps Fiber Optic Receiver Schematic

Table I. AD8015, AD807 Fiber Optic Receiver Circuit:

Output Bit Error Rate & Output Jitter vs. Average Input Power
Average Optical Output Bit Output Jitter
Input Power (dBm) Error Rate (ps rms)
–6.4 Loses Lock
–6.45 1.2 × 10–2
–6.50 7.5 × 10–3
–6.60 9.4 × 10–4
–6.70 1 × 10–14
–7.0 to 1 × 10–14 < 40
–35.50
–36.00 3.0 × 10–12 < 40
–36.50 4.8 × 10–10
–37.00 2.8 × 10–8
–37.50 8.2 × 10–7
–38.00 1.3 × 10–5
–38.50 1.1 × 10–4
–39.00 1.0 × 10–3
–39.1 1.3 × 10–3
–39.20 1.9 × 10–3
–39.25 2.2 × 10–3
–39.30 Loses Lock

REV. A –7–
AD8015
AC COUPLED PHOTODIODE APPLICATION FOR and typical sensitivity of –35 dBm. AC coupling the input also
IMPROVED DYNAMIC RANGE results in improved pulse width modulation performance.
AC coupling the photodiode current input to the AD8015 (Fig- Careful attention to minimize parasitic capacitance at the
ure 17) extends fiber optic receiver overload by 3 dB while sacri- AD8015 input (from the photodetector input), RAC and CAC are
ficing only 1 dB of sensitivity (increasing receiver dynamic range critical for sensitivity performance in this application. Note that
by 2 dB). This application results in typical overload of –4 dBm, CAC of 0.01 µF was chosen for a low frequency cutoff equal to
2.2 kHz.

C1973–6–1/96
+VS
+VS

AD8015
1 8 V1
10kΩ
CAC LPF: R
50Ω 3dB@ R
2 +1 7 0.7 x F CLOCK CLK
0.01µF G = 30 LPF: RECOVERY DATA
RAC G=3 3dB@
7k 3 6 0.7 x F QUANTIZER
50Ω
+1 R > 40Ω
C1 >100pF
4 – + +VS 5 4.5V < VS < 11V
1.7V

C1

Figure 17. AC Coupled Photodiode Application for Improved Dynamic Range

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Small Outline IC Package (SO-8)

0.1968 (5.00)
0.1890 (4.80)

8 5
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 4
0.2284 (5.80)

PIN 1 0.0688 (1.75) 0.0196 (0.50)

x 45°
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
0.0040 (0.10)

8°
0.0500 0.020 (0.51) 0° 0.0500 (1.27)
SEATING 0.0098 (0.25)
(1.27) 0.013 (0.33)
PLANE 0.0160 (0.41)
BSC 0.0075 (0.19)

PRINTED IN U.S.A.

–8– REV. A