Elec-1 sem3
Elec-1 sem3
• MOVX A, @ DPTR is the instruction used to read external RAM. This has many
applications where collecting large number of bytes data is required.
• During any memory access cycle, port 0 is time multiplexed. That is, it first provides
the lower byte of the 16-bit memory address and then acts as a bidirectional data bus
to write or read a byte of memory data.
• Port 2 provides the high byte of the memory address during the entire memory
read/write cycle.
• The lower address byte from port 0 must be latched into an external register to save
the byte. Address byte save is accomplished by the ALE clock pulse that provides the
correct timing for 74373 to latch. The port 0 pins then become free to serve as a data
bus.
Q) Interrupts in 8051
• 5 interrupts:
o INT0 (external)
o INT1 (external)
o Timer 0
o Timer 1
o Serial (Rx/Tx)
• Controlled by IE (enable) and IP (priority) registers.
Q) Explain internal RAM organisation of 8051 microcontroller.
• The 128 byte internal RAM, which is organized into three distinct areas
• Thirty-two bytes from address 00H to 1FH that make up 32 working registers are
organized as four banks of eight registers each.
• The four register banks are numbered from 0 to 3 and are made up of eight registers
named R0 to R7.
• Each register can be addressed by name (when its bank is selected) or by its RAM
address. Thus, R0 of bank 3 is R0 (if bank 3 is currently selected) or address 18H
(whether bank 3 is selected or not).
• Bits RS0 and RS1 in the PSW determine which bank of registers is currently in use
at any time when the program is running.
• Register banks not selected can be used as general purpose RAM. Bank 0 is selected
on reset.
• A bit-addressable area of 16 bytes occupies RAM byte addresses 20H to 2FH,
forming a total of 128 addressable bits
• A general purpose RAM and above bit area, from 30H to 7FH is addressable as
bytes.
Q) Input/Output ports of 8051
• 4 I/O Ports (P0–P3), each 8-bit:
o Port 0: Open-drain, needs pull-up
o Port 1: Full I/O
o Port 2: Higher address lines
o Port 3: Special functions (INT, Tx/Rx, etc.)
#include <reg51.h>
void delay() {
int i;
for(i = 0; i < 5000; i++);
}
void main() {
unsigned char val = 0;
while (1) {
for(val = 0; val < 255; val++) {
P1 = val;
delay();
}
for(val = 255; val > 0; val--) {
P1 = val;
delay();
}
}
}
Q) Write any five features of 8051 microcontroller.
1. 8-bit processor
2. 128 bytes internal RAM
3. 4 parallel I/O ports
4. Two 16-bit timers/counters
5. Full duplex serial communication
6. 32 I/O lines, 64 KB external ROM support
7. Bit-addressable memory
Q) Stepper Motor
• Electromechanical motor that rotates in steps.
• Step angle = 360° / steps per revolution.
• Controlled using pulses and drivers.
Q) Register Banks in 8051
• Total 4 banks (Bank 0 to Bank 3)
• Each has 8 registers (R0–R7)
• Located from 00H–1FH
• Select bank using bits of PSW (RS1, RS0)
Q) Data types used in 8051 C Program
• unsigned char, signed char, int, unsigned int, bit
• Example:
unsigned char a = 0xFF;
bit flag = 1;
Q) Logical Instructions (Any three)
1. ANL A, #data – Logical AND
2. ORL A, #data – Logical OR
3. XRL A, #data – Exclusive OR
4. CPL A – Complement accumulator
5. CLR A – Clear accumulator
Q) TCON Register
• TCON = Timer/Counter Control
• Bit-addressable register
• Controls timers and external interrupts
Bit Function
Timer 0 000BH 2
Timer 1 001BH 4
MOV A, #00H
INC R0
SJMP $
• The block diagram of the 8051 in Fig. 1.2 shows all of the features which are unique
to microcontrollers.
• The basic architecture of 8051 microcontroller can be divided into seven parts : 1.
Processing unit
2. Register set
3. Memory units 4. I/O ports and serial port
5. Timing and control unit 6. Interrupt structures 7. Timers
• The programming model of 8051 is shown in Fig. 1.3. From the block diagram and
programming model registers, Special Function Registers (SFR) and its memory
location can be studied.
Q) Differentiate between Asynchronous and synchronous serial communication.
Feature Synchronous Asynchronous
Communication Communication
Clock Signal Uses a common clock signal No clock signal is shared;
shared between sender and sender and receiver use their
receiver. own clocks.
Data Data is transmitted in a Data is sent in individual
Transmission continuous stream. bytes with start and stop bits.
Synchronization Synchronization is achieved Synchronization is done using
using the clock signal. start and stop bits.
Speed Generally faster due to Slower due to overhead of
continuous transmission. start/stop bits.
Complexity More complex hardware Simpler hardware and easier
(requires clock management). to implement.
Example SPI (Serial Peripheral UART (Universal
Protocols Interface), I²C (Inter- Asynchronous Receiver
Integrated Circuit) Transmitter)
6 – Reserved