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BE COA Syllabus 4th Semester

Coa University (Chandigarh University)

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Course Code Course Title: L T P C CH Course

23CST-204 / Computer Organization & Architecture Type
23ITT-204 3 0 0 3 3 MJC

a. Course Description
This course is primarily meant to teach undergraduate students the basic operations of computing hardware and how it
interfaces with software. It would provide the students with an understanding of system-level programming and provide a
high-level understanding of the role played by compilers, assemblers, instruction sets, and hardware. Students would know
how to represent fixed-point and floating-point numbers in a computer and develop hardware algorithms using them for
fixed-point and floating-point arithmetic. The course would display an understanding of the instruction set of RISC
processors and develop an understanding of how memory is organized and managed in a modern digital computer, including
cache, virtual and physical memory. It discusses input-output units and how they communicate with the processor, and how
their performance is computed. Finally, the students would be able to analyze the performance of a digital computer using
different parameters and profiling results for various algorithms in a benchmark.
b. Course Objectives
1. To get familiarized with the architecture of a processor.
2. To get a good understanding of various functional units of computer.
3. To understand the design of a basic computer system.
c. Course Outcomes

CO1 Understand the organization of a computer system in terms of its main components.
CO2 Identify different processor architectures and their way of working.
CO3 Classifying various parts of a system memory hierarchy.
CO4 Analyze and compare different input/output mechanisms.
CO5 Evaluate interface digital circuits to microprocessor systems.

d. Syllabus
Unit I 15 Hours
Chapter 1.1 Basic concepts: Digital computer with its block diagram, CPU, memory, input-output
subsystems, control unit; Computer Registers, System bus structure-data, address, and control
bus, Common Bus System, Overview of memory and I/O addressing
Chapter 1.2 Instruction Set Architectures: Levels of Programming Languages, Assembly Language
Instructions: instruction cycle, Machine language program execution – machine cycle and bus
cycle, instruction types, addressing modes, Operations in the instruction set; Arithmetic and
Logical, Data Transfer, Timing and control; Instructionset formats.
Chapter 1.3 Computer Organization: CPU organization, General register organization, Stack
organization, Memory Subsystem Organization: Types of memory, Internal Chip Organization.
Unit 2 15 Hours
Chapter 2.1 Design of control unit: Hardwired control unit, Micro-Programmed control unit and
comparative study.
Chapter 2.2 Memory organization: Memory hierarchy, Main memory, Auxiliary memory, Associative
memory, Cache memory and its design issues, Virtual memory: Paging, Segmentation,
Memory management hardware.
Chapter 2.3 Input-output organization: Asynchronous Data transfer, Interrupts, Modes of transfer,
Programmed I/O, Priority interrupt, DMA, and I/O Processor.
Unit 3 15 Hours
Chapter 3.1 Introduction to Parallel Processing: Parallelism in uniprocessorsystem, Flynn’s
Classification, Concept of pipelining, Pipeline hazards, Instruction Pipeline,
Amdahl’s Law, Throughput and Speedup, RISC and CISC architecture.
Chapter 3.2 Multiprocessors: Characteristics of multiprocessors, Uniform and non-uniform
memory access multi processors, various interconnection networks, Tiled chip
multicore processors.

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e. Textbooks
a. Carpinelli J.D,” Computer systems organization &Architecture”, Fourth Edition, AddisonWesley.
b. Patterson and Hennessy, “Computer Architecture”, Fifth Edition MorgaonKauffman.

f. Reference books
1. J.P. Hayes, “Computer Architecture and Organization”, ThirdEdition.
2. Mano, M., “Computer System Architecture”, Third Edition, Prentice Hall.
3. Stallings, W., “Computer Organization and Architecture”, Eighth Edition,

g. Assessment Pattern -Internal and External

The performance of student is evaluated as follows:

Theory
Components Internal Mid Term End Term
Assessment Assessment Assessment
Marks 20 20 60
Total Marks 100

Internal Evaluation Component

Type of Weightageof Final Weightage in

Frequencyof
Sr.No. Assessment actual Internal Assessment Remarks
Task
Task conduct (Prorated Marks)
10 marks of
each One Per
1. Assignment* Unit 10 marks
assignment

Time Bound 12 marks of One Per

2. 4 marks
Surprise Test each test Unit

4 marks of
3. Quiz 2 Per Unit 4 marks
each quiz

Mid- 20 marksfor
Semester one 2 per
4. semester 20 marks
Test** MST.

Only for Self

Presentation Study MNG
5. Non Graded: Engagement Task
***
Course

One per
6. Homework NA lecture Non Graded: Engagement Task
(2 questions)

Discussion One per

7. NA Non Graded: Engagement Task
Forum Chapter

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h. CO-PO Mapping

Course PO PO PO PO PO PO PO PO PO PO PO PO PO P0 PO PO PO

Outcome 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CO1 3 - 2 3 - - - - - 3 - 2 1 2 0 0 0

CO2 3 - 2 3 - - - - - 3 - 2 0 0 0 0 0

CO3 3 1 2 2 - - - - - 2 - 1 0 0 0 0 0

CO4 3 1 2 2 - - - - - 2 - 1 1 2 0 0 0

CO5 3 1 2 2 - - - - - 2 - 1 1 1 0 0 0

Course Outcome
PSO1 PSO2 PSO3

CO1 - 3 1
CO2 - 3 2
CO3 - 2 3
CO4 - 2 -
CO5 - 2 -

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