RHFLVDSR2D2

Rad-hard dual LVDS driver-receiver

Datasheet - production data

 Large input common mode: -4 V to +5 V

 Guaranteed up to 300 krad TID
 SEL immune up to 135 [Link]²/mg
 SET/SEU immune up to 32 [Link]²/mg

Description
Dual low voltage differential signaling (LVDS),
Ceramic Flat-18 driver receiver designed, packaged and qualified
The upper metallic lid is for use in aerospace environments in a low-power
electrically connected to ground and fast-transmission standard, and operating at
3.3 V power supply (3.6 V max operating and
4.8 V AMR). The RHFLVDSR2D2 operates over a
Features controlled impedance of 100-ohm transmission
media that may be printed circuit board traces,
 Dual drivers, TTL compatible inputs/LVDS back planes, or cables.
outputs
The circuit features an internal fail-safe function to
 Dual receivers, LVDS inputs/TTL compatible
ensure a known state in case of an input short
outputs
circuit or floating input. All pins have cold spare
 Individual Enable/Disable function with high- buffers to ensure they are in high impedance
impedance when VCC is tied to GND.
 ANSI TIA/EIA-644 compliant The RHFLVDSR2D2 can operate over a large
 400 Mbps (200 MHz) temperature range of -55 °C to +125 °C and it is
 Cold spare on all pins housed in an hermetic Ceramic Flat-18 package.

 Fail-safe function
 3.3 V operating power supply
 4.8 V absolute rating
 Power consumption: 50 mW at 3.3 V
 Hermetic package

Table 1. Device summary

Lead
Reference SMD pin Quality level Package Mass EPPL(1) Temp. range
finish

Engineering
RHFLVDSR2D2K1 - Ceramic - -55 °C to
model Gold 0.8 g
Flat-18 125 °C
RHFLVDSR2D2K01V 5962F0620202 QML-V flight Target
1. EPPL = ESA preferred part list

March 2015 DocID025372 Rev 3 1/17

This is information on a product in full production. [Link]
Contents RHFLVDSR2D2

Contents

1 Functional description and pin configuration . . . . . . . . . . . . . . . . . . . . 3

2 Maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . 4

3 Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Test circuit for the driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6 Test circuit for the receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 Ceramic Flat-18 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

9 Shipping information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2/17 DocID025372 Rev 3

RHFLVDSR2D2 Functional description and pin configuration

1 Functional description and pin configuration

Figure 1. Functional diagram and pinout

RIN1+
Receiver ROUT1
RIN1- RIN1- 1 18 REN1

REN1 RIN1+ 2 17 ROUT1

RIN2+ RIN2+ 3 16 ROUT2

Receiver ROUT2
RIN2- RIN2- 4 15 GND

REN2 REN2 5 14 Vcc

DOUT1+ DOUT2- 6 13 DEN2

DIN1 Driver
DOUT1- DOUT2+ 7 12 DIN2
DEN1
DOUT1+ 8 11 DIN1
DOUT2+
DIN2 Driver DOUT1- 9 10 DEN1
DOUT2-
DEN2

Table 2. Truth table: Driver

Enables Input Output

DEN DIN DOUT+ DOUT-

L X Z Z
L L H
H or floating
H H L
(internal pull-up)
Open L H

Table 3. Truth table: Receiver

Enables Input Output

REN RIN+ - RIN- ROUT

L X Z
Vid  0.1 V H
Vid  -0.1 V L
H or floating
(internal pull-up) -0.1 V < Vid < +0.1 V ?
Full fail-safe Open/Short or
H
terminated

Note: Vid = (VIN+) - (VIN-), L = low level, H = high Level, X = don’t care, Z = high impedance (off)

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Maximum ratings and operating conditions RHFLVDSR2D2

2 Maximum ratings and operating conditions

Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

VCC (1)
Supply voltage 4.8
Vi TTL inputs (operating or cold-spare) -0.3 to +4.8
LVDS outputs and TTL outputs (operating or V
VOUT -0.3 to +4.8
cold-spare)
VCM LVDS common mode (operating or cold-spare) -5 to +6
Tstg Storage temperature range -65 to +150
°C
Tj Maximun junction temperature +150
Rthjc Thermal resistance junction to case(2) 21 °C/W
HBM: Human body model
– All pins excepted LVDS inputs and outputs 2 kV
ESD – LVDS inputs and outputs vs. GND 8
CDM: Charge device model 500 V
1. All voltages, except the differential I/O bus voltage, are with respect to the network ground terminal.
2. Short-circuits can cause excessive heating. Destructive dissipation can result from short-circuits on the
amplifiers.

Table 5. Operating conditions

Symbol Parameter Min. Typ. Max. Unit

VCC Supply voltage 3 3.3 3.6

VCM Static common mode on the receiver -4 +5 V
VIN Driver DC input voltage (TTL inputs) 0 3.6
TA Ambient temperature range -55 +125 °C

4/17 DocID025372 Rev 3

RHFLVDSR2D2 Radiation

3 Radiation

Total dose (MIL-STD-883 TM 1019)

The products guaranteed in radiation within the RHA QML-V system fully comply with the
MIL-STD-883 TM 1019 specification.
The RHFLVDSR2D2 is RHA QML-V, tested and characterized in full compliance with the 
MIL-STD-883 specification, between 50 and 300 rad/s only (full CMOS technology).
All parameters provided in Table 7: Electrical characteristics apply to both pre- and post-
irradiation, as follows:
 All test are performed in accordance with MIL-PRF-38535 and test method 1019 of
MIL-STD-883 for total ionizing dose (TID).
 The initial characterization is performed in qualification only on both biased and
unbiased parts.
 Each wafer lot is tested at high dose rate only, in the worst bias case condition, based
on the results obtained during the initial qualification.

Heavy ions
The behavior of the product when submitted to heavy ions is not tested in production.
Heavy-ion trials are performed on qualification lots only.

Table 6. Radiations
Type Characteristics Value Unit

TID High-dose rate (50 - 300 rad/sec) 300 krad

SEL immunity up to: 135
(with a particle angle of 60 °, at 125 °C)
SEL immunity up to: 67
Heavy ions [Link]²/mg
(with a particle angle of 0 °, at 125 °C)
SET/SEU immunity up to: 32
(at 25 °C)

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17
Electrical characteristics RHFLVDSR2D2

4 Electrical characteristics

In Table 7 below, VCC = 3 V to 3.6 V, capa-load (CL) = 10 pF, typical values are at 
Tamb = +25 °C, min. and max values are at Tamb = - 55 °C and + 125 °C unless otherwise
specified.

Table 7. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Whole circuit
Total enabled supply current, Driver: VIN = 0 V or VCC and
ICC drivers and receivers enabled, load = 100 W.  15 19
not switching receiver: VID = 400 mV
mA
Total disabled supply current, REN and DEN = GND
ICCZ loaded or not loaded, drivers Driver: VIN = 0 V or VCC 4
and receivers disabled Receiver: VID = 400 mV
VIH Input voltage high 2 VCC
REN, DEN, and TTL inputs V
VIL Input voltage low GND 0.8
REN, DEN, and TTL inputs
IIH High level input current -10 10
VCC = 3.6 V, VIN = VCC
REN, DEN and TTL inputs
IIL Low level input current -10 10
VCC = 3.6 V, VIN = 0
LVDS outputs power off
VCC = 0 V, VOUT = 3.6 V -50 +50
leakage current µA
LVDS inputs power off leakage
VCC = 0 V, VIN = -4 V to 5 V -60 60
IOFF (1) current
VCC = 0 V
TTL I/Os power off leakage
VIN, REN, and DEN = 3.6 V -10 10
current
VOUT = 3.6 V
Driver
VOH Output voltage high 1.65
V
VOL Output voltage low 0.925
VOD Differential output voltage 250 400
Change of magnitude of VOD1 mV
DVOD for complementary output RL = 100 Ω 10
states
VOS Offset voltage 1.125 1.45 V
Change of magnitude of VOS for
DVOS 15 mV
complementary output states
VIN= 0V and VOUT- = 0 V 
IOS Output short-circuit current -9 mA
or VIN = VCC and VOUT+ = 0 V
IOZ High impedance output current Disabled, VOUT = 3.6 V or GND -10 10 µA
CIN Input capacitance 3 pF

6/17 DocID025372 Rev 3

RHFLVDSR2D2 Electrical characteristics

Table 7. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Propagation delay time, high to

tPHLD 0.5 1.5
low output
Propagation delay time, low to
tPLHD 0.5 1.5
high output
Differential output signal rise
tr 0.8
time
Load: refer to Figure 3
Differential output signal fall
tf 0.8
time
tSK1 Channel-to-channel skew(2) 0.28
tSK2 Chip-to-chip skew(3)(4) 0.7
ns
Differentialskew(5)
tSKD 0.3
(tPHLD-tPLHD)
Propagation delay time, high
tPHZ 2.8
level to high impedance output
Propagation delay time, low
tPLZ 2.8
level to high impedance output
Load: refer to Figure 4
Propagation delay time, high
tPZH 2.5
impedance to high level output
Propagation delay time, high
tPZL 2.5
impedance to low level output
Receiver
VCM = 1.2 V -100
VTL Differential input low threshold
-4 V < VCM < +5 V -130
mV
VCM = 1.2 V +100
VTH Differential input high threshold
-4 V < VCM < +5 V +130
VCL TTL input clamp voltage ICL = 18 mA 1.5
V
VCMR Common mode voltage range VID = 200 mVp-p -4 +5
VCMREJ Common mode rejection(6) F = 10 MHz 300 mVp-p
IID Differential Input current VID = 400 mVp-p -10 10
µA
IICM Common mode Input current VIC = - 4 V to + 5 V -70 70
VOH Output voltage high IOH = -0.4 mA, VCC = 3 V 2.7
V
VOL Output voltage low IOL = 2 mA, VCC = 3 V 0.25
IOS Output short circuit current VOUT = 0 V -90 -30 mA
IOZ Output tri-state current Disabled, VOUT = 0 V or VCC -10 10 µA
CIN Input capacitance IN+ or IN- to GND 3 pF
Rout Output resistance 45 W

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17
Electrical characteristics RHFLVDSR2D2

Table 7. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Propagation delay time, high to

tPHLD VID = 200 mVp-p, input pulse 1 2.5
low output
from 1.1 V to 1.3 V, VCM = 1.2 V ns
Propagation delay time, low to Load: refer to Figure 6
tPLHD 1 2.5
high output
tSK1 Channel-to-channel skew(2) 0.25
tSK2 Chip-to-chip skew(3)(4) VID = 200 mVp-p 0.7
(5) Load: refer to Figure 3
Differential skew 
tSKD 0.3
(tPHLD-tPLHD)
tr Output signal rise time 0.9
Load: refer to Figure 3
tf Output signal fall time 0.9
Propagation delay time, low ns
tPLZ 3.8
level to high impedance output
Propagation delay time, high
tPHZ 3.8
level to high impedance output
Load: refer to Figure 4
Propagation delay time, high
tPZH 3.8
impedance to high level output
Propagation delay time, high
tPZL 3.8
impedance to low level output
tD1 Fail-safe to active time 1
µs
tD2 Active to fail-safe time 1
1. All pins except pin under test and VCC are floating
2. tSK1 is the maximum delay time difference between all outputs of the same device (measured with all inputs connected
together).
3. tSK2 is the maximum delay time difference between outputs of all devices when they operate with the same supply voltage,
at the same temperature.
4. Guaranteed by design
5. tSKD is the maximum delay time difference between tPHLD and tPLHD, see Figure 3.
6. Guaranteed by characterization on bench.

Cold sparing
The RHFLVDSR2D2 features a cold spare input and output buffer. In high reliability
applications, cold sparing enables a redundant device to be tied to the data bus with its
power supply at 0 V (VCC = GND) without affecting the bus signals or injecting current from
the I/Os to the power supplies. Cold sparing also allows redundant devices to be kept
powered off so that they can be switched on only when required. This has no impact on the
application. Cold sparing is achieved by implementing a high impedance between the I/Os
and VCC. ESD protection is ensured through a non-conventional dedicated structure.

Fail-safe
In many applications, inputs need a fail-safe function to avoid an uncertain output state
when the inputs are not connected properly. For the drivers: in case of an LVDS input short
circuit or floating inputs, the TTL outputs remain in stable logic-high state.

8/17 DocID025372 Rev 3

RHFLVDSR2D2 Test circuit for the driver

5 Test circuit for the driver

Figure 2. Voltage and current definition

OUT+
II
LVDS VOS=(VOUT+ + VOUT-)/2
VOD
Driver

OUT-

VIN
VOUT- VOUT+

Figure 3. Test circuit, timing and voltage definitions for differential output signal

LVDS 100ohm
Driver

CL=10pF CL=10pF

VIN
1.5V 1.5V

tPHLD tPLHD

80% 80%
VOD
20% 20%

tf tr

1. All input pulses are supplied by a generator with the following characteristics: tr or tf ≤ 1 ns, 
f = 1 MHz, ZO = 50 Ω, and duty cycle = 50%.
2. The product is guaranteed in test with CL = 10 pF.

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Test circuit for the driver RHFLVDSR2D2

Figure 4. Enable and disable waveforms

50ohm
OUT+

LVDS VOD 1.2V

Driver OUT- 50ohm

VOS

CL=10pF CL=10pF

DEN 50% 50%

TPZH TPHZ

VOUT+ or VOUT- 50% 50%

TPZL TPLZ

50% 50%
VOUT+ or VOUT-

1. All input pulses are supplied by a generator with the following characteristics: tr or tf ≤ 1 ns, 
fREN or fDEN = 500 kHz, and pulse width REN or DEN = 500 ns.
2. The product is guaranteed in test with CL = 10 pF.

10/17 DocID025372 Rev 3

RHFLVDSR2D2 Test circuit for the receiver

6 Test circuit for the receiver

Figure 5. Timing test circuit and waveforms

II
IN+

VCM=(VIN+ + VIN-)/2 LVDS

VID
Receiver

IN-

10pF VO
VIN+ VIN-

VIN+
50% 50% VID=200mVp-p
VIN-

tPHLD tPLHD

80% 80%
VO
20% 20%

tf tr

1. All input pulses are supplied by a generator with the following characteristics: tr or tf ≤ 1 ns, 
f = 1 MHz, ZO = 50 Ω, and duty cycle = 50%.
2. The product is guaranteed in test with CL = 10 pF.

DocID025372 Rev 3 11/17

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Test circuit for the receiver RHFLVDSR2D2

Figure 6. Enable and disable waveforms

Vcc
II
(A) IN+
400 ohm
VCM=(VIA+VIB)/2 LVDS
VID Receiver

(B) IN- 400 ohm

10pF VO
VIA VIB

DEN 50% 50%

TPZH TPHZ
VOH
VOH – 0.5V
VO
high 50%
VCC /2 VCC /2

VO TPZL TPLZ
Low VCC /2 VCC /2

50%
VOL VOL + 0.5V

1. All input pulses are supplied by a generator with the following characteristics: tr or tf ≤ 1 ns, 
fG or fG = 500 kHz, and pulse width G or G = 500 ns.
2. The product is guaranteed in test with CL = 10 pF.

12/17 DocID025372 Rev 3

RHFLVDSR2D2 Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: [Link].
ECOPACK® is an ST trademark.

DocID025372 Rev 3 13/17

17
Package information RHFLVDSR2D2

7.1 Ceramic Flat-18 package information

Figure 7. Ceramic Flat 18 package mechanical drawing

1. The upper metallic lid is electrically connected to ground.

Table 8. Ceramic Flat 18 package mechanical data

Dimensions

Ref. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 2.18 2.46 2.74 0.86 0.097 0.108

A1 0.66 - - 0.026 - -
b 0.38 0.43 0.48 0.015 0.017 0.019
c 0.10 0.14 0.18 0.004 0.005 0.007
D 11.61 11.81 12.01 0.457 0.465 0.473
E 6.99 7.11 7.24 0.275 0.280 0.285
E2 4.67 4.82 4.98 0.184 0.19 0.196
E3 0.76 - - 0.03 - -
e - 1.27 - - 0.050 -
L 7.37 7.87 8.37 0.290 0.031 0.330
S1 0.13 - - 0.005 - -

14/17 DocID025372 Rev 3

RHFLVDSR2D2 Ordering information

8 Ordering information

Table 9. Order codes

Order code Description Temp. range Package Marking(1) Packing

Engineering
RHFLVDSR2D2K1 -55 °C to Ceramic RHFLVDSR2D2K1 Strip
model
125 °C Flat-18 pack
RHFLVDSR2D2K01V QML-V flight 5962F0620202VYC
1. Specific marking only. Complete marking includes the following:
- SMD pin (on QML-V flight only)
- ST logo
- Date code (date the package was sealed) in YYWWA (year, week, and lot index of week)
- QML logo (Q or V)
- Country of origin (FR = France).

Note: Contact your ST sales office for information regarding the specific conditions for products in
die form and QML-Q versions.

9 Shipping information

Date code
The date code is structured as follows:
 Engineering model: EM xyywwz
 QML flight model: FM yywwz
Where:
x = 3 (EM only), assembly location Rennes (France)
yy = last two digits of the year
ww = week digits
z = lot index of the week

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17
Revision history RHFLVDSR2D2

10 Revision history

Table 10. Document revision history

Date Revision Changes

29-Oct-2013 1 Initial release

– Updated production status and marking information
relative to order code RHFLVDSR2D2K01V in
Table 1: Device summary and Table 9: Order codes.
– Removed row regarding CL parameter from Table 5:
30-Oct-2014 2 Operating conditions.
– Changed title of Section 3 to “Radiation” and moved
Electrical characteristics to Section 4.
– Updated the maximum channel-to-channel skew
value from 0.2 ns to 0.25 ns in Table 7.
– Added VOUT to Table 4: Absolute maximum ratings.
04-Mar-2015 3
– Added VCL to Table 7: Electrical characteristics.

16/17 DocID025372 Rev 3

RHFLVDSR2D2

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DocID025372 Rev 3 17/17

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