Aashish Pawankumar Pandia 203196001

Electrical Engineering M.Tech.

Indian Institute of Technology Bombay Gender: Male
Specialization: Electronic Systems DOB: 17/01/1994

Examination University Institute Year CPI / %

Post Graduation IIT Bombay IIT Bombay 2023 7.91
Graduation Gujarat Technological University Govt. Engineering College, Surat 2017 7.91
Graduation Specialization: Electronics & Communication
Intermediate Gujarat S & HS Education Board M.T. Jariwala Madhyamik Shala 2012 63.00%
Matriculation Gujarat S & HS Education Board Modern English School 2010 74.15%

AREAS OF INTEREST
Digital VLSI Design, Computer Architecture, DSP System, Testing and Verification of VLSI Circuits, AI - ML.
MAJOR PROJECTS
M.Tech Dissertation : Light weight AI/ML algorithms for load disaggregation [Jun’22 - Present]
Guide: Prof. Anupama Kowli, Department of Electrical Engineering, IIT Bombay
Objective:
• To have a non-intrusive load monitoring system capable of disaggregating appliance level power consumption with
data available at a single Point-of-Connection.
Completed Work:
• Identification of electrical parameters and features that can disaggregate different appliances from a single
set of measurements collected at the point-of-connection through literature review on load disaggregation.
• Development of simulator for emulating the electrical behavior of typical household appliances and simulating
the electrical parameters recorded by residential smart meters.
Ongoing Work:
• Calibrating & verifying the simulator using available recorded data sets and data from industry partner.
• Development of Machine Learning based load disaggregation algorithms on simulated and recorded data.
Future Work:
• Develop a light weight algorithm for load disaggregation capable of running on low-end computing devices.
• Implementation of developed load disaggregation algorithm on Edge computing device.
M.Tech Seminar: Understanding of Different Thermal Building Energy Models. [July’20 - Dec’20]
Guide: Prof. Anupama Kowli, Department of Electrical Engineering, IIT Bombay
• Studied state-of-art Thermal-Energy Models providing thermal profile & energy expenditure of the system.
• Summarised advantages & drawbacks of using physics-based, data-driven & Hybrid methods for generating
Thermal Building Energy Models.
ACADEMIC & SELF PROJECTS
Design of 5-stage Pipelined RISC Processor [May’21]
Course Project: Processor Design, Prof. Virendra Singh
• Designed the architecture of a 16-bit, 5-stage-pipelined RISC processor with R, I, and J type instruction.
• Implemented five stages of pipeline in VHDL, simulated & verified using Altera Quartus II.
• Resolved all data & control hazards, implemented Forwarding Unit & Branch Predictor to improve IPC.
HDL based approach for Texture Classification using Gabor Filters [May’21]
Course Project: VLSI Design Lab, Prof. Sachin Patkar
• Designed a digital system for texture classification using a 5 × 5 filter mask in Verilog, simulated in Modelsim.
• Implemented the convolution operation by designing and implementing a 32-bit Floating point MAC unit.
• Implemented FSM with data fetch and convolution stages for classification of edges with similar orientations.
Six Band Audio Equalizer Implementation on FPGA [May’22]
Course Project: DSP System Design and Implementation, Prof. V Rajbabu
• Implemented six digital FIR filters with configurable coefficients on Zynq-xc7z020 FPGA board.
• Implemented DSP equalizer system processing samples at 44kHz, with hardware switch for band activation.
• Studied implications of using 16-bit fixed point (Q8.8) format over 16-bit floating point format for convolution.
Automatic Test Pattern Generator(ATPG) [Oct’21]
Course Project: Foundation of VLSI CAD, Prof. Virendra Singh
• Implemented PoDeM algorithm to generate Test vectors for stuck-at faults in combinational circuits.
• Generated test vectors by applying single stuck-at fault at different nets in ISCAS’89 benchmark circuits.
• Implemented algorithm in python, reported testability of faults & the fault coverage of combinational circuit.
Heuristic-based Logic Minimizer [Nov’21]
Course Project: Foundation of VLSI CAD, Prof. Virendra Singh
• Implemented 2-level logic minimization of boolean logic functions using ESPRESSO algorithm in Python.
• The algorithm applies Expand, Reduce & Redundancy checks to settle to logic with minimum implicants.
• Successfully verified the working of the algorithm with worked out by hand boolean functions as golden results.
Brent-Kung Logarithmic Adder [Dec’21]
Project : Self
• Designed a logarithmic adder using Brent-Kung methodology operating on 32-bit wide operands.
• Implemented the design in Verilog and verified operation using Modelsim with appropriate test vectors.
• Compared the critical path delay for carry-out and sum bits with delays of a 32-bit Ripple Carry Adder.
Asynchronous FIFO Design [Dec’21]
Project : Self
• Designed N-byte Asynchronous FIFO using Verilog on Intel Quartus tool & Simulated using ModelSim.
• Implemented Two Flip-Flop Synchronizer to avoid condition of Metastability in Clock Domain Crossing.
• Gray code encoding used for inter clock domain controlled data transmission to avoid multi-bit data transition.
16 × 16-bit Digital Multipliers [Dec’21]
Project : Self
• Designed a 16-bit unsigned Wallace multiplier circuit in Verilog & used Brent-Kung Adder for final addition.
• Designed a 16-bit unsigned Dadda multiplier circuit in Verilog & used Brent-Kung Adder for final addition.
• Verified the design by simulations by generating typical test cases in Modelsim Altera.
• Compared the hardware resource uses, identified the critical path & computed the critical path delay(s).
Mathematical hand-written digit recognition using Feed Forward Neural Network [May’21]
Course Project: Introduction to Machine Learning, Prof. Amit Sethi
• Written a generic multilayer perceptron neural network (MLP) from scratch in python without use
of public domain ML libraries, designed NN has provision to include desired number of layers and neurons.
• Trained a NN with 90 neurons (64 input, 16 hidden, 10 output) for digit recognition having sigmoid activation
on neurons & employed MSE loss for back propagation.
• Training and Testing done on UCI handwritten digits data set with 86% accuracy achieved on test data.
Artificial Intelligence based Voice Assistant [May’17]
Bachelor of Engineering Project, Prof. K.I.Tandel. GEC,Surat
• Achieved Voice based Home Automation using Raspberry PI 3 capable of load actuation using relays.
• Interfaced USB mic with R-PI 3 for voice recording, completed speech-to-text conversion with GOOGLE API.
• Trained artificial-intelligence based model for extraction of commands from speech-to-text converted strings.
RELEVANT COURSES
•VLSI Design Lab •VLSI Design Lab •Testing & Verification of VLSI circuits
•Processor Design •VLSI CAD •Introduction to Machine Learning
•DSP & Application •DSP System Design •Algorithmic Design of Digital Systems

TECHNICAL SKILLS
• Tools: Intel Quartus, Altera ModelSim, MATLAB, Ngspice, Eagle, GHDL, GTKWAVE, CCS, Vivado HLS.
• Languages: VHDL, Verilog, Python, C.
• Hardware Platforms: Cyclone IV(DE0-Nano), Arduino, RaspberryPi, TMS320C5535, TIVA C-TM4C123GXL,.
POSITIONS OF RESPONSIBILITY
Project Research Assistant [Aug’20 - Present]
Guide: Prof. Anupama Kowli, Department of Electrical Engineering, IIT Bombay
• Study of different occupant detection techniques.
• Field study of using PIRs for non-intrusive occupant detection: study involved creation of a suitable test-bed,
data collection and analysis performed on recorded data to investigate the efficiency of PIR-based occupant
detection techniques.
• Development of temperature simulators for both CAF and VOC type air conditioning models.
• Set-up of multi-piped data acquisition framework performed by wireless sensor node via NRF module.
• Calibration of sensors for wireless sensor nodes developed at IIT Bombay for building energy management.
• Development of an IR remote for mimicking typical AC remotes for eventual use in an IoT based BEMS.
• Involved in demonstrations of IoT-based building energy management (BEMS) solutions for TEQIP/CEP
courses & department-level activities.
EXTRACURRICULAR ACTIVITIES AND INTEREST
• Performed bhangra in Annual In-sync Dance Showcase, an event by dance club of IIT Bombay. [2022]
• Won 1 st prize in Air Rifle Shooting in ANVASION event of GEC,surat. [2014]
• Completed Basics of SCADA(50 hrs) and Basic of PLC(50 hrs) course from Siemens Centre of Excellence.
• Interest: Balisong tricks, Reading Fiction, Playing Chess, Travelling.