MP QB IA1:

1.8086 Architecture.

8086 Microprocessor Architecture

The 8086 microprocessor consists of two main units:

1. Bus Interface Unit (BIU)

o Handles communication with memory and I/O devices.

o Performs instruction fetching, address calculation, and memory operations.

o Contains the Instruction Queue, Segment Registers, Instruction Pointer, and

Address Adder.

2. Execution Unit (EU)

o Decodes and executes instructions.

o Consists of Control Circuitry, Instruction Decoder, Arithmetic Logic Unit

(ALU), Pointer & Index Registers, and Flag Register.

o Works with the BIU using a pipelined structure to improve e iciency.

3. Memory Segmentation
 o Divides the memory into Code Segment (CS), Data Segment (DS), Stack
Segment (SS), and Extra Segment (ES).

o Helps in e icient memory management and faster execution.

4. Registers

o General-purpose registers (AX, BX, CX, DX) for operations.

o Segment registers (CS, DS, SS, ES) to access memory.

o Special registers like Instruction Pointer (IP) and Flags Register for controlling
execution.

2.All registers in 8086.

The 8086 microprocessor has a 16-bit register architecture divided into
the following categories:

1. General Purpose Registers (GPRs)

These registers are used for arithmetic, logic, and data transfer
operations. Each is 16-bit but can be accessed as two 8-bit registers
(High & Low).

Higher Lower
Register Purpose
8-bit 8-bit

AX Used in arithmetic, logic, and I/O

AH AL
(Accumulator) operations

BX (Base Used in addressing memory (Base

BH BL
Register) pointer)

CX (Count Used in loop and shift/rotate

CH CL
Register) instructions

DX (Data Used in I/O operations and

DH DL
Register) multiplication/division

2. Segment Registers
8086 uses segmentation to divide memory into four 64KB segments.
Register Purpose

CS (Code Segment) Stores the starting address of the code segment

DS (Data Segment) Stores the starting address of the data segment

SS (Stack Segment) Stores the starting address of the stack segment

ES (Extra Segment) Used for string operations

Each segment register holds only the upper 16-bits of a 20-bit address.
The o set is added to calculate the physical address.

3. Pointer and Index Registers

Used for memory addressing, stack operations, and string operations.

Register Purpose

SP (Stack Pointer) Points to the top of the stack

Used for accessing stack memory (helps in

BP (Base Pointer)
function calls)

SI (Source Index) Used for string operations (Source)

DI (Destination
Used for string operations (Destination)
Index)

4. Special Purpose Registers

Register Purpose

IP (Instruction Holds the o set of the next instruction to be

Pointer) executed

Stores status flags that indicate the result of

Flags Register
operations

Flag Register (16-bit)

The 8086 Flag Register consists of 9 active flags divided into:
  Status Flags (Indicate arithmetic results)
o CF (Carry Flag) – Set if an operation generates a carry/borrow
o PF (Parity Flag) – Set if the result has even parity
o AF (Auxiliary Carry Flag) – Used for BCD arithmetic
o ZF (Zero Flag) – Set if result is zero
o SF (Sign Flag) – Set if result is negative
o OF (Overflow Flag) – Set if signed operation results in overflow
 Control Flags (A ect execution)
o TF (Trap Flag) – Enables single-step debugging
o IF (Interrupt Flag) – Enables or disables interrupts
o DF (Direction Flag) – Used in string operations
(increment/decrement)

3.Features of 8086.

 16-bit Microprocessor:
 8086 is a 16-bit processor, meaning it can process 16-bit data at a
time.
 20-bit Address Bus:
 Can access up to 220=1MB2^{20} = 1MB220=1MB memory
locations.
 64K I/O Ports:
 Supports up to 64K input/output ports for peripheral
communication.
 14 Registers:
 It has 14 16-bit registers for e icient execution.
 Multiplexed Address/Data Bus:
  Address and data buses are multiplexed (shared), reducing pin
count.
 Supports Two Modes of Operation:
 Minimum Mode – Used for single processor systems.
 Maximum Mode – Used for multiprocessor systems.
 Instruction Queue (Prefetching):
 Can fetch up to 6 instruction bytes in advance, enabling pipelining.
 High-Speed Execution:
 Executes both arithmetic and logical operations, including
multiplication and division.
 Clock Speed Variants:
 Available in 5 MHz, 8 MHz, and 10 MHz versions.
 40-Pin Dual Inline Package (DIP):
 Comes in a 40-pin DIP package.
 Byte-Addressable Memory:
 Can access memory byte by byte.
 Power Supply Requirement:
 Requires a +5V DC power supply.

4.8086 Pin Diagram.

1. Power Supply & Clock Signals
 VCC (Pin 40): Provides +5V DC power supply.
 VSS (Pins 1 & 20): Ground connection.
 CLK (Pin 19): Clock input; provides the timing signal for the
processor. Operates at 5 MHz, 8 MHz, or 10 MHz.
2. Address/Data Bus (Multiplexed Pins)
 AD0 – AD15 (Pins 2-16, 39):
o Multiplexed address/data bus.
o Carries addresses during T1 state (ALE = 1) and data during
remaining T states (ALE = 0).
 A16/S3 – A19/S6 (Pins 35-38):
o Used as address lines during memory operations.
o Serve as status signals (S3-S6) in I/O operations.

3. Control & Status Signals

 ALE (Pin 25):
o Address Latch Enable—helps separate address and data bus.
 RD’ (Pin 32):
o Read signal—indicates that the processor is reading data from
memory or I/O devices.
 WR’ (Pin 29):
o Write signal—indicates that the processor is writing data to
memory or I/O devices.
 M/IO’ (Pin 28):
o Memory/IO selection—indicates whether an operation is for
memory (1) or I/O (0).
 DEN’ (Pin 26):
o Data Enable—activates external transceivers during data
transfer.
 DT/R’ (Pin 27):
o Data Transmit/Receive—determines direction of data flow in
transceivers.
4. Interrupt Signals
 INTR (Pin 18):
o Interrupt Request—a general-purpose interrupt input,
processed if enabled.
 NMI (Pin 17):
o Non-Maskable Interrupt—a high-priority interrupt that cannot
be disabled.
 INTA’ (Pin 24):
o Interrupt Acknowledge—indicates that the processor has
acknowledged an interrupt request.

5. Minimum/Maximum Mode Signals

(These determine whether the 8086 operates in minimum or maximum
mode.)
 MN/MX’ (Pin 33):
o Minimum/Maximum mode selector
o 1 = Minimum Mode (Single Processor Mode)
o 0 = Maximum Mode (Multiprocessor Mode)
Minimum Mode Signals (Used when MN/MX' = 1)
 HOLD (Pin 31):
o Hold request from external devices—requests control of
system buses.
 HLDA (Pin 30):
o Hold Acknowledge—processor grants bus control to an
external device.
Maximum Mode Signals (Used when MN/MX' = 0)
 S0’, S1’, S2’ (Pins 26-28):
 o Indicate the operation type (memory read/write, I/O read/write,
etc.).
 LOCK’ (Pin 29):
o Bus lock signal—prevents other processors from accessing
the bus.
 RQ’/GT0’, RQ’/GT1’ (Pins 30, 31):
o Request/Grant—used in multiprocessor communication for
bus control.

6. Other Control Pins

 TEST (Pin 23):
o Used for debugging—halts execution if low.
 READY (Pin 22):
o Indicates whether external devices are ready for
communication.
 RESET (Pin 21):
o Resets the microprocessor and restarts execution.

5. physical address num:

Physical Address Calculation in 8086 Microprocessor
The physical address in the 8086 microprocessor is the actual 20-bit
address used to access memory. It is computed using segment and o set
addressing.
Formula for Physical Address Calculation
Physical Address=(Segment Register×10H)+O set\text{Physical Address} =
(\text{Segment Register} \times 10H) +
\text{O set}Physical Address=(Segment Register×10H)+O set
  The segment register (CS, DS, SS, ES) holds the starting address of
a 64KB memory segment.
 The o set is the location within that segment.

Example 1: Code Segment Addressing

Given:
 CS = 3456H
 IP = 789AH
 Find the physical address.
Solution:
Physical Address=(3456H×10H)+789AH\text{Physical Address} = (3456H
\times 10H) + 789AHPhysical Address=(3456H×10H)+789AH
=34560H+789AH= 34560H + 789AH=34560H+789AH =3BEFAH=
3BEFAH=3BEFAH
Final Physical Address = 3BEFAH

Example 2: Data Segment Addressing

Given:
 DS = 1234H
 O set = 4321H
 Find the physical address.
Solution:
Physical Address=(1234H×10H)+4321H\text{Physical Address} = (1234H
\times 10H) + 4321HPhysical Address=(1234H×10H)+4321H
=12340H+4321H= 12340H + 4321H=12340H+4321H =16661H=
16661H=16661H
Final Physical Address = 16661H
6.timing Diagram:
7.Addressing modes with EX:

Addressing Modes in 8086 Microprocessor

Addressing modes define the way an operand (data) is accessed in an
instruction. There are eight addressing modes in 8086, as described in
your PDF.

1. Immediate Addressing Mode

 The operand (data) is directly specified in the instruction.
 Used for loading constant values into registers.
Example:
assembly
CopyEdit
MOV CX, 4929H ; Moves immediate value 4929H into CX
ADD AX, 2387H ; Adds immediate value 2387H to AX
MOV AL, FFH ; Moves immediate value FFH to AL

2. Register Addressing Mode

 The operand is in a register.
 The instruction specifies the source and destination registers.
Example:
assembly
CopyEdit
MOV CX, AX ; Copies the contents of AX into CX
ADD BX, AX ; Adds AX to BX

3. Direct Addressing Mode

 The operand is stored in a memory location, and its address is
directly given in the instruction.
Example:
assembly
CopyEdit
MOV AX, [1592H] ; Moves data from memory address 1592H into AX
MOV AL, [0300H] ; Moves data from memory address 0300H into AL

4. Register Indirect Addressing Mode

 The memory address is stored in a register (BX, BP, SI, DI), and the
instruction uses the register to access memory.
Example:
assembly
CopyEdit
MOV AX, [BX] ; If BX = 4895H, data from address 4895H is moved to AX
ADD CX, [BX] ; Adds value from memory at [BX] to CX

5. Based Addressing Mode

 The e ective memory address is calculated by adding a
displacement to a base register (BX or BP).
Example:
assembly
CopyEdit
MOV DX, [BX+04] ; Moves data from memory address (BX + 04H) into DX
ADD CL, [BX+08] ; Adds value from memory address (BX + 08H) to CL

6. Indexed Addressing Mode

 The e ective address is calculated by adding a displacement to an
index register (SI or DI).
Example:
assembly
CopyEdit
MOV BX, [SI+16] ; Moves data from (SI + 16H) into BX
ADD AL, [DI+16] ; Adds value from (DI + 16H) to AL

7. Based Indexed Addressing Mode

 The e ective address is calculated by adding base register (BX/BP)
and index register (SI/DI).
Example:
assembly
CopyEdit
ADD CX, [AX+SI] ; Adds value from memory at (AX + SI) to CX
MOV AX, [AX+DI] ; Moves data from memory at (AX + DI) into AX

8. Based Indexed with Displacement Mode

 The e ective address is computed using a base register + index
register + displacement.
Example:
assembly
CopyEdit
MOV AX, [BX+DI+08] ; Moves data from (BX + DI + 08H) into AX
ADD CX, [BX+SI+16] ; Adds value from (BX + SI + 16H) to CX
Summary of Addressing Modes

E ective Address
Addressing Mode Example
Calculation

Immediate Direct operand MOV AX, 100H

Register Operands in registers MOV BX, CX

Direct Given memory address MOV AL, [2000H]

Register Indirect Register holds address MOV AX, [BX]

Based Base register + displacement MOV DX, [BX+04H]

Indexed Index register + displacement MOV BX, [SI+16H]

Based Indexed Base + Index register MOV AX, [BX+DI]

Based Indexed + MOV CX,

Base + Index + Displacement
Disp. [BX+SI+16H]

8.Instructions with syntax and EX:

The 8086 instruction set consists of di erent types of instructions used to
perform operations like data transfer, arithmetic, logical, program control,
and more.

1. Data Transfer Instructions

Used to transfer data between registers, memory, and I/O ports.

Instruction Syntax Example

MOV (Move) MOV destination, source MOV AX, BX

PUSH (Push onto Stack) PUSH register/memory PUSH AX

POP (Pop from Stack) POP register/memory POP AX

Instruction Syntax Example

IN (Input from port) IN AL, port IN AL, 60H

OUT (Output to port) OUT port, AL OUT 60H, AL

Example:
assembly
CopyEdit
MOV AX, 5000H ; Load immediate value into AX
MOV DS, AX ; Move AX content to Data Segment (DS)

2. Arithmetic Instructions
Used for performing arithmetic operations.

Instruction Syntax Example

ADD (Addition) ADD destination, source ADD AX, BX

SUB (Subtraction) SUB destination, source SUB AX, BX

MUL (Multiplication) MUL source MUL BX

DIV (Division) DIV source DIV CX

INC (Increment) INC register/memory INC AX

DEC (Decrement) DEC register/memory DEC AX

3. Bit Manipulation Instructions

Used for logical operations on bits.

Instruction Syntax Example

AND (Logical AND) AND destination, source AND AX, BX

OR (Logical OR) OR destination, source OR AL, 0F0H

Instruction Syntax Example

XOR (Logical XOR) XOR destination, source XOR CX, AX

NOT (Logical NOT) NOT destination NOT AX

SHL (Shift Left) SHL destination, count SHL AX, 1

SHR (Shift Right) SHR destination, count SHR BX, 2

4. String Instructions
Used for string and memory operations.

Instruction Syntax Example

MOVS (Move String) MOVS destination, source MOVS BYTE PTR [DI], [SI]

LODS (Load String) LODS source LODS BYTE PTR [SI]

STOS (Store String) STOS destination STOS BYTE PTR [DI]

5. Program Execution Transfer Instructions (Branch & Loop)

Used for jumping, looping, and procedure calls.

Instruction Syntax Example

JMP (Jump) JMP label JMP START

CALL (Call Procedure) CALL procedure CALL FUNCTION1

RET (Return from Procedure) RET RET

LOOP (Looping) LOOP label LOOP BACK

6. Processor Control Instructions

Used for enabling and disabling interrupts.
Instruction Syntax Example

STI (Set Interrupt Flag) STI STI

CLI (Clear Interrupt Flag) CLI CLI

HLT (Halt) HLT HLT

7. Iteration Control Instructions

Used for looping based on conditions.

Instruction Syntax Example

LOOP (Loop CX times) LOOP label LOOP AGAIN

JC (Jump if Carry) JC label JC NEXT

JZ (Jump if Zero) JZ label JZ END

8. Interrupt Instructions
Used to handle interrupts in the processor.

Instruction Syntax Example

INT (Interrupt) INT interrupt_number INT 21H

IRET (Interrupt Return) IRET IRET

Example Program (Adding Two Numbers)

assembly
CopyEdit
MOV AX, 1000H ; Load first number into AX
MOV BX, 2000H ; Load second number into BX
ADD AX, BX ; Add BX to AX
MOV [3000H], AX ; Store result at memory location 3000H
9.8255 PPI Block diagram