Configurable, Dual 2 A/Single 4 A,

Synchronous Step-Down DC-to-DC Regulator

Data Sheet ADP2114
FEATURES TYPICAL APPLICATION CIRCUIT
Configurable 2 A/2 A or 3 A/1 A dual output load VIN = 5V

combinations or 4 A combined single output 10Ω

1µF
High efficiency: up to 95% 100kΩ 100kΩ

Input voltage VIN: 2.75 V to 5.5 V EN2 EN1

VDD
VIN4 VIN1
Selectable fixed output: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V or 22µF 22µF
VIN5 VIN2
adjustable output voltage to 0.6 V minimum PGOOD2 VIN6 VIN3 PGOOD1
PGOOD2 PGOOD1
±1.5% accurate reference voltage 4.7µH VOUT1 = 3.3V, 2A
VOUT2 = 1.8V, 2A 2.2µH SW1
SW3 ADP2114
Selectable switching frequency: 300 kHz, 600 kHz, 1.2 MHz SW2
SW4
PGND1 47µF
or synchronized from 200 kHz to 2 MHz 22µF 47µF PGND3
PGND2
Optimized gate slew rate for reduced EMI PGND4
FB1
FB2
External synchronization input or internal clock output V2SET V1SET
47kΩ
SYNC 15kΩ
Dual-phase, 180° phase shifted PWM channels SYNC/CLKOUT
Current mode for fast transient response COMP2 COMP1

OPCFG
FREQ

SCFG
22kΩ SS2 SS1 22kΩ

GND
10nF 10nF
Pulse skip under light load or forced PWM operation 1.2nF
Input undervoltage lockout (UVLO) 1.2nF
8.2kΩ
Independent enable inputs and PGOOD outputs

08143-001
Overcurrent and thermal overload protection fSW = 600kHz

Externally programmable soft start Figure 1.

32-lead 5 mm × 5 mm LFCSP package
Supported by ADIsimPower™ design tool

APPLICATIONS
Point of load regulation
Telecommunications and networking systems
Consumer electronics out-of-phase output clock, providing the possibility for a
Industrial and instrumentation stackable multiphase power solution.
Medical
The ADP2114 input voltage range is from 2.75 V to 5.5 V, and it
GENERAL DESCRIPTION converts to fixed outputs of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or
The ADP2114 is a versatile, synchronous step-down, switching 3.3 V that can be set independently for each channel using
regulator that satisfies a wide range of customer point-of-load external resistors. Using a resistor divider, it is also possible to
requirements. The two PWM channels can be configured to set the output voltage as low as 0.6 V. The ADP2114 operates
deliver independent outputs at 2 A and 2 A (or 3 A/1 A) or can be over the −40°C to +125°C junction temperature range.
configured as a single interleaved output capable of delivering 4 A. 100
VIN = 3.3V; VOUT = 1.8V
The two PWM channels are 180º phase shifted to reduce input VIN = 5.0V; VOUT = 3.3V

95
ripple current and to reduce input capacitance. The ADP2114
provides high efficiency and operates at switching frequencies of
90
EFFICIENCY (%)

up to 2 MHz. At light loads, the ADP2114 can be set to operate

in pulse skip mode for higher efficiency or in forced PWM mode 85
to reduce EMI.
80
The ADP2114 is designed with an optimized gate slew rate to
VIN = 5.0V; VOUT = 1.8V
reduce EMI emissions, allowing it to power sensitive, high
75
performance signal chain circuits. The switching frequency can
be set to 300 kHz, 600 kHz, or 1.2 MHz and can be synchronized 70
08143-002

to an external clock that minimizes the system noise. The 0.01 0.1 1 3
LOAD CURRENT (A)
bidirectional synchronization pin is also configurable as a 90
Figure 2. Typical Efficiency vs. Load Current

Rev. C Document Feedback

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ADP2114 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Thermal Overload Protection .................................................. 23
Applications ....................................................................................... 1 Maximum Duty Cycle Operation ............................................ 23
General Description ......................................................................... 1 Synchronization .......................................................................... 23
Typical Application Circuit ............................................................. 1 Converter Configuration ............................................................... 24
Revision History ............................................................................... 2 Selecting the Output Voltage .................................................... 24
Specifications..................................................................................... 3 Setting the Oscillator Frequency .............................................. 25
Absolute Maximum Ratings............................................................ 5 Synchronization and CLKOUT ................................................ 25
ESD Caution .................................................................................. 5 Operation Mode Configuration ............................................... 26
Pin Configuration and Function Descriptions ............................. 6 External Components Selection ................................................... 27
Typical Performance Characteristics ............................................. 8 Input Capacitor Selection .......................................................... 27
Supply Current ............................................................................ 13 VDD RC Filter ............................................................................ 27
Load Transient Response........................................................... 14 Inductor Selection ...................................................................... 27
Bode Plots .................................................................................... 19 Output Capacitor Selection....................................................... 28
Simplified Block Diagram ............................................................. 20 Control Loop Compensation .................................................... 28
Theory of Operation ...................................................................... 21 Design Example .............................................................................. 30
ADIsimPower Design Tool ....................................................... 21 Channel 1 Configuration and Components Selection .......... 30
Control Architecture .................................................................. 21 Channel 2 Configuration and Components Selection .......... 31
Undervoltage Lockout (UVLO) ............................................... 21 System Configuration ................................................................ 32
Enable/Disable Control ............................................................. 21 Application Circuits ....................................................................... 33
Soft Start ...................................................................................... 21 Power Dissipation, Thermal Considerations .............................. 35
Power Good................................................................................. 22 Circuit Board Layout Recommendations ................................... 36
Pulse Skip Mode ......................................................................... 22 Outline Dimensions ....................................................................... 37
Hiccup Mode Current Limit ..................................................... 23 Ordering Guide .......................................................................... 37

REVISION HISTORY
3/16—Rev. B to Rev. C
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changes to Figure 3 .......................................................................... 6
Updated Outline Dimensions ....................................................... 37
Changes to Ordering Guide .......................................................... 37

11/12—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 37

8/12—Rev. 0 to Rev. A
Change to Features Section ............................................................. 1
Added ADIsimPower Design Tool Section ................................. 21
Updated Outline Dimensions ....................................................... 37

7/09—Revision 0: Initial Version

Rev. C | Page 2 of 37
Data Sheet ADP2114

SPECIFICATIONS
If unspecified, VDD = VINx = EN1 = EN2 = 5.0 V. The minimum and maximum specifications are valid for TJ = −40°C to +125°C, unless
otherwise specified. Typical values are at TJ = 25°C. All limits at temperature extremes are guaranteed via correlation using standard
statistical quality control (SQC).

Table 1.
Parameter Symbol Conditions Min Typ Max Unit
POWER SUPPLY
VDD Bias Voltage VDD 2.75 5.5 V
Undervoltage Lockout Threshold UVLO VDD rising 2.65 2.75 V
VDD falling 2.35 2.47
Undervoltage Lockout Hysteresis 0.18 V
Quiescent Current IDDCh1 EN1 = VDD = 5 V, EN2 = GND, VFB1 = VDD, 1.7 2.5 mA
OPCFG = GND
IDDCh2 EN2 = VDD = 5V, EN1 = GND, VFB2 = VDD, 1.7 2.5 mA
OPCFG = GND
IDDCh1 + Ch2 EN1 = EN2 = VDD = 5 V, VFB2 = VFB1 = VDD, 3.0 4.0 mA
OPCFG = GND
Shutdown Current IDDSD EN1 = EN2 = GND, VDD = VINx = 2.75 V to 5.5 V, 1.0 10 μA
TJ = −40°C to +115°C
ERROR INTEGRATOR (OTA)
FB1, FB2 Input Bias Current IFB Adjustable output, VFBx = 0.6 V, 1 65 nA
V1SET, V2SET = VDD or via 82 kΩ to GND
Fixed output; VFBx = 1.2 V, 11 15 μA
V1SET, V2SET via 4.7 kΩ to GND
Transconductance gM 550 μA/V
COMPx VOLTAGE RANGE
COMPx Zero-Current Threshold VCOMP, ZCT Guaranteed by design 1.12 V
COMPx Clamp High Voltage VCOMP, HI VDD = VINx = 2.75 V to 5.5 V 2.36 2.45 V
COMPx Clamp Low Voltage VCOMP, LO VDD = VINx = 2.75 V to 5.5 V 0.65 0.70 V
OUTPUT CHARACTERISTICS
Output Voltage Accuracy VFB Adjustable output, TJ = 25C, 0.597 0.600 0.603 V
V1SET, V2SET = VDD or via 82 kΩ to GND
Adjustable output, TJ = −40C to +125C, 0.594 0.600 0.606 V
V1SET, V2SET = VDD or via 82 kΩ to GND
VFB ERROR Fixed output, TJ = 25C, V1SET, V2SET = GND −1.0 +1.0 %
or via 4.7 kΩ, 8.2 kΩ, 15 kΩ, 27 kΩ,
47 kΩ to GND
Fixed output, TJ = −40C to +125C, −1.5 +1.5 %
V1SET, V2SET = GND or via 4.7 kΩ, 8.2 kΩ,
15 kΩ, 27 kΩ, 47 kΩ to GND
Line Regulation VDD = VINx = 2.75 V to 5.5 V 0.05 %/V
Load Regulation VDD = VINx = 2.75 V to 5.5 V 0.03 %/A
OSCILLATOR All oscillator parameters provided for
VDD = 2.75 V to 5.5 V
Switching Frequency fSW FREQ tied to GND 255 300 345 kHz
FREQ via 8.2 kΩ to GND 510 600 690 kHz
FREQ via 27 kΩ to GND 1020 1200 1380 kHz
SYNC Frequency Range fSYNC fSYNC = 2 × fSW
FREQ tied to GND 400 1000 kHz
FREQ via 8.2 kΩ to GND 800 2000 kHz
FREQ via 27 kΩ to GND 1600 4000 kHz
SYNC Input Pulse Width 100 ns

Rev. C | Page 3 of 37
ADP2114 Data Sheet
Parameter Symbol Conditions Min Typ Max Unit
SYNC Pin Capacitance to GND CSYNC 5 pF
SYNC Input Logic Low VIL_SYNC 0.8 V
SYNC Input Logic High VIH_SYNC 2.0 V
Phase Shift Between Channels 180 Degrees
CLKOUT Frequency fCLKOUT fCLKOUT = 2 × fSW
FREQ tied to GND 510 600 690 kHz
FREQ via 8.2 kΩ to GND 1020 1200 1380 kHz
FREQ via 27 kΩ to GND 2040 2400 2760 kHz
CLKOUT Positive Pulse Time tCLKOUT 100 ns
CLKOUT Rise or Fall Time CCLKOUT = 20 pF 10 ns
CURRENT LIMIT All current limit parameters provided for
VDD = VINx = 2.75 V to 5.5 V
Peak Output Current Limit, Channel 1 ILIMIT1 OPCFG tied to GND or via 4.7 kΩ to GND 2.4 3.3 4.0 A
OPCFG via 8.2 kΩ or 15 kΩ to GND 3.5 4.5 5.3 A
Peak Output Current Limit, Channel 2 ILIMIT2 OPCFG tied to GND or via 4.7 kΩ to GND 2.4 3.3 4.0 A
OPCFG via 8.2 kΩ or 15 kΩ to GND 1.2 1.9 2.6 A
Current Sense Amplifier Gain GCS 4 A/V
Hiccup Time fSW = 300 kHz 10 13.6 17 ms
Number of Cumulative Current Limit 8 Cycles
Cycles to Go into Hiccup
SWITCH NODE CHARACTERISTICS
High-Side, P-Channel RDS ON1 VDD = VINx = 3.3 V 68 mΩ
VDD = VINx = 5.0 V 52 mΩ
Low-Side, N-Channel RDS ON1 VDD = VINx = 3.3 V 32 mΩ
VDD = VINx = 5.0 V 27 mΩ
SWx Minimum On Time SWON MIN VDD = VINx = 2.75 V to 5.5 V 107 ns
SWx Minimum Off Time SWOFF MIN VDD = VINx = 5.5 V 192 ns
VDD = VINx = 2.75 V 255 ns
SWx Maximum Leakage Current VDD = VINx = 2.75 V to 5.5 V; ENx = GND, 0.1 15 μA
TJ = −40°C to +115°C
ENABLE INPUT
EN1, EN2 Logic Low Level ENLOW VDD = VINx = 2.75 V to 5.5 V 0.8 V
EN1, EN2 Logic High Level ENHI VDD = VINx = 2.75 V to 5.5 V 2 V
EN1, EN2 Input Leakage Current IEN_LEAK VDD = VINx = ENx = 2.75 V to 5.5 V, 0.1 1 μA
TJ = −40°C to +115°C
THERMAL SHUTDOWN
Thermal Shutdown Threshold TTMSD 150 C
Thermal Shutdown Hysteresis 25 C
SOFT START
SS1, SS2 Pin Current ISS1, ISS2 VDD = VINx = 2.75 V to 5.5 V; VSS = 0 V 4.8 6.0 7.8 μA
Soft Start Threshold Voltage VSS_THRESH VDD = VINx = 2.75 V to 5.5 V 0.65 V
Soft Start Pull-Down Current VDD = VINx = 2.75 V to 5.5 V; EN = GND 0.5 mA
POWER GOOD All power good parameters provided for
VDD = VINx = 2.75 V to 5.5 V
Overvoltage PGOODx Rising Threshold2 116 %
Overvoltage PGOODx Falling Threshold2 100 108 114 %
Undervoltage PGOODx Rising Threshold2 85 92 97 %
Undervoltage PGOODx Falling Threshold2 84 %
PGOODx Delay 50 μs
PGOODx Leakage Current VPGOODx = VDD 0.1 1 μA
PGOODx Low Saturation Voltage IPGOODx = 1 mA 50 110 mV
1
Pin-to-pin measurements.
2
The thresholds are expressed in percentage terms of the nominal output voltage.

Rev. C | Page 4 of 37
Data Sheet ADP2114

ABSOLUTE MAXIMUM RATINGS

Table 2. Stresses at or above those listed under Absolute Maximum
Parameter Rating Ratings may cause permanent damage to the product. This is a
VDD to GND −0.3 V to +6 V stress rating only; functional operation of the product at these
VIN1, VIN2, VIN3, VIN4, VIN5, VIN6 to −0.3 V to +6 V or any other conditions above those indicated in the operational
PGND1, PGND2, PGND3, PGND4 section of this specification is not implied. Operation beyond
EN1, EN2, SCFG, FREQ, FB1, FB2, SYNC/ −0.3 V to (VDD + 0.3 V) the maximum operating conditions for extended periods may
CLKOUT, PGOOD1, PGOOD2, V1SET, affect product reliability.
V2SET, COMP1, COMP2, SS1, SS2 to GND
FB1, FB2 to GND −0.3V to +3.6V Absolute maximum ratings apply individually only, not in
SW1, SW2, SW3, SW4 to PGND1, PGND2, −0.3 V to (VDD + 0.3 V) combination.
PGND3, PGND4
PGND1, PGND2, PGND3, PGND4 to GND 0.3 V
ESD CAUTION
VIN1, VIN2, VIN3, VIN4, VIN5, VIN6 to VDD 0.3 V
θJA, JEDEC 1S2P PCB, Natural Convection 34°C/W
Operating Junction Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Soldering Lead 260°C
Temperature (10 sec)

Rev. C | Page 5 of 37
ADP2114 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PGOOD1
V1SET

VIN1
VIN2
VIN3
EN1
FB1

SS1
32
31
30
29
28
27
26
25
GND 1 24 SW1
COMP1 2 23 SW2
FREQ 3 22 PGND1
SCFG 4 ADP2114 21 PGND2
SYNC/CLKOUT 5 TOP VIEW 20 PGND3
(Not to Scale)
OPCFG 6 19 PGND4
COMP2 7 18 SW3
VDD 8 17 SW4

9
10
11
12
13
14
15
16
PGOOD2
FB2

SS2

VIN4
VIN5
VIN6
EN2
V2SET

08143-003
NOTES
1. CONNECT THE EXPOSED THERMAL PAD
TO THE SIGNAL/ANALOG GROUND PLANE.

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description
1 GND Ground for the Internal Analog and Digital Circuits. Connect GND to the signal/analog ground plane before
connecting to the power ground.
2 COMP1 Error Amplifier Output for Channel 1. Connect a series RC network from COMP1 to GND to compensate for
Channel 1. For multiphase operation, tie COMP1 and COMP2 together.
3 FREQ Frequency Select Input. Connect this pin through a resistor to GND to set the appropriate switching frequency
(see Table 5).
4 SCFG Synchronization Configuration Input. SCFG configures the SYNC/CLKOUT pin as an input or output. Tie this pin
to VDD to configure SYNC/CLKOUT as an output. Tie this pin to GND to configure SYNC/CLKOUT as an input.
5 SYNC/CLKOUT This is a configurable bidirectional pin (configured with the SCFG pin—see the Pin 4 description for details).
When SYNC/CLKOUT is an output, a buffered clock of twice the switching frequency with a phase shift of 90°
is available on this pin. When configured as an input, this pin accepts an external clock to which the converters
are synchronized. The frequency select resistor, mentioned in the description of Pin 3, must be selected close to
the expected switching frequency for stable operation.
6 OPCFG Operation Configuration Input. Connect this pin through a resistor to GND to set the system mode of operation
according to Table 7. This pin can be used to select a peak current limit for each power channel and enable or
disable the pulse skip mode.
7 COMP2 Error Amplifier Output for Channel 2. Connect a series RC network from COMP2 to GND to compensate the
Channel 2. Tie COMP1 and COMP2 together for multiphase configuration.
8 VDD Power Supply Input. The power source for the ADP2114 internal circuitry. Connect VDD and VINx with a
10 Ω resistor as close as possible to the ADP2114. Bypass VDD to GND with a 1 μF or greater capacitor.
9 FB2 Feedback Voltage Input for Channel 2. For the fixed output voltage option, connect FB2 to VOUT2. For the
adjustable output voltage option, connect this pin to a resistor divider between VOUT2 and GND. The reference
voltage for the adjustable output voltage option is 0.6 V. With multiphase configurations, connect FB2 to FB1
and then connect them to VOUT.
10 V2SET Output Voltage Set Pin for Channel 2. Connect this pin through a resistor to GND or tie to VDD to select a fixed
output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V) or an adjust output voltage for VOUT2. See Table 4
for output voltage selection.
11 SS2 Soft Start Input for Channel 2. Place a capacitor from SS2 to GND to set the soft start period. A 10 nF capacitor
sets a 1 ms soft start period. For multiphase configuration, connect SS2 to SS1.
12 PGOOD2 Open-Drain Power Good Output for Channel 2. Place a 100 kΩ pull-up resistor to VDD or any other voltage ≤ 5.5 V;
PGOOD2 pulls low when Channel 2 is out of regulation.
13 EN2 Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 converter and drive EN2 low to turn off
Channel 2. Tie EN2 to VDD for startup with VDD. With multiphase configuration, tie EN2 to EN1.

Rev. C | Page 6 of 37
Data Sheet ADP2114
Pin No. Mnemonic Description
14 VIN4 Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
15 VIN5 Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
16 VIN6 Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
17 SW4 Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.
Tie SW3 to SW4 and then connect the output LC filter between SW and the output voltage.
18 SW3 Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.
Tie SW3 to SW4 and then connect the output LC filter between SW and the output voltage.
19 PGND4 Power Ground. Source of the low-side internal power MOSFET of Channel 2.
20 PGND3 Power Ground. Source of the low-side internal power MOSFET of Channel 2.
21 PGND2 Power Ground. Source of the low-side internal power MOSFET of Channel 1.
22 PGND1 Power Ground. Source of the low-side internal power MOSFET of Channel 1.
23 SW2 Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.
Tie SW1 to SW2 and connect the output LC filter between SW and the output voltage.
24 SW1 Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.
Tie SW1 to SW2 and connect the output LC filter between SW and the output voltage.
25 VIN3 Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
26 VIN2 Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
27 VIN1 Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
28 EN1 Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 converter and drive EN1 low to turn off
Channel 1. Tie EN1 to VDD for startup with VDD. With multiphase configurations, connect EN1 to EN2.
29 PGOOD1 Open-Drain Power Good Output for Channel 1. Place a 100 kΩ pull-up resistor to VDD or any other voltage ≤ 5.5 V;
PGOOD1 pulls low when Channel 1 is out of regulation.
30 SS1 Soft Start Input for Channel 1. Place a capacitor from SS1 to GND to set the soft start period. A 10 nF capacitor
sets a 1 ms soft start period. For multiphase configuration, connect SS1 to SS2.
31 V1SET Output Voltage Set Pin for Channel 1. Connect this pin through a resistor to GND or tie to VDD to select a fixed
output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V) or an adjustable output voltage for VOUT1. See Table 4
for output voltage selection.
32 FB1 Feedback Voltage Input for Channel 1. For the fixed output voltage option, connect FB1 to VOUT1. For the
adjusted output voltage option, connect this pin to a resistor divider between VOUT1 and GND. With multiphase
configurations, connect FB1 to FB2 and then connect them to VOUT.
EPAD (EP) Exposed Thermal Pad. Connect to the signal/analog ground plane.

Rev. C | Page 7 of 37
ADP2114 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

100 100

95 95

90 90
EFFICIENCY (%)

EFFICIENCY (%)
85 85

80 80
VIN = 5V,
75 75 VOUT = 2.5V FORCED PWM
VIN = 5V,
70 70 VOUT = 2.5V PULSE SKIP
VOUT = 3.3V
VIN = 3.3V,
VOUT = 3.3V; PULSE SKIP VOUT = 1.2V FORCED PWM
65 VOUT = 1.8V 65
VIN = 3.3V,
VOUT = 1.8V; PULSE SKIP VOUT = 1.2V PULSE SKIP
60 60

08143-004

08143-006
10 100 1k 10k 10 100 1k 10k
LOAD CURRENT (mA) LOAD CURRENT (mA)

Figure 4. Channel 1 Efficiency vs. Load, VIN = 5 V and fsw = 300 kHz; Figure 6. Efficiency vs. Load at fSW = 1.2 MHz;
VOUT = 3.3 V, Inductor Cooper Bussmann DR1050-8R2-R, 8.2 μH, 15 mΩ; Inductor TOKO FDV0620-1R0M, 1.0 μH, 14 mΩ
VOUT = 1.8 V, Inductor TOKO FDV0620-4R7M, 4.7 μH, 53 mΩ

100 90

95
85
90 VIN = 3.3V

80
EFFICIENCY (%)

EFFICIENCY (%)

85
VIN = 5V

80 75

75
70
70
VOUT = 3.3V
VOUT = 3.3V; PULSE SKIP 65
65 VOUT = 1.8V
VOUT = 1.8V; PULSE SKIP
60 60
08143-005

08143-007
10 100 1k 10k 100 1k 10k
LOAD CURRENT (mA) LOAD CURRENT (mA)

Figure 5. Channel 2 Efficiency vs. Load, VIN = 5 V and fSW = 600 kHz; Figure 7. Efficiency Combined Dual-Phase Output, VOUT = 0.8 V and
VOUT = 3.3 V, Inductor TOKO FDV0620-4R7M, 4.7 μH, 53 mΩ; fSW = 1.2 MHz; Inductor TOKO FDV0620-1R0M, 1.0 μH, 14 mΩ
VOUT = 1.8 V, Inductor TOKO FDV0620-2R2M, 2.2 μH, 30 mΩ

Rev. C | Page 8 of 37
Data Sheet ADP2114
0.50 0.50
VOUT ERROR, NORMALIZED (%)

VOUT ERROR, NORMALIZED (%)

0.25 0.25

0 0

–0.25 –0.25

–0.50 –0.50

08143-008

08143-011
0 500 1000 1500 2000 2500 3000 0 500 1000 1500 2000
LOAD CURRENT (mA) LOAD CURRENT (mA)

Figure 8. Load Regulation, Channel 1: VIN = 5 V, fSW = 600 kHz, and TA = 25°C Figure 11. Load Regulation, Channel 2: VIN = 5 V, fSW = 300 kHz, and TA = 25°C

0.5 0.5

0.4 0.4

0.3
VOUT ERROR, NORMALIZED (%)

0.3

VOUT ERROR, NORMALIZED (%)

0.2 0.2

0.1 0.1

0 0

–0.1 –0.1

–0.2 –0.2

–0.3 –0.3

–0.4 –0.4

–0.5 –0.5
08143-009

08143-012
2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V) VIN (V)

Figure 9. Line Regulation, Channel 1: Load Current = 3 A and fSW = 600 kHz Figure 12. Line Regulation, Channel 2: Load Current = 1 A and fSW = 600 kHz

1.00 1.00

0.75 0.75

0.50 0.50
VOUT ERROR (%)

VOUT ERROR (%)

0.25 0.25
VIN = 5.5V, NO LOAD VIN = 5.5V, NO LOAD
0 0

–0.25 VIN = 2.75V; 3A LOAD –0.25 VIN = 2.75V; 2A LOAD

–0.50 –0.50

–0.75 –0.75

–1.00 –1.00
08143-010

08143-013

–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125

TEMPERATURE (°C) TEMPERATURE (°C)
Figure 10. Output Voltage vs. Temperature, Figure 13. Output Voltage vs. Temperature,
Channel 1: VOUT = 0.6 V and fSW = 600 kHz Channel 2: VOUT = 1.5 V and fSW = 600 kHz

Rev. C | Page 9 of 37
ADP2114 Data Sheet
250 330
fSW = 300kHz
225 fSW = 600kHz
320
fSW = 1.2MHz
200
MINIMUM ON-TIME (ns)

310
175

fSW (kHz)
150 300

125
290
100
280
75

50 270

08143-014

08143-017
2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V) VIN (V)

Figure 14. Minimum On-Time, Open Loop, Includes Dead Time Figure 17. Switching Frequency vs. Input Voltage, fSW = 300 kHz

350 660
fSW = 300kHz
330 fSW = 600kHz
640
310 fSW = 1.2MHz
MINIMUM OFF-TIME (ns)

290
620
270
fSW (kHz)

250 600

230
580
210

190
560
170

150 540
08143-015

08143-018
2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V) VIN (V)

Figure 15. Minimum Off-Time, Open Loop, Includes Dead Time Figure 18. Switching Frequency vs. Input Voltage, fSW = 600 kHz

120 80

70
100
60
NMOS RDS ON (mΩ)
PMOS RDS ON (mΩ)

80
50

60 40

30
40

+125°C 20 +125°C
+115°C +115°C
20
+85°C 10 +85°C
+25°C +25°C
–40°C –40°C
0 0
08143-016

08143-019

2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V) VIN (V)

Figure 16. High-Side PMOS Resistance vs. Input Voltage, Includes Bond Wires Figure 19. Low-Side NMOS Resistance vs. Input Voltage, Includes Bond Wires

Rev. C | Page 10 of 37
Data Sheet ADP2114
330 2.0
1.9
320 1.8

ENABLE/DISABLE THRESHOLD (V)

1.7
310 1.6
VIN = 2.75V ENABLE; VIN = 5.5V
1.5
fSW (kHz)

ENABLE; VIN = 2.75V

300 VIN = 5.5V 1.4 DISABLE; VIN = 5.5V
1.3 DISABLE; VIN = 2.75V

290 1.2
1.1
280 1.0
0.9
270 0.8

08143-020

08143-023
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 20. Switching Frequency vs. Temperature, fSW = 300 kHz Figure 23. Enable/Disable Threshold vs. Temperature

660 2.8

640
2.7
VDD RISING

UVLO THRESHOLD (V)

620
VIN = 2.75V
2.6
fSW (kHz)

600 VIN = 5.5V

2.5
580
VDD FALLING

2.4
560

540 2.3
08143-021

08143-024
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 21. Switching Frequency vs. Temperature, fSW = 600 kHz Figure 24. UVLO Threshold vs. Temperature

1300 1300

1280 1280

1260 1260

1240 1240
VIN = 2.75 V
1220 1220
fSW (kHz)

fSW (kHz)

1200 1200
VIN = 5.5 V
1180 1180

1160 1160

1140 1140

1120 1120

1100 1100
08143-022

2.5 3.0 3.5 4.0 4.5 5.0 5.5

08143-025

–50 –25 0 25 50 75 100 125

VIN (V) TEMPERATURE (°C)
Figure 22. Switching Frequency vs. Input Voltage, fSW = 1.2 MHz Figure 25. Switching Frequency vs. Temperature, fSW = 1.2 MHz

Rev. C | Page 11 of 37
ADP2114 Data Sheet
120 6.0
OVERVOLTAGE; VOUT RISING 5.5
115
5.0
3A OPTION
110 OVERVOLTAGE; VOUT FALLING 4.5
PGOOD THRESHOLD (%)

CURRENT LIMIT (A)

4.0
105
3.5 2A OPTION

100 3.0
2.5
95 1A OPTION
UNDERVOLTAGE; VOUT RISING 2.0

90 1.5
UNDERVOLTAGE, VOUT FALLING 1.0
85
0.5
80 0

08143-026

08143-029
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 26. PGOOD Threshold vs. Temperature Figure 29. Peak Current Limit vs. Temperature, VIN = 5 V

10 700

9
650
8
SHUTDOWN CURRENT (µA)

600
7 VIN = 5.5V
550
6
gm (µA/V)

VIN = 2.75V
5 500

4
450
VIN = 5.5V
3
400
2 VIN = 2.75V
350
1

0 300
08143-027

08143-030
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 27. Shutdown Current vs. Temperature Figure 30. gM vs. Temperature

4
VDD CURRENT (mA)

3 VIN = 5.5V

VIN = 2.75V
2

0
08143-028

–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

Figure 28. VDD Input Current vs. Temperature (Not Switching)

Rev. C | Page 12 of 37
Data Sheet ADP2114
SUPPLY CURRENT
5.0 5.0

4.5 4.5
FORCED PWM
4.0 4.0
VDD CURRENT (mA)

VDD CURRENT (mA)

3.5 3.5

3.0 3.0

2.5 2.5
FORCED PWM
PULSE SKIP
2.0 2.0

PULSE SKIP
1.5 1.5

1.0 1.0

08143-033
08143-031
2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD VOLTAGE (V) VDD VOLTAGE (V)

Figure 31. VDD Supply Current, No Load, Figure 33. VDD Supply Current, No Load,
Channel 1: VOUT = 1.5 V, Channel 2 Off, fSW = 1.2 MHz Channel 1: VOUT = 1.5 V, Channel 2: VOUT = 0.8 V, fSW = 1.2 MHz

5.0 5.0
VDD = 5.5V, FORCED PWM
4.5 4.5

4.0 4.0 VDD = 2.75V, FORCED PWM

VDD CURRENT (mA)

3.5 VDD CURRENT (mA) 3.5

3.0 3.0
FORCED PWM VDD = 5.5V PULSE SKIP
2.5 2.5
VDD = 2.75V, PULSE SKIP
2.0 2.0
PULSE SKIP
1.5 1.5

1.0 1.0

08143-034
08143-032

2.5 3.0 3.5 4.0 4.5 5.0 5.5 –50 –25 0 25 50 75 100 125
VDD VOLTAGE (V) TEMPERATURE (°C)

Figure 32. VDD Supply Current, No Load, Figure 34. VDD Supply Current vs. Temperature,
Channel 2: VOUT = 0.8 V, Channel 1 Off, fSW = 1.2 MHz Channel 1: VOUT = 1.5 V, Channel 2: VOUT = 0.8 V, fSW = 1.2 MHz

Rev. C | Page 13 of 37
ADP2114 Data Sheet
LOAD TRANSIENT RESPONSE

VOUT VOUT
2
2

IOUT

IOUT

4
SW 4
SW

1 3

08143-035

08143-038
CH1 5.0V CH2 50mV M200µs 50MS/s A CH2 –33mV CH3 5.0V CH2 50mV M200µs 50MS/s A CH2 –34mV
CH4 2.0A 200ns/pt CH4 1.0A 20ns/pt
Figure 35. Channel 1: VIN = 5 V, VOUT = 3.3V, fSW = 600 kHz; Forced PWM Figure 38. Channel 2: VIN = 5 V, VOUT = 1.8 V, fSW = 600 kHz; Pulse Skip
(See Table 12 for the Circuit Details) (See Table 12 for the Circuit Details)

VOUT
2 VOUT
2

IOUT

4 IOUT

SW
4 SW

3 1
08143-036

08143-039
CH3 5.0V CH2 50mV M200µs 50MS/s A CH2 –23mV CH1 5.0V CH2 10mV M200µs 12.5MS/s A CH4 960mA
CH4 2.0A 200ns/pt CH4 2.0A 80ns/pt
Figure 36. Channel 2: VIN = 5 V, VOUT = 1.8 V, fSW = 600 kHz; Forced PWM Figure 39. Channel 1: VIN = 3.3 V, VOUT = 1.2 V, fSW = 1.2 MHz; Forced PWM
(See Table 12 for the Circuit Details) (See Table 12 for the Circuit Details)

2
2

VOUT VOUT

IOUT
IOUT

4 SW
4 SW

1 1
08143-037

08143-040

CH1 5.0V CH2 10mV M200µs 12.5MS/s A CH4 960mA CH1 5.0V CH2 10mV M200µs 12.5MS/s A CH4 960mA
CH4 2.0A 80ns/pt CH4 2.0A 80ns/pt
Figure 37. Channel 1: VIN = 5 V, VOUT = 1.2 V, fSW = 1.2 MHz; Forced PWM Figure 40. Channel 1: VIN = 3.3 V, VOUT = 1.2 V, fSW = 1.2 MHz; Pulse Skip
(See Table 12 for the Circuit Details) (See Table 12 for the Circuit Details)

Rev. C | Page 14 of 37
Data Sheet ADP2114

VOUT VOUT

VIN

VIN

SW
SW

1 1
3 3

08143-041

08143-044
CH1 5.0V CH2 10mV M400µs A CH3 4.86V CH1 5.0V CH2 10mV M400µs A CH3 3.50V
CH3 1.0V CH3 1.0V
Figure 41. 3.3 V to 5 V Line Transient, VOUT = 1.5 V, Load = 1 A Figure 44. 5 V to 3.3 V Line Transient, VOUT = 1.5 V, Load = 1 A
fSW = 1.2 MHz, Pulse Skip Enabled fSW = 1.2 MHz, Forced PWM

VOUT
VOUT
2

VIN

VIN

SW

SW

1
3 3
08143-042

08143-045
CH1 5.0V CH2 10mV M400µs A CH3 3.58V CH1 2.0V CH2 10mV M400µs A CH3 4.82V
CH3 1.0V CH3 1.0V
Figure 42. 5 V to 3.3 V Line Transient, VOUT = 1.5 V, Load = 1 A Figure 45. 3.3 V to 5 V Line Transient, VOUT = 0.6 V, Load = 1 A
fSW = 1.2 MHz, Pulse Skip Enabled fSW = 600 kHz, Pulse Skip Enabled

VOUT
VOUT
2
2
VIN

VIN SW

SW
1

1
3 3
08143-043

08143-046

CH1 5.0V CH2 10mV M400µs A CH3 4.84V CH1 2.0V CH2 10mV M400µs A CH3 3.62V
CH3 1.0V CH3 1.0V
Figure 43. 3.3 V to 5 V Line Transient, VOUT = 1.5 V, Load = 1 A Figure 46. 5 V to 3.3 V Line Transient, VOUT = 0.6 V, Load = 1 A
fSW = 1.2 MHz, Forced PWM fSW = 600 kHz, Pulse Skip Enabled

Rev. C | Page 15 of 37
ADP2114 Data Sheet
VOUT, AC
2
VOUT
2
SW

VIN
3

SW
INDUCTOR CURRENT

1 4

08143-047

08143-050
CH1 2.0V CH2 10mV M400µs A CH3 4.84V CH2 20mV M1µs A CH3 2.52V
CH3 1.0V CH3 2.0V CH2 500mA
Figure 47. 3.3 V to 5 V Line Transient, VOUT = 0.6 V, Load = 1 A Figure 50. Forced PWM Mode, CCM Operation, 200 mA Load, fSW = 600 kHz
fSW = 600 kHz, Forced PWM

VOUT VOUT, AC
2 2

SW
VIN

SW
3

INDUCTOR CURRENT

1
4

3
08143-048

08143-051
CH1 2.0V CH2 10mV M400µs A CH3 3.50V CH2 20mV M1µs A CH3 4.32V
CH3 1.0V CH3 2.0V CH2 500mA
Figure 48. 5 V to 3.3 V Line Transient, VOUT = 0.6 V, Load = 1 A Figure 51. Pulse Skip Enabled, DCM Operation, 200 mA Load, fSW = 600 kHz
fSW = 600 kHz, Forced PWM

VOUT, AC
2
EN2
1

SW
VOUT2
2

3
SS2
4

INDUCTOR CURRENT

4 SW
3
08143-049

08143-052

CH2 10mV M4µs A CH3 4.32V CH1 5.0V CH2 1.0V M1.0ms A CH1 2.4V
CH3 2.0V CH4 500mA CH3 5.0V CH4 2.0V
Figure 49. Pulse Skip Mode, 110 mA Load Figure 52. Soft Start, Channel 2 VOUT = 1.8 V, CSS2 = 10 nF

Rev. C | Page 16 of 37
Data Sheet ADP2114

INDUCTOR CURRENT
EN2
1
VOUT2

2 4

SS2
4 VOUT
2

SW
3 SW
3

08143-053

08143-056
CH1 5.0V CH2 1.0V M200µs A CH1 2.4V CH2 1.0V M2.0ms A CH4 1.72V
CH3 5.0V CH4 500mV CH3 5.0V CH4 2.0A
Figure 53. Start with Precharged Output Figure 56. Hiccup Mode, fSW = 600 kHz, 6.8 ms Hiccup Cycle

INDUCTOR CURRENT
INDUCTOR CURRENT
4 4

VOUT2 VOUT
2 2

SW SW
3 3
08143-054

08143-057
CH2 1.0V M1.0ms A CH2 1.12V CH2 1.0V M2.0ms A CH2 1.12V
CH3 5.0V CH4 2.0A CH3 5.0V CH4 2.0A
Figure 54. Current Limit Entry, Figure 57. Exit Hiccup Mode,
Channel 2 VOUT = 1.8 V, 2 A Configuration, fSW = 600 kHz Channel 2 VOUT = 1.8 V, fSW = 600 kHz

EXTERNAL SYNC

INDUCTOR CURRENT

CHANNEL 1 SW

VOUT2
2 4
CHANNEL 2 SW

SW
3 3
08143-055

08143-058

CH2 1.0V M10.0µs A CH2 1.12V CH1 5.0V M1.0µs A CH1 3.0V
CH3 5.0V CH4 2.0A CH3 5.0V CH4 5.0V
Figure 55. Current Limit Entry (Zoomed In), Figure 58. External Synchronization, fSYNC = 1.5 MHz, fSW = 750 kHz
Channel 2 VOUT = 1.8 V, 2 A Configuration, fSW = 600 kHz

Rev. C | Page 17 of 37
ADP2114 Data Sheet

CHANNEL 1 SW EN2
1

4 VOUT2
2

CHANNEL 2 SW

3
PGOOD2
INTERNAL CLKOUT 4

1 SW
3

08143-059

08143-061
CH1 5.0V M1.0µs A CH3 3.0V CH1 5.0V CH2 1.0V M200µs A CH1 3.5V
CH3 5.0V CH4 5.0V CH3 5.0V CH4 2.0V
Figure 59. Internal Clock Out, fSW = 600 kHz, fCLKOUT = 1.2 MHz Figure 61. Power Good Signal

CHANNEL 1 SW

CHANNEL 3 SW INDUCTOR CURRENT, PHASE 2

INDUCTOR CURRENT, PHASE 1

4
2

3 PHASE 2 SW
CHANNEL 2 SW

4 3

CHANNEL 4 SW 1
PHASE 1 SW
08143-060

08143-062
CH1 2.0V CH2 2.0V M1.0µs A CH1 2.0V CH1 5.0V CH2 1.0A M1.0µs A CH1 1.9V
CH3 2.0V CH4 2.0V CH3 5.0V CH4 1.0A
Figure 60. 4-Channel Operation, Two ADP2114s, One Synchronizes Another, Figure 62. Combined Dual-Phase Output Operation,
90° Phase-Shifted Switch Nodes VOUT = 1.2 V, fSW = 1.1 MHz, 4 A Load

Rev. C | Page 18 of 37
Data Sheet ADP2114
BODE PLOTS
50 150

40 120

30 90

20 PHASE 60

MAGNITUDE (dB)

PHASE (Degrees)
10 30

0 0
MAGNITUDE
–10 –30

–20 –60

–30 –90

–40 –120

–50 –150
1k 10k M1 100k M2

FREQUENCY (Hz)

M1 M2 M2 – M1
FREQUENCY 54.86kHz 210.34kHz 155.48kHz

08143-063
MAGNITUDE 0.042dB –19.632dB –19.673dB
PHASE 50.099° –0.412° –50.511°

Figure 63. VIN = 5 V, VOUT = 3.3 V, Load = 2 A, fSW = 600 kHz, Crossover Frequency (fCO) = 55 kHz; Phase Margin 50° (See Table 12 for the Circuit Details)
50 120

40 96

30 72
PHASE
20 48
MAGNITUDE (dB)

PHASE (Degrees)
10 24

0 MAGNITUDE 0

–10 –24

–20 –48

–30 –72

–40 –96

–50 –120
1k 10k M1 100k M2 1M
FREQUENCY (Hz)

M1 M2 M2 – M1
FREQUENCY 96.71kHz 335.27kHz 238.56kHz
08143-064

MAGNITUDE –0.075dB –17.371dB –17.296dB

PHASE 53.305° –0.389° –53.694°
Figure 64. VIN = 5 V, VOUT = 1.2 V, Load = 2 A, fSW = 1.2 MHz, Crossover Frequency (fCO) = 97 kHz; Phase Margin 53° (See Table 12 for the Circuit Details)

Rev. C | Page 19 of 37
ADP2114 Data Sheet

SIMPLIFIED BLOCK DIAGRAM

VDD GND

SCFG UVLO UVLO

FREQ OSC_CH1 PGOOD1

PHASE 0.7V
OSC
SHIFT
SYNC/CLKOUT OSC_CH2

VFB1
CLIM_CH1
OPCFG CURRENT LIMIT/ CLIM_CH2
CONFIGURATION VIN1
0.5V
PULSE SKIP ENABLE VIN2
VIN3
EN1
GATE
COMP1 CONTROL
UVLO LOGIC AND PMOS
V1SET SW1
VOUT MOSFET
SW2
SELECTOR OSC_CH1 DRIVERS
FB1 WITH
VFB1 PULSE SKIP ANTI-SHOOT NMOS
ENABLE THROUGH
–
PROTECTION
SS1 + OTSD
ISS = + gm ERROR PGND1
6µA AMPLIFIER PGND2
VREF = 0.6V
PWM
COMPARATOR HICCUP
TIMER POWER
VDD STAGE
SLOPE –
COMPENSATION/
RAMP GENERATOR
+
CURRENT SENSE
AMPLIFIER
CLIM_CH1
CURRENT
LIMIT
COMPARATOR CHANNEL 1

PGOOD2
0.7V

THERMAL
SHUTDOWN OTSD
VFB2

VIN4
0.5V
VIN5
VIN6
EN2
GATE
COMP2 CONTROL
UVLO LOGIC AND PMOS
V2SET SW3
VOUT MOSFET
SW4
SELECTOR OSC_CH2 DRIVERS
FB2 WITH
VFB2 PULSE SKIP ANTI-SHOOT NMOS
ENABLE THROUGH
–
PROTECTION
SS2 + OTSD
ISS = + gm ERROR PGND3
6µA AMPLIFIER PGND4
VREF = 0.6V
PWM
COMPARATOR HICCUP
TIMER POWER
VDD STAGE
SLOPE –
COMPENSATION/
RAMP GENERATOR
+
CURRENT SENSE
AMPLIFIER
CLIM_CH2
CURRENT
LIMIT
COMPARATOR CHANNEL 2
08143-065

Figure 65. Simplified Block Diagram

Rev. C | Page 20 of 37
Data Sheet ADP2114

THEORY OF OPERATION
ADIsimPower DESIGN TOOL An internal oscillator turns off the low-side, N-channel
The ADP2114 is supported by ADIsimPower design tool set. MOSFET and turns on the high-side, P-channel MOSFET at
ADIsimPower is a collection of tools that produce complete a fixed switching frequency. When the high-side P-channel
power designs optimized for a specific design goal. The tools MOSFET is enabled, the valley inductor current information is
enable the user to generate a full schematic, bill of materials, added to an emulated ramp signal and compared to the error
and calculate performance in minutes. ADIsimPower can voltage by the PWM comparator. The output of the PWM
optimize designs for cost, area, efficiency, and parts count while comparator modulates the duty cycle by adjusting the trailing
taking into consideration the operating conditions and edge of the PWM pulse that switches the power devices. Slope
limitations of the IC and all real external components. For compensation is programmed internally into the emulated ramp
more information about ADIsimPower design tools, refer to signal and automatically selected, depending on the VIN, VOUT,
www.analog.com/ADIsimPower. The tool set is available from and switching frequency. This prevents subharmonic oscil-
this website, and users can also request an unpopulated board lations on the inductor current for greater than 50% duty-cycle
through the tool. operation.

The ADP2114 is a high efficiency, dual, fixed switching frequency, Control logic with the antishoot-through circuit monitor and
synchronous step-down, dc-to-dc converter with flex mode adjust the low-side and high-side driver outputs to ensure break-
architecture, which is the Analog Devices, Inc., proprietary before-make switching. This monitoring and control prevents
version of its peak current mode control architecture. The crossconduction between the internal high-side, P-channel
device operates over an input voltage range of 2.75 V to 5.5 V. power MOSFET and the low-side, N-channel power MOSFET.
Each output channel provides an adjustable output down to 0.6 V UNDERVOLTAGE LOCKOUT (UVLO)
and delivers up to 2 A of load current. When both the output The UVLO threshold is 2.65 V when VDD is increasing and
channels are tied together, they operate 180° out of phase to 2.47 V when VDD is decreasing. The 180 mV hysteresis prevents
deliver up to 4 A of load current. The integrated high-side, the converter from turning off and on repeatedly during a slow
P-channel power MOSFET and the low-side, N-channel power voltage transition on VDD close to the 2.75 V minimum
MOSFET yield high efficiency at medium to heavy loads. Pulse operational level due to changing load conditions.
skip mode is available for improved efficiency at light loads. With
its high switching frequency (up to 2 MHz) and its integrated ENABLE/DISABLE CONTROL
power switches, the ADP2114 has been optimized to deliver The EN1 and EN2 pins are used to independently enable or
high performance in a small size for power management solutions. disable Channel 1 and Channel 2, respectively. Drive ENx high
The ADP2114 also includes undervoltage lockout (UVLO) with to turn on the corresponding channel of ADP2114. Drive ENx
hysteresis, soft start, and power good, as well as protection low to turn off the corresponding channel of ADP2114, reducing
features such as output short-circuit protection and thermal input current below 1 μA. To force a channel to start automatically
shutdown. The output voltages, current limits, switching when input power is applied, connect the corresponding ENx
frequency, pulse skip operation, and soft start time are to VDD. When shut down, the ADP2114 channels discharge
externally programmable with tiny resistors and capacitors. the soft start capacitor, causing a new soft start cycle every time
the converters are re-enabled.
CONTROL ARCHITECTURE
SOFT START
The ADP2114 consists of two step-down, dc-to-dc converters
that deliver regulated output voltages, VOUT1 and VOUT2 (see The ADP2114 soft start feature allows the output voltage to ramp
Figure 1), by modulating the duty cycle at which the internal up in a controlled manner, eliminating output voltage overshoot
high-side, P-channel power MOSFET and the low-side, N-channel during startup. Soft start begins after the undervoltage lockout
power MOSFET are switched on and off. In steady-state operation, threshold is exceeded and the enable pin, EN1 (EN2), is pulled
the output voltage, VOUT, is sensed on the feedback pin, FB1 (FB2), high above 2.0 V. External capacitors to ground are required on
and attenuated in proportion to the selected output voltage on both the SS1 and SS2 pins. Each regulating channel has its own
the V1SET (V2SET) pin. soft start circuit. When the converter powers up and is enabled,
the internal 6 μA current source charges the external soft start
An error amplifier integrates the error between the feedback capacitor, establishing a voltage ramp slope at the SS1 (SS2) pin,
voltage and the reference voltage (VREF = 0.6 V) to generate an as shown in Figure 66. The soft start time period ends when the
error voltage at the COMP1 (COMP2) pin. The valley inductor soft start ramp voltage exceeds the internal reference of 0.6 V.
current is sensed by a current-sense amplifier when the low-side,
N-channel MOSFET is on.

Rev. C | Page 21 of 37
ADP2114 Data Sheet
The power good circuitry monitors the output voltage on the
ENx
FB1 (FB2) pin and compares it to the rising and falling
1 thresholds shown in Table 1. If the output voltage, VOUT1
(VOUT2), exceeds the typical rising limit of 116% of the target
VOUT output voltage, VOUT1SET (VOUT2SET), the PGOOD1 (PGOOD2)
2
pin pulls low. The PGOOD1 (PGOOD2) pin continues to pull
low until the output voltage recovers down to 108% (typical) of
SSx
4 the target value.
If the output voltage drops below 84% of the target output voltage,
the corresponding PGOOD1 (PGOOD2) pin pulls low. The
SW
3 PGOOD1 (PGOOD2) pin continues to pull low until the output
voltage rises to within 92% of the target output voltage. The

08143-066
CH1 5.0V CH2 1.0V M1.0ms A CH1 2.4V PGOOD1 (PGOOD2) pin then releases and signals the return
CH3 5.0V CH4 2.0V
of the output voltage within the power good window.
Figure 66. Soft Start
The power good thresholds are shown in Figure 68. The PGOOD1
The capacitance value of the soft start capacitor defines the soft
and PGOOD2 outputs also sink current if an overtemperature
start time, tSS, based on
condition is detected. Use these outputs as logical power good
VREF I signals by connecting the pull-up resistors from PGOOD1
 SS (1)
t SS C SS (PGOOD2) to VDD. If the power good function is not used, the
pins can be left floating.
where:
VOUT RISING VOUT FALLING
VREF is the internal reference voltage, 0.6 V.
ISS is the soft start current, 6 μA. 116%

% OF VOUT SET
% OF VOUT SET

CSS is the soft start capacitor value. 108%

If the output voltage VOUT1 (VOUT2) is precharged prior to enabling 100% 100%

Channel 1 (Channel 2), the control logic prevents inductor 92%

current reversal by holding the power MOSFETs off until the 84%
soft start voltage ramp at SS1 (SS2) reaches the precharged
output voltage on VFB1 (VFB2), see Figure 67.
UNDERVOLTAGE POWER OVERVOLTAGE POWER UNDERVOLTAGE
GOOD GOOD

08143-068
ENx PGOOD1
1 (PGOOD2)

VOUT
Figure 68. PGOOD1 and PGOOD2 Thresholds
2
PULSE SKIP MODE
The ADP2114 has built-in, pulse skip circuitry that turns on
SSx
4 during light loads, switching only as necessary to maintain the
output voltage within regulation. This allows the converter to
maintain high efficiency during light load operation by reducing
SW
3
the switching losses. The pulse skip mode can be selected by
configuring the OPCFG pin according to Table 7. In pulse skip
08143-067

CH1 5.0V CH2 1.0V M200µs A CH1 2.4V mode, when the output voltage dips below regulation, the
CH3 5.0V CH4 500mV ADP2114 enters PWM mode for a few oscillator cycles to
Figure 67. Start with a Precharged Load increase the output voltage back to regulation. During the
POWER GOOD wait time between bursts, both power switches are off, and the
output capacitor supplies all load current. Because the output
The ADP2114 features open-drain, power-good outputs
voltage dips and recovers occasionally, the output voltage ripple
(PGOOD1 and PGOOD2) that indicate when the converter
in this mode is larger than the ripple in the PWM mode of
output voltage is within regulation. The power good signal
operation.
transitions low immediately when the corresponding channel is
disabled. If the converter is configured to operate in forced PWM mode
(by selecting that configuration on the OPCFG pin), the device
operates with a fixed switching frequency, even at light loads.

Rev. C | Page 22 of 37
Data Sheet ADP2114
HICCUP MODE CURRENT LIMIT MAXIMUM DUTY CYCLE OPERATION
The ADP2114 features a hiccup mode current limit As the input voltage drops and approaches the output voltage,
implementation. When the peak inductor current exceeds the ADP2114 smoothly transitions to maximum duty cycle
the preset current limit for more than eight consecutive clock operation, maintaining the low-side, N-channel MOSFET switch
cycles, the hiccup mode current limit condition occurs. The on for the minimum off time. In maximum duty cycle operation,
channel then goes to sleep for 6.8 ms (at a 600 kHz switching the output voltage dips below regulation because the output
frequency), which is enough time for the output to discharge voltage is the product of the input voltage and the maximum
and the average power dissipation to reduce. It then wakes up duty cycle limitation. The maximum duty cycle limit is a
with a soft start period (see Figure 69). If the current limit function of the switching frequency and the input voltage,
condition is triggered again, the channel goes to sleep and as shown in Figure 72.
wakes up after 6.8 ms. The current limits for the two channels
SYNCHRONIZATION
are programmed by configuring the OPCFG pin (see Table 7).
For the 2 A/2 A option, the output current limit is set to 3.3 A The ADP2114 can be synchronized to an external clock such
per output. For the 3 A/1 A option, the current limits are set to that the two channels operate at a switching frequency that is
4.5 A and 1.9 A for VOUT1 and VOUT2, respectively. half the input synchronization clock. The SYNC/CLKOUT pin
can be configured as an input SYNC pin or an output CLKOUT
pin through the SCFG pin, as shown in Table 6. Through the input
SYNC pin, the ADP2114 can be synchronized to an external clock
such that the two channels switch at half the external clock, 180°
INDUCTOR
CURRENT out of phase. Through the output CLKOUT pin, the ADP2114
4
provides an output clock that is twice the switching frequency of
the channels and 90° out of phase. Therefore, a single ADP2114
configured for the CLKOUT option acts as the master converter
VOUT
2
and provides an external clock for all other dc-to-dc converters
(including other ADP2114s). These other converters are configured
as slaves that accept an external clock and synchronize to it.
SW This clock distribution approach synchronizes all dc-to-dc
3
converters in the system and prevents beat harmonics that
08143-069

CH2 1.0V M2.0ms A CH4 1.72A can lead to EMI issues.

CH3 5.0V CH4 2A
Figure 69. Hiccup Mode The ADP2114 has been optimized to power high performance
signal chain circuits. The slew rate of the switch node is
THERMAL OVERLOAD PROTECTION
controlled by the size of the driver devices. Fast slewing of the
The ADP2114 has an internal temperature sensor that monitors switch node is desirable to minimize transition losses but can
the junction temperature. High current going into the switches lead to serious EMI issues due to parasitic inductance. Therefore,
or a hot printed circuit board (PCB) can cause the junction the slew rate of the drivers has been optimized such that the
temperature of the ADP2114 to rise rapidly. When the junction ADP2114 can match the performance of the low dropout
temperature reaches approximately 150°C, the ADP2114 goes regulators in supplying sensitive signal chain circuits while
into thermal shutdown and the converter is turned off. When the providing excellent power efficiency.
junction temperature drops below 125°C, the ADP2114 resumes
normal operation after the soft start sequence.

Rev. C | Page 23 of 37
ADP2114 Data Sheet

CONVERTER CONFIGURATION
SELECTING THE OUTPUT VOLTAGE To limit output voltage accuracy degradation due to FB bias
current to less than 0.05% (0.5% maximum), ensure that the
To set the output voltage, VOUT1 (VOUT2), select one of the six divider string current is greater than 20 μA. To calculate the
fixed voltages, as shown in Table 4, by connecting the V1SET desired resistor values, first determine the value of the bottom
(V2SET) pin to GND through an appropriate value resistor (see divider string resistor, R1, by
Figure 70). V1SET and V2SET set the voltage output levels for
Channel 1 and Channel 2, respectively. The feedback pin FB1 R1 = VREF/ISTRING (2)
(FB2) should be directly connected to VOUT1 (VOUT2). where:
VREF is 0.6 V, the internal reference.
Table 4. Output Voltage Programming ISTRING is the resistor divider string current.
RV1SET (Ω) ± 5% VOUT1 (V) RV2SET (Ω) ± 5% VOUT2 (V)
When R1 is determined, calculate the value of the top resistor,
0 to GND 0.8 0 to GND 0.8
R2, by
4.7 k to GND 1.2 4.7 k to GND 1.2
8.2 k to GND 1.5 8.2 k to GND 1.5 V  VREF 
R2  R1 OUT  (3)
15 k to GND 1.8 15 k to GND 1.8  V REF 
27 k to GND 2.5 27 k to GND 2.5 VIN
47 k to GND 3.3 47 k to GND 3.3 RFREQ
82 k to GND 0.6 to <1.6 82 k to GND 0.6 to <1.6
RV1SET /
(adjustable) (adjustable) RV2SET

FREQ
VDD
V1SET/
0 to VDD 1.6 to 3.3 0 to VDD 1.6 to 3.3 V2SET
(adjustable) (adjustable) VINx
ADP2114 VOUT1/VOUT2
SWx
L
If the required output voltage VOUT1 (VOUT2) is in the adjustable
FB1/FB2
range, from 0.6 V to less than 1.6 V, connect V1SET (V2SET) PGNDx
through an 82 kΩ resistor to GND. For the adjustable output COMP1/
GND COMP2
voltage range of 1.6 V to 3.3 V, tie V1SET (V2SET) to VDD (see

08143-070
Table 4). The adjustable output voltage of ADP2114 is externally
set by a resistive voltage divider from the output voltage to the Figure 70. Configuration for Fixed Outputs
feedback pin (see Figure 71). The ratio of the resistive voltage VIN
divider sets the output voltage, while the absolute value of those RFREQ
resistors sets the divider string current. For lower divider string
RV1SET /
currents, the small 10 nA (0.1 μA maximum) FB bias current RV2SET
FREQ
VDD

V1SET/
should be taken into account when calculating the resistor V2SET

values. The FB bias current can be ignored for a higher divider VINx
ADP2114 L VOUT1/VOUT2
string current; however, this degrades efficiency at very light loads. SWx
R2
FB1/FB2
PGNDx R1

COMP1/
GND COMP2
08143-071

Figure 71. Configuration for Adjustable Outputs

Rev. C | Page 24 of 37
Data Sheet ADP2114
SETTING THE OSCILLATOR FREQUENCY An external clock can be applied to the SYNC/CLKOUT pin
The ADP2114 channels can be set to operate in one of the three when configured as an input to synchronize multiple ADP2114s
preset switching frequencies: 300 kHz, 600 kHz, or 1.2 MHz. to the same external clock. The fSYNC range is 400 kHz to 4 MHz,
For 300 kHz operation, connect the FREQ pin to GND. For which produces fSW in the 200 kHz to 2 MHz range. See Figure 73
600 kHz or 1.2 MHz operation, connect a resistor between the for an illustration.
VIN
FREQ pin and GND, as shown in Table 5.
27kΩ 27kΩ
Table 5. Oscillator Frequency Setting
RFREQ (Ω) ± 5% fSW (kHz) SCFG FREQ VDD SCFG FREQ VDD
0 to GND 300 SYNC SYNC
8.2 k to GND 600 (fSW = fSYNC /2) (fSW = fSYNC /2)

27 k to GND 1200 ADP2114 ADP2114

fSYNC

08143-073
Choice of the switching frequency depends on the required EXTERNAL CLOCK (2.4MHz) TO OTHER ADP2114

dc-to-dc conversion ratio and is limited by the minimum and Figure 73. Synchronization with External Clock (fSW = 1.2 MHz in This Case)
maximum controllable duty cycle shown on Figure 72. This is When synchronizing to an external clock, the switching
due to the requirement of minimum on and minimum off times frequency fSW must be set close to half of the expected external
for current sensing and robust operation. The choice of clock frequency by appropriately terminating the FREQ pin as
switching frequency is also determined by the need for small shown in Table 5.
external components. For small, area limited power solutions, VIN
use of higher switching frequencies is recommended.
8.2kΩ 8.2kΩ
100

90
SCFG FREQ VDD SCFG FREQ VDD
80 SYNC CLKOUT
(fSW = fSYNC /2) (fSW = 2 × fSW)
DUTY-CYCLE LIMITS (%)

70
ADP2114 ADP2114
60 MAXIMUM LIMIT
fSYNC = 2 × fSW
MINIMUM LIMIT; VIN = 2.75V
50 TO OTHER ADP2114
MINIMUM LIMIT; VIN = 3.3V

08143-074
40 MINIMUM LIMIT; VIN = 5.5V NOTES
1. fSW = 600kHz SET FOR BOTH ADP2114.
30
Figure 74. ADP2114 to SYNC with Another ADP2114
20 (Note that the SCFG of the master is tied to VDD.)
10
The ADP2114 can also be configured to output a clock signal
0 on the SYNC/CLKOUT pin to synchronize multiple ADP2114s
08143-072

200 400 600 800 1000 1200

SWITCHING FREQUENCY (kHz) to it (see Figure 74). The CLKOUT signal is 90º phase shifted to
Figure 72. Duty Cycle Working Limits the internal clock of the channels so that the master ADP2114
and the slave channels are out of phase (see Figure 75 for
For single output, multiphase applications that operate at close
additional information).
to 50% duty cycle, it is recommended to use the 1.2 MHz
switching frequency to minimize crosstalk between the phases.
CHANNEL 1 SW
SYNCHRONIZATION AND CLKOUT
The ADP2114 can be configured to output an internal clock or 4
synchronize to an external clock at the STNC/CLKOUT pin.
CHANNEL 2 SW
The SYNC/CLKOUT pin is a bidirectional pin configured by
the SCFG pin, as shown in Table 6.
3
Table 6. SYNC/CLKOUT Configuration Setting
SCFG SYNC/CLKOUT
GND Input 1
VDD Output INTERNAL CLKOUT
08143-075

The converter switching frequency, fSW, is half of the synchroni- CH1 5.0V M1.0µs A CH4 3.00V
CH3 5.0V CH4 5.0V
zation frequency fSYNC/fCLKOUT as shown in Equation 4, irrespective
of whether SYNC/CLKOUT is configured as an input or output. Figure 75. CLKOUT Waveforms

fSYNC/fCLKOUT = 2 × fSW (4)

Rev. C | Page 25 of 37
ADP2114 Data Sheet
OPERATION MODE CONFIGURATION In addition, if the power-good feature is used, combine PGOOD1
The dual-channel ADP2114 can be configured to one of the four and PGOOD2 and connect them to VDD through a single
modes of operation by connecting the OPCFG pin as shown in pull-up resistor.
Table 7. This configuration sets the current limit for each When the ADP2114 is synchronized to an external clock, the
channel and enables or disables the transition to pulse skip mode converters always operate in fixed frequency CCM, and they do
at light loads. not enter into pulse skip mode at light loads. In this case, when
In the dual-phase configuration, the outputs of the two channels configuring the OPCFG pin, choose forced PWM mode.
are connected together, and they generate a single dc output
voltage, VOUT. For this single combined dual-phase output,
only Mode 2 in the OPCFG options can be used. In this mode,
the error amplifiers of both phases are used. The feedback
pins (FB1 and FB2) are tied together, the compensation pins
(COMP1 and COMP2) are tied together, the soft start pins (SS1
and SS2) are tied together, and the enable pins (EN1 and EN2)
are tied together.

Table 7. Current Limit Operation Mode and Configuration

Maximum Output Current Peak Current Limit
Mode ROPCFG (Ω) ± 5% IOUT1 (A)/IOUT2 (A) ILIMIT1 (A)/ILIMIT2 (A) Power Savings at Light Load
1 0 to GND 2/2 3.3/3.3 Pulse skip enabled
2 4.7 k to GND 2/2 3.3/3.3 Forced PWM
3 8.2 k to GND 3/1 4.5/1.9 Pulse skip enabled
4 15 k to GND 3/1 4.5/1.9 Forced PWM

Rev. C | Page 26 of 37
Data Sheet ADP2114

EXTERNAL COMPONENTS SELECTION

INPUT CAPACITOR SELECTION The internal slope compensation introduces additional limitations
on the optimal inductor value for stable operation because the
The input current to a buck converter is pulsating in nature. The internal ramp is scaled for each VOUT setting. The limits for
current is zero when the high-side switch is off and approximately different VIN, VOUT, and fSW combinations are listed in Table 8.
equal to the load current when it is on. Because this occurs at
reasonably high frequencies (300 kHz to 1.2 MHz), the input Table 8. Minimum and Maximum Inductor Values
bypass capacitor ends up supplying most of the high frequency fSW (kHz) VIN (V) VOUT (V) Min L (μH) Max L (μH)
current (ripple current), allowing the input power source to 300 5 3.3 6.8 10
supply only the average (dc) current. The input capacitor needs a 300 5 2.5 5.6 15
sufficient ripple current rating to handle the input ripple as well 300 3.3 2.5 5.6 6.8
as an ESR that is low enough to mitigate the input voltage 300 5 1.8 4.7 12
ripple. For the ADP2114, place a 22 μF, 6.3 V, X5R ceramic 300 3.3 1.8 4.7 8.2
capacitor close to the VINx pin for each channel. X5R or X7R 300 5 1.5 2.2 12
dielectrics are recommended with a voltage rating of 6.3 V or 300 3.3 1.5 2.2 8.2
10 V. Y5V and Z5U dielectrics are not recommended due to 300 5 1.2 2.2 10
their poor temperature and dc bias characteristics. 300 3.3 1.2 2.2 8.2
VDD RC FILTER 300 5 0.8 1.5 6.8
300 3.3 0.8 1.5 6.8
It is recommended to apply the input power, VIN, to the VDD pin
600 5 3.3 3.3 4.7
through a low-pass RC filter, as shown on Figure 76. Connecting a
600 5 2.5 3.3 6.8
10 Ω resistor in series with VIN and a 1 μF, 6.3 V, X5R (or X7R)
600 3.3 2.5 3.3 3.3
ceramic capacitor between VDD and GND creates a 16 kHz
600 5 1.8 2.2 6.8
(−3 dB) low-pass filter that effectively attenuates voltage glitches
600 3.3 1.8 2.2 3.3
on the input power rail caused by the switching regulator. This
600 5 1.5 1.5 5.6
provides a clean power supply to the internal, sensitive, analog
600 3.3 1.5 1.5 4.7
and digital circuits in the ADP2114, ensuring robust operation.
600 5 1.2 1.5 4.7
VIN
10Ω 600 3.3 1.2 1.5 3.3
VDD
600 5 0.8 1.0 3.3
1µF ADP2114
600 3.3 0.8 1.0 3.3
GND
08143-076

1200 5 2.5 1.0 3.3

1200 5 1.8 1.0 3.3
Figure 76. Low-Pass Filter at VDD
1200 3.3 1.8 1.0 2.2
INDUCTOR SELECTION 1200 5 1.5 0.8 2.2
The high switching frequency of ADP2114 allows for minimal 1200 3.3 1.5 0.8 2.2
output voltage ripple even with small inductors. The sizing of the 1200 5 1.2 0.8 2.2
inductor is a trade-off between efficiency and transient response. A 1200 3.3 1.2 0.8 2.2
small inductor leads to larger inductor current ripple that provides 1200 5 0.8 0.47 1.5
excellent transient response but degrades efficiency. Due to 1200 3.3 0.8 0.47 1.5
the high switching frequency of ADP2114, shielded ferrite core
inductors are recommended for their low core losses and low EMI. To avoid saturation, the rated current of the inductor has to be
larger than the maximum peak inductor IL_PEAK current given by
As a guideline, the inductor peak-to-peak current ripple, ΔIL, is
IL
typically set to 1/3 of the maximum load current for optimal I L _ PEAK  I LOAD _ MAX  (6)
2
transient response and efficiency.
where:
VOUT  (VIN  VOUT ) I LOAD(MAX )
I L   ILOAD_MAX is the maximum dc load current.
VIN  f SW  L 3 ΔIL is the inductor ripple current (peak to peak).
3  VOUT  (VIN  VOUT )
 LIDEAL  (5)
f SW  VIN  I LOAD( MAX )

where:
VIN is the input voltage on the VINx terminal.
VOUT is the desired output voltage.
fSW is the converter switching frequency.
Rev. C | Page 27 of 37
ADP2114 Data Sheet
The ADP2114 can be configured in either a 2 A/2 A or a 3 A/1 A Note that the previous equations are approximations and are
current limit configuration and, therefore, the current limit based on following assumptions:
thresholds for the two channels are different in each setting.
 The inductor value is based on the peak-to-peak current
The inductor chosen for each channel must have at least the
being 30% of the maximum load current.
peak output current limit of the IC in each case for robust
 Voltage drops across the internal MOSFET switches and
operation during short-circuit conditions. The following
across the dc resistance of the inductor are ignored.
inductors are recommended:
 In Equation 9, it is assumed that it takes up to three switching
 From 0.47 μH to 4.7 μH, the TOKO D53LC and cycles until the loop adjusts the inductor current in response
FDV0620 series to the load step.
 From 4.7 μH to 12 μH, the Cooper Bussman DR1050 series
Select the largest output capacitance given by Equation 8 and
and the Wurth Elektronik WE-PDF series.
Equation 9. While choosing the actual type of ceramic capacitor
OUTPUT CAPACITOR SELECTION for the output filter of the converter, pick one with a nominal
capacitance that is 20% to 30% larger than the calculated value
The output capacitor selection affects both the output voltage
because the effective capacitance decreases with larger dc voltages.
ripple and the loop dynamics of the converter. The ADP2114
In addition, the rated voltage of the capacitor must be higher
is designed for operation with small ceramic output capacitors
than the output voltage of the converter.
that have low ESR and ESL; therefore, comfortably able to meet
tight output voltage ripple specifications. X5R or X7R dielectrics Recommended input and output ceramic capacitors include
are recommended with a voltage rating of 6.3 V or 10 V. Y5V  Murata GRM21BR61A106KE19L, 10 μF, 10 V, X5R, 0805
and Z5U dielectrics are not recommended due to their poor  TDK C2012X5R0J226M, 22 μF, 6.3 V, X5R, 0805
temperature and dc bias characteristics. The minimum output
 Panasonic ECJ-4YB0J476M, 47 μF, 6.3 V, X5R, 1210
capacitance, COUT_MIN, is determined by Equation 7 and
 Murata GRM32ER60J107ME20L, 100 μF, 6.3 V, X5R, 1210
Equation 8.
For acceptable maximum output voltage ripple, CONTROL LOOP COMPENSATION
The ADP2114 uses a peak, current mode control architecture
 1 
ΔV RIPPLE  ΔI L   ESR   (7) for excellent load and line transient response. The external
 8  f  C OUT_MIN 
 SW  voltage loop is compensated by a transconductance amplifier
Therefore, with a simple external RC network between the COMP1
(COMP2) pin and GND, as shown in Figure 77.
ΔIL
COUT_MIN (8)
8 fSW (ΔVRIPPLE— ΔIL  ESR) ADP2114 COMPx

where: VFBx RCOMP

ΔVRIPPLE is allowable peak-to-peak output voltage ripple in volts. gm
CC2
CCOMP
ΔIL is the inductor ripple current.
0.6V
ESR is the equivalent series resistance of the capacitor in ohms. GND
08143-077

fSW is the converter switching frequency in Hertz.

If there is a step load, choose the output capacitor value based Figure 77. Compensation Components
on the value of the step load. For the maximum acceptable
The basic control loop block diagram is shown in Figure 78.
output voltage droop/overshoot caused by the step load,
VIN
 3  INDUCTOR
C OUT_MIN  ΔI OUT_STEP   

(9) CURRENT
 f SW  ΔV DROOP  SENSE
PULSE
WIDTH IL
VOUT
where: MODULATOR

ΔIOUT_STEP is the load step value in amperes.

fSW is the switching frequency in Hertz.
ΔVDROP is the maximum allowable output voltage
droop/overshoot in volts for the load step. VCOMP
gm
VREF = 0.6V
CCOMP
ADP2114
08143-078

RCOMP

Figure 78. Basic Control Block Diagram

The blocks and components shown enclosed within the dashed line
in Figure 78 are embedded inside each channel of the ADP2114.
Rev. C | Page 28 of 37
Data Sheet ADP2114
The control loop can be broken down into the following three At the crossover frequency, the gain of the open-loop transfer
sections: function is unity. This yields Equation 16 for the compensation
network impedance at the crossover frequency.
 VOUT to VCOMP
 VCOMP to IL 2  π  fCROSS  COUT VOUT
ZCOMP ( fCROSS )   (16)
 IL to VOUT g m  GCS VREF
Correspondingly, there are three transfer functions: To ensure that there is sufficient phase margin at the crossover
VCOMP(s) VREF frequency, place the compensator zero at 1/8 of the crossover
  g m  ZCOMP(s) (10)
VOUT(s) VOUT frequency, as shown in Equation 17.
1 f
I L(s)
 GCS f ZERO   CROSS (17)
VCOMP(s)
(11)   R  C
2 π COMP COMP 8
Solving Equation 16 and Equation 17 simultaneously yields the
VOUT(s)
 ZFILT(s) (12) value for the compensation resistor and compensation
I L(s) capacitor, as shown in Equation 18 and Equation 19.
where:  (2 π ) FCROSS   C OUT VOUT 
gm is the transconductance of the error amplifier, 550 μs. RCOMP  0 .9   
  V


(18)
 G m G CS   REF 
GCS is the current sense gain, 4 A/V.
VOUT is the output voltage of the converter. 1
CCOMP  (19)
VREF is the internal reference voltage of 0.6 V. 2  π  f ZERO  RCOMP
ZCOMP(s) is the impedance of the RC compensation network that
forms a pole at origin and a zero as expressed in Equation 13. The capacitor CC2 (as shown in Figure 77) forms a pole with the
compensation resistor, RCOMP, in the feedback loop to ensure
1  s  RCOMP  CCOMP
ZCOMP(s)  (13) that the loop gain keeps rolling off well beyond the unity-gain
s  CCOMP crossover frequency. The value of CC2, if used, is typically set to
ZFILT(s) is the impedance of the output filter and is expressed as 1/40 of the compensation capacitor, CCOMP.

RLOAD
ZFILT(s)  (14)
1  s  RLOAD  COUT
where s is angular frequency that can be written as s = 2πf.
The overall loop gain, H(s), is obtained by multiplying the three
transfer functions previously mentioned as follows:
VREF
H(s) = gM × GCS × × ZCOMP(s) × ZFILT(s) (15)
VOUT
When the switching frequency (fSW), output voltage (VOUT), output
inductor (L), and output capacitor (COUT) values are selected,
the unity crossover frequency of 1/12 (approximately) the
switching frequency can be targeted.

Rev. C | Page 29 of 37
ADP2114 Data Sheet

DESIGN EXAMPLE
The external component selection procedure from the Control 3. Select the inductor by using Equation 5.
Loop Compensation section is used for this design example.
(VIN  VOUT ) VOUT
L 
Table 9. 2-Channel Step-Down DC-to-DC Converter ΔI L  f SW VIN
Requirements
In Equation 5, VIN = 5 V, VOUT = 3.3 V, ΔIL = 0.3 × IL = 0.6 A,
Additional
Parameter Specification Requirements and fSW = 600 kHz, which results in L = 3.11 μH.
Input Voltage, VIN 5.0 V ±10% None Therefore, when L = 3.3 μH (the closest standard value) in
Channel 1, VOUT1 3.3 V, 2 A, 1% VOUT Maximum load step: Equation 3, ΔIL = 0.566 A.
ripple (p-p) 1 A to 2 A, 5% droop
Although the maximum output current required is 2 A, the
maximum
maximum peak current is 3.3 A under the current limit
Channel 2, VOUT2 1.8 V, 2 A, 1% VOUT Maximum load step:
ripple (p-p) 1 A to 2 A, 5% droop condition (see Table 7). Therefore, the inductor should be
maximum rated for 3.3 A of peak current and 3 A of average current
Pulse-Skip Feature Enabled None for reliable circuit operation.
4. Select the output capacitor by using Equation 8 and
Equation 9.
CHANNEL 1 CONFIGURATION AND COMPONENTS
SELECTION ΔIL
COUT_MIN
Complete the following steps to configure Channel 1: 8  fSW (ΔVRIPPLE- ΔIL  ESR)
1. For the target output voltage, VOUT = 3.3 V, connect the  3 
V1SET pin through a 47 kΩ resistor to GND (see Table 4). C OUT_MIN  ΔI OUT_STEP   

f
 SW  ΔV DROOP 
Because one of the fixed output voltage options is chosen,
the feedback pin (FB1) must be directly connected to the Equation 8 is based on the output ripple (ΔVRIPPLE), and
output of Channel 1, VOUT1. Equation 9 is for capacitor selection based on the transient
2. Estimate the duty-cycle, D, range. Ideally, load performance requirements that allow, in this case, 5%
maximum deviation. As previously mentioned, perform
VOUT
D (20) these calculations and choose whatever equation yields the
VIN larger capacitor size.
That gives the duty cycle for the 3.3 V output voltage and In this case, the following values are substituted for the
the nominal input voltage of DNOM = 0.66 at VIN = 5.0 V. variables in Equation 8 and Equation 9:
The minimum duty cycle, DMIN, for the maximum input ΔIL = 0.566 A
voltage (10% above the nominal) is DMIN = 0.60 at VIN fSW = 600 kHz
maximum = 5.5 V ΔVRIPPLE = 33 mV (1% of 3.3 V)
The maximum duty cycle, DMAX, for the minimum input ESR = 3 mΩ (typical for ceramic capacitors)
voltage (10% less than nominal) is DMAX = 0.73 at VIN ΔIOUT_STEP = 1 A
minimum = 4.5 V.
ΔVDROOP = 0.165 V (5% of 3.3 V)
However, the actual duty cycle is larger than the calculated
The output ripple based calculation (see Equation 8) dictates
values to compensate for the power losses in the converter.
that COUT = 4.0 μF, whereas the transient load based
Therefore, add 5% to 7% at the maximum load.
calculation (see Equation 9) dictates that COUT = 30 μF. To
Based on the estimated duty-cycle range, choose the meet both requirements, choose the latter. As previously
switching frequency according to the minimum and mentioned in the Control Loop Compensation section, the
maximum duty-cycle limitations, as shown in Figure 72. capacitor value reduces with applied dc bias; therefore, select a
For the Channel 1 VIN = 5 V and VOUT = 3.3 V combination, higher value. In this case, the next higher value is 47 μF
choose fSW = 600 kHz with a maximum duty cycle of 0.8. with a minimum voltage rating of 6.3 V.
This frequency option provides the smallest sized solution. 5. Calculate the feedback loop, compensation component
If a higher efficiency is required, choose the 300 kHz option. values by using Equation 15.
However, the PCB footprint area of the converter will be
larger because of the bigger inductor and output capacitors. VREF
H(s) = gM × GCS × × ZCOMP(s) × ZFILT(s)
VOUT

Rev. C | Page 30 of 37
Data Sheet ADP2114
In this case, the following values are substituted for the The switching frequency (fSW) of 600 kHz, which is chosen
variables in Equation 18: based on the Channel 1 requirements, meets the duty cycle
gm = 550 μs ranges that have been previously calculated. Therefore, this
switching frequency is acceptable.
GCS = 4A/V
VREF = 0.6 V 3. Select the inductor by using Equation 5.
VOUT = 3.3 V (VIN  VOUT ) VOUT
L 
COUT = 0.8 × 47 μF (capacitance derated by 20% to account ΔI L  f SW VIN
for dc bias).
In Equation 5, VIN = 5 V, VOUT = 1.8 V, ΔIL = 0.3 × IL =
From Equation 18, 0.6 A, and fSW = 600 kHz, which results in L = 2.9 μH.
RCOMP = 27 kΩ. Therefore, when L = 3.3 μH (the closest standard value) in
Substituting RCOMP in Equation 19 yields CCOMP = 1000 pF. Equation 3, ΔIL = 0.582 A.
Although the maximum output current required is 2 A, the
Table 10. Channel 1 Circuit Settings
maximum peak current is 3.3 A under the current limit
Circuit Parameter Setting Value condition (see Table 7). Therefore, the inductor should be
Output Voltage, VOUT Step 1 3.3 V rated for 3.3 A of peak current and 3 A of average current
Reference Voltage, VREF Fixed, typical 0.6 V for reliable circuit operation under all conditions.
Error Amp Transconductance, gm Fixed, typical 550 μs
Current Sense Gain, CCS Fixed, typical 4 A/V
4. Select the output capacitor by using Equation 8 and
Equation 9.
Switching Frequency, fSW Step 2 600 kHz
Crossover Frequency, fC 1/12 fSW 50 kHz ΔIL
COUT_MIN 
Zero Frequency, fZERO 1/8 fCROSS 6.25 kHz 8  f SW  (ΔVRIPPLE - ΔIL  ESR)
Output Inductor, LOUT Step 3 3.3 μH
 3 
Output Capacitor, COUT Step 4 47 μF, 6.3 V C OUT_MIN  ΔI OUT_STEP   

Compensation Resistor, RCOMP Equation 18 27 kΩ f
 SW  ΔV DROOP 
Compensation Capacitor, CCOMP Equation 19 1000 pF Equation 8 is based on the output ripple (ΔVRIPPLE), and
Equation 9 is for capacitor selection based on the transient
CHANNEL 2 CONFIGURATION AND COMPONENTS load performance requirements that allow, in this case, 5%
SELECTION maximum deviation. As mentioned earlier, perform these
Complete the following steps to configure Channel 2: calculations and choose whatever equation yields the larger
capacitor size.
1. For the target output voltage, VOUT = 1.8 V, connect the
V2SET pin through a 15 kΩ resistor to GND (see Table 4). In this case, the following values are substituted for the
Because one of the fixed output voltage options is chosen, variables in Equation 8 and Equation 9:
the feedback pin (FB2) must be directly connected to the ΔIL = 0.582 A
output of Channel 2, VOUT2. fSW = 600 kHz
2. Estimate the duty-cycle, D, range (see Equation 20). Ideally, ΔVRIPPLE = 18 mV (1% of 1.8 V)
VOUT ESR = 3 mΩ (typical for ceramic capacitors)
D
VIN ΔIOUT_STEP = 1 A
ΔVDROOP = 0.09 V (5% of 1.8 V)
That gives the duty cycle for the 1.8 V output voltage and
the nominal input voltage of DNOM = 0.36 at VIN = 5.0 V. The output ripple based calculation (see Equation 8) dictates
that COUT = 7.7 μF, whereas the transient load based
The minimum duty cycle for the maximum input voltage (10%
calculation (see Equation 9) dictates that COUT = 55 μF. To
above the nominal) is DMIN = 0.33 at VIN maximum = 5.5 V.
meet both requirements, choose the latter. As previously
The maximum duty cycle for the minimum input voltage (10% mentioned in the Control Loop Compensation section, the
less than nominal) is DMAX = 0.4 at VIN minimum = 4.5 V. capacitor value reduces with applied dc bias; therefore, select
However, the actual duty cycle is larger than the calculated a higher value. In this case, choose a 47 μF/6.3 V capacitor
values to compensate for the power losses in the converter. and a 22 μF/6.3 V capacitor in parallel to meet the
Therefore, add 5% to 7% at the maximum load. requirements.

Rev. C | Page 31 of 37
ADP2114 Data Sheet
5. Calculate the feedback loop, compensation component SYSTEM CONFIGURATION
values by using Equation 15. Complete the following steps to further configure the ADP2114
V for this design example:
H(s) = gm × GCS × REF × ZCOMP(s) × ZFILT(s)
VOUT 1. Set the switching frequency (fSW) = 600 kHz (see Table 5)
by connecting the FREQ pin through an 8.2 kΩ resistor
In this case, the following values are substituted for the
to GND.
variables in Equation 18:
2. Tie SCFG to VDD and use the CLKOUT signal to
gm = 550 μs synchronize other converters on the same board with the
GCS = 4 ADP2114.
VREF = 0.6 V 3. Tie OPCFG to GND for 2 A/2 A maximum output current
VOUT = 1.8 V operation and to enable pulse skip mode at light load
conditions (see Table 7).
COUT = 0.8 × (47+22) μF (capacitance derated by 20% to
account for dc bias). A schematic of the ADP2114 as configured in the design example
From Equation 18, described in this section is shown in Figure 79.

RCOMP = 22 kΩ. Table 12 provides the recommended inductor, output capacitor,

and compensation component values for a set of popular input
Substituting RCOMP in Equation 19 yields CCOMP = 1100 pF. and output voltage combinations.
Table 11. Channel 2 Circuit Settings
Circuit Parameter Setting Value
Output Voltage, VOUT Nominal 1.8 V
Reference Voltage, VREF Typical 0.6 V
Error Amp Transconductance, gm Typical 550 μs
Current Sense Gain, CCS Typical 4 A/V
Switching Frequency, fSW Step 2 600 kHz
Crossover Frequency, fCROSS 1/12 fSW 50 kHz
Zero Frequency, fZERO 1/8 fCROSS 6.25 kHz
Output Inductor, LOUT Step 3 3.3 μF
Output Capacitors, COUT Step 4 47 μF + 22 μF
Compensation Resistor, RCOMP Equation 18 22 kΩ
Compensation Capacitor, CCOMP Equation 19 1100 pF

Table 12. Selection Table of L, COUT, and Compensation Values

fSW (kHz) VIN (V) VOUT (V) Maximum Load (A) L (μH) COUT (μF) RCOMP (kΩ) CCOMP (pF)
300 5 3.3 2.0 6.8 69 (47 + 22) 20 2400
300 5 2.5 2.0 6.8 100 22 2400
300 5 1.8 2.0 6.8 147 (100 + 47) 22 2400
300 5 1.2 2.0 4.7 200 (2 × 100 ) 20 2400
600 5 3.3 2.0 3.3 47 27 1000
600 5 2.5 2.0 3.3 57 (47 + 10) 24 1100
600 5 1.8 2.0 3.3 69 (47 + 22) 22 1100
600 5 1.2 2.0 2.2 100 20 1200
1200 5 2.5 2.0 1.8 32 (22 + 10) 27 470
1200 5 1.8 2.0 1.8 44 (2 × 22) 27 470
1200 5 1.2 2.0 1.2 57 (47 + 10) 24 510
1200 5 0.8 2.0 1.0 100 27 470

Rev. C | Page 32 of 37
Data Sheet ADP2114

APPLICATION CIRCUITS
VIN = 5V

10Ω
1µF
100kΩ 100kΩ
EN2 EN1

VDD
VIN4 VIN1
22µF 22µF
VIN5 VIN2

PGOOD2 VIN6 VIN3 PGOOD1

PGOOD2 PGOOD1
3.3µH VOUT1 = 3.3V, 2A
VOUT2 = 1.8V, 2A 3.3µH SW1
SW3 ADP2114 SW2
SW4
22µF 47µF PGND1 47µF
PGND3
PGND2
PGND4
FB1
FB2 47kΩ
V2SET V1SET
15kΩ
SYNC
SYNC/CLKOUT

OPCFG
COMP2 COMP1

FREQ

SCFG
GND
SS2 SS1 27kΩ
10nF
22kΩ 10nF
1000pF
1100pF 8.2kΩ

08143-079
fSW = 600kHz

Figure 79. Application Circuit for 2 A/2 A Outputs

VIN = 5V
10Ω
100kΩ

10µF 10µF
1µF

PGOOD2 PGOOD1
SCFG
VDD

4.7kΩ 4.7kΩ PGOOD

V2SET V1SET
VIN4 VIN1

VIN5 VIN2
VIN3
VIN6 1.2µH VOUT = 1.2V, 4A
1.2µH ADP2114 SW1
SW3
SW2
SW4 47µF 22µF
47µF FB1
FB2 PGND1
PGND3 PGND2
PGND4 COMP1
COMP2
12kΩ
SYNC/CLKOUT
OPCFG

1000pF
FREQ

GND
EN1
EN2
SS1
SS2

22nF fSW =
08143-080

VIN 27kΩ 4.7kΩ 1.2MHz

Figure 80. Application Circuit for a Single 4 A Output

Rev. C | Page 33 of 37
ADP2114 Data Sheet
VIN = 5V

10Ω
1µF
100kΩ 100kΩ
EN2 EN1

SCFG
VDD
VIN4 VIN1
22µF 22µF
VIN5 VIN2

PGOOD2 VIN6 VIN3 PGOOD1

PGOOD2 PGOOD1
6.8µH VOUT1 = 1.8V, 3A
VOUT2 = 3.3V, 1A 6.8µH SW1
SW3 ADP2114 SW2
SW4
PGND1 47µF 100µF
22µF 47µF PGND3
PGND2
PGND4
FB1
FB2 15kΩ
V2SET V1SET
47kΩ
CLKOUT
SYNC/CLKOUT

OPCFG
COMP1

FREQ
COMP2

GND
SS1 22kΩ
SS2 10nF
20kΩ 10nF
2.4nF

8.2kΩ
2.4nF

08143-081
fSW = 300kHz

Figure 81. Application Circuit for 3 A/1 A Outputs

VIN = 3.3V

10Ω
1µF
100kΩ 100kΩ
EN2 EN1
VDD

VIN4 VIN1
22µF 22µF
VIN5 VIN2

PGOOD2 VIN6 VIN3 PGOOD1

PGOOD2 PGOOD1
SW1 VOUT1 = 1.0V, 2A
VOUT2 = 1.4V, 2A
SW3 ADP2114 SW2 1µH
1µH
12.1kΩ 16.2kΩ

SW4
PGND1 100µF
12.1kΩ 8.06kΩ

47µF PGND3
PGND2
PGND4
FB1
FB2 82kΩ
V2SET V1SET
82kΩ
SYNC/CLKOUT COMP1
SYNC COMP2 SS1 33kΩ
OPCFG

10nF
FREQ

SCFG

22kΩ SS2
GND

10nF
390pF
560pF
4.7kΩ
27kΩ

08143-082

fSW = 1.2MHz
Figure 82. Application Circuit for Adjustable Outputs

Rev. C | Page 34 of 37
Data Sheet ADP2114

POWER DISSIPATION, THERMAL CONSIDERATIONS

Power dissipated by the ADP2114 dual switching regulator is a Transition losses occur because the P-channel power MOSFET
major factor that affects the efficiency of the two dc-to-dc cannot be turned on or off instantaneously. The amount of
converters. The efficiency is given by transition loss is calculated by
POUT PTRAN = VIN × IOUT × (tRISE + tFALL) × fSW (26)
Efficiency 100% (21)
PIN where tRISE and tFALL are the rise time and the fall time of the
where: switching node, SW. In the ADP2114, the rise and fall times of
PIN is the input power. the switching node are in the order of 5 ns.
POUT is the output power. The power dissipated by the regulator increases the die junction
Power loss is given by PLOSS = PIN − POUT. temperature, TJ, above the ambient temperature, TA.
The power loss of the step-down dc-to-dc converter is TJ = TA + TR (27)
approximated by where the temperature rise, TR, is proportional to the power
PLOSS = PD + PL (22) dissipation in the package, PD.
where: The proportionality coefficient is defined as the thermal resistance
PD is the power dissipation on the ADP2114. from the junction of the die to the ambient temperature.
PL is the inductor power losses. TR = θJA × PD (28)
The inductor losses are estimated (without core losses) by where θJA is the junction-ambient thermal resistance (34°C/W
PL  IOUT2 × DCRL (23) for the JEDEC 1S2P board, see Table 2).
where: When designing an application for a particular ambient
IOUT is the dc load current. temperature range, calculate the expected ADP2114 power
DCRL is the inductor series resistance. dissipation (PD) due to conductive, switching, and transition
losses of both channels by using Equation 24, Equation 25,
The ADP2114 power dissipation, PD, includes the power switch
and Equation 26 and estimate the temperature rise by using
conductive losses, the switch losses, and the transition losses of
each channel. Equation 27 and Equation 28. The reliable operation of the
two converters can be achieved only if the estimated die junction
The power switch conductive losses are due to the output current, temperature of the ADP2114 (Equation 27) is less than 125°C.
IOUT, flowing through the PMOSFET and the NMOSET power Therefore, at higher ambient temperatures, reduce the power
switches that have internal resistance, RDSON. The amount of dissipation of the system. Figure 83 provides the power derating
conductive power loss is found by for the elevated ambient temperature at different air flow
PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT2 (24) conditions. The area below the curves is the safe operation area
where the duty-cycle, D, = VOUT/VIN. for ADP2114 dual regulators.
2.2
Switching losses are associated with the current drawn by the 2.0
driver to turn on and turn off the power devices at the switching AIR VELOCITY = 500 LFM
MAXIMUM POWER DISSIPATION (W)

1.8
frequency. The amount of switching power loss is given by AIR VELOCITY = 200 LFM
1.6
2
PSW = (CGATE-P + CGATE-N) × VIN × fSW (25) 1.4

where: 1.2

CGATE-P is the PMOSFET gate capacitance. 1.0 AIR VELOCITY = 0 LFM

CGATE-N is the NMOSFET gate capacitance. 0.8

0.6

0.4

0.2

0
08143-083

70 85 100 115
AMBIENT TEMPERATURE (°C)

Figure 83. Power Dissipation Derating (JEDEC 1S2P Board)

Rev. C | Page 35 of 37
ADP2114 Data Sheet

CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good circuit board layout is essential in obtaining the best  Connect the ADP2114 exposed pad to a large copper plane
performance from each channel of the ADP2114. Poor circuit to maximize its power dissipation capability. Thermal
layout degrades the output ripple and regulation, as well as the conductivity can be obtained using the method described
EMI and electromagnetic compatibility performance. For in JEDEC specification JESD51-7.
optimum layout, refer to the following guidelines:  Place the feedback resistor divider network as close as
 Use separate analog and power ground planes. Connect the possible to the FBx pin to prevent noise pickup. Try to
ground reference of sensitive analog circuitry, such as output minimize the length of the trace connecting the top of the
voltage divider components, to analog ground. In addition, feedback resistor divider to the output while keeping away
connect the ground references of power components, such as from the high current traces and the switch node, SWx, that
input and output capacitors, to power ground. Connect can lead to noise pickup. To reduce noise pickup, place an
both ground planes to the exposed pad of the ADP2114. analog ground plane on either side of the FBx trace and
 Place the input capacitor of each channel as close to the make it as small as possible to reduce the parasitic
VINx pins as possible and connect the other end to the capacitance pickup.
closest power ground plane. VIN
10Ω
 For low noise and better transient performance, a filter is 1µF

recommended between VINx and VDD. Place a 1 μF, 10 Ω GND

low-pass input filter between the VDD pin and the VINx GND VDD VINx
CIN
L VOUT
pins, as close to the GND pin as possible.
SWx
 Ensure that the high current loop traces are as short and as ADP2114 COUT
LOAD
wide as possible. Make the high current path from CIN PGNDx
through L, COUT, and the power ground plane back to CIN as
short as possible. To accomplish this, ensure that the input and
output capacitors share a common power ground plane. In FBx
addition, make the high current path from the PGNDx pin

08143-084
through L and COUT back to the power ground plane as
short as possible. To do this, ensure that the PGNDx pin of Figure 84. High Current Traces in the PCB Circuit
the ADP2114 is tied to the PGND plane as close as possible
to the input and output capacitors (see Figure 84).

Rev. C | Page 36 of 37
Data Sheet ADP2114

OUTLINE DIMENSIONS
5.10 0.30
5.00 SQ 0.25
PIN 1 4.90 0.18
INDICATOR PIN 1
25 32 INDICATOR
24 1
0.50
BSC
EXPOSED 3.25
PAD
3.10 SQ
2.95

17 8
16 9
0.50 0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.30 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE

112408-A
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

Figure 85. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range2 Package Description Package Option Ordering Quantity
ADP2114ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 1,500
ADP2114ACPZ-R2 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 250
ADP2114-2PH-EVALZ Single output, dual-phase interleaved, 1.2 V at 4 A,
1.2 MHz switching frequency, forced PWM
ADP2114-EVALZ Dual output, 3.3 V at 2 A and 1.8 V at 2 A, 600 kHz
switching frequency, pulse skip enabled
1
Z = RoHS Compliant Part.
2
Operating junction temperature is −40°C to +125°C.

©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D08143-0-3/16(C)

Rev. C | Page 37 of 37