Prime Time 1

Guidelines to improve runtime and memory

 Run PT on the best machine (unix or linux)

 Use the latest PT version

 Reduce the # of Timing updates

 Use 64 bit mode only if necessary

 Avoid exec or sh commands

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Agenda
DAY
2 6 Summary Reports

7 Create a Setup File and Run Script

8 Validate a Run Script

9 Getting to Know Your Clocks

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Review of Run Scripts

1) You know that no errors occurred during execution of the run script
because:
A. You searched through run.log for the word Error.
B. The script executed completely (i.e did not terminate prematurely)
2) print_message_info:
A. Used to generate man pages for specific messages.
B. Lists all messages (errors, warnings or informational) that have
occurred.
3) quit:
A. Place early in the run script to drastically improve runtime.
B. Reports the number and type of timing updates that have occurred.

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Objectives

After completing this unit, you should be able to:

 On an unfamiliar design, gather basic information about
the design clocks:
• How many clocks
• What type and where are the clocks defined
• Which clocks are interacting

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Clocks are STA

STA is dictated largely by the design clocks.

Faster, easier debugging of timing violations with
familiarity of the design clocks!

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Three Types of Clocks

3 Types of Clocks

Asynchronous, synchonous, and

and exclusive clocks

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What Are Master Clocks?

 Master clocks are typically created at input ports

create_clock -period 4 [get_ports Clk]
• Clocks are propagated through combinational logic

Inversion through negative_unate arcs.

FF1
Simple delay propagation
D Q

CLK

Clk 1
0

Describe what happens if Clk is: Ideal or Propagated

Public chat

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Generated Clocks: Internally Derived Clocks

Circle an interanl pin where a "generated clocks" should be
defined.

Master Clock

FF1 FF2

D Q D Q

Clk CLK CLK

FF3
Q

create_generated_clock -divide_by 2 -name div_clk -source [get_ports Clk] FF3/Q

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Generated Clocks: Source Latency

Prime Time calculates source

latency for generated clocks.
Master Clock

FF1 FF2

D Q D Q
Generated Clock

Clk CLK CLK

FF3
Q

dive_clk

Draw the source latency of the generated clock div_clk.

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More Clocks - Source Synchronous Interface

The chip specification

includes a min/max
path requirement with
FF1 respect to Out_Clk.
D Q Out_Data

U4
CLK

My_Clk Out_Clk

The entire latency from the input port My_Clk to the output port
Out_Clk is a component of the path requirement.

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Generated Clocks: Outgoing Clocks

Generated
Clock
Master FF1
Clock D Q Out_Data
PT calculates
U4
CLK
source latency
for generated
My_Clk Out_Clk clocks.

What happens if the

Public chat clocks are ideal?

Draw the source latency of the generated clock Out_Clk.

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Third Kind of Clock - Virtual Clocks

 Virtual clocks:
• Are clock objects without a source
• Do not clock sequential devices within the current_design
• Serve as references for input or output delays

create_clock -period 5 -name vclk

set_input_delay -max 2 -clock vclk [get_ports in1]
set_output_delay -max 1 -clock vclk [get_ports out2]

If a virtual clock is propagared:

Prime Time calculates network latency.
There is no network latency to calculate!

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Use report_clock For All Clocks

Circle the source (definition point) for each clock.
Identify the generated clocks.
Identify the virtual clocks (if any).

pt_shell> report_clock
Attributes:
p - Propagated clock
G - Generated clock
I - Inactive clock

Clock Period Waveform Attra Sources

---------------------------------------------------------------------------
PCI_CLK 15.00 {0 7.5} p {pclk}
SDRAM_CLK 7.50 {0 3.75} p {sdr_clk}
SD_DDR_CLK 7.50 {0 3.75} p, G {sd_CK}
SD_DDR_CLKn 7.50 {3.75 7.5} p, G {sd_CKn}
SYS_2x_CLK 4.00 {0 2} p, G
{I_CLOCK_GEN/I_CLKMUL/CLK_2x}
SYS_CLK 8.00 {0 4} p {sys_clk}

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How Many Clocks Are In Your Design?

pt_shell> sizeof_collection [all_clocks]

6

All clocks includes all master, generated and

virtual clocks defined in your design.

pt_shell> sizeof_collection [get_generated_clocks *]

3

How many reports will report_timing

Public chat generated by default?

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A Useful Tcl Procedure

A Tcl procedure that reports all ports with clocks defined.

pt_shell> rpt_clock_ports
Port Name Direction Clock Name Is Generated
----------------------------------------------------
Clk in myclk false

FF1
D Q

CLK

Clk 1
0

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Test For Understanding 1/2

pt_shell> rpt_clock_ports
Port Name Direction Clock Name Is Generated
----------------------------------------------------
pclk in PCI_CLK false
sys_clk in SYS_CLK false
sdr_clk in SDRAM_CLK false
sd_CK out SD_DDR_CLK false
sd_CKn out SD_DDR_CLKn false

Offer one reason for generated clocks to be

Public chat created on output ports?

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Test For Understanding 2/2

pt_shell> check_timing -verbose
Information: Checking 'unconstrained_endpoints'.
Warning: There are 2 endpoints which are not constrained
for maximum delay.

Endpoint
----------------------------------------------------------
sd_CK
sd_CKn

Information: Checking 'unexpandable_clocks'.

Information: Checking 'generic'.

Continuing the example from the previous page,

Public chat can the warning above be ignored?

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Generate a Timing Report

For calculated source latency details of generated clocks.

report_timing -to sd_DQ[0] -path_type full_clock_expanded

The chip specification

includes a min/max
FF1
path requirement with
D Q Out_Data
respect to sd_CK.
U4
CLK

My_Clk Out_Clk

SDRAM_CLK
SDRAM_CLK
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Test for Understanding

Use -path_type full_clock_expand with virtual clocks:

To see the calculated source latency.
This will not provide additional information.

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Break

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Asynchronous, Synchronous, & Exclusive Clocks

3 Types of Clocks

Asynchronous, synchonous, and

and exclusive clocks

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Synchronous versus Asynchronous Clocks

Define:
Synchronous clocks
Public chat
Asynchronous clocks

Use STA to verify timing between synchronous clocks?

Yes No
Use STA to verify timing between asynchronous clocks?
Yes No

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Interacting Clocks and Multiple STA Runs

CLKGEN DESA DESA

CLK1 A CLK3 A
Y Y

CLK2 B CLK4 B
S S

SEL1 SEL2

4 clock combinations over 2 analysis types means

8 STA runs!

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Single Analysis with Multiple Clocks!

Step #1: Create all clocks. Use -add if necessary.
CLKGEN DESA DESA

CLK1 A CLK3 A
Y Y

CLK2 B CLK4 B
S S

SEL1 SEL2

Step #2: Specify exclusive clock groups.

set_clock_groups -exclusive -group CLK1 -group CLK2
set_clock_groups -exclusive -group CLK3 -group CLK4
# Now perform a single analysis run with all clock
combinations.

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Different Example: Multiple Clocks

CLKGEN DESA DESA

CLK1 A CLK3 A
Y Y

CLK2 B CLK4 B
S S

SEL

set_clock_groups -name SEL -exclusive -group "CLK1 CLK3"\

-group "CLK2 CLK4"
# Now perform a single analysis run with all clock
combinations.

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Test for Understanding

CLK1 has a range of possible duty cycles. -> 40/60 to 60/40

CLKGEN DESA DESA

CLK1a
CLK1b A
A CLK3
Y Y

CLK2 B CLK4 B
S S

SEL

Write the commands to specify the exclusive clock groups.

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Asynchronous
Asychronous Clocks clock groups

FF2 does not need to be checked for reliable data capture.

FF1 FF2 FF3

Q D Q D Q

Clk CLK CLK CLK

Clk2

# Specify asynchronous clock groups

set_clock_group -name my_asynch_clocks -asynchronous\
-group Clk -group Clk2

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Identify All Clock Crossings

pt_shell> check_timing -verbose -override clock_crossing
Information: There are 4 clocks having domains interacting.

* all paths are false paths

# part of path are false paths

From Clock Crossing Clocks

-----------------------------------------------------------
SYS_CLK SDRAM_CLK*, SYS_2x_CLK, PCI_CLK*
SDRAM_CLK SYS_CLK*
PCI_CLK SYS_CLK*
SYS_2x_CLK SDRAM_CLK*, SYS_CLK

Circle the one clock pair that has constrained clock crossings.
Do any timing paths exist between PCI_CLK and SDRAM_CLK?
Yes No
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How Do You Perform These Checks?

Interactively
pt_shell> restore_session orca_savesession
pt_shell> check_timing -v -override clock_crossing

Or
During initial run

lappend timing_check_defaults clock_crossing

# Perform default checks + clock_crossing
check_timing -verbose

Where will you place this

Public chat variable?

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Generate Timing Reports Between Clocks

Write the command to generated a timing report between

Clk1 and Clk2.

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Interpret Timing Reports Between Clocks

One by one, circle in the report below:

The launch and capture clocks.
The launch and capture edges.

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Which Edges for Setup and Hold

How Prime Time finds clock edges for multi-frequency clocks.

1. Evaluate waveform over smallest common base period
2. For each capture edge, find the clossest setup lauch edge. Call these
the primary pairs.
3. Out of the primary pairs, pick the most restrictive setup lauch and
capture edges.
4. For each primary pair, draw two hold relationships. Launch to (Capture
- 1); (Launch + 1) to Capture. From all of these hold relationships, pick
the most restrictive.
0ns 4ns 8ns 12ns
setup
L L+1 hold
L launch
C-1 C
C capture
0ns 3ns 6ns 9ns 12ns

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Message During Timing Updates

set timing_update_status_level high

Information: Related clock set 0 includes clock 'SYS_2x_CLK'
with period 4.00. (PTE-064)
Information: Related clock set 0 includes clock 'SYS_CLK'
with period 8.00 (PTE-064)
Information: Related clock set 0 has base period 8.00 (PTE-065)
Information: Expanding clock ‘SYS_2x_CLK' to base period of
8.00 (old period 4.00, added 2 edges). (PTE-016)
Information: Expanding clock 'SYS_CLK' to base period of
8.00 (old period was 8.00, added 0 edges). (PTE-016)

Circle the base period between two clocks.

Are these messages you would suppress

and why?
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Timing Reports for Asynchrous Clocks

FF2 does not need to be checked for reliable data capture.

FF1 FF2 FF3

Q D Q D Q

SYS_CLK CLK CLK CLK

SDRAM_CLK

pt_shell> report_timing -from [get_clocks SYS_CLK] -to\

[get_clocks SDRAM_CLK]

Not constrained paths.

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Reports for Unconstrained Paths

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No Paths versus No Constrained Paths

FF1 FF2 FF3

Q D Q D Q

SYS_CLK CLK CLK CLK

SDRAM_CLK

pt_shell> report_timing -from FF1/CLK -to FF3/D

No constrained paths.
pt_shell> set timing_report_unconstrained_paths true
pt_shell> report_timing -from FF1/CLK -to FF3/D
No paths

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General Guidelines

 There should be no constrained paths between asynchronous clock

domains

How will you validate this?

Public chat

 For the best runtime, turn off report of unconstrained paths when
generating a large number of reports (warning UITE-413)

alias ________ (set timing_report_uncontrained_paths true)

alias ________ (set timing_report_uncontrained_paths false)

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Lab 9: Getting to Know Your Clocks

10 Minute Break

60 minutes
30 Minute LAB

The objective is to:

Apply the commands from lecture to gain familiarity with the
design clocks
Use the Gui for another view of the clock relationships in a
design

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Lab 9 Wrap Up: Propagated Clocks

All subsequently created clocks are propagated by default.

set timing_all_clocks_propagated true

After clocks are created, propagate them.

set_propagated_clock [all_clocks]

Flag ideal clocks in a design.

lappend timing_check_defaults ideal_clocks
check_timing

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Agenda
DAY
3 6 Analysis Type and Back Annotation

7 Additional Checks and Constraints

8 Conclusion

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Objectives

After completing this lecture, you should be able to:

 Describe two kinds of back annotation files
• Parasitics
• SDF
 Describe two methods for calculating path delay
• One "traditional" but inaccurate method
• One safe method recommended for all designs
 Describe how to apply and the benefits of the types
of annotation files

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Topics in this module

1. Parasitic back annotation

2. Delay (SDF) back annotation
3. Slew effects
4. Controlling slew affects with analysis mode
5. Support analysis mode with libraries, back annotation files,
and constraints
6. Accuracy: Removing reconvergent clock pessimism;
Derating delays
7. Validating an SDF file
8. Back annotation-enabled checks - Design Rule Checking
9. Advantage of parasitics over SDF

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Back Annotation Files

 To perform post-layouts STA, you back annotate data into PT with

either a SPEF or an SDF file:
• SPEF
o From a layout extraction tool
o Constrains net R and C values
o Prime Time calculates 'signoff' net and cell delays and transition
times based on these values
• SDF
o From a third party delay calcutor, or from Prime Time
o Constrains calculated net and cell delays
o PT performs timing checks based on these delays

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Back Annotation for the PT Delay Calculator

Parasitic RCs from
extraction

read_parasitics my_chip.spef
PT

CLK

CLK

C total Delay calculation

DRC STA
D Q
D Q
D Q
D Q
CLK
CLK
CLK
CLK

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How Prime Time Calculates Cell Delay

 Call delay is a function of output loading and input slew

 Output loading and input slew affect the cell delay and output
slew
 Output slew becomes the next cell's input slew

Example

Output load = 0.05pF Input slew = 0.5ns

Cell Delay = 0.23ns Output slew = 0.3ns

Output Load (pF) Output Load (pF)

SPICE SPICE
0.005 0.05 0.10 0.15 0.005 0.05 0.10 0.15
Input Trans (ns)

Input Trans (ns)

0.00 0.1 0.15 0.2 0.25 0.00 0.1 0.20 0.37 0.60

0.50 0.15 0.23 0.3 0.38 0.50 0.18 0.30 0.49 0.80

1.00 0.25 0.4 0.3 0.38 1.00 0.25 0.4 0.62 1.00

Cell Delay (ns) Output Slew (ns)

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Do Parasitic Files Supply All Needed Data?

CLK

CLK

 What else do you need to supply?

• External drive cells for inputs
set_driving_cell -lib_cell mpad [get_ports A]
• External loads for outputs
set_load 5 [get_ports O1]

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Reading Parasitic RCs

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Example of Missing Parasitic RC Data

Design input port Internal net driver

TE

CLK

Incomplete
A net is simply
A net tied high parasiticc Error
missing data.
or low is PARA-006
missing data.
Generate a new parasitics RC file!

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Long Runtime Reading Parasitics

 Use Synopsys binary parasitics

My_Chip.sbpf
 If reading multiple parasitics files
• Read from bottom up
• Suppress complaints about incomplete parasitics at the module level

read_parasitcis -quiet -increment -path I_ALU I_ALU.spef.gz

read_parasitics -quiet -increment -path I_DATA_PATH\
I_DATA_PATH.spef.gz
read_parasitics -increment TOP.spef.gz

Read top-level last

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SDF: Using Third-Party Delay Calculators

Parasitic RCs from Third-Party Delay

extraction Calculator
For each PVT

SDF
SDF
SDF

read_parasitics my_chip.spef
read_sdf my_chip.sdf
Pin to pin timing
PT C total
annotations
DRC STA
D Q
D Q
D Q
D Q
CLK
CLK
CLK
CLK

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What Affects SDF Generation?

Circle 4 things that affect SDF generation.

Net
Parasitcs Clock
Drive and load Period
on ports
How slews are
propagated

Input and PVT Corner

output delays
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Effects of Slew

In a single PVT corner, the same cell delay timing arc may have:
2 different delays based on slow/fast slew propagation.
1 delay only.

Max
PVT
U33
A
Y
B FF1
U1

CLK

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Prime Time Slew Propagation and Cell Delays

Two different input pin slews. Which slew gets propagated
for U1 cell delay calculation?

U33
A
Y ?
B FF1
U1

CLK

 Ideally, the specific slew for each path under analysis is used:
• Computationlly prohibitive for the entire design

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Launch versus Capture Path - Use Which Slew?

Max
PVT

Fast slew
1.77
Slow slew
“1.80” Launch Path
3.21
D Q D Q
“3.97”
0.55
“0.60”
CLK CLK

clk Setup/hold
0.21/0.08
0.62 Capture path “0.23/0.10”
“0.65”

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Which Slew Goes with Analysis Type?

bc_wc on_chip_variation

Propagate slow Propagate Propagate

slew for launch Setup slow slew for fast slew for
and capture. launch path. capture path.

Propagate fast Propagate Propagate

slew for launch Hold fast slew for slow slew for
and capture. launch path. capture path.

Which of the above is more conservative?

Public chat Which of the above can produre optimistic results?

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Setup Optimism in the bc_wc Mode

 Since 'worst case' uses all slow delays, setup checks experience
optimism in the following case:
DAT
U6 U7 U8

FF2
FF1
CLK1 U2 U3

Multi-input cell on
clock capture path
U4 U5
CLK2 U1

 Slow slew is propagated from mux output

 Slow delays computed for (U4, U5)
 But fastest possible capture path is needed
 Setup analysis is optimistic for paths captured by CLK1!

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Hold Optimism in the bc_wc Mode

 Since 'best case' uses all fast delays, setup checks experience optimism
in the following case:
DAT
U6 U7 U8

FF2
FF1
CLK1 U2 U3

Multi-input cell on
clock capture path U4 U5
CLK2 U1

 Fast slew is propagated from mux output

 Fast delays computed for (U4, U5)
 But slowest possible capture path is needed
 Hold analysis is optimistic for paths captured by CLK2!

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On Chip Variation: Single Library

Most optimismtic OCV: Setup and
WORST_OC
hold for each corner:
set_operating_conditions
Delay -analysis_type
on_chip_variation
-max_lib WORST_LIB
-max WORST_OC
BEST_OC
-min_lib WORST_LIB
-min WORST_OC
Operating Conditions
-P/-V/T

Pessimistic but safe: Setup and

WORST_OC
hold in each corner: calculated
WORST_OCV_min OCV OCs in library
set_operating_conditions
Delay
-analysis_type
on_chip_variation
-max_lib WORST_LIB
BEST_OCV_min -max WORST_OC
BEST_OC
-min_lib WORST_LIB
Operating Conditions
-min WORST_OCV_min
-P/-V/T

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On-Chip Variation: Multiple Libraries, Derating

Most accurate: Setup and hold for each
WORST_OC
corner: separated calculated OCV libs
WORST_OC_min
set_operating_conditions
Delay -analysis_type
on_chip_variation
-max_lib WORST_LIB
-max WORST_OC
BEST_OC_max
BEST_OC
-min_lib WORST_LIB_OCV_min
-min WORST_OCV_min
Operating Conditions
-P/-V/T

Pessimistic but safe: Setup and

hold in each corner: User-specified derating
WORST_OC
Derated delays
set_operating_conditions
-analysis_type
Delay
on_chip_variation
-max_lib WORST_LIB
-max WORST_OC
Derated delays -min_lib WORST_LIB
BEST_OC -min WORST_OC
Operating Conditions
set_timing_derate -early ....
-P/-V/T

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To Support OCV ...

Worst Corner
 To support recommended analysis of
• Setup and hold in each corner Delay

recommended
Best_corner

Operating Conditions
 How many files do you need? -P/-V/T

• Back annotation files

WORST_OC

• Constraints WORST_OC_min

Delay

 Logistically
• How many runs? BEST_OC_max
BEST_OC

Operating Conditions
-P/-V/T

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How Many Back Annotation Files?

 Parasitics - R + C values
• One SPEF file for all corners Exellent - for most designs
o Prime Time calculates delays for
best case and worst case slews
• Multiple SPEF files
More granular - for
o High cost
 Extraction runtime aggressive designs
 Multiple PT runs
o Benefit generally measured in ps
 SDF - Cell and Net delay
• min::max delays for each corner
o Either one file with OCV
min::max delays
• Or two files representing a single
corner
 One with max ocv delays
 One with min ocv delays

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How Many Constraint Files?

Latency in OCV constraint file: one per corner

# worst case constraint file

set_clock_latency -source -early 2.8 CLK
set_clock_latency -source -late 3.2 CLK

# best case constraint file

set_clock_latency -source -early 0.8 CLK
set_clock_latency -source -late 1.2 CLK

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How many OCV Runs?

Slowest Delays Fastest Delays

Max Min

PVT PVT

Violate Violate Violate Violate

Setup? Hold? Setup? Hold?

Offer one reason to perform setup and hold in both corners.

Public chat

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# STA Runs is Equal to?

Max Min

PVT PVT

Functional Mode Test Mode

How are different

Public chat modes represented? You will have to perform:
2 separates STA runs.
4 separate STA runs.

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Break

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Summary - Analysis Type

 Avoid optimistic results

Default since 2004.12
• Use on_chip_variation
set_operating_conditions -analysis_type on_chip_variation
report_design; # to show current operating condition

 Remove unrealistic clock pessimism caused by the two slews

propagated in on-chip variation mode.

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Clock Reconvergence Pessimism (CRP)

CRP = Lastest arrival time to common point - Earliest arrival time to common
point
FF1 FF2

Common point D Q D Q

U4
U5

U1 CLK CLK

CLK U7 U3 U2
Setup/hold

What causes a non

Public chat zero CRP?

The delay to the common point

should be the same for the launch
Yes No and capture path (i.e. CRP == 0).

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Example: CRP

0.8 + 0.6

0.64 + 0.52

0.8 - 0.64

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Removal of CRP from STA (CRPR)

 By default, Prime Time does not remove CRP

 When performing on-chip variation, set the variable below to true to
remove CRP from STA:
• Especially important for signal sign-off when pushing design
performance
• Expect memory and runtime increase when using CRPR

set timing_remove_clock_reconvergence_pessimism true

Where will you place this variable?

Public chat

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Back annotation: Why use Derating Factor?

 Some PT users apply derating

factors to:
• Static IR drop
• Temperature variation WORST_OC
Derated delays
• Transistor level effects Delay

• On-die process variation

• Chemical process Derated delays

• Mechanical process
BEST_OC

Operating Conditions

• Aging -P/-V/T

The actual factors used must

come from your research!

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Back Annotation: Applying Derating Factors

 Derating factors will scale the delay values

 Prime Time allows for global or specific derating:
• Cells versus nets
• Launch path versus capture path
• Timing checks
•Early versus late

Prime Time

D Q

D Q
CLK

Clk CLK

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How Will You Validate SDF?

With UDSM designs, there is much less

margin for error!

You must understand what your SDF

represents, how it was generated and
how it should be applied during STA.

How will you validate the SDF

information?

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Open the SDF File and Take a Look!

Circle the:
Operating conditions used to generate the SDF.
Time Units (which should match the library units).

orca.sdf

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Pay Attention to Output from read_sdf

Circle the:
Operating conditions used to generate the SDF.
Analysis type.

In which file will you

Public chat find this output logged?

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Validate Design Analysis Type

Circle the analysis type below.

pt_shell> report_design

Design Attribute
-------------------------------------------------------
Operating Condition:
analysis_type single
operating_condition_max_name slow_125_1.162
process max 1
temperature 125
voltage_max 1.62
tree_type_max balanced_case

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Completeness of SDF

In verify the completeness of your SDF,

Public chat
what is the difference between the
following two command?

report_annotated_delay
report_annotated_check

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Reporting Design Rule Violations

read_parasitics clock_gen.spef.gz Parasitic flow

report_constraint

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Summary: Why use Parasitic instead of SDF?

For speed, use save_session and restore_session
 Parasitics
• Accurate - Use BOTH of Prime Time's strengths:
 'signoff quality' delay calculation
 Static timing analysis
• Necessary for Signal Intergrity Analysis
• Enables Design Rule Checking
• Responsive to change
 Size cell
 Constraint or mode changes
 Sign-off (at close of design cycles)
 SDF
• Fast - uses pre-calculated delays
• Not responsive to change
• Often used early in design cycle
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Useful Commands for Lab

report_annotated_delay report existing delay values

report_annotated_check report existing timing checks

set_annotated_delay Overwrite existing SDF with a new delay

(discarding what was initially there).

remove_annotated_delay Remove existing SDF of user specified

remove_annotated_check delays or timing checks.

set_load If SDF is missing, force net parasitic for

set_resistance specific nets.

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Lab 10: SDF and Analysis Type

10 Minute Break

30 minutes
30 Minute LAB

The objective is to:

Debug a hold violation using your understanding of the SDF

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Lab 10 Wrap Up: Missing SDF Annotations

 Prime Time does not assume a zero delay for nets or cells missing
SDF!
• Prime Time will calculate delays using either provided net parasitic
or WLMs
 Timing reports have different annotation for the dominant annotations on
that timing arc

Symbol Annotation
------ ----------
H Hybrid annotation
* SDF back-annotation
& RC network back-annotation
$ RC pi back-annotation
+ Lumped RC
<none> Wire-load model or none

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Lab 10 Wrap Up: CRPR

Is CRPR turned on?
?
pt_shell> print reconvergence
******** Commands **********
Information: No command matched "*reconv". (CMD-040)
******** Variables **********
timing_clock_reconvergence_pessimism = "normal"
timing_remove_clock_reconvergence_pessimism = "true"

report_timing -to sd_DQ[7] -delay min

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Agenda
DAY
3 6 Analysis Type and Back Annotation

7 Additional Checks and Constraints

8 Conclusion

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Review of Units 9-10

List the three types of clocks

Public chat

Why are generated clocks created on

Public chat output ports and the benefit gained?

When will you use bc_wc analysis type

Public chat versus on_chip_variation?

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Objectives

After completing this lecture, you should be able to:

 Address additional constraints and timing checks
while performing STA on a design.
 Recommend a timing modeling technology that
meets the needs of deep sub-micron design

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Additional Timing Checks

Min Pulse Width Checks

Recovery and Removal

Latchs and Time Borrow

Multicycle Paths

Combinational Feedback Loops

Non-unate Cells in Clock Paths

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Timing Checks Verified by STA

Check the timing checks "Timing checks": specfific by the user
already covered. Timing checks: specified by the vendor

recovery
setup
removal
hold MY_DESIGN

Clk4 Clk4
nochange
Clk1
ClkEn U1
clk_gating_setup
Clk2 clock_gating_hold

Timing Model
max_skew
min_period

min_pulse_width

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Asynchronous Clear/Reset Pins

Data Arrival

ClrN ClrN

FF5 ClrN
FF6
clk clk FF2
clk

Data Required

Min Data
Max Data
Arrival clk
0ns 4ns Arrival

FF2/ClrN Max Data

Required
Min Data
FF2/Clk
Required 1ns 5ns

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Timing Report Recovery

One by one, circle the:
Path group. Data transition at the endpoint
Timing path endpoint Library recovery time.

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Recall Path Groups - Full Picture

**clock_gating_default** **async_default**

Clock Gating Out Recovery/

Setup/Hold
Setup/Hold Setup/Hold Removal

clk div_clk clk_slow

Timing paths grouped by the capture clocks.

Write the command to generate

a single timing report for removal

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Test for Understanding

report_timing -delay max_fall -to FF2/ClrN

What is the result?

No constrained paths.
Will generated a timing report.

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Clock Min Pulse Width

Min Pulse FF2

With

Clk
clk
U1 U2

clk
0ns 4ns

U1/Z

Min Pulse
U2/Z
With
FF2/clk

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Summary Min Pulse Width Reports

pt_shell> report_min_pulse_width -verbose \

I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/REG_FILE_B_RAM/CE2

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Report for Min Pulse Width

One by one, circle:
The constrained clock pin. Required width.
This report is for a pulse width: High Low

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Summary Report for All Timing Checks

Circle the new checks just learned.

Which command generated this report?

Public chat

Type of check Total Met Violated Untested

setup 6724 5366 (80%) 0 (0%) 1358 (20%)

hold 6732 5366 (80%) 0 (0%) 1366 (20%)
recovery 362 302 (83%) 0 (0%) 60 (17%)
removal 354 302 (85%) 0 (0%) 52 (15%)
min_period 20 20 (100%) 0 (0%) 0 (0%)
min_pulse_width 4672 4310 (92%) 0 (0%) 362 (8%)
out_setup 138 138 (100%) 0 (0%) 0 (0%)
out_hold 138 74 (54%) 64 (46%) 0 (0%)

All Checks 19250 15988 (84%) 64 (0%) 3198 (16%)

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Latches and Time Borrow

Min Pulse Width Checks

Recovery and Removal

Latchs and Time Borrow

Multicycle Paths

Combinational Feedback Loops

Non-unate Cells in Clock Paths

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What About Latches?

FSM
FF7
clk
Q
L2
FF2
Q
clk

Clk U1
G A
B

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Latches with Zero Time Borrow

Zero Time Borrow
means data arrives FSM Data Arrival
FF7
before the latch
Q
opens L2
Q
clk
Max Data U1
Arrival G A
SYS_CLK
B

Data Required
SYS_CLK
0ns 4ns 8ns

Max Data
L2/D
Require

Circle the clock

L2/G
Public chat edges for hold.
2ns 10ns

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Latches with Time Borrow: Setup

Time Borrow FSM

FF7
allow data to arrive after Q
L2
the latch opens for setup Q
clk

U1
EN A
SYS_CLK
Max Data B
Arrival
Time
Borrow
SYS_CLK
0ns 4ns 8ns

L2/D Max Data

Require
setup
L2/EN

2ns 6ns 10ns

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Max Allowable Time Borrow

One by one, circle:

The time borrowed
Slack
Max allowable time borrow
Setup time of latch

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Break

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Multicycle Paths

Min Pulse Width Checks

Recovery and Removal

Latchs and Time Borrow

Multicycle Paths

Combinational Feedback Loops

Non-unate Cells in Clock Paths

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What Are Multicycle Paths?

Circle the number paths

A 64
D
A
E
< 12 ns
C_reg
64
+ D Y
64
B D E
B
E

D Q
0 0 0 0 0 1
Clk
shift_register

create_clock -p 2 Clk
PrimeTime automatically
identifies multicycle paths!
Yes No

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By Default, What Does PT Report?

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How do you Guide Prime Time?

set_multicycle_path 6 -from reg[26]/CP -to reg/D

report_exceptions
-------------------------------------------------
From Through To Setup Hold
reg[26]/CP * reg/D cycles =6

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Multicycle Paths

Circle the indication this is a multicycle path.

There is no indication!

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Where Should the Hold Check Be?

Setup check after
set_multicycle_path
Capture
Launch

CLK
-2 0ns 2 4 6 8 10 12

C_reg/D

Change could occur near any clock edge

causing metastability!

Circle the clock edges for hold

assuming the flip-flops are:
Active on every clock edge.
Active on every sixth clock edge.

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Prime Time Does Hold Checks Relative to Setup

Default Our Multicycle
Setup = 1 Setup = 6
Capture
Launch

CLK
-2 0ns 2 4 6 8 10 12

C_reg/D Must be stable from launch until hold check

Default
Hold = 0

By default, hold checks are done one cycle

prior to setup.

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Set the Proper Hold Constraint

set_multicycle_path -setup 6 -to [get_pins "*reg[*]/D"]

set_multicycle_path -hold 5 -to [get_pins "*reg[*]/D"]

M H  MS  1

DESIRED RESULT: ALLOW 12ns for ADDER

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Validate Hold Multipliers

What is the hold multiplier?

Public chat

Is this consistent with what we specified?

Public chat

pt_shell> report_exceptions

Reasons: f invalid start points

t invalid end points
p non-existent paths
o overridden pahts
From Through To Setup Hold Ignored
----------------------------------------------------------
* * Zro_Flag_reg/D cycles = 6 cycles =5

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Combinational Feedback Loops

Min Pulse Width Checks

Recovery and Removal

Latchs and Time Borrow

Multicycle Paths

Combinational Feedback Loops

Non-unate Cells in Clock Paths

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STA and Combinational Loops

 Combinational Loops are NOT verifiable using STA

 PT will disable a single timing arc to break this loop

U21

U23

FF3 FF4

How will you verify timing of the combo loop?

Public chat

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Will Prime Time Generate a Warning?

One of the default checks!

pt_shell> check_timing -verbose

Information: Checking 'loops'
Warning: There is 1 timing loop in the design.

Pin (timing loop #1)

-------------------------------------------
U23/Y
U21/B
U21/Y
U23/A
U23/Y
-----------------------------------------

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Gotcha's with Cominational Loops

Does the disable timing arc also break a valid

timing path?
A valid timing path has no combinational
feedback loop.
If yes - turn on dynamic loop breaking.
If no - ignore the check_timing warning.
Do not turn dynamic loop breaking
because it is not required and this allows
for the best PT runtime.

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Identify the Valid Timing Path

Timing arc disable by Prime Time to break the

combinational loop.
Z B D
D U21
FF1 A FF2

A
Z
Q B U23 D

FF3 FF4

CLK

Identify the valid timing path is also broken !

Public chat

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For This Example, Turn On Dynamic Loop

pt_shell> report_disable_timing
Cell or Port From To Sense Flag Reason
-------------------------------------------------------------
U23 B Z * 1

pt_shell> report_timing –through U23/B

No constrained paths

pt_shell> set timing_dynamic_loop_breaking true

pt_shell> report_timing –through U23/B

Point Incr Path

clock clk (rise edge) 0.00 0.00
clock network delay (idea) 0.00 0.00
FF2/CP (PD1) 0.00 0.00 r
FF2/CP (FD1) 1.44 1.44 f
U21/Z (AN2) 0.90 2.35 f
U23/B (AN2) <- 0.00 2.35 f
U23/Z (AN2) 0.00 2.35 f
FF4/D (FD1) 0.00 2.35 f
data arrival time 2.35 f

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Combinational Feedback Loops

Min Pulse Width Checks

Recovery and Removal

Latchs and Time Borrow

Multicycle Paths

Combinational Feedback Loops

Non-unate Cells in Clock Paths

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Propagating Both Sense of the Clock

Information: A non-unate path in clock network detected.
Propagating both inverting and noninverting senses of
clock ‘CLK_TEST’ from pin ‘AND/Z’. (PTE-070)

A non-unate path is one where:

The edge sensitivity is unclear in the library
The edge sensitivity is both positive and negative unate

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PTE-070 non-unateness and set_clock_sense

You can restrict the clock sense with:

set_clock_sense –positive AND/Z; # From AND/Z, propagate
the non-inverting (pin A) path
set_clock_sense –negative AND/Z ;# From AND/Z,
propagapation the inverting (pin B) path

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Lab 11: Additional Checks and Constraints

10 Minute Break

30 minutes
30 Minute LAB

The objective is to:

Apply user specified annoated delays to explore time
borrowing with libraries
Debug PTE-070 messages

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Agenda
DAY
3 6 Analysis Type and Back Annotation

7 Additional Checks and Constraints

8 Conclusion

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After Units 1-6, You Can Now

 Identify problems by interpreting report_timing report

 Debug and explore further by controlling the output of
report_timing reports

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After Units 7-9, You Can Now

 Setup your PrimeTime envirenment

 Using a straight forward and simple methodology, create and debug
a run script
 Create runtime metrics, the key to improving PrimeTime runtime
 Gather information about clocks in an unfamiliar design

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After Units 10-11, You Can Now

 Apply back annotation and on chip variation

 Apply the min and max SDF delays correctly
 Address additional constraints and timing checks

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Thank You!

125