Public Authority for Applied Education and Training

College of Technological Studies

Department of Electronics Engineering Technology

ELECTRONIC CIRCUITS 1
ENT 137
BY: TURKI DARWEESH

PAAET
Electronic Circuits 1 ENT 137 Turki Darweesh

Chapter 1
Semiconductor Diodes

1.2 Ideal Diode

 Ideal diode is a two-terminal device having the symbol shown in figure 1-1 and
characteristics shown in figure 1-2.

 Since the diode conducts current only in one direction defined by the arrow in the
symbol, ideal diode acts like a switch.
 One important parameter of diode is resistance:
a) Conduction Region:
 In the first quadrant of the characteristics.
 Voltage is zero.
 Forward resistance: RF = VF / IF = 0 Ω.
 Diode acts like a short circuit.

b) Nonconduction Region:
 In the third quadrant.
 Current is zero.
 Reverse resistance: RR = VR / IR = ∞ Ω.
 Diode acts like an open circuit.

1.3 Semiconductor Material

 Basic Resistance equation of any material is:
ρl
R= Ω (1-1)
A

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Electronic Circuits 1 ENT 137 Turki Darweesh

Where l = length, A = cross sectional area, and ρ = resistivity of material.

 Based on the value of resistivity, materials are classified into:
a) Conductors:
 low value of resistivity which allow a generous flow of charge.
 One example is Copper with ρ = 10-6 Ω.cm
b) Insulators:
 high value of resistivity which allows very low level of charge flow.
 One example is Mica with ρ = 1012 Ω.cm
c) Semiconductors:
 Intermediate value of resistivity between those of conductors and
insulators.
 Examples are Silicon with ρ = 50x103 Ω.cm and Germanium ρ = 50 Ω.cm.

 Studying the atomic structure of both Silicon and Germanium:

 There are four electrons in the outermost orbit (i.e. Valence electrons).
 In pure silicon or germanium crystal, these 4 valence electrons are bonded
to 4 adjoining atoms by a Covalent Bonding.
 Valence electrons can break covalent bond and become free by absorbing
sufficient kinetic energy from natural source like voltage source.

 Intrinsic material: it is the semiconductor material that is carefully refined to reduce the
impurities to the lowest possible level.

1.5 Extrinsic Materials n-Type and p-Type

 Doping: It is the process of adding certain impurity atoms into pure semiconductor
material.
 Added impurities can be 1 part in 10 million.
 Doping will cause a change in the electrical properties of the material.
 Extrinsic Material: it is the semiconductor that has been subjected to doping process.
a) n-Type Material:
 Created by using impurities elements with 5 free valence electrons such as
Antimony, Arsenic, and Phosphorus.
 This will result in one free (extra) electron from each impurity atom as
shown in figure 1-3.
 Impurity atoms are called Donor Atoms.

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Electronic Circuits 1 ENT 137 Turki Darweesh

b) p-Type Material:
 Created by using impurity elements with 3 valence electrons such as
Boron, Gallium, and Indium.
 This will result in one missing electron for each impurity atom as shown
in figure 1-4.
 This electron vacancy is called a hole.
 Impurity atom are called Acceptor Atoms.

 When an electron moves in one direction to fill a hole, it can be said that the hole is
moving in the opposite direction.
 In an n-type material, electron is called majority carrier while hole is the minority carrier.
 In p-type material, hole is the majority carrier while electron is the minority carrier.

1.6 Semiconductor Diode

 Semiconductor diode is formed by bringing n-type and p-type materials together as in
figure 1-5.

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Electronic Circuits 1 ENT 137 Turki Darweesh

 The application of voltage source (VD) across the terminals of the p-n diode have three
possible cases:
a) No Applied Bias (VD = 0):
 Shown in figure 1-6.
 The net flow of charge in any direction is zero.
 Current ID = 0

b) Reverse Bias (VD < 0):

 Shown in figure 1-7.
 Very low value saturation current (IS) will flow against the direction of the
arrow.
 IS is in the range of µA to nA.

c) Forward Bias (VD > 0):

 Shown in figure 1-8.
 An exponential current (ID) will flow in the direction of the arrow.

 Combining the three previous cases will produce a generalized equation for the current

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K VD
ID = IS (e Tk
− 1) (1-2)

Where IS = reverse saturation current.

K = 11600/η, where η = 1 for Germanium and η = 2 for Silicon.
Tk = TC + 273o is the temperature in Kelvin.

 Equation (1-2) is shown in figure 1-9 where diode current ID is plotted versus diode
voltage VD.

 The Forward voltage at which the forward current starts to rise is called Threshold
voltage (VT) where VT ≈ 0.7 v for Silicon and 0.3 v for Germanium.
 The diode minimum reverse voltage that causes a rapid flow of the current is called
Breakdown voltage (≈ 50 v).

1.8 Resistance Levels

 The Forward resistance of diode is listed in table 1-1. The reverse resistance is too high.
Type Equation Special Characteristics

DC (Static) RD = VD/ID Defined as a point on the characteristics curve

(Q-point).
AC ∆Vd 26mv Defined by a tangent line at the Q-point.
rd = ≅
∆Id Id
(Dynamic)
Average ∆Vd Defined by a straight line between two points
rav = (pt to pt)
AC ∆Id representing limits of operation.
Table 1-1
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1.9 Diode Equivalent Circuits (Models)

 Equivalent circuit is a combination of elements properly chosen to best represent the

actual terminals characteristics of a device.
 Three different models of the diode are discussed next.
1. Piecewise Linear Model:
 Can be used with no conditions.
 Consists of a VT voltage source, rav resistor, and an ideal diode in
series.
 Model and Characteristics curve are Shown in figure 1-10.

2. Simplified Model:
 Used only when Rnetweork >> rav (rav can be ignored).
 Consists of a VT voltage source and an ideal diode in series.
 Model and Characteristics curve are shown in figure 1-11.

3. Ideal Model:
 Used only when both Rnetweork >> rav and Enetwork >> VT (rav and VT
can be ignored).

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Electronic Circuits 1 ENT 137 Turki Darweesh

 Consists only of an ideal diode.

 Model and Characteristics curve are shown in figure 1-12.

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Electronic Circuits 1 ENT 137 Turki Darweesh

Chapter 2
Diode Applications
2.4 Series Diode Configurations with DC Inputs
 For each configuration, the state of the diode (ON or OFF) must be determined first.
 Diode is ON if:
a) The current coming from the voltage source matches with the arrow direction in
diode symbol.
b) Voltage across diode VD is greater than or equal V T of the diode.
 If the diode is found to be ON, it can be replaced with a DC voltage source equals VT (i.e.
use the simplified model discussed earlier in section 1-9).
 An example is shown in circuits of figure 2-1.

 As a result:
 VD = VT
 VR = E – VT
 ID = IR = VR/R
 If The diode is found to be OFF, it can be replaced with an open circuit.
 An example is shown in circuits of figure 2-2.

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 As a result:
a) VD = E
b) VR = 0
c) ID = IR = 0
Example 2-1: Determine Vo and ID in the circuit of figure 2-3.

Solution:

 Considering the polarity of the voltage source, it can be seen that both diodes are
(ON)
 Redrawing the equivalent circuit with diodes Si and Ge replaced by DC voltage
sources VT1 = 0.7 v and VT2 = 0.3 v respectively as in circuit 2-4.

 Applying KVL: E – VT1 – VT2 – Vo = 0

Vo = E – VT1 – VT2
= 12 – 0.7 – 0.3 = 11 v.
 Ohm’s Law: ID = Vo/R = 11/5.6k = 1.96 mA.

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2.7 Sinusoidal Inputs: Half Wave Rectification

 Half wave rectifier makes use of only one half cycle of the AC input wave.
 For the circuit of half wave rectifier shown in figure 2-5 with ideal diode used:

a) vi = Vm sin ωt
b) The average value of vi over one cycle (0 to T) is zero.

 The output of the circuit vo depends on whether the diode is ON or OFF which in turn
depends on the sign of the input vi.

a) During interval from 0 to T/2:

Polarity of vi matches that of the diode, so the diode is ON and can be replaced by
a short circuit. Therefore, vo = vi as shown in figure 2-6.

b) During interval from T/2 to T:

Polarity of vi is opposite to that of the diode, so the diode is OFF and can be
replaced by an open circuit. Therefore, vo = 0 as shown in figure 2-7.

 The average dc value of the output is

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Vo(dc) = 0.318 Vm (2-1)

 If a silicon diode is used in the half wave rectifier:
 The diode will be replaced by a voltage source VT when it is ON.
 Since silicon diode will be ON only when the input voltage exceeds V T, output
voltage vo will suffer an offset as shown in figure 2-8.
 Vo(dc) ≈ 0.318 (Vm – VT) (2-2)

Example 2-2: For the circuit in figure 2-9:

a) Sketch output wave vo.
b) Find Vo(dc).
c) Repeat (a) and (b) if Silicon diode is used.

Solution:
a)
 Diode will be OFF during interval from 0 to T/2.
Therefore, vo = 0.
 Diode will be ON during interval from T/2 to T.
Therefore, vo = vi.
 The output wave is sketched in figure 2-10.

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Electronic Circuits 1 ENT 137 Turki Darweesh

b) Vo(dc) = - 0.318 Vm = (-0.318) (20) = - 6.36 v.

c) When silicon diode is used:
 The output will suffer an offset as shown in figure 2-11.
 Vo(dc) = - 0.318 (Vm – VT) = (-0.318) (20 – 0.7) = - 6.14 v.

2.8 Full Wave Rectification

 Full wave rectifier makes use of both half cycles of the AC input wave.
 One way to implement the full wave rectifier is through bridge network as shown in
figure 2-12.

 The output wave vo of the bridge network should be studied in each half cycle separately:

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a) Interval from 0 to T/2:

 Diodes D1 and D4 are OFF and can be replaced by open circuit.
 Diodes D2 and D3 are ON and can be replaced by short circuit.
 When circuit is redrawn, the output vo will equal input vi. as shown
in figure 2-13.

b) Interval from T/2 to T:

 Diodes D1 and D4 are ON and can be replaced by short circuit.
 Diodes D2 and D3 are OFF and can be replaced by open circuit.
 When circuit is redrawn, the output vo will again equal input vi. as
shown in figure 2-14.

 Note that the polarity of the output vo is the same in both intervals.
 Vo(dc) = 0.636 Vm (2-3)
 If silicon diodes are used:
 Diode should be replaced by VT when it is ON.
 Offsets can be seen in output wave as in figure 2-15.
 Vo(dc) = 0.636 (Vm – 2VT) (2-4)

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2.11 Zener Diodes

 Zener diode is a special type of diode designed to allow current to flow backwards (i.e. in
reverse direction).
 This will happen when certain reverse voltage level is reached. This voltage is called
Zener voltage VZ of the diode.
 Different Zener diodes can have different values of VZ.
 Each zener diode has a maximum allowable current IZmax and power PZmax.
 Values of VZ, IZmax and PZmax can be found in the data sheet of the zener diode.
 The symbol of Zener diode is shown in figure 2-16.
 Zener diode main use is in voltage regulation circuits.

 The analysis of circuits having Zener diodes includes two steps:

a) Determine whether the diode is ON or OFF:
 If V ≥ VZ, diode is ON.
 Otherwise diode is OFF.

b) Replace diode with appropriate model.

 If diode is ON, replace it by voltage source with value VZ.
 If diode is OFF, replace it by an open circuit.

 In studying zener diode, three cases will be considered:

1) Fixed input Vi and Fixed Load RL

 Considering the circuit of basic zener diode regulator shown in figure 2-17:

 Step1: Remove the zener diode (i.e. replace it with open circuit). See figure 2-18.

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 Step2: Calculate voltage across open circuit using VDR

R V
VOC = VL = R L+ Ri (2-5)
L

 Step3: If VOC ≥ VZ, then diode is ON, otherwise it is OFF.

 Step4: Use appropriate equivalent circuit (model) to replace diode.
 Step5: Solve for desired unknowns.

 Assuming the zener diode is ON, equivalent circuit will be as in figure 2-19:

a) VL = VZ (parallel components).
b) KCL: IR = IZ + IL, which means that IZ = IR – IL (2-6)
c) Ohm’s Law: IL = VL/RL
IR = (Vi – VL)/R
 PZ = VZ IZ should be less than PZmax. (2-7)
Example 2-3: For the zener diode circuit shown in figure 2-20:
a) Find VL, VR, IZ and PZ when RL = 1.2 kΩ.
b) Repeat when RL = 3 kΩ.

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Electronic Circuits 1 ENT 137 Turki Darweesh

Solution: Following the 5-steps procedure mentioned earlier to decide whether the zener diode is
ON or OFF by Removing the zener diode and calculating the open circuit voltage and comparing
it with the zener voltage.
R V (1.2)(16)
a) For RL = 1.2 kΩ, VOC = VL = R L+ Ri = = 8.73 v < VZ (10v).
L 1 + 1.2

Therefore, diode is OFF and should be replaced by open circuit as in figure 2-21:

 VL = VOC = 8.73 v.
 KVL: VR = Vi – VL = 16 – 8.73 = 7.27 v.
 IZ = 0 A.
 PZ = VZ IZ = 0 watt.

b) For RL = 3 kΩ, VOC = 12 v > VZ (10v)

Therefore, the diode is ON and should be replaced by a voltage source V Z as in
figure 2-22:

 VL = Vz = 10v.
 VR = Vi – VL = 16 – 10 = 6 v.
 IL = VL/RL = 10/3k = 3.33 mA.
 IR = VR/R = 6/1k = 6 mA.
 IZ = IR – IL = 6 – 3.33 = 2.67 mA.
 PZ = VZ IZ = (10) (2.67m) = 26.7 mw which is less than P Zmax.

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2) Fixed input (Vi) and Variable Load (RL)

 There is a certain range of load values [RLmin, RLmax] that will ensure that the zener diode
is ON.
 It is of great importance to know this range when using zener diode. When diode in
circuit of figure 2-17 is ON:
VL = VZ = (RL Vi) / (R + RL)
 Solving for RLmin leads to
R
 RLmin = VZ (2-8)
V i − VZ
VL VZ
 ILmax = R = (2-9)
Lmin RLmin
 VR = Vi – VZ and IR = VR/R
 IZ = IR – IL and IL = IR – IZ
ILmin = IR – IZmax (2-10)
VZ
 RLmax = I (2-11)
Lmin

 From equation 2-11, maximum load resistor is limited by I Zmax.

Example 2-4: For the circuit in figure 2-23:
a) Determine the range of RL and IL that will result in VL = 10v.
b) Determine the maximum power of diode.

Solution:

a)
Equation 2-8: RLmin = 250 Ω.
Equation 2-9: ILmax = 10/250 = 40 mA.
VR = Vi – VZ = 50 -10 = 40 v.
IR = VR/R = 40 / 1K = 40 mA.
Equation 2-10: ILmin = 40 – 32 = 8 mA.
Equation 2-11: RLmax = 10 / 8m = 1.25 KΩ.
RL = [ 250, 1250] Ω.
IL = [8, 40] mA.
b) PZmax = VZ IZmax = (10) (32m) = 320 mw.

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3- Fixed Load (RL) and variable input (Vi)

 There is a certain range of input values [Vimin, Vimax] that can maintain the zener diode in
the ON state.
 As mentioned before, when zener diode in figure 2-17 is ON,
VL = VZ = (RL Vi) / (R + RL)
 Solving for Vimin:
(RL +R)
 Vimin = VZ (2-12)
RL
 Vimax is limited by maximum zener current IZmax
IRmax = IZmax + IL (2-13)
 Vimax = VRmax + VZ
Vimax = IRmax R + VZ (2-14)
Example 2-5: Determine the range of Vi values that will keep zener diode in figure 2-24 in ON
state.

Solution:

 Equation 2-12: Vimin = 23.67 v.

 IL = VL/RL = 20/1.2K = 16.67 mA.
 Equation 2-13: IRmax = IZmax + IL = 60 + 16.67 = 76.67 mA.
 Equation 2-14: Vimax = (76.67m) (220) + 20 = 36.87 v.
Vi = [23.67, 36.87] v.

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Chapter 3
Bipolar Junction Transistor (BJT)
 Transistor is a three terminal semiconductor device consisting of (n, p, n) or (p, n, p)
layers.
 Outer layers have width much greater than the middle layer (150:1).
 A diagrams of DC biased BJT of both pnp and npn types are shown in figure 3-1.

Where Collector (C), Base (B), and Emitter (E) are the three terminals of the transistor.
 Considering the pnp transistor, it can be noticed that:
 It has two pn junctions, one junction (right) is reversed biased while the other
(left) is forward biased.
 Applying KCL: IE = IB + I C (3-1)
 Circuit symbols of pnp and npn transistors are shown in figure 3-2.

- Arrow always indicates the emitter terminal, inward for pnp and outward for npn.

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3.4 Common-Base Configuration (CB)

 The base is common to both input terminal (E) and output terminal (C). See figures 3-1
and 3-3.

 The input set characteristics of CB configuration relates the input current (IE) to an input
voltage (VBE) for various values of output voltage (VCB) as shown in figure 3-4.

 Note that The input set characteristics of the Common Base configuration shown in
figure 3-4 resembles the diode characteristics discussed in chapter 1.
 Input current IE will start to flow (i.e. transistor is ON) when VBE reaches a value of 0.7 v,
which equals the threshold voltage of the silicon pn junction (diode).
 The output set characteristics relates the output current (IC) to an output voltage (VCB) for
various values of input current (IE) as shown in figure 3-5.

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 The characteristics can be divided into three regions:

 Active Region
o When B-E junction is forward biased while C-B junction is
reversed biased.
o IC ≈ IE (3-2)
o VCB has no effect on IC value in active region.
 Cutoff Region
o Both Junctions are reversed biased.
o IC = 0
 Saturation Region
o Both Junctions are forward biased.
o The region to the left of IC axis (i.e. VCB < 0).
o Dramatic change in characteristics in this region.
 The quantity alpha (α) is defined as the ratio of output current (I C) to input current (IE)
IC
α= (3-3)
IE
 Value of α is less than or equal one, α equals one only when IC = IE (i.e. IB = 0)

3.5 Transistor Amplifying Action

 The basic voltage amplifying common base transistor circuit is shown in figure 3-6.

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 Referring to previously discussed input set and output set characteristics, the typical
range of input resistance Ri is [10, 100] Ω, while the output resistance R o range is (50KΩ
- 1 MΩ).
 Assuming Ri = 20 Ω, Ro = 100 kΩ, and α = 1:
 Ohm’s law: Ii = Vi/Ri = 200m/20 = 10 mA = IE
 IC/IE = α = 1, therefore IC = IE = 10 mA.
 Ohm’s law: VL = IL R = (10m) (5K) = 50 v.
 Voltage Amplification Gain is Av = Vo/Vi = 50/(200m) = 250

3.6 Common-Emitter Configuration (CE)

 The emitter is common or reference to both the input and output terminals.
 Notation and symbol of a pnp common emitter configuration are shown in figure 3-7.

 As for the common base configuration, the following relations are still valid for the
common emitter configuration.

IE = IC + I B
IC = α IE

 The input set characteristics relates the input current (I B) to the input voltage (VBE) for
various values of output voltage (VCE) as shown in figure 3-8.

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 Note that The input set characteristics of Common Emitter configuration shown in figure
3-8 resembles the diode characteristics discussed in chapter 1.
 Input current IB will start to flow (i.e. transistor is ON) when VBE reaches a value of 0.7v,
which equals the threshold voltage of the silicon pn junction (diode).
 The output set characteristics relates the output current (IC) to an output voltage (VCE) for
various values of input current (IB) as shown in figure 3-9.

 Studying figure 3-9, it can be noticed that:

 IB is in (µA) while IC is in (mA).
 Curves of IB are not horizontal which indicates that output current I C is affected
by output voltage VCE.
 The characteristics can be divided into three regions:
 Active Region
o BE junction is forward biased while CB junction is reversed biased.
o This region is used for voltage, current, and power amplification.

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
Cutoff Region
o The region below the curve of IB = 0.
 Saturation Region
o The region to the left of VCEsat.
 The quantity beta (β) is defined as the ratio of output current (I C) to the input current (IB)
I
β = IC (3-4)
B

 Using the relation from equation (3-4) into equation (3-1) leads to the following
equations:
IE = (β +1) IB (3-5)
α = β / (β +1) (3-6)
β = α / (1- α) (3-7)

3.7 Common Collector Configuration (CC)

 The collector is common or reference to both the input and output terminals.
 Notation and symbol of a pnp common collector configuration are shown in figure 3-10.

 Input set characteristics of common collector transistor (IB vs VBC) are similar to those of
common emitter transistor (IB vs VBE).
 Output set characteristics of common collector transistor (I E vs VCE) is similar to those of
common emitter transistor (IC vs VCE).

3.8 Limits of Operation

 For each transistor, there is a region of operation on the characteristics which will ensure
that maximum ratings (voltage, current, and power) of the transistor are not exceeded
and the output signal exhibits minimum distortion.
 For a common emitter configuration, the limits of operation are:

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 ICE0 ≤ IC ≤ ICmax
 VCEsat ≤ VCE ≤ VCEmax
 VCE IC ≤ PCmax
Example 3-1: Describe (graphically) the limits of operation for a CE BJT transistor with the
following characteristics:
VCEsat = 0.3 v, VCEmax = 20 v, ICmax = 50 mA, and PCmax = 300 mw.
Solution:
 IC = ICmax = 50 mA leads to VCE = PCmax/ICmax = 300m/50m = 6 v.
Point P1(6, 50m) is obtained.
 VCE = VCEmax = 20 v leads to IC = PCmax/VCEmax = 300m/20 = 15 mA.
Point P2(20, 15m) is obtained.
 Select IC = 25 mA which leads to VCE = 300m/25m = 12 v.
Point P3(12, 25m) is obtained.
 Points P1, P2, and P3 are marking the region of operation as shown in figure 3-11.

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Chapter 4
DC Biasing BJTs
4.2 Operating Point
 For transistor amplifier, the resulting DC current and voltage establish an operating point
on the characteristics.
 Operating point is also called Quiescent Point (Q-point).
 The Q-point should be within the active region and inside the maximum limits of
operation. Otherwise, it will cause a life shortening and destruction of the device.

4.3 Fixed Bias Circuit

 Consider The fixed bias circuit shown in figure 4-1, for DC analysis:
1. Replace capacitors C1 and C2 by open circuit (just remove).
2. Separate VCC to terminal B and C.

 Redraw the DC equivalent circuit as shown in figure 4-2.

 For the Base-Emitter circuit (input side) in figure 4-3, applying KVL will result in
+VCC – IBRB – VBE = 0
VCC − VBE
IB = (4-1)
RB
 Equation 4-1 indicates that the value of base current IB will depend on the value of base
resistor RB.

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 For the Collector-Emitter circuit (output side) in figure 4-4, applying KVL will result in
+VCE + IC RC – VCC = 0
VCE = VCC – IC RC (4-2)
 Remember that IC = β IB.
 Note that VE = 0, therefore:
VCE = VC and VBE = VB
Example 4-1: For the fixed bias circuit shown in figure 4-5, determine:
a) IB b) IC
c) VCE d) VBC

Solution:
VCC − VBE 12 − 0.7
a) Equation 4-1: IB = = = 47.08 µA.
RB 240K
b) IC = β IB = (50) (47.08 µA) = 2.35 mA.
c) Equation 4-2: VCE = VCC – IC RC = 12 – (2.35m) (2.2K) = 6.83 v.
d) Since VE = 0, therefore, VB = VBE =0.7 v.
VC = VCE = 6.83 v.
and VBC =VB – VC = 0.7 – 6.83 = - 6.13 v.

 From equation 4-2, the saturation output current (ICsat) can be found for VCE ≈ VCEsat ≈ 0
ICsat = VCC/RC (4-3)

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Load Line Analysis:

 Consider the CE transistor circuit shown in figure 4-6:


The output characteristics (IC vs VCE) are shown in figure 3-9 (discussed in CH3).

The output equation is 4-2: VCE = VCC – IC RC

Output equation represents a straight line called Load Line which can be
superimposed on the output characteristics. See figure 4-7.
 Load Line can be determined by having two points:
 When VCE = 0 in equation 4-2, then IC = VCC/RC.
 When IC = 0 in equation 4-2, then VCE = VCC.
 Q-point is the intersection of the load line with the curve of the resulting level of IB.
Example 4-2 For the Load Line and Q-point shown in figure 4-8, determine:
a) VCC b) RC c) RB

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Electronic Circuits 1 ENT 137 Turki Darweesh

Solution: From Figure 4-8:

a) When IC = 0, VCE = VCC = 20v
b) When VCE = 0, IC = VCC/RC = 10 mA.
Therefore, RC = VCC/IC = 20/10m = 2 KΩ.
VCC − VBE
c) At Q-point IB = 25 µA. But IB = RB
VCC − VBE 20 − 0.7
Therefore, RB = = = 772 KΩ.
IB 25 x 10−6

4.4 Emitter-Stabilized Bias Circuit

 The DC bias circuit shown in figure 4-9 contains an emitter resistor (RE) to improve the
stability level compared to that of fixed bias circuit.
 The more stable a configuration, the less its response will change due to undesirable
changes in temperature or transistor β.

 Applying KVL to the base-emitter loop (input side) in DC equivalent circuit shown in
figure 4-10:
+VCC – IBRB – VBE – IE RE = 0
But IE = (β + 1) IB
Therefore, +VCC – IBRB – VBE – (β + 1) IB RE = 0
-IB (RB + (β + 1) RE) + VCC – VBE = 0
VCC − VBE
 IB = R (4-3)
B +(β+1)RE

 Let Ri = (β + 1) RE (4-4)

 Applying KVL to the collector-emitter (output side) in DC equivalent circuit shown in

figure 4-11:
+IE RE + VCE + IC RC – VCC = 0
But IE ≈ IC
Therefore, VCE – VCC + IC (RE + RC) = 0
 VCE = VCC – IC (RE + RC) (4-5)

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Electronic Circuits 1 ENT 137 Turki Darweesh

 Single Subscript Voltages:

 VE = IE RE (4-6)
 VCE = VC – VE then, VC = VCE + VE
 VC = VCC – IC RC (4-7)
 VB = VCC – IB RB or VB = VBE + VE (4-8)
 The Saturation output current (ICsat) is given by:
VCC
ICsat = R (4-9)
C + RE
at which the output voltage is zero (i.e.VCE ≈ VCEsat ≈ 0.)
 The value of IC from equation 4-9 is less than that obtained in the fixed bias circuit in
section 4.3 (i.e. VCC/RC) due to the added emitter resistor RE.
Example 4-3: For the circuit in figure 4-13, determine:
a) IB b) IC c) VCE
d) VC e) VE f) VBC

Solution:
VCC − VBE 20− 0.7
a) Equation 4-3: IB = R = = 40.1 𝜇𝐴.
B +(β+1)RE 430K +(50+1)1K

b) IC = β IB = (50) (40.1µ) = 2.01 mA.

c) Equation 4-5: VCE = VCC – IC (RE + RC) = 20 – (2.01m) (2K+1K) = 13.97 v.
d) Equation 4-7: VC = VCC – IC RC = 20 – (2.01m) (2K) = 15.98 v.
e) VE = VC – VCE = 15.98 – 13.97 = 2.01 v.
f) Equation 4-8: VB = VBE + VE = 0.7 + 2.01 = 2.71 v.
and VBC = VB – VC = 2.71 – 15.98 = -13.27 (reverse bias as expected).

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Electronic Circuits 1 ENT 137 Turki Darweesh

Load Line Analysis

 Recall that the output equation is: VCE = VCC – IC (RE + RC)
 This equation represents the straight line that was called Load Line which can be
determined by having two points as following:
 When IC = 0, VCE = VCC
VCC
 When VCE = 0, IC = R
C + RE
 The Load Line is superimposed on the output characteristics as shown in figure 4-14.
 Q-point is the intersection of the load line with the curve of the resulting level of I B.

4.5 Voltage Divider Bias

 The voltage divider bias configuration is shown in figure 4-15.

 In contrary to fixed bias and emitter stabilized configurations, output set (I C) and (VCE) of
voltage divider configuration are independent of transistor β (i.e. temperature
independent).
 Analysis of this circuit can be done in two methods: Exact method, and Approximate
method.
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Electronic Circuits 1 ENT 137 Turki Darweesh

1. Exact Method
 Redraw the circuit as in figure 4-15 (remove capacitors for DC analysis).
 Find the Thevenin equivalent circuit of the input side (BE junction):
o Remove source VCC
o RTH = R1//R2 = R1R2/(R1+R2)
o Return VCC and open output
R2
o VDR: ETH = VCC R1 +R2
 Replace the input side with the Thevenin equivalent. See figure 4-16.

 Apply KVL:
o ETH – IBRTH – VBE – IERE = 0
o But IE = (β +1) IB
ETH − VBE
o Substitute and simplify: IB = (4-10)
RTH +(β+1)RE
o IC = β IB
 Apply KVL for output side:
o +IERE + VCE + ICRC - VCC = 0
o Assume: IE ≈ IC.
o Substitute and simplify: VCE = VCC – IC(RC+RE) (4-11)
Example 4-4: Determine the DC bias current IC and voltage VCE for circuit in figure 4-17.

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Electronic Circuits 1 ENT 137 Turki Darweesh

Solution:
 RTH = R1//R2 = (3.9K)(39K)/(3.9K+39K) = 3.55 KΩ.
R2 3.9K
 ETH = VCC = (22) = 2 v.
R1 +R2 3.9K+39K
2− 0.7
 Equation 4-10: IB = 3.55K+(100+1)(1.5K) = 8.38 µA.
 IC = β IB = (100) (8.38µA) = 0.838 mA
 Equation 4-11: VCE = VCC –IC(RC+RE) = 22 – (0.838mA) (10K+1.5K) = 12.34 v.

2. Approximate Method
 This method can be applied ONLY when βRE ≥ 10R2.
 If the above condition is satisfied, Base current I B is much smaller than the current
in R2 and can be ignored (IB = 0). Other values can be calculated in the following
sequence:
R2
 VB = VR2 = VCC R (4-12)
1 + R2
 VE = VB – VBE
 IE = VE/RE
 IC ≈ IE
 Output voltage is same as before: VCE = VCC –IC(RC+RE)
Example 4-5: Repeat example 4-4 using the approximate method.
Solution: Check condition: βRE = (100) (1.5K) = 150 KΩ.
10R2 = (10) (3.9K) = 39 KΩ. Therefore, Condition is satisfied.
R2 3.9K
 Equation 4-12: VB = VR2 = VCC = 22 = 2 v.
R1 + R2 3.9K+ 39K
 VE = VB – VBE = 2 – 0.7 = 1.3 v.
 IE = VE/RE = 1.3/1.5k = 0.867 mA.
 IC = IE = 0.867 mA. **
 VCE = VCC –IC(RC+RE) = 22 – (0.867m) (10K + 1.5K) = 12.03 v. **
** Compare with the result of previous example using exact method.

 The saturation output current (ICsat) for VCEsat ≈ 0 is given by:

VCC
ICsat =
RC + RE
 Load Line analysis is similar to that of emitter stabilized configuration which requires
finding two points on the IC vs VCE line as following:
 When IC = 0, VCE = VCC
VCC
 When VCE = 0, IC = R
C + RE

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Electronic Circuits 1 ENT 137 Turki Darweesh

Chapter 5
BJT AC Analysis
5.2 Amplification in the AC Domain
 One of the main functions of transistor is amplification.
 Amplification means that the output ac power of the transistor is greater than its input ac
power.
 This does not contradict with the Conservation of Power Principle because this
amplification is due to the dc input power of the circuit.
 To better understand how transistor behaves, ac analysis (also called small signal
analysis) is important to study.
 The DC Analysis introduced in chapter 4 main objective was to determine the Q-point of
the transistor. However, This Chapter is meant to discuss the small signal (AC) analysis.

5.3 BJT Transistor Modeling

 The key to small signal analysis is the use of equivalent circuit which is also called a
model.
 A model is a combination of elements that best approximate (i.e. equivalent) the
transistor behavior under specific operating conditions.
 There are many BJT models that can be used such as Hybrid, r e, and Hybrid π models.
 As an example, the small signal analysis for the circuit in figure 5-1is studied.

 The DC voltage source VCC should be removed (replaced by short circuit).

 Coupling capacitors C1 and C2 as well as bypass capacitor C3 are chosen so their
reactances are very small (negligible) and can be replaced by short circuits.
 Redraw the circuit as in figure 5-2 with RE shorted out.

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Electronic Circuits 1 ENT 137 Turki Darweesh

 It is important to properly determine the system parameters such as input impedance Zi,
output impedance Zo, input current Ii, and output current Io. See figure 5-3.
 Zo is defined as the impedance determined when input is set to zero.
 Voltage Gain is defined as Av = Vo/Vi.
 Current Gain is defined as Ai = Io/Ii, where Io = IC and Ii = IB.

 For circuit in figure 5-2, establishing a common ground and rearranging the elements will
lead to the circuit in figure 5-4.

 When the transistor in figure 5-4 is replaced by its model which includes familiar
components, the circuit theorems such as Superposition theorem and Thevenin’s theorem
can be applied to determine the desired quantities.

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Electronic Circuits 1 ENT 137 Turki Darweesh

5.4 The re Transistor Model

 The re model employs a diode and a current-controlled current source.
A) Common-Emitter Configuration
 Circuits in figure 5-5a to 5-5c show a common-emitter npn transistor, its diode-current
source equivalent circuit, and its re model respectively.

 Results obtained with the re model circuit should be close to those obtained by the actual
transistor.
 Note that capital letters are used for variables in dc analysis while small letters are used in
ac analysis.
 Recall from chapter 1 that the ac resistance of diode is given by: r ac(diode) = 26m/ID
 Applying previous equation to circuit in figure 5-5b where ID = IE,
re = 26m/IE (5-1)
 Recall that:
 Ic = β Ib
 Ie = (β+1) Ib ≈ β Ib.
 The four parameters can be found from circuit 5-5c as following:
a) Input Impedance Zi
 Vi = Vbe = Ie re ≈ β Ib re
 Ii = Ib
β Ib r e
 By definition Zi = Vi/Ii ≈ = β re (5-2)
Ib
 Zi ranges from few hundreds to few kilo ohms.

b) Output Impedance Zo
 Zo can be determined from the slope of lines in output characteristics (I C
vs VCB). See figure 5-6.
 Zo = ro = 1 / slope.
 Note that slope increases when IC increases.
 Zo value is in the range of 40 KΩ.
 If ro is ignored, Zo = ∞. Otherwise, the re model of CE should include ro as
shown in figure 5-7.

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Electronic Circuits 1 ENT 137 Turki Darweesh

c) Voltage Gain Av
 Vo = - Io RL = - β Ib RL where RL is the load of the circuit.
 Vi = Ii Zi = Ib β re.
− RL
 By definition: Av = Vo/Vi = (5-3)
re
d) Current Gain Ai
Io Ic βIb
 Ai = = = = β (5-4)
Ii Ib Ib

Example 5-1: For the CE circuit, assume that β = 120, I E = 3.2mA, and ro = ∞. Determine:
a) Zi b) Av when RL= 2KΩ. c) Ai when RL= 2KΩ.
Solution:
a) Equation 5-1: re = 26m/IE = (26m)/(3.2m) = 8.125 Ω.
Equation 5-2: Zi = β re = (120) (8.125) = 975 Ω.
− RL −2𝐾
b) Equation 5-3: Av = = = −246.15
re 8.125
c) Equation 5-4: Ai = β = 120.

B) Common-Base Configuration
 Circuits in figure 5-8a to 5-8c show a common-base pnp transistor, its diode-current
source equivalent circuit, and its re model respectively.

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Electronic Circuits 1 ENT 137 Turki Darweesh

 The four parameters can be found from circuit 5-8c as following:

a) Input Impedance Zi
 Zi = re (5-5)
b) Output Impedance Zo
 To determine Zo, set input to zero (Ie = Ic = 0).
 Zo = ∞. (5-6)
 Actually Zo is in the range of Mega Ohm.
 Note that output resistance ro can be determined from the slope of the lines
of output characteristics (IC vs VCB) where slope = 1/ ro.
 Since lines are almost horizontal in figure 5-9, slope will be zero.

c) Voltage Gain Av
 Vo = - Io RL= IC RL = α Ie RL
 Note that Io is in the opposite direction of Ic (i.e. Ic = - Io)
 Vi = Ie Zi = Ie re
α Ie RL α RL
 Av = Vo/Vi = = (5-7)
Ie r e re
RL
 Note that if α ≈1, then Av = re
d) Current Gain Ai
Io −Ic − α Ie
Ai = = = = −α , (α ≈ 1) (5-8)
Ii Ie Ie

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Electronic Circuits 1 ENT 137 Turki Darweesh

Example 5-2: For a common-base configuration with IE = 4 mA, α = 0.98, and an ac input signal
of 2 mv between base and emitter. Determine:
a) Zi b) Av when RL=0.56 KΩ. c) Zo d) Ai
Solution:
a) Equation 5-5: Zi = re = 26m/IE = (26m) / (4m) = 6.5 Ω.
α RL (0.98) (0.56K)
b) Equation 5-7: Av = = = 84.43
re 6.5

c) Equation 5-6: Zo = ∞.
d) Equation 5-8: Ai = −𝛼 = −0.98

5.5 Common-Emitter Fixed Bias Configuration

 The re model introduced in the previous section will now be used to perform a small
signal analysis.
 The small signal analysis of fixed bias configuration (figure 5-10) begins by:
 Removing dc source VCC and replace capacitors by short circuits. (figure 5-11)
 Replace the CE transistor by its re model. (figure 5-12)

 Value of resistor re is determined from dc analysis while β and ro are given by data sheet.

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Electronic Circuits 1 ENT 137 Turki Darweesh

 Model circuit in figure 5-12 can be used to determine the four parameters as following:
a) Zi = RB // βre (5-9)
 When R B ≥ 10 βr e: Zi ≈ βr e

b) Zo = ro // RC (5-10)
 When ro ≥ 10 RC: Zo ≈ RC
(If input set to zero, Vi = 0, then Ii = 0 which leads to Ib = 0. Therefore, open
circuit the dependent current source βIb)

c) To determine Av:
Vi = Ib βre
Vo = - (βIb) (ro // RC)
Vo − (RC //ro )
Therefore, Av = = (5-11)
Vi re
 When ro ≥ 10 RC: Av = -RC/re

d) To determine Ai:
RB Ib RB
CDR: Ib = Ii R  = (a)
B +β re Ii RB +β re
𝑟𝑜 Io 𝛽r
CDR: Io = (βIb) 𝑟  = 𝑟 + o𝑅 (b)
𝑜 + 𝑅𝐶 Ib 𝑜 𝐶
I I
From (a) and (b): Ai = ( Ib ) (Io )
i b
RB 𝛽ro
Ai = (R (5-12)
B +β re ) (𝑟𝑜+ 𝑅𝐶 )
 When ro ≥ 10 RC and RB ≥ 10 βre: Ai ≈ β
 Current gain is related to voltage gain by the following equation:
Ai = - Av (Zi/RC) (5-13)

Example 5-3: For the circuit shown in figure 5-13, with ro = ∞. Determine:

a) re b) Zi c) Zo

d) Av e) Ai f) repeat c, d, and e for ro=50 KΩ.

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Electronic Circuits 1 ENT 137 Turki Darweesh

VCC − VBE 12 − 0.7

Solution: a) dc analysis: IB = = = 24.04 μA
RB 470K

IE = (β+1) IB = (101) (24.04 µ) = 2.428 mA.

re = 26m/IE = (26m)/(2.428) = 10.71 Ω.

b) βre = (100) (10.71) = 1.071 KΩ.

Zi = RB// βre = (470K) (1.071K)/(470K+1.071K) = 1.069 KΩ.

c) Since condition (ro ≥ 10 RC) is satisfied: Zo ≈ RC = 3 KΩ.

d) Since condition (ro ≥ 10 RC) is satisfied: Av = - RC/re = -3K/10.71 = - 280.11

e) Since the conditions (RB ≥ 10 βre) and (ro ≥ 10 RC) are satisfied: Ai ≈ β = 100

f) Equation 5-10: Zo = ro // RC = 2.83 KΩ.

Vo − (RC //ro )
Equation 5-11: Av = Vi
= re
= - 264.24 (compare to -280.11)

RB 𝛽ro
Equation 5-12: Ai = = 94.13 (compare to 100)
(RB +β re ) (𝑟𝑜+ 𝑅𝐶 )

Or using equation 5-13: Ai = - Av (Zi/RC) = 94.16

5.6 CE Voltage Divider Bias

 The small signal analysis of voltage divider bias configuration (figure 5-14) begins by:
a) Removing dc source VCC and replace capacitors by short circuits.
b) Replace the CE transistor by its re model. (figure 5-15)

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Electronic Circuits 1 ENT 137 Turki Darweesh

 Let R’ = R1//R2
 The model with R’ is similar to that of CE fixed bias configuration with R B. Therefore,
the equations of the four parameters found in the previous section can be used for
voltage divider bias circuit with replacing RB by R’ as shown in the following:
a) Zi = R’ // βre (5-9)
 When R’ ≥ 10 βre: Zi ≈ βre

b) Zo = ro // RC (5-10)
 When ro ≥ 10 RC: Zo ≈ RC
(If input set to zero, Vi = 0, then Ii = 0 which leads to Ib = 0. Therefore, open
circuit the dependent current source βIb)

c) To determine Av:
Vi = Ib βre
Vo = - (βIb) (ro // RC)
Vo − (RC //ro )
Therefore, Av = =
Vi re
 When ro ≥ 10 RC: Av = -RC/re

d) To determine Ai:
R′ Ib R′
CDR: Ib = Ii R′ +β r  = (a)
e Ii R′ +β r e
𝑟𝑜 Io 𝛽ro
CDR: Io = (βIb) 𝑟  = (b)
𝑜 + 𝑅𝐶 Ib 𝑟𝑜 + 𝑅𝐶
I I
From (a) and (b): Ai = ( b ) ( o )
Ii Ib
R′ βro
Ai = (R′ +β r
e ) (ro + RC )
 When ro ≥ 10 RC and R’ ≥ 10 βre: Ai ≈ β
 Current gain is related to voltage gain by the following equation:
Ai = - Av (Zi/RC)

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Electronic Circuits 1 ENT 137 Turki Darweesh

Example 5-4: For the circuit shown in figure 5-16, with ro = ∞. Determine:

a) re b) Zi c) Zo

d) Av e) Ai

Solution: a) dc analysis: Testing the condition βRE ≥ 10R2

(90) (1.5K) ≥ (10) (8.2K)  135K ≥ 82 K

condition is satisfied, therefore, the approximate method introduced in section 4.5 can be used
for dc analysis.
R2 8.2K
VB = VCC = (22) = 2.81 v.
R1 + R2 56K+8.2K

VE = VB – VBE = 2.81 – 0.7 = 2.11 v.

IE = VE/RE = 2.11/1.5K = 1.41 mA.

re = 26m/IE = (26m)/(1.41m) = 18.44 Ω. And βre = (90) (18.44) = 1.669 KΩ.

b) R’ = R1//R2 = (56K)(8.2K) / (56K+8.2K) = 7.15 KΩ.

Zi = R’ // βre = 1.35 KΩ.

c) Zo ≈ RC = 6.8 KΩ.

d) Av ≈ - RC / re = - 6.8K/18.44 = - 368.76

e) Condition (R’ ≥ 10 βre) is not satisfied. Therefore,

R′ β
Ai = (R′ +β r = 73.04
e)

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Electronic Circuits 1 ENT 137 Turki Darweesh

5.7 CE Emitter-Bias Configuration

A) Unbypassed

 The Unbypassed configuration circuit and its r e equivalent model are shown in figure 5-
17a and b.
 Note that the effect of resistance ro is ignored in circuit of figure 5-17b.

 Applying KVL to the input side:

Vi - Ib βre - Ie RE = 0, But Ie = (β + 1) Ib

Vi = Ib βre + (β + 1) Ib RE
Since Zb = Vi/Ib, Therefore:
Zb = βre + (β + 1) RE (5-12)
 If ro ≥ 10 (RC + RE), equation 5-12 can be approximated to be:
Zb ≈ β (re + RE) (5-13)
 Since usually (RE >> re), further approximation will lead to:
Zb ≈ βRE (5-14)

 The four parameters can therefore be determined as following:

a) Zi = RB // Zb (5-15)

b) Zo = RC (5-16)

c) To determine Av
 Since Ib = Vi/Zb
 And Vo = - Io RC = - β Ib RC
 Then Vo = - β (Vi/Zb) RC
 Finally, Av = Vo/Vi = (- βRC)/Zb (5-17)

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Electronic Circuits 1 ENT 137 Turki Darweesh

d) To determine Ai
RB Ib RB
 CDR: Ib = R Ii  = (a)
B + Zb Ii RB + Zb
I
 Io = β I b  I o = β (b)
b
 From equations (a) and (b):
Io Ib Io β RB
Ai = = x = (5-18)
Ii Ii Ib RB + Zb
 Or, as mentioned before:
Ai = - Av (Zi/RC)

B) Bypassed

 If resistor RE is bypassed by capacitor CE, then all equations will be exactly similar to
those of CE fixed bias configuration studied in section 5.5.

Example 5-5: For the circuit in figure 5-18 (Unbypassed), determine:

a) re b) Zi c) Zo

d) Av e) Ai

Solution: a) dc analysis as discussed in chapter 4:

VCC − VBE
 Equation 4-3: IB = R = 35.89 µA.
B +(β+1)RE
 IE = (β + 1) IB = (121) (35.89µ) = 4.34 mA.
 re = 26m/IE = (26m) / (4.34m) = 5.99 Ω.

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Electronic Circuits 1 ENT 137 Turki Darweesh

b) Check condition: ro ≥ 10 (RC + RE)  40K ≥ (10) (2.2K + 0.56K)

40k ≥ 27.6K Condition is satisfied

 Therefore, use approximation in equation 5-13 for Zb:

Zb ≈ β (re + RE) = 67.92 KΩ.
 Finally, Zi = RB // Zb = 59.34 KΩ.

c) Zo = RC =2.2 KΩ.

d) Since ro ≥ 10 RC  use equation 5-17:

Av = (- βRC)/Zb = - 3.89

e) Ai = - Av (Zi/RC) = 104.92 (same answer when using equation 5-18).

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Electronic Circuits 1 ENT 137 Turki Darweesh

Chapter 6
Field Effect Transistor (FET)
6.1 Introduction

 Field Effect Transistor (FET) is a three-terminal device used for many applications.
 The main difference between BJT and FET is that FET is a voltage controlled device
while BJT is a current controlled device as shown in figure 6-1.

 FET has a higher input impedance compared to BJT which has a higher voltage gain.
 FET is more temperature stable and smaller in size (used in IC chips).

6.2 Construction and Characteristics of FET

 FET is either n-channel or p-channel with symbols of both types shown in figure 6-2.
 The No-Bias n-channel FET construction is shown in figure 6-3.

Where (D) is Drain, (G) is Gate, and (S) is Source are the three terminals of FET.

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Electronic Circuits 1 ENT 137 Turki Darweesh

 Voltages VGS and VDS have varying values depending on the applied dc sources (i.e. V GG
and VDD).
 For VGS = 0, no dc source is applied between Gate and Source. Rather, a direct
connection (short circuit) is used.
 When the dc source VDD is applied between Drain and Source as in figure 6-4, Voltage
VDS will be established and will cause current ID to flow.

 Depletion region changes with respect to the applied VDS and VGS which leads to
changing the value of current ID.
 As the voltage VDS increases to few volts in positive direction, current ID will increase
accordingly. Plot of ID vs VDS for (VGS = 0) and (VDS ≥ 0) is shown in figure 6-5.
 Saturation level IDSS is the maximum drain current for FET and is defined by the
conditions VGS = 0 and VDS ≥ |Vp |. where Vp is called pinch-off voltage.
 No gate current is flowing which means that drain current is equal to source current:
 IG = 0 (6-1)
 ID = I S (6-2)
 Voltage VGS is controlling the (ID vs VDS) curves when applying a dc source with positive
side connected to the Source terminal as shown in figure 6-6.
 When VGS becomes more and more negative, the saturation level (I DSS) as well as the
pinch-off voltage (VP) will be decreased as shown in figure 6-7.
 The value of VGS that results in making ID = 0 is defined as Vp.
 Vp value is negative for n-channel and positive for p-channel.
 For VGS values between 0 and Vp, current ID ranges between 0 and IDSS.
 Values of Vp and IDSS are given by the specification sheet and can be different from one
FET to another.
 The region to the right of the pinch-off locus is called saturation region or constant
current region which is suitable for use in linear amplification.

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Electronic Circuits 1 ENT 137 Turki Darweesh

 The region to left of pinch off locus is called the ohmic region or voltage-controlled
resistance region.
 The resistance level in this region is given by:
ro
rd = 𝑉𝐺𝑆 2 (6-3)
(1 − Vp
)

Where ro is the resistance when VGS = 0.

6.3 Transfer Characteristics

 The relationship between current ID and voltage VGS is defined by Shockley’s equation:
VGS 2
ID = IDSS (1 − ) (6-4)
Vp

 DC analysis will use a graphical approach by plotting (I D vs VGS) curve.

 The transfer characteristics defined by Shockley’s equation are not affected by the
network in which the device is employed.
 The transfer curve (ID vs VGS) can be obtained in two ways:

a) From Characteristics (ID vs VDS)

 For Vp = -4 v, and IDSS = 8 mA. The (ID vs VDS) curve is shown in the right
section of figure 6-8.
 For the different values of VGS, the values of ID are reflected on the left section of
figure 6-8.
 For example, for VGS = 0, ID will be IDSS. And for VGS = Vp, ID will be zero.

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Electronic Circuits 1 ENT 137 Turki Darweesh

b) From Shockley’s Equation

 For the given values of IDSS and Vp, Shockley’s equation can give many points on
the (ID vs VGS) curve:
0
 For VGS = 0  ID = IDSS (1 − )2 = IDSS
Vp
Vp 2
 For VGS = Vp  ID = IDSS (1 − ) =0
Vp


More points can be obtained by substituting different values of V GS
between 0 and Vp.
 For a given value of ID, the value of VGS is calculated by:
ID
VGS = Vp ( 1 − √I ) (6-5)
DSS

Example 6-1: Sketch the transfer curve defined by IDSS = 12 mA and Vp = - 6 v.

Solution:

 To sketch the required curve, four points should be determined using Shockley’s equation
 When ID = IDSS = 12 mA  VGS = 0 v.  p1(0, 12m)
 When VGS = Vp = -6 v  ID = 0 mA.  p2(- 6, 0)
 When VGS = Vp /2 = -3 v.  ID = (12) (1 – Vp/2Vp) 2

ID = 12/4 = 3 mA  p3(- 3, 3m)

 When VGS = 0.3 Vp  ID = (12) (1- 0.3Vp/Vp)2
ID ≈ (12 (0.5) = 6 mA  p4(- 1.8, 6 m)
 Using the four points found before (p1, p2, p3, and p4), the (I D vs VGS) curve can be
plotted as shown in figure 6-9.

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Electronic Circuits 1 ENT 137 Turki Darweesh

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Electronic Circuits 1 ENT 137 Turki Darweesh

Chapter 7
FET Biasing
7.1 Introduction
 As mentioned in chapter 6, the general relationships used for dc analysis of FET
amplifiers are:

IG ≈ 0 A.

ID = I S
VGS 2
ID = IDSS (1 − )
Vp

7.2 Fixed-Bias Configuration

 The fixed-bias configuration is the simplest configuration as shown in figure 7-1.

 For dc analysis, both capacitors C1 and C2 act like open circuits.

a) Applying KVL to input side:

 - VGG – IGRG – VGS = 0 But IG = 0

Therefore, - VGG – VGS = 0 and VGS = - VGG (7-1)

 ID can now be calculated by Shockley’s equation with the V GS value found earlier.
 A graphical analysis can also be used by plotting (I D vs VGS) for the given values
of IDSS and Vp in addition to the above value of VGS as explained in the following:

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Electronic Circuits 1 ENT 137 Turki Darweesh

o Determining three points at VGS = 0, Vp/2, and Vp as in table 7-1. They

will be enough to plot the curve as in figure 7-2.

VGS(v) ID(mA)

0 IDSS

Vp/2 IDSS/4

Vp 0

Table 7-1

o Adding a vertical line at VGS = - VGG.

o The intersection point of the two curves is called Quiescent Point (I DQ vs
VGSQ). See figure 7-3.

B) Applying KVL to output side:

 VDS + IDRD – VDD = 0  VDS = VDD – IDRD (7-2)

 Single- subscript voltages:
o VS = 0 (Ground) (7-3)
o VD = VDS (7-4)
o VG = VGS (7-5)

Example 7-1: For the circuit in figure 7-4, determine:

a) VGSQ b) IDQ c) VDS

d) VD e) VG f) VS

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Electronic Circuits 1 ENT 137 Turki Darweesh

Solution:

 Mathematical Approach:
a) VGSQ = - VGG = -2
b) IDQ = IDSS (1- VGSQ/Vp)2 = (10m) (1 – (-2)/(-8))2 = 5.625 mA.
c) VDS = VDD – ID RD = 16 – (5.625m)(2K) = 4.75 v.
d) VD = VDS = 4.75 v.
e) VG = VGS = -2 v.
f) VS = 0.

 Graphical Approach
o Plotting (ID vs VGS) curve using Shockley’s equation with IDSS = 10 mA, Vp = -8
v, and VGS = -2 v.
o Plotting the VGSQ = - VGG = - 2 v. The curve is shown in figure 7-5.
o The intersection point is the Q-point
a) VGS = - VGG = - 2 v.
b) IDQ = 5.6 mA.
c) VDS = VDD – IDRD = 16 – (5.6m) (2K) = 4.8 v.
d) VD = VDS = 4.8 v.
e) VG = VGS = -2
f) VS = 0

7.3 Self – Bias Configuration

 The self – bias configuration differs than fixed – bias by the source resistor RS as shown
in figure 7-6.
 For dc analysis, capacitors C1 and C2 act like open circuits.

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Electronic Circuits 1 ENT 137 Turki Darweesh

a) Applying KVL to input side:

 - IG RG – VGS – IS RS = 0 But IG = 0 and IS = ID

Therefore, VGS = - ID RS (7-6)
 Equation 7-6 indicates that VGS is not constant, rather it is a function of Drain current I D.
 Equation 7-6 as well as Shockley’s equation relate input voltage VGS to output current ID.
 Substituting one equation into the other:
V −I R I R
ID = IDSS (1 − VGS )2 = IDSS (1 − VD S )2 = IDSS (1 + DV S )2
p p p
2 Vp V2p V2p
 Rearranging and simplifying  ID2 + ( − ) ID + = 0 (7-7)
RS R2
IDSS S R2S
 Equation 7-7 is a quadratic and might be complicated.
 One way to solve it is through a graphical solution by plotting both equation 7-6 and
Shockley’s equation, then finding the Q-point which is the intersection of the two curves.
 The graphical solution will be explained in the next example.

B) Applying KVL to output side:

 VDD – ID RD – VDS – IS RS = 0 But IS = ID

Therefore, VDS = VDD – ID (RD + RS) (7-8)
 Single Subscript Voltages:
o VS = ID RS (7-9)
o VG = 0 (7-10)
o VD = VDS + VS (7-11)
o or VD = VDD – ID RD (7-12)

Example 7-2: For the circuit in figure 7-7, determine:

a) VGSQ b) IDSQ c) VDS

d) VS e) VG f) VD
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Electronic Circuits 1 ENT 137 Turki Darweesh

Solution:

a) VGS = - ID RS This equation represents a straight line that can be plotted by having two
points as following:

at ID = 0 mA  VGS = 0 v  p1(0, 0)

at ID = 4 mA  VGS = -(4m)(1K) = - 4 v p2(-4, 4m)

Shockley’s curve is also plotted for the given I DSS and Vp. The intersection point of the two
curves determines Q-point as shown in figure 7-8.

From Q-point: VGSQ = - 2.6 v.

b) from Q-point: IDQ = 2.6 mA.

c) VDS = VDD - ID (RS + RD) = 20 – (2.6m) (1K + 3.3K) = 8.82 v.

d) VS = ID RS = (2.6m) (1K) = 2.6 v.

e) VG = 0 v.

f) VD = VDS + VS = 8.82 + 2.6 = 11.42 v. or VD = VDD – IDRD = 11.42 v.

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Electronic Circuits 1 ENT 137 Turki Darweesh

7.4 Voltage – Divider Biasing

 The Voltage – Divider Bias circuit and its dc analysis equivalent circuit are shown in
figure 7-9 and 7-10 respectively.

 Note that resistors R1 and R2 are connected in series because IG = 0.

R2
 VDR: VG = VDD (7-13)
R1 + R2

A) Applying KVL to the input side:

 VG – VGS – ISRS = o But IS = ID

VGS = VG – IDRS (7-14)
 Equation 7-14 relates VGS to ID and can be represented by a straight line which needs
two points to be plotted:
o For ID = 0  VGS = VG  p1(VG, 0)
o For VGS = 0  ID = VG/RS  p2(0, VG/RS)
 The intersection of the straight line with the Shockley’s curve defines the Q-point.
See figure 7-11.
 Note that increasing the value of RS will result in lower Q-point which means lower
ID value and higher VGS value.

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Electronic Circuits 1 ENT 137 Turki Darweesh

B) Applying KVL to the output side:

 VDD – IDRD – VDS – ISRS = 0 But IS = ID

Therefore, VDS = VDD – ID (RD + RS) (7-15)
 Single- Subscript Voltages:
o VD = VDD – IDRD (7-16)
o VS = ID RS (7-17)
 Also: IR1 = IR2 = VDD / (R1 + R2) (7-18)

Example 7-3: For the circuit in figure 7-12, determine:

a) IDQ and VGSQ b) VD

c) VS d) VDS

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Electronic Circuits 1 ENT 137 Turki Darweesh

Solution:

a) First, Shockley’s curve need to be plotted by having three point:

 When VGS = 0  ID = IDSS = 8 mA.  p1(0, 8m)

 When VGS = Vp = - 4 v  ID = 0 mA.  p2(- 4, 0)
 When VGS = Vp/2 = - 2  ID =IDSS/4 = 2 mA  p3(- 2, 2m)

R2 270K
VG = VDD = (16) = 1.82 v.
R1 + R2 270K+ 2100K

Now, VGS = VG – IDRS

VGS = 1.82 – (1.5K) ID This equation represent a straight line that need to be plotted by
having two points:

 When ID = 0  VGS = VG = 1.82 v.  p1(1.82, 0)

 When VGS = 0  ID = VG/RS = 1.82/1.5K = 1.21 mA.  p2(0, 1.21m)

Both Shockley’s curve and straight line are plotted superimposed as in figure 7-13.

From figure 7-13, the resulting Q-point is (-1.8, 2.4m), i.e. IDQ = 2.4 mA and VGSQ = - 1.8 v.

b) VD = VDD – IDRD = 16 – (2.4m) (2.4K) = 10.24 v.

c) VS = ID RS = (2.4m) (1.5K) = 3.6 v.

d) VDS = VDD – ID (RD + RS) = 16 – (2.4m) (1.5K + 2.4K) = 6.64 v.

or, VDS = VD – VS = 10.24 – 3.6 = 6.64 v.

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Electronic Circuits 1 ENT 137 Turki Darweesh

Chapter 8

FET Amplifiers
8.2 FET Small-Signal Model

 As discussed earlier, input voltage VGS controls the output current ID through the
relationship known as Shockley’s equation.
 The change in drain current ID that will result from a change in VGS depends on the
transconductance factor gm as following:

∆ID = g m ∆VGS (8-1)

∆ID
Therefore, gm = (Siemens) (8-2)
∆VGS

 Transconductance factor gm value can be found by two ways:

a) Graphically
Where gm is the slope of Shockley’s curve at the Q-point. See figure 8-1.

b) Mathematically
By Finding the derivative of Shockley’s equation at certain value of VGS
d ID 2 IDSS VGS
gm = = [1 − ] (8-3)
d VGS |Vp | Vp
2 IDSS
When VGS = 0  gm = gm0 = (8-4)
|Vp |
Equation 8-3 can be rewritten in terms of g m0 as following:
VGS
g m = g m0 [1 − ] (8-5)
Vp

 From parts (a) and (b) above, it can be noticed that gm is maximum at VGS = 0 and ID
approaching IDSS. While it is minimum at VGS = Vp and ID = 0.
 In FET specification sheet, gm is given as yfs where gm = yfs which ranges [1m, 5m] S.

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Electronic Circuits 1 ENT 137 Turki Darweesh

 The important ac parameters of FET are:

FET Input Impedance

 Zi = ∞ (8-6)

FET Output Impedance

∆VDS
 Zo = rd = (where VGS is constant) (8-7)
∆ID
 rd = 1/yos (8-8)
where yos is given in FET specification sheet
 rd ranges between 20 KΩ and 100KΩ.
 Zo is (1/slope) of (ID vs VDS) curve at the point of operation. Hence, the more
horizontal the curve, the greater the value of output impedance Z o. See figure 8-2.

FET AC Equivalent Circuit (Model)

 The model for FET transistor in the ac domain is shown in figure 8-3 below.

 Note that Zi = ∞ is represented by the open circuit in the input.

 Output impedance is represented by rd.

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Electronic Circuits 1 ENT 137 Turki Darweesh

Example 8-1: Given yfs = 3.8 mS and yos = 20 µS. Sketch the FET model.

Solution:

 gm = yfs = 3.8 mS
 rd = 1/yos = 1/(20µ) = 50 KΩ.
 The equivalent model is shown in figure 8-4.

8.3 Fixed-Bias Configuration

 The fixed-bias configuration and its equivalent model are shown in figures 8-5 and 8-6.
 gm and rd can be determined by:
a) DC biasing
b) Specification sheet. Or
c) Characteristics.

 For ac analysis, capacitors act like short circuits while dc voltage sources are short
circuits.
 The ac parameters can be found using the model circuit in figure 8-6:

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Electronic Circuits 1 ENT 137 Turki Darweesh

 Zi = RG (8-9)
 To determine Zo:
o set Vi = 0  Vgs = 0 v and also gmVgs = 0 A.
o Zo = RD//rd (8-10)
o When rd ≥ 10 RD  Zo ≈ RD
 To determine voltage gain Av:
o Vo = - gmVgs(RD//rd) = - gmVi (RD//rd) (where Vgs = Vi)
o Av = Vo/Vi = - gm (RD//rd) (8-11)
o When rd ≥ 10 RD  Av ≈ - gm RD

Example 8-2: For the fixed-bias circuit in figure 8-7, IDSS = 10 mA, Vp = - 8 v, and yos = 40 µS.
Determine:

a) gm b) rd c) Zi

d) Zo e) Av

Solution:

a) dc analysis:

 VGSQ = - VGG = - 2 v.
VGS 2
 IDQ = IDSS (1 − ) = 5.625 mA.
Vp
2 IDSS VGS 2 (10m) −2
 gm = [1 − ]= |8|
[1 − ] = 1.88 mS.
|Vp | Vp −8

b) rd = 1/yos = 1/40µ = 25 KΩ.

c) Zi = RG = 1 MΩ.

d) Zo = RD//rd = (2K)(25K) / (2K+25K) = 1.85 KΩ.

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Electronic Circuits 1 ENT 137 Turki Darweesh

e) Av = - gm (RD//rd) = - (1.88m) (1.85K) = - 3.48

But since ro = 25K ≥ 10 RD = 20K  Av ≈ - gm RD = -(1.88m) (2K) = - 3.76

8.4 FET Self-Bias Configuration

A) Bypassed RS

 the self-bias configuration circuit with resistor RS bypassed by capacitor CS and its ac
equivalent model are shown in figures 8-8 and 8-9 respectively.

 Note that this ac model is exactly the same as that of the fixed-bias FET studied in
section 8.3, Therefore the equations to find Zi, Zo, and Av will also be the same.

B) Unbypassed RS

 The capacitor CS is removed. Ignoring the effect of resistor r d (i.e. assuming rd = ∞):
 Zi = RG (8-12)
 Zo = RD (8-13)
 When rd is taken into consideration, a complicated expressions are used to calculate Z o
and Av.

8.5 FET Voltage-Divider Configurations

 The voltage-divider configuration circuit and its ac equivalent model are shown in figures
8-10 and 8-11 respectively.
 For ac analysis, capacitors act like short circuits, and dc voltage source should be short
circuit too.

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Electronic Circuits 1 ENT 137 Turki Darweesh

 The ac parameters can be found using the model in figure 8-11:

 Zi = R1//R2 (8-14)
 To determine Zo:
o set Vi = 0  Vgs = 0 v and also gmVgs = 0 A.
o Zo = RD//rd (8-15)
o When rd ≥ 10 RD  Zo ≈ RD
 To determine Av:
o Vo = - gmVgs(RD//rd) = - gmVi (RD//rd) (where Vgs = Vi)
o Av = Vo/Vi = - gm (RD//rd) (8-16)
o When rd ≥ 10 RD  Av ≈ - gm RD

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